Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012-2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * Daniel Vetter <daniel.vetter@ffwll.ch> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/vgaarb.h> |
| 31 | |
| 32 | #include "i915_drv.h" |
| 33 | #include "intel_drv.h" |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 34 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 35 | /** |
| 36 | * DOC: runtime pm |
| 37 | * |
| 38 | * The i915 driver supports dynamic enabling and disabling of entire hardware |
| 39 | * blocks at runtime. This is especially important on the display side where |
| 40 | * software is supposed to control many power gates manually on recent hardware, |
| 41 | * since on the GT side a lot of the power management is done by the hardware. |
| 42 | * But even there some manual control at the device level is required. |
| 43 | * |
| 44 | * Since i915 supports a diverse set of platforms with a unified codebase and |
| 45 | * hardware engineers just love to shuffle functionality around between power |
| 46 | * domains there's a sizeable amount of indirection required. This file provides |
| 47 | * generic functions to the driver for grabbing and releasing references for |
| 48 | * abstract power domains. It then maps those to the actual power wells |
| 49 | * present for a given platform. |
| 50 | */ |
| 51 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 52 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
| 53 | for (i = 0; \ |
| 54 | i < (power_domains)->power_well_count && \ |
| 55 | ((power_well) = &(power_domains)->power_wells[i]); \ |
| 56 | i++) \ |
Jani Nikula | 95150bd | 2015-11-24 21:21:56 +0200 | [diff] [blame] | 57 | for_each_if ((power_well)->domains & (domain_mask)) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 58 | |
| 59 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ |
| 60 | for (i = (power_domains)->power_well_count - 1; \ |
| 61 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
| 62 | i--) \ |
Jani Nikula | 95150bd | 2015-11-24 21:21:56 +0200 | [diff] [blame] | 63 | for_each_if ((power_well)->domains & (domain_mask)) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 64 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 65 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
| 66 | int power_well_id); |
| 67 | |
Daniel Stone | 9895ad0 | 2015-11-20 15:55:33 +0000 | [diff] [blame] | 68 | const char * |
| 69 | intel_display_power_domain_str(enum intel_display_power_domain domain) |
| 70 | { |
| 71 | switch (domain) { |
| 72 | case POWER_DOMAIN_PIPE_A: |
| 73 | return "PIPE_A"; |
| 74 | case POWER_DOMAIN_PIPE_B: |
| 75 | return "PIPE_B"; |
| 76 | case POWER_DOMAIN_PIPE_C: |
| 77 | return "PIPE_C"; |
| 78 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: |
| 79 | return "PIPE_A_PANEL_FITTER"; |
| 80 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: |
| 81 | return "PIPE_B_PANEL_FITTER"; |
| 82 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: |
| 83 | return "PIPE_C_PANEL_FITTER"; |
| 84 | case POWER_DOMAIN_TRANSCODER_A: |
| 85 | return "TRANSCODER_A"; |
| 86 | case POWER_DOMAIN_TRANSCODER_B: |
| 87 | return "TRANSCODER_B"; |
| 88 | case POWER_DOMAIN_TRANSCODER_C: |
| 89 | return "TRANSCODER_C"; |
| 90 | case POWER_DOMAIN_TRANSCODER_EDP: |
| 91 | return "TRANSCODER_EDP"; |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 92 | case POWER_DOMAIN_TRANSCODER_DSI_A: |
| 93 | return "TRANSCODER_DSI_A"; |
| 94 | case POWER_DOMAIN_TRANSCODER_DSI_C: |
| 95 | return "TRANSCODER_DSI_C"; |
Daniel Stone | 9895ad0 | 2015-11-20 15:55:33 +0000 | [diff] [blame] | 96 | case POWER_DOMAIN_PORT_DDI_A_LANES: |
| 97 | return "PORT_DDI_A_LANES"; |
| 98 | case POWER_DOMAIN_PORT_DDI_B_LANES: |
| 99 | return "PORT_DDI_B_LANES"; |
| 100 | case POWER_DOMAIN_PORT_DDI_C_LANES: |
| 101 | return "PORT_DDI_C_LANES"; |
| 102 | case POWER_DOMAIN_PORT_DDI_D_LANES: |
| 103 | return "PORT_DDI_D_LANES"; |
| 104 | case POWER_DOMAIN_PORT_DDI_E_LANES: |
| 105 | return "PORT_DDI_E_LANES"; |
| 106 | case POWER_DOMAIN_PORT_DSI: |
| 107 | return "PORT_DSI"; |
| 108 | case POWER_DOMAIN_PORT_CRT: |
| 109 | return "PORT_CRT"; |
| 110 | case POWER_DOMAIN_PORT_OTHER: |
| 111 | return "PORT_OTHER"; |
| 112 | case POWER_DOMAIN_VGA: |
| 113 | return "VGA"; |
| 114 | case POWER_DOMAIN_AUDIO: |
| 115 | return "AUDIO"; |
| 116 | case POWER_DOMAIN_PLLS: |
| 117 | return "PLLS"; |
| 118 | case POWER_DOMAIN_AUX_A: |
| 119 | return "AUX_A"; |
| 120 | case POWER_DOMAIN_AUX_B: |
| 121 | return "AUX_B"; |
| 122 | case POWER_DOMAIN_AUX_C: |
| 123 | return "AUX_C"; |
| 124 | case POWER_DOMAIN_AUX_D: |
| 125 | return "AUX_D"; |
| 126 | case POWER_DOMAIN_GMBUS: |
| 127 | return "GMBUS"; |
| 128 | case POWER_DOMAIN_INIT: |
| 129 | return "INIT"; |
| 130 | case POWER_DOMAIN_MODESET: |
| 131 | return "MODESET"; |
| 132 | default: |
| 133 | MISSING_CASE(domain); |
| 134 | return "?"; |
| 135 | } |
| 136 | } |
| 137 | |
Damien Lespiau | e8ca932 | 2015-07-30 18:20:26 -0300 | [diff] [blame] | 138 | static void intel_power_well_enable(struct drm_i915_private *dev_priv, |
| 139 | struct i915_power_well *power_well) |
| 140 | { |
| 141 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
| 142 | power_well->ops->enable(dev_priv, power_well); |
| 143 | power_well->hw_enabled = true; |
| 144 | } |
| 145 | |
Damien Lespiau | dcddab3 | 2015-07-30 18:20:27 -0300 | [diff] [blame] | 146 | static void intel_power_well_disable(struct drm_i915_private *dev_priv, |
| 147 | struct i915_power_well *power_well) |
| 148 | { |
| 149 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
| 150 | power_well->hw_enabled = false; |
| 151 | power_well->ops->disable(dev_priv, power_well); |
| 152 | } |
| 153 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 154 | /* |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 155 | * We should only use the power well if we explicitly asked the hardware to |
| 156 | * enable it, so check if it's enabled and also check if we've requested it to |
| 157 | * be enabled. |
| 158 | */ |
| 159 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
| 160 | struct i915_power_well *power_well) |
| 161 | { |
| 162 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
| 163 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); |
| 164 | } |
| 165 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 166 | /** |
| 167 | * __intel_display_power_is_enabled - unlocked check for a power domain |
| 168 | * @dev_priv: i915 device instance |
| 169 | * @domain: power domain to check |
| 170 | * |
| 171 | * This is the unlocked version of intel_display_power_is_enabled() and should |
| 172 | * only be used from error capture and recovery code where deadlocks are |
| 173 | * possible. |
| 174 | * |
| 175 | * Returns: |
| 176 | * True when the power domain is enabled, false otherwise. |
| 177 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 178 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 179 | enum intel_display_power_domain domain) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 180 | { |
| 181 | struct i915_power_domains *power_domains; |
| 182 | struct i915_power_well *power_well; |
| 183 | bool is_enabled; |
| 184 | int i; |
| 185 | |
| 186 | if (dev_priv->pm.suspended) |
| 187 | return false; |
| 188 | |
| 189 | power_domains = &dev_priv->power_domains; |
| 190 | |
| 191 | is_enabled = true; |
| 192 | |
| 193 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 194 | if (power_well->always_on) |
| 195 | continue; |
| 196 | |
| 197 | if (!power_well->hw_enabled) { |
| 198 | is_enabled = false; |
| 199 | break; |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | return is_enabled; |
| 204 | } |
| 205 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 206 | /** |
Damien Lespiau | f61ccae | 2014-11-25 13:45:41 +0000 | [diff] [blame] | 207 | * intel_display_power_is_enabled - check for a power domain |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 208 | * @dev_priv: i915 device instance |
| 209 | * @domain: power domain to check |
| 210 | * |
| 211 | * This function can be used to check the hw power domain state. It is mostly |
| 212 | * used in hardware state readout functions. Everywhere else code should rely |
| 213 | * upon explicit power domain reference counting to ensure that the hardware |
| 214 | * block is powered up before accessing it. |
| 215 | * |
| 216 | * Callers must hold the relevant modesetting locks to ensure that concurrent |
| 217 | * threads can't disable the power well while the caller tries to read a few |
| 218 | * registers. |
| 219 | * |
| 220 | * Returns: |
| 221 | * True when the power domain is enabled, false otherwise. |
| 222 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 223 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 224 | enum intel_display_power_domain domain) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 225 | { |
| 226 | struct i915_power_domains *power_domains; |
| 227 | bool ret; |
| 228 | |
| 229 | power_domains = &dev_priv->power_domains; |
| 230 | |
| 231 | mutex_lock(&power_domains->lock); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 232 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 233 | mutex_unlock(&power_domains->lock); |
| 234 | |
| 235 | return ret; |
| 236 | } |
| 237 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 238 | /** |
| 239 | * intel_display_set_init_power - set the initial power domain state |
| 240 | * @dev_priv: i915 device instance |
| 241 | * @enable: whether to enable or disable the initial power domain state |
| 242 | * |
| 243 | * For simplicity our driver load/unload and system suspend/resume code assumes |
| 244 | * that all power domains are always enabled. This functions controls the state |
| 245 | * of this little hack. While the initial power domain state is enabled runtime |
| 246 | * pm is effectively disabled. |
| 247 | */ |
Daniel Vetter | d9bc89d9 | 2014-09-30 10:56:40 +0200 | [diff] [blame] | 248 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
| 249 | bool enable) |
| 250 | { |
| 251 | if (dev_priv->power_domains.init_power_on == enable) |
| 252 | return; |
| 253 | |
| 254 | if (enable) |
| 255 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
| 256 | else |
| 257 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
| 258 | |
| 259 | dev_priv->power_domains.init_power_on = enable; |
| 260 | } |
| 261 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 262 | /* |
| 263 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
| 264 | * when not needed anymore. We have 4 registers that can request the power well |
| 265 | * to be enabled, and it will only be disabled if none of the registers is |
| 266 | * requesting it to be enabled. |
| 267 | */ |
| 268 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 269 | { |
| 270 | struct drm_device *dev = dev_priv->dev; |
| 271 | |
| 272 | /* |
| 273 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 274 | * we'll get unclaimed register interrupts. This stops after we write |
| 275 | * anything to the VGA MSR register. The vgacon module uses this |
| 276 | * register all the time, so if we unbind our driver and, as a |
| 277 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 278 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 279 | * sure vgacon can keep working normally without triggering interrupts |
| 280 | * and error messages. |
| 281 | */ |
| 282 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 283 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 284 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 285 | |
Damien Lespiau | 2540039 | 2015-03-06 18:50:52 +0000 | [diff] [blame] | 286 | if (IS_BROADWELL(dev)) |
Damien Lespiau | 4c6c03b | 2015-03-06 18:50:48 +0000 | [diff] [blame] | 287 | gen8_irq_power_well_post_enable(dev_priv, |
| 288 | 1 << PIPE_C | 1 << PIPE_B); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 289 | } |
| 290 | |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 291 | static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) |
| 292 | { |
| 293 | if (IS_BROADWELL(dev_priv)) |
| 294 | gen8_irq_power_well_pre_disable(dev_priv, |
| 295 | 1 << PIPE_C | 1 << PIPE_B); |
| 296 | } |
| 297 | |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 298 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
| 299 | struct i915_power_well *power_well) |
| 300 | { |
| 301 | struct drm_device *dev = dev_priv->dev; |
| 302 | |
| 303 | /* |
| 304 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 305 | * we'll get unclaimed register interrupts. This stops after we write |
| 306 | * anything to the VGA MSR register. The vgacon module uses this |
| 307 | * register all the time, so if we unbind our driver and, as a |
| 308 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 309 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 310 | * sure vgacon can keep working normally without triggering interrupts |
| 311 | * and error messages. |
| 312 | */ |
| 313 | if (power_well->data == SKL_DISP_PW_2) { |
| 314 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 315 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 316 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 317 | |
| 318 | gen8_irq_power_well_post_enable(dev_priv, |
| 319 | 1 << PIPE_C | 1 << PIPE_B); |
| 320 | } |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 321 | } |
| 322 | |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 323 | static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, |
| 324 | struct i915_power_well *power_well) |
| 325 | { |
| 326 | if (power_well->data == SKL_DISP_PW_2) |
| 327 | gen8_irq_power_well_pre_disable(dev_priv, |
| 328 | 1 << PIPE_C | 1 << PIPE_B); |
| 329 | } |
| 330 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 331 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
| 332 | struct i915_power_well *power_well, bool enable) |
| 333 | { |
| 334 | bool is_enabled, enable_requested; |
| 335 | uint32_t tmp; |
| 336 | |
| 337 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
| 338 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
| 339 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; |
| 340 | |
| 341 | if (enable) { |
| 342 | if (!enable_requested) |
| 343 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
| 344 | HSW_PWR_WELL_ENABLE_REQUEST); |
| 345 | |
| 346 | if (!is_enabled) { |
| 347 | DRM_DEBUG_KMS("Enabling power well\n"); |
| 348 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
| 349 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
| 350 | DRM_ERROR("Timeout enabling power well\n"); |
Paulo Zanoni | 6d729bf | 2014-10-07 16:11:11 -0300 | [diff] [blame] | 351 | hsw_power_well_post_enable(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 352 | } |
| 353 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 354 | } else { |
| 355 | if (enable_requested) { |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 356 | hsw_power_well_pre_disable(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 357 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
| 358 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
| 359 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
| 360 | } |
| 361 | } |
| 362 | } |
| 363 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 364 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
| 365 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ |
| 366 | BIT(POWER_DOMAIN_PIPE_B) | \ |
| 367 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ |
| 368 | BIT(POWER_DOMAIN_PIPE_C) | \ |
| 369 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ |
| 370 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ |
| 371 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 372 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
| 373 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
| 374 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
| 375 | BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 376 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 377 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 378 | BIT(POWER_DOMAIN_AUX_D) | \ |
| 379 | BIT(POWER_DOMAIN_AUDIO) | \ |
| 380 | BIT(POWER_DOMAIN_VGA) | \ |
| 381 | BIT(POWER_DOMAIN_INIT)) |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 382 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 383 | BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ |
| 384 | BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 385 | BIT(POWER_DOMAIN_INIT)) |
| 386 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 387 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 388 | BIT(POWER_DOMAIN_INIT)) |
| 389 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 390 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 391 | BIT(POWER_DOMAIN_INIT)) |
| 392 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 393 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 394 | BIT(POWER_DOMAIN_INIT)) |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 395 | #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ |
| 396 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
| 397 | BIT(POWER_DOMAIN_MODESET) | \ |
| 398 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 399 | BIT(POWER_DOMAIN_INIT)) |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 400 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
Imre Deak | 4a76f29 | 2015-11-04 19:24:15 +0200 | [diff] [blame] | 401 | (POWER_DOMAIN_MASK & ~( \ |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 402 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
| 403 | SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \ |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 404 | BIT(POWER_DOMAIN_INIT)) |
| 405 | |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 406 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
| 407 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ |
| 408 | BIT(POWER_DOMAIN_PIPE_B) | \ |
| 409 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ |
| 410 | BIT(POWER_DOMAIN_PIPE_C) | \ |
| 411 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ |
| 412 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ |
| 413 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 414 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
| 415 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 416 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 417 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 418 | BIT(POWER_DOMAIN_AUDIO) | \ |
| 419 | BIT(POWER_DOMAIN_VGA) | \ |
Ville Syrjälä | f0ab43e | 2015-11-09 16:48:19 +0100 | [diff] [blame] | 420 | BIT(POWER_DOMAIN_GMBUS) | \ |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 421 | BIT(POWER_DOMAIN_INIT)) |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 422 | #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ |
| 423 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
| 424 | BIT(POWER_DOMAIN_MODESET) | \ |
| 425 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 426 | BIT(POWER_DOMAIN_INIT)) |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 427 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
Imre Deak | d7d7c9e | 2016-04-01 16:02:42 +0300 | [diff] [blame^] | 428 | (POWER_DOMAIN_MASK & ~( \ |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 429 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ |
| 430 | BIT(POWER_DOMAIN_INIT)) |
| 431 | |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 432 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
| 433 | { |
Imre Deak | bfcdabe | 2016-04-01 16:02:37 +0300 | [diff] [blame] | 434 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), |
| 435 | "DC9 already programmed to be enabled.\n"); |
| 436 | WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, |
| 437 | "DC5 still not disabled to enable DC9.\n"); |
| 438 | WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); |
| 439 | WARN_ONCE(intel_irqs_enabled(dev_priv), |
| 440 | "Interrupts not disabled yet.\n"); |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 441 | |
| 442 | /* |
| 443 | * TODO: check for the following to verify the conditions to enter DC9 |
| 444 | * state are satisfied: |
| 445 | * 1] Check relevant display engine registers to verify if mode set |
| 446 | * disable sequence was followed. |
| 447 | * 2] Check if display uninitialize sequence is initialized. |
| 448 | */ |
| 449 | } |
| 450 | |
| 451 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) |
| 452 | { |
Imre Deak | bfcdabe | 2016-04-01 16:02:37 +0300 | [diff] [blame] | 453 | WARN_ONCE(intel_irqs_enabled(dev_priv), |
| 454 | "Interrupts not disabled yet.\n"); |
| 455 | WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, |
| 456 | "DC5 still not disabled.\n"); |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 457 | |
| 458 | /* |
| 459 | * TODO: check for the following to verify DC9 state was indeed |
| 460 | * entered before programming to disable it: |
| 461 | * 1] Check relevant display engine registers to verify if mode |
| 462 | * set disable sequence was followed. |
| 463 | * 2] Check if display uninitialize sequence is initialized. |
| 464 | */ |
| 465 | } |
| 466 | |
Mika Kuoppala | 779cb5d | 2016-02-18 17:58:09 +0200 | [diff] [blame] | 467 | static void gen9_write_dc_state(struct drm_i915_private *dev_priv, |
| 468 | u32 state) |
| 469 | { |
| 470 | int rewrites = 0; |
| 471 | int rereads = 0; |
| 472 | u32 v; |
| 473 | |
| 474 | I915_WRITE(DC_STATE_EN, state); |
| 475 | |
| 476 | /* It has been observed that disabling the dc6 state sometimes |
| 477 | * doesn't stick and dmc keeps returning old value. Make sure |
| 478 | * the write really sticks enough times and also force rewrite until |
| 479 | * we are confident that state is exactly what we want. |
| 480 | */ |
| 481 | do { |
| 482 | v = I915_READ(DC_STATE_EN); |
| 483 | |
| 484 | if (v != state) { |
| 485 | I915_WRITE(DC_STATE_EN, state); |
| 486 | rewrites++; |
| 487 | rereads = 0; |
| 488 | } else if (rereads++ > 5) { |
| 489 | break; |
| 490 | } |
| 491 | |
| 492 | } while (rewrites < 100); |
| 493 | |
| 494 | if (v != state) |
| 495 | DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", |
| 496 | state, v); |
| 497 | |
| 498 | /* Most of the times we need one retry, avoid spam */ |
| 499 | if (rewrites > 1) |
| 500 | DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", |
| 501 | state, rewrites); |
| 502 | } |
| 503 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 504 | static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 505 | { |
| 506 | uint32_t val; |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 507 | uint32_t mask; |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 508 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 509 | mask = DC_STATE_EN_UPTO_DC5; |
| 510 | if (IS_BROXTON(dev_priv)) |
| 511 | mask |= DC_STATE_EN_DC9; |
| 512 | else |
| 513 | mask |= DC_STATE_EN_UPTO_DC6; |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 514 | |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 515 | if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) |
| 516 | state &= dev_priv->csr.allowed_dc_mask; |
Patrik Jakobsson | 443646c | 2015-11-16 15:01:06 +0100 | [diff] [blame] | 517 | |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 518 | val = I915_READ(DC_STATE_EN); |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 519 | DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", |
| 520 | val & mask, state); |
Patrik Jakobsson | 832dba8 | 2016-02-18 17:21:11 +0200 | [diff] [blame] | 521 | |
| 522 | /* Check if DMC is ignoring our DC state requests */ |
| 523 | if ((val & mask) != dev_priv->csr.dc_state) |
| 524 | DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", |
| 525 | dev_priv->csr.dc_state, val & mask); |
| 526 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 527 | val &= ~mask; |
| 528 | val |= state; |
Mika Kuoppala | 779cb5d | 2016-02-18 17:58:09 +0200 | [diff] [blame] | 529 | |
| 530 | gen9_write_dc_state(dev_priv, val); |
Patrik Jakobsson | 832dba8 | 2016-02-18 17:21:11 +0200 | [diff] [blame] | 531 | |
| 532 | dev_priv->csr.dc_state = val & mask; |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 533 | } |
| 534 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 535 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) |
| 536 | { |
| 537 | assert_can_enable_dc9(dev_priv); |
| 538 | |
| 539 | DRM_DEBUG_KMS("Enabling DC9\n"); |
| 540 | |
| 541 | gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); |
| 542 | } |
| 543 | |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 544 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) |
| 545 | { |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 546 | assert_can_disable_dc9(dev_priv); |
| 547 | |
| 548 | DRM_DEBUG_KMS("Disabling DC9\n"); |
| 549 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 550 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 551 | } |
| 552 | |
Daniel Vetter | af5fead | 2015-10-28 23:58:57 +0200 | [diff] [blame] | 553 | static void assert_csr_loaded(struct drm_i915_private *dev_priv) |
| 554 | { |
| 555 | WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), |
| 556 | "CSR program storage start is NULL\n"); |
| 557 | WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); |
| 558 | WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); |
| 559 | } |
| 560 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 561 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 562 | { |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 563 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
| 564 | SKL_DISP_PW_2); |
| 565 | |
Jesse Barnes | 6ff8ab0 | 2015-09-10 08:20:28 -0700 | [diff] [blame] | 566 | WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 567 | |
Jesse Barnes | 6ff8ab0 | 2015-09-10 08:20:28 -0700 | [diff] [blame] | 568 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), |
| 569 | "DC5 already programmed to be enabled.\n"); |
Imre Deak | c9b8846 | 2015-12-15 20:10:34 +0200 | [diff] [blame] | 570 | assert_rpm_wakelock_held(dev_priv); |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 571 | |
| 572 | assert_csr_loaded(dev_priv); |
| 573 | } |
| 574 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 575 | static void gen9_enable_dc5(struct drm_i915_private *dev_priv) |
| 576 | { |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 577 | assert_can_enable_dc5(dev_priv); |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 578 | |
| 579 | DRM_DEBUG_KMS("Enabling DC5\n"); |
| 580 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 581 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 582 | } |
| 583 | |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 584 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 585 | { |
Jesse Barnes | 6ff8ab0 | 2015-09-10 08:20:28 -0700 | [diff] [blame] | 586 | WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
| 587 | "Backlight is not disabled.\n"); |
| 588 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), |
| 589 | "DC6 already programmed to be enabled.\n"); |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 590 | |
| 591 | assert_csr_loaded(dev_priv); |
| 592 | } |
| 593 | |
Animesh Manna | 0a9d2be | 2015-09-29 11:01:59 +0530 | [diff] [blame] | 594 | void skl_enable_dc6(struct drm_i915_private *dev_priv) |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 595 | { |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 596 | assert_can_enable_dc6(dev_priv); |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 597 | |
| 598 | DRM_DEBUG_KMS("Enabling DC6\n"); |
| 599 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 600 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); |
| 601 | |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 602 | } |
| 603 | |
Animesh Manna | 0a9d2be | 2015-09-29 11:01:59 +0530 | [diff] [blame] | 604 | void skl_disable_dc6(struct drm_i915_private *dev_priv) |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 605 | { |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 606 | DRM_DEBUG_KMS("Disabling DC6\n"); |
| 607 | |
Imre Deak | 13ae3a0 | 2015-11-04 19:24:16 +0200 | [diff] [blame] | 608 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 609 | } |
| 610 | |
Imre Deak | c6782b7 | 2016-04-05 13:26:05 +0300 | [diff] [blame] | 611 | static void |
| 612 | gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv, |
| 613 | struct i915_power_well *power_well) |
| 614 | { |
| 615 | enum skl_disp_power_wells power_well_id = power_well->data; |
| 616 | u32 val; |
| 617 | u32 mask; |
| 618 | |
| 619 | mask = SKL_POWER_WELL_REQ(power_well_id); |
| 620 | |
| 621 | val = I915_READ(HSW_PWR_WELL_KVMR); |
| 622 | if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n", |
| 623 | power_well->name)) |
| 624 | I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask); |
| 625 | |
| 626 | val = I915_READ(HSW_PWR_WELL_BIOS); |
| 627 | val |= I915_READ(HSW_PWR_WELL_DEBUG); |
| 628 | |
| 629 | if (!(val & mask)) |
| 630 | return; |
| 631 | |
| 632 | /* |
| 633 | * DMC is known to force on the request bits for power well 1 on SKL |
| 634 | * and BXT and the misc IO power well on SKL but we don't expect any |
| 635 | * other request bits to be set, so WARN for those. |
| 636 | */ |
| 637 | if (power_well_id == SKL_DISP_PW_1 || |
| 638 | (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO)) |
| 639 | DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on " |
| 640 | "by DMC\n", power_well->name); |
| 641 | else |
| 642 | WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n", |
| 643 | power_well->name); |
| 644 | |
| 645 | I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask); |
| 646 | I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask); |
| 647 | } |
| 648 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 649 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
| 650 | struct i915_power_well *power_well, bool enable) |
| 651 | { |
| 652 | uint32_t tmp, fuse_status; |
| 653 | uint32_t req_mask, state_mask; |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 654 | bool is_enabled, enable_requested, check_fuse_status = false; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 655 | |
| 656 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
| 657 | fuse_status = I915_READ(SKL_FUSE_STATUS); |
| 658 | |
| 659 | switch (power_well->data) { |
| 660 | case SKL_DISP_PW_1: |
| 661 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
| 662 | SKL_FUSE_PG0_DIST_STATUS), 1)) { |
| 663 | DRM_ERROR("PG0 not enabled\n"); |
| 664 | return; |
| 665 | } |
| 666 | break; |
| 667 | case SKL_DISP_PW_2: |
| 668 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { |
| 669 | DRM_ERROR("PG1 in disabled state\n"); |
| 670 | return; |
| 671 | } |
| 672 | break; |
| 673 | case SKL_DISP_PW_DDI_A_E: |
| 674 | case SKL_DISP_PW_DDI_B: |
| 675 | case SKL_DISP_PW_DDI_C: |
| 676 | case SKL_DISP_PW_DDI_D: |
| 677 | case SKL_DISP_PW_MISC_IO: |
| 678 | break; |
| 679 | default: |
| 680 | WARN(1, "Unknown power well %lu\n", power_well->data); |
| 681 | return; |
| 682 | } |
| 683 | |
| 684 | req_mask = SKL_POWER_WELL_REQ(power_well->data); |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 685 | enable_requested = tmp & req_mask; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 686 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 687 | is_enabled = tmp & state_mask; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 688 | |
Ville Syrjälä | aae8ba8 | 2016-02-19 20:47:30 +0200 | [diff] [blame] | 689 | if (!enable && enable_requested) |
| 690 | skl_power_well_pre_disable(dev_priv, power_well); |
| 691 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 692 | if (enable) { |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 693 | if (!enable_requested) { |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 694 | WARN((tmp & state_mask) && |
| 695 | !I915_READ(HSW_PWR_WELL_BIOS), |
| 696 | "Invalid for power well status to be enabled, unless done by the BIOS, \ |
| 697 | when request is to disable!\n"); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 698 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 699 | } |
| 700 | |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 701 | if (!is_enabled) { |
Damien Lespiau | 510e6fd | 2015-03-06 18:50:50 +0000 | [diff] [blame] | 702 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 703 | check_fuse_status = true; |
| 704 | } |
| 705 | } else { |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 706 | if (enable_requested) { |
Imre Deak | 4a76f29 | 2015-11-04 19:24:15 +0200 | [diff] [blame] | 707 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
| 708 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
| 709 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 710 | } |
Imre Deak | c6782b7 | 2016-04-05 13:26:05 +0300 | [diff] [blame] | 711 | |
| 712 | if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) |
| 713 | gen9_sanitize_power_well_requests(dev_priv, power_well); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 714 | } |
| 715 | |
Imre Deak | 1d963af | 2016-04-01 16:02:36 +0300 | [diff] [blame] | 716 | if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable, |
| 717 | 1)) |
| 718 | DRM_ERROR("%s %s timeout\n", |
| 719 | power_well->name, enable ? "enable" : "disable"); |
| 720 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 721 | if (check_fuse_status) { |
| 722 | if (power_well->data == SKL_DISP_PW_1) { |
| 723 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
| 724 | SKL_FUSE_PG1_DIST_STATUS), 1)) |
| 725 | DRM_ERROR("PG1 distributing status timeout\n"); |
| 726 | } else if (power_well->data == SKL_DISP_PW_2) { |
| 727 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
| 728 | SKL_FUSE_PG2_DIST_STATUS), 1)) |
| 729 | DRM_ERROR("PG2 distributing status timeout\n"); |
| 730 | } |
| 731 | } |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 732 | |
| 733 | if (enable && !is_enabled) |
| 734 | skl_power_well_post_enable(dev_priv, power_well); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 735 | } |
| 736 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 737 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 738 | struct i915_power_well *power_well) |
| 739 | { |
| 740 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 741 | |
| 742 | /* |
| 743 | * We're taking over the BIOS, so clear any requests made by it since |
| 744 | * the driver is in charge now. |
| 745 | */ |
| 746 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) |
| 747 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 748 | } |
| 749 | |
| 750 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, |
| 751 | struct i915_power_well *power_well) |
| 752 | { |
| 753 | hsw_set_power_well(dev_priv, power_well, true); |
| 754 | } |
| 755 | |
| 756 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, |
| 757 | struct i915_power_well *power_well) |
| 758 | { |
| 759 | hsw_set_power_well(dev_priv, power_well, false); |
| 760 | } |
| 761 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 762 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
| 763 | struct i915_power_well *power_well) |
| 764 | { |
| 765 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | |
| 766 | SKL_POWER_WELL_STATE(power_well->data); |
| 767 | |
| 768 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; |
| 769 | } |
| 770 | |
| 771 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 772 | struct i915_power_well *power_well) |
| 773 | { |
| 774 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 775 | |
| 776 | /* Clear any request made by BIOS as driver is taking over */ |
| 777 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 778 | } |
| 779 | |
| 780 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, |
| 781 | struct i915_power_well *power_well) |
| 782 | { |
| 783 | skl_set_power_well(dev_priv, power_well, true); |
| 784 | } |
| 785 | |
| 786 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, |
| 787 | struct i915_power_well *power_well) |
| 788 | { |
| 789 | skl_set_power_well(dev_priv, power_well, false); |
| 790 | } |
| 791 | |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 792 | static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, |
| 793 | struct i915_power_well *power_well) |
| 794 | { |
| 795 | return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; |
| 796 | } |
| 797 | |
| 798 | static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, |
| 799 | struct i915_power_well *power_well) |
| 800 | { |
Imre Deak | 5b773eb | 2016-02-29 22:49:05 +0200 | [diff] [blame] | 801 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 802 | } |
| 803 | |
| 804 | static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, |
| 805 | struct i915_power_well *power_well) |
| 806 | { |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 807 | if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 808 | skl_enable_dc6(dev_priv); |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 809 | else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 810 | gen9_enable_dc5(dev_priv); |
| 811 | } |
| 812 | |
| 813 | static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 814 | struct i915_power_well *power_well) |
| 815 | { |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 816 | if (power_well->count > 0) |
| 817 | gen9_dc_off_power_well_enable(dev_priv, power_well); |
| 818 | else |
| 819 | gen9_dc_off_power_well_disable(dev_priv, power_well); |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 820 | } |
| 821 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 822 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
| 823 | struct i915_power_well *power_well) |
| 824 | { |
| 825 | } |
| 826 | |
| 827 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, |
| 828 | struct i915_power_well *power_well) |
| 829 | { |
| 830 | return true; |
| 831 | } |
| 832 | |
| 833 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
| 834 | struct i915_power_well *power_well, bool enable) |
| 835 | { |
| 836 | enum punit_power_well power_well_id = power_well->data; |
| 837 | u32 mask; |
| 838 | u32 state; |
| 839 | u32 ctrl; |
| 840 | |
| 841 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 842 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : |
| 843 | PUNIT_PWRGT_PWR_GATE(power_well_id); |
| 844 | |
| 845 | mutex_lock(&dev_priv->rps.hw_lock); |
| 846 | |
| 847 | #define COND \ |
| 848 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) |
| 849 | |
| 850 | if (COND) |
| 851 | goto out; |
| 852 | |
| 853 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); |
| 854 | ctrl &= ~mask; |
| 855 | ctrl |= state; |
| 856 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
| 857 | |
| 858 | if (wait_for(COND, 100)) |
Masanari Iida | 7e35ab8 | 2015-05-10 01:00:23 +0900 | [diff] [blame] | 859 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 860 | state, |
| 861 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
| 862 | |
| 863 | #undef COND |
| 864 | |
| 865 | out: |
| 866 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 867 | } |
| 868 | |
| 869 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 870 | struct i915_power_well *power_well) |
| 871 | { |
| 872 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 873 | } |
| 874 | |
| 875 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, |
| 876 | struct i915_power_well *power_well) |
| 877 | { |
| 878 | vlv_set_power_well(dev_priv, power_well, true); |
| 879 | } |
| 880 | |
| 881 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, |
| 882 | struct i915_power_well *power_well) |
| 883 | { |
| 884 | vlv_set_power_well(dev_priv, power_well, false); |
| 885 | } |
| 886 | |
| 887 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, |
| 888 | struct i915_power_well *power_well) |
| 889 | { |
| 890 | int power_well_id = power_well->data; |
| 891 | bool enabled = false; |
| 892 | u32 mask; |
| 893 | u32 state; |
| 894 | u32 ctrl; |
| 895 | |
| 896 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 897 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); |
| 898 | |
| 899 | mutex_lock(&dev_priv->rps.hw_lock); |
| 900 | |
| 901 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; |
| 902 | /* |
| 903 | * We only ever set the power-on and power-gate states, anything |
| 904 | * else is unexpected. |
| 905 | */ |
| 906 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && |
| 907 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); |
| 908 | if (state == ctrl) |
| 909 | enabled = true; |
| 910 | |
| 911 | /* |
| 912 | * A transient state at this point would mean some unexpected party |
| 913 | * is poking at the power controls too. |
| 914 | */ |
| 915 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; |
| 916 | WARN_ON(ctrl != state); |
| 917 | |
| 918 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 919 | |
| 920 | return enabled; |
| 921 | } |
| 922 | |
Ville Syrjälä | 766078d | 2016-04-11 16:56:30 +0300 | [diff] [blame] | 923 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
| 924 | { |
| 925 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
| 926 | |
| 927 | /* |
| 928 | * Disable trickle feed and enable pnd deadline calculation |
| 929 | */ |
| 930 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
| 931 | I915_WRITE(CBR1_VLV, 0); |
| 932 | } |
| 933 | |
Ville Syrjälä | 2be7d54 | 2015-06-29 15:25:51 +0300 | [diff] [blame] | 934 | static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 935 | { |
Ville Syrjälä | 5a8fbb7 | 2015-06-29 15:25:53 +0300 | [diff] [blame] | 936 | enum pipe pipe; |
| 937 | |
| 938 | /* |
| 939 | * Enable the CRI clock source so we can get at the |
| 940 | * display and the reference clock for VGA |
| 941 | * hotplug / manual detection. Supposedly DSI also |
| 942 | * needs the ref clock up and running. |
| 943 | * |
| 944 | * CHV DPLL B/C have some issues if VGA mode is enabled. |
| 945 | */ |
| 946 | for_each_pipe(dev_priv->dev, pipe) { |
| 947 | u32 val = I915_READ(DPLL(pipe)); |
| 948 | |
| 949 | val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
| 950 | if (pipe != PIPE_A) |
| 951 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 952 | |
| 953 | I915_WRITE(DPLL(pipe), val); |
| 954 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 955 | |
Ville Syrjälä | 766078d | 2016-04-11 16:56:30 +0300 | [diff] [blame] | 956 | vlv_init_display_clock_gating(dev_priv); |
| 957 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 958 | spin_lock_irq(&dev_priv->irq_lock); |
| 959 | valleyview_enable_display_irqs(dev_priv); |
| 960 | spin_unlock_irq(&dev_priv->irq_lock); |
| 961 | |
| 962 | /* |
| 963 | * During driver initialization/resume we can avoid restoring the |
| 964 | * part of the HW/SW state that will be inited anyway explicitly. |
| 965 | */ |
| 966 | if (dev_priv->power_domains.initializing) |
| 967 | return; |
| 968 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 969 | intel_hpd_init(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 970 | |
| 971 | i915_redisable_vga_power_on(dev_priv->dev); |
| 972 | } |
| 973 | |
Ville Syrjälä | 2be7d54 | 2015-06-29 15:25:51 +0300 | [diff] [blame] | 974 | static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) |
| 975 | { |
| 976 | spin_lock_irq(&dev_priv->irq_lock); |
| 977 | valleyview_disable_display_irqs(dev_priv); |
| 978 | spin_unlock_irq(&dev_priv->irq_lock); |
| 979 | |
Ville Syrjälä | 2230fde | 2016-02-19 18:41:52 +0200 | [diff] [blame] | 980 | /* make sure we're done processing display irqs */ |
| 981 | synchronize_irq(dev_priv->dev->irq); |
| 982 | |
Ville Syrjälä | 2be7d54 | 2015-06-29 15:25:51 +0300 | [diff] [blame] | 983 | vlv_power_sequencer_reset(dev_priv); |
| 984 | } |
| 985 | |
| 986 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
| 987 | struct i915_power_well *power_well) |
| 988 | { |
| 989 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 990 | |
| 991 | vlv_set_power_well(dev_priv, power_well, true); |
| 992 | |
| 993 | vlv_display_power_well_init(dev_priv); |
| 994 | } |
| 995 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 996 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
| 997 | struct i915_power_well *power_well) |
| 998 | { |
| 999 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 1000 | |
Ville Syrjälä | 2be7d54 | 2015-06-29 15:25:51 +0300 | [diff] [blame] | 1001 | vlv_display_power_well_deinit(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1002 | |
| 1003 | vlv_set_power_well(dev_priv, power_well, false); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 1007 | struct i915_power_well *power_well) |
| 1008 | { |
| 1009 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 1010 | |
Ville Syrjälä | 5a8fbb7 | 2015-06-29 15:25:53 +0300 | [diff] [blame] | 1011 | /* since ref/cri clock was enabled */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1012 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 1013 | |
| 1014 | vlv_set_power_well(dev_priv, power_well, true); |
| 1015 | |
| 1016 | /* |
| 1017 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
| 1018 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
| 1019 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
| 1020 | * b. The other bits such as sfr settings / modesel may all |
| 1021 | * be set to 0. |
| 1022 | * |
| 1023 | * This should only be done on init and resume from S3 with |
| 1024 | * both PLLs disabled, or we risk losing DPIO and PLL |
| 1025 | * synchronization. |
| 1026 | */ |
| 1027 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
| 1028 | } |
| 1029 | |
| 1030 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 1031 | struct i915_power_well *power_well) |
| 1032 | { |
| 1033 | enum pipe pipe; |
| 1034 | |
| 1035 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 1036 | |
| 1037 | for_each_pipe(dev_priv, pipe) |
| 1038 | assert_pll_disabled(dev_priv, pipe); |
| 1039 | |
| 1040 | /* Assert common reset */ |
| 1041 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); |
| 1042 | |
| 1043 | vlv_set_power_well(dev_priv, power_well, false); |
| 1044 | } |
| 1045 | |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1046 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 1047 | |
| 1048 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
| 1049 | int power_well_id) |
| 1050 | { |
| 1051 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1052 | int i; |
| 1053 | |
Imre Deak | fc17f22 | 2015-11-04 19:24:11 +0200 | [diff] [blame] | 1054 | for (i = 0; i < power_domains->power_well_count; i++) { |
| 1055 | struct i915_power_well *power_well; |
| 1056 | |
| 1057 | power_well = &power_domains->power_wells[i]; |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1058 | if (power_well->data == power_well_id) |
| 1059 | return power_well; |
| 1060 | } |
| 1061 | |
| 1062 | return NULL; |
| 1063 | } |
| 1064 | |
| 1065 | #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) |
| 1066 | |
| 1067 | static void assert_chv_phy_status(struct drm_i915_private *dev_priv) |
| 1068 | { |
| 1069 | struct i915_power_well *cmn_bc = |
| 1070 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 1071 | struct i915_power_well *cmn_d = |
| 1072 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); |
| 1073 | u32 phy_control = dev_priv->chv_phy_control; |
| 1074 | u32 phy_status = 0; |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 1075 | u32 phy_status_mask = 0xffffffff; |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1076 | u32 tmp; |
| 1077 | |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 1078 | /* |
| 1079 | * The BIOS can leave the PHY is some weird state |
| 1080 | * where it doesn't fully power down some parts. |
| 1081 | * Disable the asserts until the PHY has been fully |
| 1082 | * reset (ie. the power well has been disabled at |
| 1083 | * least once). |
| 1084 | */ |
| 1085 | if (!dev_priv->chv_phy_assert[DPIO_PHY0]) |
| 1086 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | |
| 1087 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | |
| 1088 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | |
| 1089 | PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | |
| 1090 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | |
| 1091 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); |
| 1092 | |
| 1093 | if (!dev_priv->chv_phy_assert[DPIO_PHY1]) |
| 1094 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | |
| 1095 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | |
| 1096 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); |
| 1097 | |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1098 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { |
| 1099 | phy_status |= PHY_POWERGOOD(DPIO_PHY0); |
| 1100 | |
| 1101 | /* this assumes override is only used to enable lanes */ |
| 1102 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) |
| 1103 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); |
| 1104 | |
| 1105 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) |
| 1106 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); |
| 1107 | |
| 1108 | /* CL1 is on whenever anything is on in either channel */ |
| 1109 | if (BITS_SET(phy_control, |
| 1110 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | |
| 1111 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) |
| 1112 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); |
| 1113 | |
| 1114 | /* |
| 1115 | * The DPLLB check accounts for the pipe B + port A usage |
| 1116 | * with CL2 powered up but all the lanes in the second channel |
| 1117 | * powered down. |
| 1118 | */ |
| 1119 | if (BITS_SET(phy_control, |
| 1120 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && |
| 1121 | (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) |
| 1122 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); |
| 1123 | |
| 1124 | if (BITS_SET(phy_control, |
| 1125 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) |
| 1126 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); |
| 1127 | if (BITS_SET(phy_control, |
| 1128 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) |
| 1129 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); |
| 1130 | |
| 1131 | if (BITS_SET(phy_control, |
| 1132 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) |
| 1133 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); |
| 1134 | if (BITS_SET(phy_control, |
| 1135 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) |
| 1136 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); |
| 1137 | } |
| 1138 | |
| 1139 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { |
| 1140 | phy_status |= PHY_POWERGOOD(DPIO_PHY1); |
| 1141 | |
| 1142 | /* this assumes override is only used to enable lanes */ |
| 1143 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) |
| 1144 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); |
| 1145 | |
| 1146 | if (BITS_SET(phy_control, |
| 1147 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) |
| 1148 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); |
| 1149 | |
| 1150 | if (BITS_SET(phy_control, |
| 1151 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) |
| 1152 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); |
| 1153 | if (BITS_SET(phy_control, |
| 1154 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) |
| 1155 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); |
| 1156 | } |
| 1157 | |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 1158 | phy_status &= phy_status_mask; |
| 1159 | |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1160 | /* |
| 1161 | * The PHY may be busy with some initial calibration and whatnot, |
| 1162 | * so the power state can take a while to actually change. |
| 1163 | */ |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 1164 | if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1165 | WARN(phy_status != tmp, |
| 1166 | "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", |
| 1167 | tmp, phy_status, dev_priv->chv_phy_control); |
| 1168 | } |
| 1169 | |
| 1170 | #undef BITS_SET |
| 1171 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1172 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 1173 | struct i915_power_well *power_well) |
| 1174 | { |
| 1175 | enum dpio_phy phy; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1176 | enum pipe pipe; |
| 1177 | uint32_t tmp; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1178 | |
| 1179 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 1180 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 1181 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1182 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 1183 | pipe = PIPE_A; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1184 | phy = DPIO_PHY0; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1185 | } else { |
| 1186 | pipe = PIPE_C; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1187 | phy = DPIO_PHY1; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1188 | } |
Ville Syrjälä | 5a8fbb7 | 2015-06-29 15:25:53 +0300 | [diff] [blame] | 1189 | |
| 1190 | /* since ref/cri clock was enabled */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1191 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 1192 | vlv_set_power_well(dev_priv, power_well, true); |
| 1193 | |
| 1194 | /* Poll for phypwrgood signal */ |
| 1195 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) |
| 1196 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
| 1197 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1198 | mutex_lock(&dev_priv->sb_lock); |
| 1199 | |
| 1200 | /* Enable dynamic power down */ |
| 1201 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); |
Ville Syrjälä | ee27921 | 2015-07-08 23:45:57 +0300 | [diff] [blame] | 1202 | tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | |
| 1203 | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1204 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); |
| 1205 | |
| 1206 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 1207 | tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); |
| 1208 | tmp |= DPIO_DYNPWRDOWNEN_CH1; |
| 1209 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); |
Ville Syrjälä | 3e28878 | 2015-07-08 23:45:58 +0300 | [diff] [blame] | 1210 | } else { |
| 1211 | /* |
| 1212 | * Force the non-existing CL2 off. BXT does this |
| 1213 | * too, so maybe it saves some power even though |
| 1214 | * CL2 doesn't exist? |
| 1215 | */ |
| 1216 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
| 1217 | tmp |= DPIO_CL2_LDOFUSE_PWRENB; |
| 1218 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1219 | } |
| 1220 | |
| 1221 | mutex_unlock(&dev_priv->sb_lock); |
| 1222 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 1223 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
| 1224 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1225 | |
| 1226 | DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", |
| 1227 | phy, dev_priv->chv_phy_control); |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1228 | |
| 1229 | assert_chv_phy_status(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1230 | } |
| 1231 | |
| 1232 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 1233 | struct i915_power_well *power_well) |
| 1234 | { |
| 1235 | enum dpio_phy phy; |
| 1236 | |
| 1237 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 1238 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 1239 | |
| 1240 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 1241 | phy = DPIO_PHY0; |
| 1242 | assert_pll_disabled(dev_priv, PIPE_A); |
| 1243 | assert_pll_disabled(dev_priv, PIPE_B); |
| 1244 | } else { |
| 1245 | phy = DPIO_PHY1; |
| 1246 | assert_pll_disabled(dev_priv, PIPE_C); |
| 1247 | } |
| 1248 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 1249 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
| 1250 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1251 | |
| 1252 | vlv_set_power_well(dev_priv, power_well, false); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1253 | |
| 1254 | DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", |
| 1255 | phy, dev_priv->chv_phy_control); |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1256 | |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 1257 | /* PHY is fully reset now, so we can enable the PHY state asserts */ |
| 1258 | dev_priv->chv_phy_assert[phy] = true; |
| 1259 | |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1260 | assert_chv_phy_status(dev_priv); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1261 | } |
| 1262 | |
Ville Syrjälä | 6669e39 | 2015-07-08 23:46:00 +0300 | [diff] [blame] | 1263 | static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
| 1264 | enum dpio_channel ch, bool override, unsigned int mask) |
| 1265 | { |
| 1266 | enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; |
| 1267 | u32 reg, val, expected, actual; |
| 1268 | |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 1269 | /* |
| 1270 | * The BIOS can leave the PHY is some weird state |
| 1271 | * where it doesn't fully power down some parts. |
| 1272 | * Disable the asserts until the PHY has been fully |
| 1273 | * reset (ie. the power well has been disabled at |
| 1274 | * least once). |
| 1275 | */ |
| 1276 | if (!dev_priv->chv_phy_assert[phy]) |
| 1277 | return; |
| 1278 | |
Ville Syrjälä | 6669e39 | 2015-07-08 23:46:00 +0300 | [diff] [blame] | 1279 | if (ch == DPIO_CH0) |
| 1280 | reg = _CHV_CMN_DW0_CH0; |
| 1281 | else |
| 1282 | reg = _CHV_CMN_DW6_CH1; |
| 1283 | |
| 1284 | mutex_lock(&dev_priv->sb_lock); |
| 1285 | val = vlv_dpio_read(dev_priv, pipe, reg); |
| 1286 | mutex_unlock(&dev_priv->sb_lock); |
| 1287 | |
| 1288 | /* |
| 1289 | * This assumes !override is only used when the port is disabled. |
| 1290 | * All lanes should power down even without the override when |
| 1291 | * the port is disabled. |
| 1292 | */ |
| 1293 | if (!override || mask == 0xf) { |
| 1294 | expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; |
| 1295 | /* |
| 1296 | * If CH1 common lane is not active anymore |
| 1297 | * (eg. for pipe B DPLL) the entire channel will |
| 1298 | * shut down, which causes the common lane registers |
| 1299 | * to read as 0. That means we can't actually check |
| 1300 | * the lane power down status bits, but as the entire |
| 1301 | * register reads as 0 it's a good indication that the |
| 1302 | * channel is indeed entirely powered down. |
| 1303 | */ |
| 1304 | if (ch == DPIO_CH1 && val == 0) |
| 1305 | expected = 0; |
| 1306 | } else if (mask != 0x0) { |
| 1307 | expected = DPIO_ANYDL_POWERDOWN; |
| 1308 | } else { |
| 1309 | expected = 0; |
| 1310 | } |
| 1311 | |
| 1312 | if (ch == DPIO_CH0) |
| 1313 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; |
| 1314 | else |
| 1315 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; |
| 1316 | actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; |
| 1317 | |
| 1318 | WARN(actual != expected, |
| 1319 | "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", |
| 1320 | !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), |
| 1321 | !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), |
| 1322 | reg, val); |
| 1323 | } |
| 1324 | |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 1325 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
| 1326 | enum dpio_channel ch, bool override) |
| 1327 | { |
| 1328 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1329 | bool was_override; |
| 1330 | |
| 1331 | mutex_lock(&power_domains->lock); |
| 1332 | |
| 1333 | was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
| 1334 | |
| 1335 | if (override == was_override) |
| 1336 | goto out; |
| 1337 | |
| 1338 | if (override) |
| 1339 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
| 1340 | else |
| 1341 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
| 1342 | |
| 1343 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
| 1344 | |
| 1345 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", |
| 1346 | phy, ch, dev_priv->chv_phy_control); |
| 1347 | |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1348 | assert_chv_phy_status(dev_priv); |
| 1349 | |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 1350 | out: |
| 1351 | mutex_unlock(&power_domains->lock); |
| 1352 | |
| 1353 | return was_override; |
| 1354 | } |
| 1355 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1356 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
| 1357 | bool override, unsigned int mask) |
| 1358 | { |
| 1359 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 1360 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1361 | enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); |
| 1362 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
| 1363 | |
| 1364 | mutex_lock(&power_domains->lock); |
| 1365 | |
| 1366 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); |
| 1367 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); |
| 1368 | |
| 1369 | if (override) |
| 1370 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
| 1371 | else |
| 1372 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); |
| 1373 | |
| 1374 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
| 1375 | |
| 1376 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", |
| 1377 | phy, ch, mask, dev_priv->chv_phy_control); |
| 1378 | |
Ville Syrjälä | 3014227 | 2015-07-08 23:46:01 +0300 | [diff] [blame] | 1379 | assert_chv_phy_status(dev_priv); |
| 1380 | |
Ville Syrjälä | 6669e39 | 2015-07-08 23:46:00 +0300 | [diff] [blame] | 1381 | assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); |
| 1382 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 1383 | mutex_unlock(&power_domains->lock); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1384 | } |
| 1385 | |
| 1386 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, |
| 1387 | struct i915_power_well *power_well) |
| 1388 | { |
| 1389 | enum pipe pipe = power_well->data; |
| 1390 | bool enabled; |
| 1391 | u32 state, ctrl; |
| 1392 | |
| 1393 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1394 | |
| 1395 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); |
| 1396 | /* |
| 1397 | * We only ever set the power-on and power-gate states, anything |
| 1398 | * else is unexpected. |
| 1399 | */ |
| 1400 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); |
| 1401 | enabled = state == DP_SSS_PWR_ON(pipe); |
| 1402 | |
| 1403 | /* |
| 1404 | * A transient state at this point would mean some unexpected party |
| 1405 | * is poking at the power controls too. |
| 1406 | */ |
| 1407 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); |
| 1408 | WARN_ON(ctrl << 16 != state); |
| 1409 | |
| 1410 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1411 | |
| 1412 | return enabled; |
| 1413 | } |
| 1414 | |
| 1415 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, |
| 1416 | struct i915_power_well *power_well, |
| 1417 | bool enable) |
| 1418 | { |
| 1419 | enum pipe pipe = power_well->data; |
| 1420 | u32 state; |
| 1421 | u32 ctrl; |
| 1422 | |
| 1423 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); |
| 1424 | |
| 1425 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1426 | |
| 1427 | #define COND \ |
| 1428 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) |
| 1429 | |
| 1430 | if (COND) |
| 1431 | goto out; |
| 1432 | |
| 1433 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 1434 | ctrl &= ~DP_SSC_MASK(pipe); |
| 1435 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); |
| 1436 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); |
| 1437 | |
| 1438 | if (wait_for(COND, 100)) |
Masanari Iida | 7e35ab8 | 2015-05-10 01:00:23 +0900 | [diff] [blame] | 1439 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1440 | state, |
| 1441 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); |
| 1442 | |
| 1443 | #undef COND |
| 1444 | |
| 1445 | out: |
| 1446 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1447 | } |
| 1448 | |
| 1449 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 1450 | struct i915_power_well *power_well) |
| 1451 | { |
Ville Syrjälä | 8fcd5cd | 2015-06-29 15:25:50 +0300 | [diff] [blame] | 1452 | WARN_ON_ONCE(power_well->data != PIPE_A); |
| 1453 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1454 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
| 1455 | } |
| 1456 | |
| 1457 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, |
| 1458 | struct i915_power_well *power_well) |
| 1459 | { |
Ville Syrjälä | 8fcd5cd | 2015-06-29 15:25:50 +0300 | [diff] [blame] | 1460 | WARN_ON_ONCE(power_well->data != PIPE_A); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1461 | |
| 1462 | chv_set_pipe_power_well(dev_priv, power_well, true); |
Ville Syrjälä | afd6275 | 2014-10-30 19:43:03 +0200 | [diff] [blame] | 1463 | |
Ville Syrjälä | 2be7d54 | 2015-06-29 15:25:51 +0300 | [diff] [blame] | 1464 | vlv_display_power_well_init(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1465 | } |
| 1466 | |
| 1467 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, |
| 1468 | struct i915_power_well *power_well) |
| 1469 | { |
Ville Syrjälä | 8fcd5cd | 2015-06-29 15:25:50 +0300 | [diff] [blame] | 1470 | WARN_ON_ONCE(power_well->data != PIPE_A); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1471 | |
Ville Syrjälä | 2be7d54 | 2015-06-29 15:25:51 +0300 | [diff] [blame] | 1472 | vlv_display_power_well_deinit(dev_priv); |
Ville Syrjälä | afd6275 | 2014-10-30 19:43:03 +0200 | [diff] [blame] | 1473 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1474 | chv_set_pipe_power_well(dev_priv, power_well, false); |
| 1475 | } |
| 1476 | |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 1477 | static void |
| 1478 | __intel_display_power_get_domain(struct drm_i915_private *dev_priv, |
| 1479 | enum intel_display_power_domain domain) |
| 1480 | { |
| 1481 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1482 | struct i915_power_well *power_well; |
| 1483 | int i; |
| 1484 | |
| 1485 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
| 1486 | if (!power_well->count++) |
| 1487 | intel_power_well_enable(dev_priv, power_well); |
| 1488 | } |
| 1489 | |
| 1490 | power_domains->domain_use_count[domain]++; |
| 1491 | } |
| 1492 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1493 | /** |
| 1494 | * intel_display_power_get - grab a power domain reference |
| 1495 | * @dev_priv: i915 device instance |
| 1496 | * @domain: power domain to reference |
| 1497 | * |
| 1498 | * This function grabs a power domain reference for @domain and ensures that the |
| 1499 | * power domain and all its parents are powered up. Therefore users should only |
| 1500 | * grab a reference to the innermost power domain they need. |
| 1501 | * |
| 1502 | * Any power domain reference obtained by this function must have a symmetric |
| 1503 | * call to intel_display_power_put() to release the reference again. |
| 1504 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1505 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
| 1506 | enum intel_display_power_domain domain) |
| 1507 | { |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 1508 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1509 | |
| 1510 | intel_runtime_pm_get(dev_priv); |
| 1511 | |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 1512 | mutex_lock(&power_domains->lock); |
| 1513 | |
| 1514 | __intel_display_power_get_domain(dev_priv, domain); |
| 1515 | |
| 1516 | mutex_unlock(&power_domains->lock); |
| 1517 | } |
| 1518 | |
| 1519 | /** |
| 1520 | * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain |
| 1521 | * @dev_priv: i915 device instance |
| 1522 | * @domain: power domain to reference |
| 1523 | * |
| 1524 | * This function grabs a power domain reference for @domain and ensures that the |
| 1525 | * power domain and all its parents are powered up. Therefore users should only |
| 1526 | * grab a reference to the innermost power domain they need. |
| 1527 | * |
| 1528 | * Any power domain reference obtained by this function must have a symmetric |
| 1529 | * call to intel_display_power_put() to release the reference again. |
| 1530 | */ |
| 1531 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
| 1532 | enum intel_display_power_domain domain) |
| 1533 | { |
| 1534 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1535 | bool is_enabled; |
| 1536 | |
| 1537 | if (!intel_runtime_pm_get_if_in_use(dev_priv)) |
| 1538 | return false; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1539 | |
| 1540 | mutex_lock(&power_domains->lock); |
| 1541 | |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 1542 | if (__intel_display_power_is_enabled(dev_priv, domain)) { |
| 1543 | __intel_display_power_get_domain(dev_priv, domain); |
| 1544 | is_enabled = true; |
| 1545 | } else { |
| 1546 | is_enabled = false; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1547 | } |
| 1548 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1549 | mutex_unlock(&power_domains->lock); |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 1550 | |
| 1551 | if (!is_enabled) |
| 1552 | intel_runtime_pm_put(dev_priv); |
| 1553 | |
| 1554 | return is_enabled; |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1555 | } |
| 1556 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1557 | /** |
| 1558 | * intel_display_power_put - release a power domain reference |
| 1559 | * @dev_priv: i915 device instance |
| 1560 | * @domain: power domain to reference |
| 1561 | * |
| 1562 | * This function drops the power domain reference obtained by |
| 1563 | * intel_display_power_get() and might power down the corresponding hardware |
| 1564 | * block right away if this is the last reference. |
| 1565 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1566 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
| 1567 | enum intel_display_power_domain domain) |
| 1568 | { |
| 1569 | struct i915_power_domains *power_domains; |
| 1570 | struct i915_power_well *power_well; |
| 1571 | int i; |
| 1572 | |
| 1573 | power_domains = &dev_priv->power_domains; |
| 1574 | |
| 1575 | mutex_lock(&power_domains->lock); |
| 1576 | |
Daniel Stone | 11c86db | 2015-11-20 15:55:34 +0000 | [diff] [blame] | 1577 | WARN(!power_domains->domain_use_count[domain], |
| 1578 | "Use count on domain %s is already zero\n", |
| 1579 | intel_display_power_domain_str(domain)); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1580 | power_domains->domain_use_count[domain]--; |
| 1581 | |
| 1582 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
Daniel Stone | 11c86db | 2015-11-20 15:55:34 +0000 | [diff] [blame] | 1583 | WARN(!power_well->count, |
| 1584 | "Use count on power well %s is already zero", |
| 1585 | power_well->name); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1586 | |
Imre Deak | d314cd4 | 2015-11-17 17:44:23 +0200 | [diff] [blame] | 1587 | if (!--power_well->count) |
Damien Lespiau | dcddab3 | 2015-07-30 18:20:27 -0300 | [diff] [blame] | 1588 | intel_power_well_disable(dev_priv, power_well); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1589 | } |
| 1590 | |
| 1591 | mutex_unlock(&power_domains->lock); |
| 1592 | |
| 1593 | intel_runtime_pm_put(dev_priv); |
| 1594 | } |
| 1595 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1596 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 1597 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 1598 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1599 | BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ |
| 1600 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
| 1601 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
| 1602 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1603 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
| 1604 | BIT(POWER_DOMAIN_PLLS) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1605 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 1606 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 1607 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 1608 | BIT(POWER_DOMAIN_AUX_D) | \ |
Ville Syrjälä | f0ab43e | 2015-11-09 16:48:19 +0100 | [diff] [blame] | 1609 | BIT(POWER_DOMAIN_GMBUS) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1610 | BIT(POWER_DOMAIN_INIT)) |
| 1611 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
| 1612 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 1613 | BIT(POWER_DOMAIN_INIT)) |
| 1614 | |
| 1615 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 1616 | HSW_ALWAYS_ON_POWER_DOMAINS | \ |
| 1617 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
| 1618 | #define BDW_DISPLAY_POWER_DOMAINS ( \ |
| 1619 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 1620 | BIT(POWER_DOMAIN_INIT)) |
| 1621 | |
| 1622 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
| 1623 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK |
| 1624 | |
| 1625 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1626 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
| 1627 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1628 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1629 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 1630 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1631 | BIT(POWER_DOMAIN_INIT)) |
| 1632 | |
| 1633 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1634 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1635 | BIT(POWER_DOMAIN_AUX_B) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1636 | BIT(POWER_DOMAIN_INIT)) |
| 1637 | |
| 1638 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1639 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1640 | BIT(POWER_DOMAIN_AUX_B) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1641 | BIT(POWER_DOMAIN_INIT)) |
| 1642 | |
| 1643 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1644 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1645 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1646 | BIT(POWER_DOMAIN_INIT)) |
| 1647 | |
| 1648 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1649 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1650 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1651 | BIT(POWER_DOMAIN_INIT)) |
| 1652 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1653 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1654 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
| 1655 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1656 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 1657 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1658 | BIT(POWER_DOMAIN_INIT)) |
| 1659 | |
| 1660 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ |
Patrik Jakobsson | 6331a70 | 2015-11-09 16:48:21 +0100 | [diff] [blame] | 1661 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1662 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1663 | BIT(POWER_DOMAIN_INIT)) |
| 1664 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1665 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
| 1666 | .sync_hw = i9xx_always_on_power_well_noop, |
| 1667 | .enable = i9xx_always_on_power_well_noop, |
| 1668 | .disable = i9xx_always_on_power_well_noop, |
| 1669 | .is_enabled = i9xx_always_on_power_well_enabled, |
| 1670 | }; |
| 1671 | |
| 1672 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { |
| 1673 | .sync_hw = chv_pipe_power_well_sync_hw, |
| 1674 | .enable = chv_pipe_power_well_enable, |
| 1675 | .disable = chv_pipe_power_well_disable, |
| 1676 | .is_enabled = chv_pipe_power_well_enabled, |
| 1677 | }; |
| 1678 | |
| 1679 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { |
| 1680 | .sync_hw = vlv_power_well_sync_hw, |
| 1681 | .enable = chv_dpio_cmn_power_well_enable, |
| 1682 | .disable = chv_dpio_cmn_power_well_disable, |
| 1683 | .is_enabled = vlv_power_well_enabled, |
| 1684 | }; |
| 1685 | |
| 1686 | static struct i915_power_well i9xx_always_on_power_well[] = { |
| 1687 | { |
| 1688 | .name = "always-on", |
| 1689 | .always_on = 1, |
| 1690 | .domains = POWER_DOMAIN_MASK, |
| 1691 | .ops = &i9xx_always_on_power_well_ops, |
| 1692 | }, |
| 1693 | }; |
| 1694 | |
| 1695 | static const struct i915_power_well_ops hsw_power_well_ops = { |
| 1696 | .sync_hw = hsw_power_well_sync_hw, |
| 1697 | .enable = hsw_power_well_enable, |
| 1698 | .disable = hsw_power_well_disable, |
| 1699 | .is_enabled = hsw_power_well_enabled, |
| 1700 | }; |
| 1701 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1702 | static const struct i915_power_well_ops skl_power_well_ops = { |
| 1703 | .sync_hw = skl_power_well_sync_hw, |
| 1704 | .enable = skl_power_well_enable, |
| 1705 | .disable = skl_power_well_disable, |
| 1706 | .is_enabled = skl_power_well_enabled, |
| 1707 | }; |
| 1708 | |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 1709 | static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { |
| 1710 | .sync_hw = gen9_dc_off_power_well_sync_hw, |
| 1711 | .enable = gen9_dc_off_power_well_enable, |
| 1712 | .disable = gen9_dc_off_power_well_disable, |
| 1713 | .is_enabled = gen9_dc_off_power_well_enabled, |
| 1714 | }; |
| 1715 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1716 | static struct i915_power_well hsw_power_wells[] = { |
| 1717 | { |
| 1718 | .name = "always-on", |
| 1719 | .always_on = 1, |
| 1720 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, |
| 1721 | .ops = &i9xx_always_on_power_well_ops, |
| 1722 | }, |
| 1723 | { |
| 1724 | .name = "display", |
| 1725 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
| 1726 | .ops = &hsw_power_well_ops, |
| 1727 | }, |
| 1728 | }; |
| 1729 | |
| 1730 | static struct i915_power_well bdw_power_wells[] = { |
| 1731 | { |
| 1732 | .name = "always-on", |
| 1733 | .always_on = 1, |
| 1734 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, |
| 1735 | .ops = &i9xx_always_on_power_well_ops, |
| 1736 | }, |
| 1737 | { |
| 1738 | .name = "display", |
| 1739 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
| 1740 | .ops = &hsw_power_well_ops, |
| 1741 | }, |
| 1742 | }; |
| 1743 | |
| 1744 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
| 1745 | .sync_hw = vlv_power_well_sync_hw, |
| 1746 | .enable = vlv_display_power_well_enable, |
| 1747 | .disable = vlv_display_power_well_disable, |
| 1748 | .is_enabled = vlv_power_well_enabled, |
| 1749 | }; |
| 1750 | |
| 1751 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { |
| 1752 | .sync_hw = vlv_power_well_sync_hw, |
| 1753 | .enable = vlv_dpio_cmn_power_well_enable, |
| 1754 | .disable = vlv_dpio_cmn_power_well_disable, |
| 1755 | .is_enabled = vlv_power_well_enabled, |
| 1756 | }; |
| 1757 | |
| 1758 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
| 1759 | .sync_hw = vlv_power_well_sync_hw, |
| 1760 | .enable = vlv_power_well_enable, |
| 1761 | .disable = vlv_power_well_disable, |
| 1762 | .is_enabled = vlv_power_well_enabled, |
| 1763 | }; |
| 1764 | |
| 1765 | static struct i915_power_well vlv_power_wells[] = { |
| 1766 | { |
| 1767 | .name = "always-on", |
| 1768 | .always_on = 1, |
| 1769 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 1770 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 56fcfd6 | 2015-11-04 19:24:10 +0200 | [diff] [blame] | 1771 | .data = PUNIT_POWER_WELL_ALWAYS_ON, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1772 | }, |
| 1773 | { |
| 1774 | .name = "display", |
| 1775 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 1776 | .data = PUNIT_POWER_WELL_DISP2D, |
| 1777 | .ops = &vlv_display_power_well_ops, |
| 1778 | }, |
| 1779 | { |
| 1780 | .name = "dpio-tx-b-01", |
| 1781 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1782 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1783 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1784 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1785 | .ops = &vlv_dpio_power_well_ops, |
| 1786 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 1787 | }, |
| 1788 | { |
| 1789 | .name = "dpio-tx-b-23", |
| 1790 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1791 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1792 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1793 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1794 | .ops = &vlv_dpio_power_well_ops, |
| 1795 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 1796 | }, |
| 1797 | { |
| 1798 | .name = "dpio-tx-c-01", |
| 1799 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1800 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1801 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1802 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1803 | .ops = &vlv_dpio_power_well_ops, |
| 1804 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 1805 | }, |
| 1806 | { |
| 1807 | .name = "dpio-tx-c-23", |
| 1808 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1809 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1810 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1811 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1812 | .ops = &vlv_dpio_power_well_ops, |
| 1813 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 1814 | }, |
| 1815 | { |
| 1816 | .name = "dpio-common", |
| 1817 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, |
| 1818 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 1819 | .ops = &vlv_dpio_cmn_power_well_ops, |
| 1820 | }, |
| 1821 | }; |
| 1822 | |
| 1823 | static struct i915_power_well chv_power_wells[] = { |
| 1824 | { |
| 1825 | .name = "always-on", |
| 1826 | .always_on = 1, |
| 1827 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 1828 | .ops = &i9xx_always_on_power_well_ops, |
| 1829 | }, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1830 | { |
| 1831 | .name = "display", |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 1832 | /* |
Ville Syrjälä | fde61e4 | 2015-05-26 20:22:39 +0300 | [diff] [blame] | 1833 | * Pipe A power well is the new disp2d well. Pipe B and C |
| 1834 | * power wells don't actually exist. Pipe A power well is |
| 1835 | * required for any pipe to work. |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 1836 | */ |
Ville Syrjälä | fde61e4 | 2015-05-26 20:22:39 +0300 | [diff] [blame] | 1837 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1838 | .data = PIPE_A, |
| 1839 | .ops = &chv_pipe_power_well_ops, |
| 1840 | }, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1841 | { |
| 1842 | .name = "dpio-common-bc", |
Ville Syrjälä | 71849b6 | 2015-04-10 18:21:29 +0300 | [diff] [blame] | 1843 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1844 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 1845 | .ops = &chv_dpio_cmn_power_well_ops, |
| 1846 | }, |
| 1847 | { |
| 1848 | .name = "dpio-common-d", |
Ville Syrjälä | 71849b6 | 2015-04-10 18:21:29 +0300 | [diff] [blame] | 1849 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1850 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
| 1851 | .ops = &chv_dpio_cmn_power_well_ops, |
| 1852 | }, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1853 | }; |
| 1854 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 1855 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
| 1856 | int power_well_id) |
| 1857 | { |
| 1858 | struct i915_power_well *power_well; |
| 1859 | bool ret; |
| 1860 | |
| 1861 | power_well = lookup_power_well(dev_priv, power_well_id); |
| 1862 | ret = power_well->ops->is_enabled(dev_priv, power_well); |
| 1863 | |
| 1864 | return ret; |
| 1865 | } |
| 1866 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1867 | static struct i915_power_well skl_power_wells[] = { |
| 1868 | { |
| 1869 | .name = "always-on", |
| 1870 | .always_on = 1, |
| 1871 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, |
| 1872 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 56fcfd6 | 2015-11-04 19:24:10 +0200 | [diff] [blame] | 1873 | .data = SKL_DISP_PW_ALWAYS_ON, |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1874 | }, |
| 1875 | { |
| 1876 | .name = "power well 1", |
Imre Deak | 4a76f29 | 2015-11-04 19:24:15 +0200 | [diff] [blame] | 1877 | /* Handled by the DMC firmware */ |
| 1878 | .domains = 0, |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1879 | .ops = &skl_power_well_ops, |
| 1880 | .data = SKL_DISP_PW_1, |
| 1881 | }, |
| 1882 | { |
| 1883 | .name = "MISC IO power well", |
Imre Deak | 4a76f29 | 2015-11-04 19:24:15 +0200 | [diff] [blame] | 1884 | /* Handled by the DMC firmware */ |
| 1885 | .domains = 0, |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1886 | .ops = &skl_power_well_ops, |
| 1887 | .data = SKL_DISP_PW_MISC_IO, |
| 1888 | }, |
| 1889 | { |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 1890 | .name = "DC off", |
| 1891 | .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, |
| 1892 | .ops = &gen9_dc_off_power_well_ops, |
| 1893 | .data = SKL_DISP_PW_DC_OFF, |
| 1894 | }, |
| 1895 | { |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1896 | .name = "power well 2", |
| 1897 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, |
| 1898 | .ops = &skl_power_well_ops, |
| 1899 | .data = SKL_DISP_PW_2, |
| 1900 | }, |
| 1901 | { |
| 1902 | .name = "DDI A/E power well", |
| 1903 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, |
| 1904 | .ops = &skl_power_well_ops, |
| 1905 | .data = SKL_DISP_PW_DDI_A_E, |
| 1906 | }, |
| 1907 | { |
| 1908 | .name = "DDI B power well", |
| 1909 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, |
| 1910 | .ops = &skl_power_well_ops, |
| 1911 | .data = SKL_DISP_PW_DDI_B, |
| 1912 | }, |
| 1913 | { |
| 1914 | .name = "DDI C power well", |
| 1915 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, |
| 1916 | .ops = &skl_power_well_ops, |
| 1917 | .data = SKL_DISP_PW_DDI_C, |
| 1918 | }, |
| 1919 | { |
| 1920 | .name = "DDI D power well", |
| 1921 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, |
| 1922 | .ops = &skl_power_well_ops, |
| 1923 | .data = SKL_DISP_PW_DDI_D, |
| 1924 | }, |
| 1925 | }; |
| 1926 | |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 1927 | static struct i915_power_well bxt_power_wells[] = { |
| 1928 | { |
| 1929 | .name = "always-on", |
| 1930 | .always_on = 1, |
| 1931 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, |
| 1932 | .ops = &i9xx_always_on_power_well_ops, |
| 1933 | }, |
| 1934 | { |
| 1935 | .name = "power well 1", |
Imre Deak | d7d7c9e | 2016-04-01 16:02:42 +0300 | [diff] [blame^] | 1936 | .domains = 0, |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 1937 | .ops = &skl_power_well_ops, |
| 1938 | .data = SKL_DISP_PW_1, |
| 1939 | }, |
| 1940 | { |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 1941 | .name = "DC off", |
| 1942 | .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, |
| 1943 | .ops = &gen9_dc_off_power_well_ops, |
| 1944 | .data = SKL_DISP_PW_DC_OFF, |
| 1945 | }, |
| 1946 | { |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 1947 | .name = "power well 2", |
| 1948 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, |
| 1949 | .ops = &skl_power_well_ops, |
| 1950 | .data = SKL_DISP_PW_2, |
Patrik Jakobsson | 9f836f9 | 2015-11-16 16:20:01 +0100 | [diff] [blame] | 1951 | }, |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 1952 | }; |
| 1953 | |
Imre Deak | 1b0e3a0 | 2015-11-05 23:04:11 +0200 | [diff] [blame] | 1954 | static int |
| 1955 | sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, |
| 1956 | int disable_power_well) |
| 1957 | { |
| 1958 | if (disable_power_well >= 0) |
| 1959 | return !!disable_power_well; |
| 1960 | |
Matt Roper | 1802419 | 2015-12-01 09:26:58 -0800 | [diff] [blame] | 1961 | if (IS_BROXTON(dev_priv)) { |
| 1962 | DRM_DEBUG_KMS("Disabling display power well support\n"); |
| 1963 | return 0; |
| 1964 | } |
| 1965 | |
Imre Deak | 1b0e3a0 | 2015-11-05 23:04:11 +0200 | [diff] [blame] | 1966 | return 1; |
| 1967 | } |
| 1968 | |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 1969 | static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, |
| 1970 | int enable_dc) |
| 1971 | { |
| 1972 | uint32_t mask; |
| 1973 | int requested_dc; |
| 1974 | int max_dc; |
| 1975 | |
| 1976 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
| 1977 | max_dc = 2; |
| 1978 | mask = 0; |
| 1979 | } else if (IS_BROXTON(dev_priv)) { |
| 1980 | max_dc = 1; |
| 1981 | /* |
| 1982 | * DC9 has a separate HW flow from the rest of the DC states, |
| 1983 | * not depending on the DMC firmware. It's needed by system |
| 1984 | * suspend/resume, so allow it unconditionally. |
| 1985 | */ |
| 1986 | mask = DC_STATE_EN_DC9; |
| 1987 | } else { |
| 1988 | max_dc = 0; |
| 1989 | mask = 0; |
| 1990 | } |
| 1991 | |
Imre Deak | 66e2c4c | 2016-02-29 22:49:04 +0200 | [diff] [blame] | 1992 | if (!i915.disable_power_well) |
| 1993 | max_dc = 0; |
| 1994 | |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 1995 | if (enable_dc >= 0 && enable_dc <= max_dc) { |
| 1996 | requested_dc = enable_dc; |
| 1997 | } else if (enable_dc == -1) { |
| 1998 | requested_dc = max_dc; |
| 1999 | } else if (enable_dc > max_dc && enable_dc <= 2) { |
| 2000 | DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", |
| 2001 | enable_dc, max_dc); |
| 2002 | requested_dc = max_dc; |
| 2003 | } else { |
| 2004 | DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); |
| 2005 | requested_dc = max_dc; |
| 2006 | } |
| 2007 | |
| 2008 | if (requested_dc > 1) |
| 2009 | mask |= DC_STATE_EN_UPTO_DC6; |
| 2010 | if (requested_dc > 0) |
| 2011 | mask |= DC_STATE_EN_UPTO_DC5; |
| 2012 | |
| 2013 | DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); |
| 2014 | |
| 2015 | return mask; |
| 2016 | } |
| 2017 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2018 | #define set_power_wells(power_domains, __power_wells) ({ \ |
| 2019 | (power_domains)->power_wells = (__power_wells); \ |
| 2020 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ |
| 2021 | }) |
| 2022 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2023 | /** |
| 2024 | * intel_power_domains_init - initializes the power domain structures |
| 2025 | * @dev_priv: i915 device instance |
| 2026 | * |
| 2027 | * Initializes the power domain structures for @dev_priv depending upon the |
| 2028 | * supported platform. |
| 2029 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2030 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
| 2031 | { |
| 2032 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2033 | |
Imre Deak | 1b0e3a0 | 2015-11-05 23:04:11 +0200 | [diff] [blame] | 2034 | i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, |
| 2035 | i915.disable_power_well); |
Imre Deak | a37baf3 | 2016-02-29 22:49:03 +0200 | [diff] [blame] | 2036 | dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, |
| 2037 | i915.enable_dc); |
Imre Deak | 1b0e3a0 | 2015-11-05 23:04:11 +0200 | [diff] [blame] | 2038 | |
Ville Syrjälä | f0ab43e | 2015-11-09 16:48:19 +0100 | [diff] [blame] | 2039 | BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); |
| 2040 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2041 | mutex_init(&power_domains->lock); |
| 2042 | |
| 2043 | /* |
| 2044 | * The enabling order will be from lower to higher indexed wells, |
| 2045 | * the disabling order is reversed. |
| 2046 | */ |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2047 | if (IS_HASWELL(dev_priv)) { |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2048 | set_power_wells(power_domains, hsw_power_wells); |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2049 | } else if (IS_BROADWELL(dev_priv)) { |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2050 | set_power_wells(power_domains, bdw_power_wells); |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2051 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 2052 | set_power_wells(power_domains, skl_power_wells); |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2053 | } else if (IS_BROXTON(dev_priv)) { |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 2054 | set_power_wells(power_domains, bxt_power_wells); |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2055 | } else if (IS_CHERRYVIEW(dev_priv)) { |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2056 | set_power_wells(power_domains, chv_power_wells); |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2057 | } else if (IS_VALLEYVIEW(dev_priv)) { |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2058 | set_power_wells(power_domains, vlv_power_wells); |
| 2059 | } else { |
| 2060 | set_power_wells(power_domains, i9xx_always_on_power_well); |
| 2061 | } |
| 2062 | |
| 2063 | return 0; |
| 2064 | } |
| 2065 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2066 | /** |
| 2067 | * intel_power_domains_fini - finalizes the power domain structures |
| 2068 | * @dev_priv: i915 device instance |
| 2069 | * |
| 2070 | * Finalizes the power domain structures for @dev_priv depending upon the |
| 2071 | * supported platform. This function also disables runtime pm and ensures that |
| 2072 | * the device stays powered up so that the driver can be reloaded. |
| 2073 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 2074 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2075 | { |
Imre Deak | 25b181b | 2015-12-17 13:44:56 +0200 | [diff] [blame] | 2076 | struct device *device = &dev_priv->dev->pdev->dev; |
| 2077 | |
Imre Deak | aabee1b | 2015-12-15 20:10:29 +0200 | [diff] [blame] | 2078 | /* |
| 2079 | * The i915.ko module is still not prepared to be loaded when |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 2080 | * the power well is not enabled, so just enable it in case |
Imre Deak | aabee1b | 2015-12-15 20:10:29 +0200 | [diff] [blame] | 2081 | * we're going to unload/reload. |
| 2082 | * The following also reacquires the RPM reference the core passed |
| 2083 | * to the driver during loading, which is dropped in |
| 2084 | * intel_runtime_pm_enable(). We have to hand back the control of the |
| 2085 | * device to the core with this reference held. |
| 2086 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 2087 | intel_display_set_init_power(dev_priv, true); |
Imre Deak | d314cd4 | 2015-11-17 17:44:23 +0200 | [diff] [blame] | 2088 | |
| 2089 | /* Remove the refcount we took to keep power well support disabled. */ |
| 2090 | if (!i915.disable_power_well) |
| 2091 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
Imre Deak | 25b181b | 2015-12-17 13:44:56 +0200 | [diff] [blame] | 2092 | |
| 2093 | /* |
| 2094 | * Remove the refcount we took in intel_runtime_pm_enable() in case |
| 2095 | * the platform doesn't support runtime PM. |
| 2096 | */ |
| 2097 | if (!HAS_RUNTIME_PM(dev_priv)) |
| 2098 | pm_runtime_put(device); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2099 | } |
| 2100 | |
Imre Deak | 30eade1 | 2015-11-04 19:24:13 +0200 | [diff] [blame] | 2101 | static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2102 | { |
| 2103 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2104 | struct i915_power_well *power_well; |
| 2105 | int i; |
| 2106 | |
| 2107 | mutex_lock(&power_domains->lock); |
| 2108 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
| 2109 | power_well->ops->sync_hw(dev_priv, power_well); |
| 2110 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, |
| 2111 | power_well); |
| 2112 | } |
| 2113 | mutex_unlock(&power_domains->lock); |
| 2114 | } |
| 2115 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2116 | static void skl_display_core_init(struct drm_i915_private *dev_priv, |
Imre Deak | 443a93a | 2016-04-04 15:42:57 +0300 | [diff] [blame] | 2117 | bool resume) |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2118 | { |
| 2119 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Imre Deak | 443a93a | 2016-04-04 15:42:57 +0300 | [diff] [blame] | 2120 | struct i915_power_well *well; |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2121 | uint32_t val; |
| 2122 | |
Imre Deak | d26fa1d | 2015-11-04 19:24:17 +0200 | [diff] [blame] | 2123 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
| 2124 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2125 | /* enable PCH reset handshake */ |
| 2126 | val = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 2127 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); |
| 2128 | |
| 2129 | /* enable PG1 and Misc I/O */ |
| 2130 | mutex_lock(&power_domains->lock); |
Imre Deak | 443a93a | 2016-04-04 15:42:57 +0300 | [diff] [blame] | 2131 | |
| 2132 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); |
| 2133 | intel_power_well_enable(dev_priv, well); |
| 2134 | |
| 2135 | well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); |
| 2136 | intel_power_well_enable(dev_priv, well); |
| 2137 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2138 | mutex_unlock(&power_domains->lock); |
| 2139 | |
| 2140 | if (!resume) |
| 2141 | return; |
| 2142 | |
| 2143 | skl_init_cdclk(dev_priv); |
| 2144 | |
Imre Deak | 2abc525 | 2016-03-04 21:57:41 +0200 | [diff] [blame] | 2145 | if (dev_priv->csr.dmc_payload) |
| 2146 | intel_csr_load_program(dev_priv); |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2147 | } |
| 2148 | |
| 2149 | static void skl_display_core_uninit(struct drm_i915_private *dev_priv) |
| 2150 | { |
| 2151 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Imre Deak | 443a93a | 2016-04-04 15:42:57 +0300 | [diff] [blame] | 2152 | struct i915_power_well *well; |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2153 | |
Imre Deak | d26fa1d | 2015-11-04 19:24:17 +0200 | [diff] [blame] | 2154 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
| 2155 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2156 | skl_uninit_cdclk(dev_priv); |
| 2157 | |
| 2158 | /* The spec doesn't call for removing the reset handshake flag */ |
| 2159 | /* disable PG1 and Misc I/O */ |
Imre Deak | 443a93a | 2016-04-04 15:42:57 +0300 | [diff] [blame] | 2160 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2161 | mutex_lock(&power_domains->lock); |
Imre Deak | 443a93a | 2016-04-04 15:42:57 +0300 | [diff] [blame] | 2162 | |
| 2163 | well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); |
| 2164 | intel_power_well_disable(dev_priv, well); |
| 2165 | |
| 2166 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); |
| 2167 | intel_power_well_disable(dev_priv, well); |
| 2168 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2169 | mutex_unlock(&power_domains->lock); |
| 2170 | } |
| 2171 | |
Imre Deak | d7d7c9e | 2016-04-01 16:02:42 +0300 | [diff] [blame^] | 2172 | void bxt_display_core_init(struct drm_i915_private *dev_priv, |
| 2173 | bool resume) |
| 2174 | { |
| 2175 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2176 | struct i915_power_well *well; |
| 2177 | uint32_t val; |
| 2178 | |
| 2179 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
| 2180 | |
| 2181 | /* |
| 2182 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT |
| 2183 | * or else the reset will hang because there is no PCH to respond. |
| 2184 | * Move the handshake programming to initialization sequence. |
| 2185 | * Previously was left up to BIOS. |
| 2186 | */ |
| 2187 | val = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 2188 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 2189 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); |
| 2190 | |
| 2191 | /* Enable PG1 */ |
| 2192 | mutex_lock(&power_domains->lock); |
| 2193 | |
| 2194 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); |
| 2195 | intel_power_well_enable(dev_priv, well); |
| 2196 | |
| 2197 | mutex_unlock(&power_domains->lock); |
| 2198 | |
| 2199 | broxton_init_cdclk(dev_priv); |
| 2200 | broxton_ddi_phy_init(dev_priv); |
| 2201 | |
| 2202 | if (resume && dev_priv->csr.dmc_payload) |
| 2203 | intel_csr_load_program(dev_priv); |
| 2204 | } |
| 2205 | |
| 2206 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv) |
| 2207 | { |
| 2208 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2209 | struct i915_power_well *well; |
| 2210 | |
| 2211 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
| 2212 | |
| 2213 | broxton_ddi_phy_uninit(dev_priv); |
| 2214 | broxton_uninit_cdclk(dev_priv); |
| 2215 | |
| 2216 | /* The spec doesn't call for removing the reset handshake flag */ |
| 2217 | |
| 2218 | /* Disable PG1 */ |
| 2219 | mutex_lock(&power_domains->lock); |
| 2220 | |
| 2221 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); |
| 2222 | intel_power_well_disable(dev_priv, well); |
| 2223 | |
| 2224 | mutex_unlock(&power_domains->lock); |
| 2225 | } |
| 2226 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2227 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
| 2228 | { |
| 2229 | struct i915_power_well *cmn_bc = |
| 2230 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 2231 | struct i915_power_well *cmn_d = |
| 2232 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); |
| 2233 | |
| 2234 | /* |
| 2235 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a |
| 2236 | * workaround never ever read DISPLAY_PHY_CONTROL, and |
| 2237 | * instead maintain a shadow copy ourselves. Use the actual |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2238 | * power well state and lane status to reconstruct the |
| 2239 | * expected initial value. |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2240 | */ |
| 2241 | dev_priv->chv_phy_control = |
Ville Syrjälä | bc28454 | 2015-05-26 20:22:38 +0300 | [diff] [blame] | 2242 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
| 2243 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2244 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | |
| 2245 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | |
| 2246 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); |
| 2247 | |
| 2248 | /* |
| 2249 | * If all lanes are disabled we leave the override disabled |
| 2250 | * with all power down bits cleared to match the state we |
| 2251 | * would use after disabling the port. Otherwise enable the |
| 2252 | * override and set the lane powerdown bits accding to the |
| 2253 | * current lane status. |
| 2254 | */ |
| 2255 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { |
| 2256 | uint32_t status = I915_READ(DPLL(PIPE_A)); |
| 2257 | unsigned int mask; |
| 2258 | |
| 2259 | mask = status & DPLL_PORTB_READY_MASK; |
| 2260 | if (mask == 0xf) |
| 2261 | mask = 0x0; |
| 2262 | else |
| 2263 | dev_priv->chv_phy_control |= |
| 2264 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); |
| 2265 | |
| 2266 | dev_priv->chv_phy_control |= |
| 2267 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); |
| 2268 | |
| 2269 | mask = (status & DPLL_PORTC_READY_MASK) >> 4; |
| 2270 | if (mask == 0xf) |
| 2271 | mask = 0x0; |
| 2272 | else |
| 2273 | dev_priv->chv_phy_control |= |
| 2274 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); |
| 2275 | |
| 2276 | dev_priv->chv_phy_control |= |
| 2277 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); |
| 2278 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2279 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 2280 | |
| 2281 | dev_priv->chv_phy_assert[DPIO_PHY0] = false; |
| 2282 | } else { |
| 2283 | dev_priv->chv_phy_assert[DPIO_PHY0] = true; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2284 | } |
| 2285 | |
| 2286 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { |
| 2287 | uint32_t status = I915_READ(DPIO_PHY_STATUS); |
| 2288 | unsigned int mask; |
| 2289 | |
| 2290 | mask = status & DPLL_PORTD_READY_MASK; |
| 2291 | |
| 2292 | if (mask == 0xf) |
| 2293 | mask = 0x0; |
| 2294 | else |
| 2295 | dev_priv->chv_phy_control |= |
| 2296 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); |
| 2297 | |
| 2298 | dev_priv->chv_phy_control |= |
| 2299 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); |
| 2300 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2301 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); |
Ville Syrjälä | 3be60de | 2015-09-08 18:05:45 +0300 | [diff] [blame] | 2302 | |
| 2303 | dev_priv->chv_phy_assert[DPIO_PHY1] = false; |
| 2304 | } else { |
| 2305 | dev_priv->chv_phy_assert[DPIO_PHY1] = true; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2306 | } |
| 2307 | |
| 2308 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
| 2309 | |
| 2310 | DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", |
| 2311 | dev_priv->chv_phy_control); |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2312 | } |
| 2313 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2314 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
| 2315 | { |
| 2316 | struct i915_power_well *cmn = |
| 2317 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 2318 | struct i915_power_well *disp2d = |
| 2319 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); |
| 2320 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2321 | /* If the display might be already active skip this */ |
Ville Syrjälä | 5d93a6e | 2014-10-16 20:52:33 +0300 | [diff] [blame] | 2322 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
| 2323 | disp2d->ops->is_enabled(dev_priv, disp2d) && |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2324 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
| 2325 | return; |
| 2326 | |
| 2327 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); |
| 2328 | |
| 2329 | /* cmnlane needs DPLL registers */ |
| 2330 | disp2d->ops->enable(dev_priv, disp2d); |
| 2331 | |
| 2332 | /* |
| 2333 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: |
| 2334 | * Need to assert and de-assert PHY SB reset by gating the |
| 2335 | * common lane power, then un-gating it. |
| 2336 | * Simply ungating isn't enough to reset the PHY enough to get |
| 2337 | * ports and lanes running. |
| 2338 | */ |
| 2339 | cmn->ops->disable(dev_priv, cmn); |
| 2340 | } |
| 2341 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2342 | /** |
| 2343 | * intel_power_domains_init_hw - initialize hardware power domain state |
| 2344 | * @dev_priv: i915 device instance |
| 2345 | * |
| 2346 | * This function initializes the hardware power domain state and enables all |
| 2347 | * power domains using intel_display_set_init_power(). |
| 2348 | */ |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2349 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2350 | { |
| 2351 | struct drm_device *dev = dev_priv->dev; |
| 2352 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2353 | |
| 2354 | power_domains->initializing = true; |
| 2355 | |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2356 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
| 2357 | skl_display_core_init(dev_priv, resume); |
Imre Deak | d7d7c9e | 2016-04-01 16:02:42 +0300 | [diff] [blame^] | 2358 | } else if (IS_BROXTON(dev)) { |
| 2359 | bxt_display_core_init(dev_priv, resume); |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2360 | } else if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 770effb | 2015-07-08 23:45:51 +0300 | [diff] [blame] | 2361 | mutex_lock(&power_domains->lock); |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2362 | chv_phy_control_init(dev_priv); |
Ville Syrjälä | 770effb | 2015-07-08 23:45:51 +0300 | [diff] [blame] | 2363 | mutex_unlock(&power_domains->lock); |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 2364 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2365 | mutex_lock(&power_domains->lock); |
| 2366 | vlv_cmnlane_wa(dev_priv); |
| 2367 | mutex_unlock(&power_domains->lock); |
| 2368 | } |
| 2369 | |
| 2370 | /* For now, we need the power well to be always enabled. */ |
| 2371 | intel_display_set_init_power(dev_priv, true); |
Imre Deak | d314cd4 | 2015-11-17 17:44:23 +0200 | [diff] [blame] | 2372 | /* Disable power support if the user asked so. */ |
| 2373 | if (!i915.disable_power_well) |
| 2374 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
Imre Deak | 30eade1 | 2015-11-04 19:24:13 +0200 | [diff] [blame] | 2375 | intel_power_domains_sync_hw(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2376 | power_domains->initializing = false; |
| 2377 | } |
| 2378 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2379 | /** |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2380 | * intel_power_domains_suspend - suspend power domain state |
| 2381 | * @dev_priv: i915 device instance |
| 2382 | * |
| 2383 | * This function prepares the hardware power domain state before entering |
| 2384 | * system suspend. It must be paired with intel_power_domains_init_hw(). |
| 2385 | */ |
| 2386 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv) |
| 2387 | { |
Imre Deak | d314cd4 | 2015-11-17 17:44:23 +0200 | [diff] [blame] | 2388 | /* |
| 2389 | * Even if power well support was disabled we still want to disable |
| 2390 | * power wells while we are system suspended. |
| 2391 | */ |
| 2392 | if (!i915.disable_power_well) |
| 2393 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
Imre Deak | 2622d79 | 2016-02-29 22:49:02 +0200 | [diff] [blame] | 2394 | |
| 2395 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
| 2396 | skl_display_core_uninit(dev_priv); |
Imre Deak | d7d7c9e | 2016-04-01 16:02:42 +0300 | [diff] [blame^] | 2397 | else if (IS_BROXTON(dev_priv)) |
| 2398 | bxt_display_core_uninit(dev_priv); |
Imre Deak | 73dfc22 | 2015-11-17 17:33:53 +0200 | [diff] [blame] | 2399 | } |
| 2400 | |
| 2401 | /** |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2402 | * intel_runtime_pm_get - grab a runtime pm reference |
| 2403 | * @dev_priv: i915 device instance |
| 2404 | * |
| 2405 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
| 2406 | * code to ensure the GTT or GT is on) and ensures that it is powered up. |
| 2407 | * |
| 2408 | * Any runtime pm reference obtained by this function must have a symmetric |
| 2409 | * call to intel_runtime_pm_put() to release the reference again. |
| 2410 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2411 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
| 2412 | { |
| 2413 | struct drm_device *dev = dev_priv->dev; |
| 2414 | struct device *device = &dev->pdev->dev; |
| 2415 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2416 | pm_runtime_get_sync(device); |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2417 | |
| 2418 | atomic_inc(&dev_priv->pm.wakeref_count); |
Imre Deak | c9b8846 | 2015-12-15 20:10:34 +0200 | [diff] [blame] | 2419 | assert_rpm_wakelock_held(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2420 | } |
| 2421 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2422 | /** |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 2423 | * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use |
| 2424 | * @dev_priv: i915 device instance |
| 2425 | * |
| 2426 | * This function grabs a device-level runtime pm reference if the device is |
| 2427 | * already in use and ensures that it is powered up. |
| 2428 | * |
| 2429 | * Any runtime pm reference obtained by this function must have a symmetric |
| 2430 | * call to intel_runtime_pm_put() to release the reference again. |
| 2431 | */ |
| 2432 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) |
| 2433 | { |
| 2434 | struct drm_device *dev = dev_priv->dev; |
| 2435 | struct device *device = &dev->pdev->dev; |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 2436 | |
Chris Wilson | 135dc79 | 2016-02-25 21:10:28 +0000 | [diff] [blame] | 2437 | if (IS_ENABLED(CONFIG_PM)) { |
| 2438 | int ret = pm_runtime_get_if_in_use(device); |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 2439 | |
Chris Wilson | 135dc79 | 2016-02-25 21:10:28 +0000 | [diff] [blame] | 2440 | /* |
| 2441 | * In cases runtime PM is disabled by the RPM core and we get |
| 2442 | * an -EINVAL return value we are not supposed to call this |
| 2443 | * function, since the power state is undefined. This applies |
| 2444 | * atm to the late/early system suspend/resume handlers. |
| 2445 | */ |
| 2446 | WARN_ON_ONCE(ret < 0); |
| 2447 | if (ret <= 0) |
| 2448 | return false; |
| 2449 | } |
Imre Deak | 0973128 | 2016-02-17 14:17:42 +0200 | [diff] [blame] | 2450 | |
| 2451 | atomic_inc(&dev_priv->pm.wakeref_count); |
| 2452 | assert_rpm_wakelock_held(dev_priv); |
| 2453 | |
| 2454 | return true; |
| 2455 | } |
| 2456 | |
| 2457 | /** |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2458 | * intel_runtime_pm_get_noresume - grab a runtime pm reference |
| 2459 | * @dev_priv: i915 device instance |
| 2460 | * |
| 2461 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
| 2462 | * code to ensure the GTT or GT is on). |
| 2463 | * |
| 2464 | * It will _not_ power up the device but instead only check that it's powered |
| 2465 | * on. Therefore it is only valid to call this functions from contexts where |
| 2466 | * the device is known to be powered up and where trying to power it up would |
| 2467 | * result in hilarity and deadlocks. That pretty much means only the system |
| 2468 | * suspend/resume code where this is used to grab runtime pm references for |
| 2469 | * delayed setup down in work items. |
| 2470 | * |
| 2471 | * Any runtime pm reference obtained by this function must have a symmetric |
| 2472 | * call to intel_runtime_pm_put() to release the reference again. |
| 2473 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2474 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
| 2475 | { |
| 2476 | struct drm_device *dev = dev_priv->dev; |
| 2477 | struct device *device = &dev->pdev->dev; |
| 2478 | |
Imre Deak | c9b8846 | 2015-12-15 20:10:34 +0200 | [diff] [blame] | 2479 | assert_rpm_wakelock_held(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2480 | pm_runtime_get_noresume(device); |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2481 | |
| 2482 | atomic_inc(&dev_priv->pm.wakeref_count); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2483 | } |
| 2484 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2485 | /** |
| 2486 | * intel_runtime_pm_put - release a runtime pm reference |
| 2487 | * @dev_priv: i915 device instance |
| 2488 | * |
| 2489 | * This function drops the device-level runtime pm reference obtained by |
| 2490 | * intel_runtime_pm_get() and might power down the corresponding |
| 2491 | * hardware block right away if this is the last reference. |
| 2492 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2493 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
| 2494 | { |
| 2495 | struct drm_device *dev = dev_priv->dev; |
| 2496 | struct device *device = &dev->pdev->dev; |
| 2497 | |
Imre Deak | 542db3c | 2015-12-15 20:10:36 +0200 | [diff] [blame] | 2498 | assert_rpm_wakelock_held(dev_priv); |
Imre Deak | 2b19efe | 2015-12-15 20:10:37 +0200 | [diff] [blame] | 2499 | if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) |
| 2500 | atomic_inc(&dev_priv->pm.atomic_seq); |
Imre Deak | 1f814da | 2015-12-16 02:52:19 +0200 | [diff] [blame] | 2501 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2502 | pm_runtime_mark_last_busy(device); |
| 2503 | pm_runtime_put_autosuspend(device); |
| 2504 | } |
| 2505 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 2506 | /** |
| 2507 | * intel_runtime_pm_enable - enable runtime pm |
| 2508 | * @dev_priv: i915 device instance |
| 2509 | * |
| 2510 | * This function enables runtime pm at the end of the driver load sequence. |
| 2511 | * |
| 2512 | * Note that this function does currently not enable runtime pm for the |
| 2513 | * subordinate display power domains. That is only done on the first modeset |
| 2514 | * using intel_display_set_init_power(). |
| 2515 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 2516 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2517 | { |
| 2518 | struct drm_device *dev = dev_priv->dev; |
| 2519 | struct device *device = &dev->pdev->dev; |
| 2520 | |
Imre Deak | cbc68dc | 2015-12-17 19:04:33 +0200 | [diff] [blame] | 2521 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
| 2522 | pm_runtime_mark_last_busy(device); |
| 2523 | |
Imre Deak | 25b181b | 2015-12-17 13:44:56 +0200 | [diff] [blame] | 2524 | /* |
| 2525 | * Take a permanent reference to disable the RPM functionality and drop |
| 2526 | * it only when unloading the driver. Use the low level get/put helpers, |
| 2527 | * so the driver's own RPM reference tracking asserts also work on |
| 2528 | * platforms without RPM support. |
| 2529 | */ |
Imre Deak | cbc68dc | 2015-12-17 19:04:33 +0200 | [diff] [blame] | 2530 | if (!HAS_RUNTIME_PM(dev)) { |
| 2531 | pm_runtime_dont_use_autosuspend(device); |
Imre Deak | 25b181b | 2015-12-17 13:44:56 +0200 | [diff] [blame] | 2532 | pm_runtime_get_sync(device); |
Imre Deak | cbc68dc | 2015-12-17 19:04:33 +0200 | [diff] [blame] | 2533 | } else { |
| 2534 | pm_runtime_use_autosuspend(device); |
| 2535 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2536 | |
Imre Deak | aabee1b | 2015-12-15 20:10:29 +0200 | [diff] [blame] | 2537 | /* |
| 2538 | * The core calls the driver load handler with an RPM reference held. |
| 2539 | * We drop that here and will reacquire it during unloading in |
| 2540 | * intel_power_domains_fini(). |
| 2541 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 2542 | pm_runtime_put_autosuspend(device); |
| 2543 | } |
| 2544 | |