Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012-2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * Daniel Vetter <daniel.vetter@ffwll.ch> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/vgaarb.h> |
| 31 | |
| 32 | #include "i915_drv.h" |
| 33 | #include "intel_drv.h" |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 34 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 35 | /** |
| 36 | * DOC: runtime pm |
| 37 | * |
| 38 | * The i915 driver supports dynamic enabling and disabling of entire hardware |
| 39 | * blocks at runtime. This is especially important on the display side where |
| 40 | * software is supposed to control many power gates manually on recent hardware, |
| 41 | * since on the GT side a lot of the power management is done by the hardware. |
| 42 | * But even there some manual control at the device level is required. |
| 43 | * |
| 44 | * Since i915 supports a diverse set of platforms with a unified codebase and |
| 45 | * hardware engineers just love to shuffle functionality around between power |
| 46 | * domains there's a sizeable amount of indirection required. This file provides |
| 47 | * generic functions to the driver for grabbing and releasing references for |
| 48 | * abstract power domains. It then maps those to the actual power wells |
| 49 | * present for a given platform. |
| 50 | */ |
| 51 | |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 52 | #define GEN9_ENABLE_DC5(dev) 0 |
| 53 | #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 54 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 55 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
| 56 | for (i = 0; \ |
| 57 | i < (power_domains)->power_well_count && \ |
| 58 | ((power_well) = &(power_domains)->power_wells[i]); \ |
| 59 | i++) \ |
| 60 | if ((power_well)->domains & (domain_mask)) |
| 61 | |
| 62 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ |
| 63 | for (i = (power_domains)->power_well_count - 1; \ |
| 64 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
| 65 | i--) \ |
| 66 | if ((power_well)->domains & (domain_mask)) |
| 67 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 68 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
| 69 | int power_well_id); |
| 70 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 71 | /* |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 72 | * We should only use the power well if we explicitly asked the hardware to |
| 73 | * enable it, so check if it's enabled and also check if we've requested it to |
| 74 | * be enabled. |
| 75 | */ |
| 76 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
| 77 | struct i915_power_well *power_well) |
| 78 | { |
| 79 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
| 80 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); |
| 81 | } |
| 82 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 83 | /** |
| 84 | * __intel_display_power_is_enabled - unlocked check for a power domain |
| 85 | * @dev_priv: i915 device instance |
| 86 | * @domain: power domain to check |
| 87 | * |
| 88 | * This is the unlocked version of intel_display_power_is_enabled() and should |
| 89 | * only be used from error capture and recovery code where deadlocks are |
| 90 | * possible. |
| 91 | * |
| 92 | * Returns: |
| 93 | * True when the power domain is enabled, false otherwise. |
| 94 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 95 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 96 | enum intel_display_power_domain domain) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 97 | { |
| 98 | struct i915_power_domains *power_domains; |
| 99 | struct i915_power_well *power_well; |
| 100 | bool is_enabled; |
| 101 | int i; |
| 102 | |
| 103 | if (dev_priv->pm.suspended) |
| 104 | return false; |
| 105 | |
| 106 | power_domains = &dev_priv->power_domains; |
| 107 | |
| 108 | is_enabled = true; |
| 109 | |
| 110 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 111 | if (power_well->always_on) |
| 112 | continue; |
| 113 | |
| 114 | if (!power_well->hw_enabled) { |
| 115 | is_enabled = false; |
| 116 | break; |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | return is_enabled; |
| 121 | } |
| 122 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 123 | /** |
Damien Lespiau | f61ccae | 2014-11-25 13:45:41 +0000 | [diff] [blame] | 124 | * intel_display_power_is_enabled - check for a power domain |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 125 | * @dev_priv: i915 device instance |
| 126 | * @domain: power domain to check |
| 127 | * |
| 128 | * This function can be used to check the hw power domain state. It is mostly |
| 129 | * used in hardware state readout functions. Everywhere else code should rely |
| 130 | * upon explicit power domain reference counting to ensure that the hardware |
| 131 | * block is powered up before accessing it. |
| 132 | * |
| 133 | * Callers must hold the relevant modesetting locks to ensure that concurrent |
| 134 | * threads can't disable the power well while the caller tries to read a few |
| 135 | * registers. |
| 136 | * |
| 137 | * Returns: |
| 138 | * True when the power domain is enabled, false otherwise. |
| 139 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 140 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 141 | enum intel_display_power_domain domain) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 142 | { |
| 143 | struct i915_power_domains *power_domains; |
| 144 | bool ret; |
| 145 | |
| 146 | power_domains = &dev_priv->power_domains; |
| 147 | |
| 148 | mutex_lock(&power_domains->lock); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 149 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 150 | mutex_unlock(&power_domains->lock); |
| 151 | |
| 152 | return ret; |
| 153 | } |
| 154 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 155 | /** |
| 156 | * intel_display_set_init_power - set the initial power domain state |
| 157 | * @dev_priv: i915 device instance |
| 158 | * @enable: whether to enable or disable the initial power domain state |
| 159 | * |
| 160 | * For simplicity our driver load/unload and system suspend/resume code assumes |
| 161 | * that all power domains are always enabled. This functions controls the state |
| 162 | * of this little hack. While the initial power domain state is enabled runtime |
| 163 | * pm is effectively disabled. |
| 164 | */ |
Daniel Vetter | d9bc89d9 | 2014-09-30 10:56:40 +0200 | [diff] [blame] | 165 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
| 166 | bool enable) |
| 167 | { |
| 168 | if (dev_priv->power_domains.init_power_on == enable) |
| 169 | return; |
| 170 | |
| 171 | if (enable) |
| 172 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
| 173 | else |
| 174 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
| 175 | |
| 176 | dev_priv->power_domains.init_power_on = enable; |
| 177 | } |
| 178 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 179 | /* |
| 180 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
| 181 | * when not needed anymore. We have 4 registers that can request the power well |
| 182 | * to be enabled, and it will only be disabled if none of the registers is |
| 183 | * requesting it to be enabled. |
| 184 | */ |
| 185 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 186 | { |
| 187 | struct drm_device *dev = dev_priv->dev; |
| 188 | |
| 189 | /* |
| 190 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 191 | * we'll get unclaimed register interrupts. This stops after we write |
| 192 | * anything to the VGA MSR register. The vgacon module uses this |
| 193 | * register all the time, so if we unbind our driver and, as a |
| 194 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 195 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 196 | * sure vgacon can keep working normally without triggering interrupts |
| 197 | * and error messages. |
| 198 | */ |
| 199 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 200 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 201 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 202 | |
Damien Lespiau | 2540039 | 2015-03-06 18:50:52 +0000 | [diff] [blame] | 203 | if (IS_BROADWELL(dev)) |
Damien Lespiau | 4c6c03b | 2015-03-06 18:50:48 +0000 | [diff] [blame] | 204 | gen8_irq_power_well_post_enable(dev_priv, |
| 205 | 1 << PIPE_C | 1 << PIPE_B); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 206 | } |
| 207 | |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 208 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
| 209 | struct i915_power_well *power_well) |
| 210 | { |
| 211 | struct drm_device *dev = dev_priv->dev; |
| 212 | |
| 213 | /* |
| 214 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 215 | * we'll get unclaimed register interrupts. This stops after we write |
| 216 | * anything to the VGA MSR register. The vgacon module uses this |
| 217 | * register all the time, so if we unbind our driver and, as a |
| 218 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 219 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 220 | * sure vgacon can keep working normally without triggering interrupts |
| 221 | * and error messages. |
| 222 | */ |
| 223 | if (power_well->data == SKL_DISP_PW_2) { |
| 224 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 225 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 226 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 227 | |
| 228 | gen8_irq_power_well_post_enable(dev_priv, |
| 229 | 1 << PIPE_C | 1 << PIPE_B); |
| 230 | } |
| 231 | |
Damien Lespiau | 1d2b952 | 2015-03-06 18:50:53 +0000 | [diff] [blame] | 232 | if (power_well->data == SKL_DISP_PW_1) { |
| 233 | intel_prepare_ddi(dev); |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 234 | gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); |
Damien Lespiau | 1d2b952 | 2015-03-06 18:50:53 +0000 | [diff] [blame] | 235 | } |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 236 | } |
| 237 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 238 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
| 239 | struct i915_power_well *power_well, bool enable) |
| 240 | { |
| 241 | bool is_enabled, enable_requested; |
| 242 | uint32_t tmp; |
| 243 | |
| 244 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
| 245 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
| 246 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; |
| 247 | |
| 248 | if (enable) { |
| 249 | if (!enable_requested) |
| 250 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
| 251 | HSW_PWR_WELL_ENABLE_REQUEST); |
| 252 | |
| 253 | if (!is_enabled) { |
| 254 | DRM_DEBUG_KMS("Enabling power well\n"); |
| 255 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
| 256 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
| 257 | DRM_ERROR("Timeout enabling power well\n"); |
Paulo Zanoni | 6d729bf | 2014-10-07 16:11:11 -0300 | [diff] [blame] | 258 | hsw_power_well_post_enable(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 259 | } |
| 260 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 261 | } else { |
| 262 | if (enable_requested) { |
| 263 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
| 264 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
| 265 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
| 266 | } |
| 267 | } |
| 268 | } |
| 269 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 270 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
| 271 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ |
| 272 | BIT(POWER_DOMAIN_PIPE_B) | \ |
| 273 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ |
| 274 | BIT(POWER_DOMAIN_PIPE_C) | \ |
| 275 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ |
| 276 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ |
| 277 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ |
| 278 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 279 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 280 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 281 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 282 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 283 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 284 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 285 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 286 | BIT(POWER_DOMAIN_AUX_D) | \ |
| 287 | BIT(POWER_DOMAIN_AUDIO) | \ |
| 288 | BIT(POWER_DOMAIN_VGA) | \ |
| 289 | BIT(POWER_DOMAIN_INIT)) |
| 290 | #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ |
| 291 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
| 292 | BIT(POWER_DOMAIN_PLLS) | \ |
| 293 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 294 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
| 295 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ |
| 296 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 297 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 298 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 299 | BIT(POWER_DOMAIN_INIT)) |
| 300 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ |
| 301 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 302 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 303 | BIT(POWER_DOMAIN_INIT)) |
| 304 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ |
| 305 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 306 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 307 | BIT(POWER_DOMAIN_INIT)) |
| 308 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ |
| 309 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 310 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 311 | BIT(POWER_DOMAIN_INIT)) |
| 312 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ |
| 313 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 314 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 315 | BIT(POWER_DOMAIN_INIT)) |
| 316 | #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ |
Damien Lespiau | aeaa212 | 2015-04-30 16:39:16 +0100 | [diff] [blame] | 317 | SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
Damien Lespiau | 6222709 | 2015-04-30 16:39:20 +0100 | [diff] [blame] | 318 | BIT(POWER_DOMAIN_PLLS) | \ |
Damien Lespiau | aeaa212 | 2015-04-30 16:39:16 +0100 | [diff] [blame] | 319 | BIT(POWER_DOMAIN_INIT)) |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 320 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
| 321 | (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
| 322 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
| 323 | SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ |
| 324 | SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ |
| 325 | SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ |
| 326 | SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ |
| 327 | SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ |
| 328 | BIT(POWER_DOMAIN_INIT)) |
| 329 | |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 330 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
| 331 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ |
| 332 | BIT(POWER_DOMAIN_PIPE_B) | \ |
| 333 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ |
| 334 | BIT(POWER_DOMAIN_PIPE_C) | \ |
| 335 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ |
| 336 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ |
| 337 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ |
| 338 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 339 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 340 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 341 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 342 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 343 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 344 | BIT(POWER_DOMAIN_AUDIO) | \ |
| 345 | BIT(POWER_DOMAIN_VGA) | \ |
| 346 | BIT(POWER_DOMAIN_INIT)) |
| 347 | #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ |
| 348 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
| 349 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 350 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
| 351 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ |
| 352 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 353 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 354 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 355 | BIT(POWER_DOMAIN_PLLS) | \ |
| 356 | BIT(POWER_DOMAIN_INIT)) |
| 357 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
| 358 | (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
| 359 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ |
| 360 | BIT(POWER_DOMAIN_INIT)) |
| 361 | |
A.Sunil Kamath | 664326f | 2014-11-24 13:37:44 +0530 | [diff] [blame] | 362 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
| 363 | { |
| 364 | struct drm_device *dev = dev_priv->dev; |
| 365 | |
| 366 | WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); |
| 367 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), |
| 368 | "DC9 already programmed to be enabled.\n"); |
| 369 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, |
| 370 | "DC5 still not disabled to enable DC9.\n"); |
| 371 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); |
| 372 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); |
| 373 | |
| 374 | /* |
| 375 | * TODO: check for the following to verify the conditions to enter DC9 |
| 376 | * state are satisfied: |
| 377 | * 1] Check relevant display engine registers to verify if mode set |
| 378 | * disable sequence was followed. |
| 379 | * 2] Check if display uninitialize sequence is initialized. |
| 380 | */ |
| 381 | } |
| 382 | |
| 383 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) |
| 384 | { |
| 385 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); |
| 386 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), |
| 387 | "DC9 already programmed to be disabled.\n"); |
| 388 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, |
| 389 | "DC5 still not disabled.\n"); |
| 390 | |
| 391 | /* |
| 392 | * TODO: check for the following to verify DC9 state was indeed |
| 393 | * entered before programming to disable it: |
| 394 | * 1] Check relevant display engine registers to verify if mode |
| 395 | * set disable sequence was followed. |
| 396 | * 2] Check if display uninitialize sequence is initialized. |
| 397 | */ |
| 398 | } |
| 399 | |
| 400 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) |
| 401 | { |
| 402 | uint32_t val; |
| 403 | |
| 404 | assert_can_enable_dc9(dev_priv); |
| 405 | |
| 406 | DRM_DEBUG_KMS("Enabling DC9\n"); |
| 407 | |
| 408 | val = I915_READ(DC_STATE_EN); |
| 409 | val |= DC_STATE_EN_DC9; |
| 410 | I915_WRITE(DC_STATE_EN, val); |
| 411 | POSTING_READ(DC_STATE_EN); |
| 412 | } |
| 413 | |
| 414 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) |
| 415 | { |
| 416 | uint32_t val; |
| 417 | |
| 418 | assert_can_disable_dc9(dev_priv); |
| 419 | |
| 420 | DRM_DEBUG_KMS("Disabling DC9\n"); |
| 421 | |
| 422 | val = I915_READ(DC_STATE_EN); |
| 423 | val &= ~DC_STATE_EN_DC9; |
| 424 | I915_WRITE(DC_STATE_EN, val); |
| 425 | POSTING_READ(DC_STATE_EN); |
| 426 | } |
| 427 | |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 428 | static void gen9_set_dc_state_debugmask_memory_up( |
| 429 | struct drm_i915_private *dev_priv) |
| 430 | { |
| 431 | uint32_t val; |
| 432 | |
| 433 | /* The below bit doesn't need to be cleared ever afterwards */ |
| 434 | val = I915_READ(DC_STATE_DEBUG); |
| 435 | if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { |
| 436 | val |= DC_STATE_DEBUG_MASK_MEMORY_UP; |
| 437 | I915_WRITE(DC_STATE_DEBUG, val); |
| 438 | POSTING_READ(DC_STATE_DEBUG); |
| 439 | } |
| 440 | } |
| 441 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 442 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 443 | { |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 444 | struct drm_device *dev = dev_priv->dev; |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 445 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
| 446 | SKL_DISP_PW_2); |
| 447 | |
| 448 | WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); |
| 449 | WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); |
| 450 | WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n"); |
| 451 | |
| 452 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), |
| 453 | "DC5 already programmed to be enabled.\n"); |
| 454 | WARN(dev_priv->pm.suspended, |
| 455 | "DC5 cannot be enabled, if platform is runtime-suspended.\n"); |
| 456 | |
| 457 | assert_csr_loaded(dev_priv); |
| 458 | } |
| 459 | |
| 460 | static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) |
| 461 | { |
| 462 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
| 463 | SKL_DISP_PW_2); |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 464 | /* |
| 465 | * During initialization, the firmware may not be loaded yet. |
| 466 | * We still want to make sure that the DC enabling flag is cleared. |
| 467 | */ |
| 468 | if (dev_priv->power_domains.initializing) |
| 469 | return; |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 470 | |
| 471 | WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); |
| 472 | WARN(dev_priv->pm.suspended, |
| 473 | "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); |
| 474 | } |
| 475 | |
| 476 | static void gen9_enable_dc5(struct drm_i915_private *dev_priv) |
| 477 | { |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 478 | uint32_t val; |
| 479 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 480 | assert_can_enable_dc5(dev_priv); |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 481 | |
| 482 | DRM_DEBUG_KMS("Enabling DC5\n"); |
| 483 | |
| 484 | gen9_set_dc_state_debugmask_memory_up(dev_priv); |
| 485 | |
| 486 | val = I915_READ(DC_STATE_EN); |
| 487 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; |
| 488 | val |= DC_STATE_EN_UPTO_DC5; |
| 489 | I915_WRITE(DC_STATE_EN, val); |
| 490 | POSTING_READ(DC_STATE_EN); |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 491 | } |
| 492 | |
| 493 | static void gen9_disable_dc5(struct drm_i915_private *dev_priv) |
| 494 | { |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 495 | uint32_t val; |
| 496 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 497 | assert_can_disable_dc5(dev_priv); |
A.Sunil Kamath | 6b457d3 | 2015-04-16 14:22:09 +0530 | [diff] [blame] | 498 | |
| 499 | DRM_DEBUG_KMS("Disabling DC5\n"); |
| 500 | |
| 501 | val = I915_READ(DC_STATE_EN); |
| 502 | val &= ~DC_STATE_EN_UPTO_DC5; |
| 503 | I915_WRITE(DC_STATE_EN, val); |
| 504 | POSTING_READ(DC_STATE_EN); |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 505 | } |
| 506 | |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 507 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 508 | { |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 509 | struct drm_device *dev = dev_priv->dev; |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 510 | |
| 511 | WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); |
| 512 | WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); |
| 513 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
| 514 | "Backlight is not disabled.\n"); |
| 515 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), |
| 516 | "DC6 already programmed to be enabled.\n"); |
| 517 | |
| 518 | assert_csr_loaded(dev_priv); |
| 519 | } |
| 520 | |
| 521 | static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) |
| 522 | { |
| 523 | /* |
| 524 | * During initialization, the firmware may not be loaded yet. |
| 525 | * We still want to make sure that the DC enabling flag is cleared. |
| 526 | */ |
| 527 | if (dev_priv->power_domains.initializing) |
| 528 | return; |
| 529 | |
| 530 | assert_csr_loaded(dev_priv); |
| 531 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), |
| 532 | "DC6 already programmed to be disabled.\n"); |
| 533 | } |
| 534 | |
| 535 | static void skl_enable_dc6(struct drm_i915_private *dev_priv) |
| 536 | { |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 537 | uint32_t val; |
| 538 | |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 539 | assert_can_enable_dc6(dev_priv); |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 540 | |
| 541 | DRM_DEBUG_KMS("Enabling DC6\n"); |
| 542 | |
| 543 | gen9_set_dc_state_debugmask_memory_up(dev_priv); |
| 544 | |
| 545 | val = I915_READ(DC_STATE_EN); |
| 546 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; |
| 547 | val |= DC_STATE_EN_UPTO_DC6; |
| 548 | I915_WRITE(DC_STATE_EN, val); |
| 549 | POSTING_READ(DC_STATE_EN); |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | static void skl_disable_dc6(struct drm_i915_private *dev_priv) |
| 553 | { |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 554 | uint32_t val; |
| 555 | |
Suketu Shah | 93c7cb6 | 2015-04-16 14:22:13 +0530 | [diff] [blame] | 556 | assert_can_disable_dc6(dev_priv); |
A.Sunil Kamath | 74b4f37 | 2015-04-16 14:22:12 +0530 | [diff] [blame] | 557 | |
| 558 | DRM_DEBUG_KMS("Disabling DC6\n"); |
| 559 | |
| 560 | val = I915_READ(DC_STATE_EN); |
| 561 | val &= ~DC_STATE_EN_UPTO_DC6; |
| 562 | I915_WRITE(DC_STATE_EN, val); |
| 563 | POSTING_READ(DC_STATE_EN); |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 564 | } |
| 565 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 566 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
| 567 | struct i915_power_well *power_well, bool enable) |
| 568 | { |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 569 | struct drm_device *dev = dev_priv->dev; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 570 | uint32_t tmp, fuse_status; |
| 571 | uint32_t req_mask, state_mask; |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 572 | bool is_enabled, enable_requested, check_fuse_status = false; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 573 | |
| 574 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
| 575 | fuse_status = I915_READ(SKL_FUSE_STATUS); |
| 576 | |
| 577 | switch (power_well->data) { |
| 578 | case SKL_DISP_PW_1: |
| 579 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
| 580 | SKL_FUSE_PG0_DIST_STATUS), 1)) { |
| 581 | DRM_ERROR("PG0 not enabled\n"); |
| 582 | return; |
| 583 | } |
| 584 | break; |
| 585 | case SKL_DISP_PW_2: |
| 586 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { |
| 587 | DRM_ERROR("PG1 in disabled state\n"); |
| 588 | return; |
| 589 | } |
| 590 | break; |
| 591 | case SKL_DISP_PW_DDI_A_E: |
| 592 | case SKL_DISP_PW_DDI_B: |
| 593 | case SKL_DISP_PW_DDI_C: |
| 594 | case SKL_DISP_PW_DDI_D: |
| 595 | case SKL_DISP_PW_MISC_IO: |
| 596 | break; |
| 597 | default: |
| 598 | WARN(1, "Unknown power well %lu\n", power_well->data); |
| 599 | return; |
| 600 | } |
| 601 | |
| 602 | req_mask = SKL_POWER_WELL_REQ(power_well->data); |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 603 | enable_requested = tmp & req_mask; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 604 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 605 | is_enabled = tmp & state_mask; |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 606 | |
| 607 | if (enable) { |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 608 | if (!enable_requested) { |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 609 | WARN((tmp & state_mask) && |
| 610 | !I915_READ(HSW_PWR_WELL_BIOS), |
| 611 | "Invalid for power well status to be enabled, unless done by the BIOS, \ |
| 612 | when request is to disable!\n"); |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 613 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
| 614 | power_well->data == SKL_DISP_PW_2) { |
| 615 | if (SKL_ENABLE_DC6(dev)) { |
| 616 | skl_disable_dc6(dev_priv); |
| 617 | /* |
| 618 | * DDI buffer programming unnecessary during driver-load/resume |
| 619 | * as it's already done during modeset initialization then. |
| 620 | * It's also invalid here as encoder list is still uninitialized. |
| 621 | */ |
| 622 | if (!dev_priv->power_domains.initializing) |
| 623 | intel_prepare_ddi(dev); |
| 624 | } else { |
| 625 | gen9_disable_dc5(dev_priv); |
| 626 | } |
| 627 | } |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 628 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 629 | } |
| 630 | |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 631 | if (!is_enabled) { |
Damien Lespiau | 510e6fd | 2015-03-06 18:50:50 +0000 | [diff] [blame] | 632 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 633 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
| 634 | state_mask), 1)) |
| 635 | DRM_ERROR("%s enable timeout\n", |
| 636 | power_well->name); |
| 637 | check_fuse_status = true; |
| 638 | } |
| 639 | } else { |
Damien Lespiau | 2a51835 | 2015-03-06 18:50:49 +0000 | [diff] [blame] | 640 | if (enable_requested) { |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 641 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
| 642 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
| 643 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 644 | |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 645 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 646 | power_well->data == SKL_DISP_PW_2) { |
| 647 | enum csr_state state; |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 648 | /* TODO: wait for a completion event or |
| 649 | * similar here instead of busy |
| 650 | * waiting using wait_for function. |
| 651 | */ |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 652 | wait_for((state = intel_csr_load_status_get(dev_priv)) != |
| 653 | FW_UNINITIALIZED, 1000); |
| 654 | if (state != FW_LOADED) |
| 655 | DRM_ERROR("CSR firmware not ready (%d)\n", |
| 656 | state); |
| 657 | else |
Suketu Shah | f75a198 | 2015-04-16 14:22:11 +0530 | [diff] [blame] | 658 | if (SKL_ENABLE_DC6(dev)) |
| 659 | skl_enable_dc6(dev_priv); |
| 660 | else |
| 661 | gen9_enable_dc5(dev_priv); |
Suketu Shah | dc17430 | 2015-04-17 19:46:16 +0530 | [diff] [blame] | 662 | } |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 663 | } |
| 664 | } |
| 665 | |
| 666 | if (check_fuse_status) { |
| 667 | if (power_well->data == SKL_DISP_PW_1) { |
| 668 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
| 669 | SKL_FUSE_PG1_DIST_STATUS), 1)) |
| 670 | DRM_ERROR("PG1 distributing status timeout\n"); |
| 671 | } else if (power_well->data == SKL_DISP_PW_2) { |
| 672 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & |
| 673 | SKL_FUSE_PG2_DIST_STATUS), 1)) |
| 674 | DRM_ERROR("PG2 distributing status timeout\n"); |
| 675 | } |
| 676 | } |
Damien Lespiau | d14c034 | 2015-03-06 18:50:51 +0000 | [diff] [blame] | 677 | |
| 678 | if (enable && !is_enabled) |
| 679 | skl_power_well_post_enable(dev_priv, power_well); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 680 | } |
| 681 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 682 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 683 | struct i915_power_well *power_well) |
| 684 | { |
| 685 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 686 | |
| 687 | /* |
| 688 | * We're taking over the BIOS, so clear any requests made by it since |
| 689 | * the driver is in charge now. |
| 690 | */ |
| 691 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) |
| 692 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 693 | } |
| 694 | |
| 695 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, |
| 696 | struct i915_power_well *power_well) |
| 697 | { |
| 698 | hsw_set_power_well(dev_priv, power_well, true); |
| 699 | } |
| 700 | |
| 701 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, |
| 702 | struct i915_power_well *power_well) |
| 703 | { |
| 704 | hsw_set_power_well(dev_priv, power_well, false); |
| 705 | } |
| 706 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 707 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
| 708 | struct i915_power_well *power_well) |
| 709 | { |
| 710 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | |
| 711 | SKL_POWER_WELL_STATE(power_well->data); |
| 712 | |
| 713 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; |
| 714 | } |
| 715 | |
| 716 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 717 | struct i915_power_well *power_well) |
| 718 | { |
| 719 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 720 | |
| 721 | /* Clear any request made by BIOS as driver is taking over */ |
| 722 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 723 | } |
| 724 | |
| 725 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, |
| 726 | struct i915_power_well *power_well) |
| 727 | { |
| 728 | skl_set_power_well(dev_priv, power_well, true); |
| 729 | } |
| 730 | |
| 731 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, |
| 732 | struct i915_power_well *power_well) |
| 733 | { |
| 734 | skl_set_power_well(dev_priv, power_well, false); |
| 735 | } |
| 736 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 737 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
| 738 | struct i915_power_well *power_well) |
| 739 | { |
| 740 | } |
| 741 | |
| 742 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, |
| 743 | struct i915_power_well *power_well) |
| 744 | { |
| 745 | return true; |
| 746 | } |
| 747 | |
| 748 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
| 749 | struct i915_power_well *power_well, bool enable) |
| 750 | { |
| 751 | enum punit_power_well power_well_id = power_well->data; |
| 752 | u32 mask; |
| 753 | u32 state; |
| 754 | u32 ctrl; |
| 755 | |
| 756 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 757 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : |
| 758 | PUNIT_PWRGT_PWR_GATE(power_well_id); |
| 759 | |
| 760 | mutex_lock(&dev_priv->rps.hw_lock); |
| 761 | |
| 762 | #define COND \ |
| 763 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) |
| 764 | |
| 765 | if (COND) |
| 766 | goto out; |
| 767 | |
| 768 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); |
| 769 | ctrl &= ~mask; |
| 770 | ctrl |= state; |
| 771 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
| 772 | |
| 773 | if (wait_for(COND, 100)) |
Masanari Iida | 7e35ab8 | 2015-05-10 01:00:23 +0900 | [diff] [blame] | 774 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 775 | state, |
| 776 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
| 777 | |
| 778 | #undef COND |
| 779 | |
| 780 | out: |
| 781 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 782 | } |
| 783 | |
| 784 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 785 | struct i915_power_well *power_well) |
| 786 | { |
| 787 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 788 | } |
| 789 | |
| 790 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, |
| 791 | struct i915_power_well *power_well) |
| 792 | { |
| 793 | vlv_set_power_well(dev_priv, power_well, true); |
| 794 | } |
| 795 | |
| 796 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, |
| 797 | struct i915_power_well *power_well) |
| 798 | { |
| 799 | vlv_set_power_well(dev_priv, power_well, false); |
| 800 | } |
| 801 | |
| 802 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, |
| 803 | struct i915_power_well *power_well) |
| 804 | { |
| 805 | int power_well_id = power_well->data; |
| 806 | bool enabled = false; |
| 807 | u32 mask; |
| 808 | u32 state; |
| 809 | u32 ctrl; |
| 810 | |
| 811 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 812 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); |
| 813 | |
| 814 | mutex_lock(&dev_priv->rps.hw_lock); |
| 815 | |
| 816 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; |
| 817 | /* |
| 818 | * We only ever set the power-on and power-gate states, anything |
| 819 | * else is unexpected. |
| 820 | */ |
| 821 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && |
| 822 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); |
| 823 | if (state == ctrl) |
| 824 | enabled = true; |
| 825 | |
| 826 | /* |
| 827 | * A transient state at this point would mean some unexpected party |
| 828 | * is poking at the power controls too. |
| 829 | */ |
| 830 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; |
| 831 | WARN_ON(ctrl != state); |
| 832 | |
| 833 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 834 | |
| 835 | return enabled; |
| 836 | } |
| 837 | |
| 838 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
| 839 | struct i915_power_well *power_well) |
| 840 | { |
| 841 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 842 | |
| 843 | vlv_set_power_well(dev_priv, power_well, true); |
| 844 | |
| 845 | spin_lock_irq(&dev_priv->irq_lock); |
| 846 | valleyview_enable_display_irqs(dev_priv); |
| 847 | spin_unlock_irq(&dev_priv->irq_lock); |
| 848 | |
| 849 | /* |
| 850 | * During driver initialization/resume we can avoid restoring the |
| 851 | * part of the HW/SW state that will be inited anyway explicitly. |
| 852 | */ |
| 853 | if (dev_priv->power_domains.initializing) |
| 854 | return; |
| 855 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 856 | intel_hpd_init(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 857 | |
| 858 | i915_redisable_vga_power_on(dev_priv->dev); |
| 859 | } |
| 860 | |
| 861 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
| 862 | struct i915_power_well *power_well) |
| 863 | { |
| 864 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 865 | |
| 866 | spin_lock_irq(&dev_priv->irq_lock); |
| 867 | valleyview_disable_display_irqs(dev_priv); |
| 868 | spin_unlock_irq(&dev_priv->irq_lock); |
| 869 | |
| 870 | vlv_set_power_well(dev_priv, power_well, false); |
| 871 | |
| 872 | vlv_power_sequencer_reset(dev_priv); |
| 873 | } |
| 874 | |
| 875 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 876 | struct i915_power_well *power_well) |
| 877 | { |
| 878 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 879 | |
| 880 | /* |
| 881 | * Enable the CRI clock source so we can get at the |
| 882 | * display and the reference clock for VGA |
| 883 | * hotplug / manual detection. |
| 884 | */ |
| 885 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 886 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 887 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 888 | |
| 889 | vlv_set_power_well(dev_priv, power_well, true); |
| 890 | |
| 891 | /* |
| 892 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
| 893 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
| 894 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
| 895 | * b. The other bits such as sfr settings / modesel may all |
| 896 | * be set to 0. |
| 897 | * |
| 898 | * This should only be done on init and resume from S3 with |
| 899 | * both PLLs disabled, or we risk losing DPIO and PLL |
| 900 | * synchronization. |
| 901 | */ |
| 902 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
| 903 | } |
| 904 | |
| 905 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 906 | struct i915_power_well *power_well) |
| 907 | { |
| 908 | enum pipe pipe; |
| 909 | |
| 910 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 911 | |
| 912 | for_each_pipe(dev_priv, pipe) |
| 913 | assert_pll_disabled(dev_priv, pipe); |
| 914 | |
| 915 | /* Assert common reset */ |
| 916 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); |
| 917 | |
| 918 | vlv_set_power_well(dev_priv, power_well, false); |
| 919 | } |
| 920 | |
| 921 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 922 | struct i915_power_well *power_well) |
| 923 | { |
| 924 | enum dpio_phy phy; |
| 925 | |
| 926 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 927 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 928 | |
| 929 | /* |
| 930 | * Enable the CRI clock source so we can get at the |
| 931 | * display and the reference clock for VGA |
| 932 | * hotplug / manual detection. |
| 933 | */ |
| 934 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 935 | phy = DPIO_PHY0; |
| 936 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 937 | DPLL_REFA_CLK_ENABLE_VLV); |
| 938 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 939 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 940 | } else { |
| 941 | phy = DPIO_PHY1; |
| 942 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | |
| 943 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 944 | } |
| 945 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 946 | vlv_set_power_well(dev_priv, power_well, true); |
| 947 | |
| 948 | /* Poll for phypwrgood signal */ |
| 949 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) |
| 950 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
| 951 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 952 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
| 953 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 957 | struct i915_power_well *power_well) |
| 958 | { |
| 959 | enum dpio_phy phy; |
| 960 | |
| 961 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 962 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 963 | |
| 964 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 965 | phy = DPIO_PHY0; |
| 966 | assert_pll_disabled(dev_priv, PIPE_A); |
| 967 | assert_pll_disabled(dev_priv, PIPE_B); |
| 968 | } else { |
| 969 | phy = DPIO_PHY1; |
| 970 | assert_pll_disabled(dev_priv, PIPE_C); |
| 971 | } |
| 972 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 973 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
| 974 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 975 | |
| 976 | vlv_set_power_well(dev_priv, power_well, false); |
| 977 | } |
| 978 | |
| 979 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, |
| 980 | struct i915_power_well *power_well) |
| 981 | { |
| 982 | enum pipe pipe = power_well->data; |
| 983 | bool enabled; |
| 984 | u32 state, ctrl; |
| 985 | |
| 986 | mutex_lock(&dev_priv->rps.hw_lock); |
| 987 | |
| 988 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); |
| 989 | /* |
| 990 | * We only ever set the power-on and power-gate states, anything |
| 991 | * else is unexpected. |
| 992 | */ |
| 993 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); |
| 994 | enabled = state == DP_SSS_PWR_ON(pipe); |
| 995 | |
| 996 | /* |
| 997 | * A transient state at this point would mean some unexpected party |
| 998 | * is poking at the power controls too. |
| 999 | */ |
| 1000 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); |
| 1001 | WARN_ON(ctrl << 16 != state); |
| 1002 | |
| 1003 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1004 | |
| 1005 | return enabled; |
| 1006 | } |
| 1007 | |
| 1008 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, |
| 1009 | struct i915_power_well *power_well, |
| 1010 | bool enable) |
| 1011 | { |
| 1012 | enum pipe pipe = power_well->data; |
| 1013 | u32 state; |
| 1014 | u32 ctrl; |
| 1015 | |
| 1016 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); |
| 1017 | |
| 1018 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1019 | |
| 1020 | #define COND \ |
| 1021 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) |
| 1022 | |
| 1023 | if (COND) |
| 1024 | goto out; |
| 1025 | |
| 1026 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 1027 | ctrl &= ~DP_SSC_MASK(pipe); |
| 1028 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); |
| 1029 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); |
| 1030 | |
| 1031 | if (wait_for(COND, 100)) |
Masanari Iida | 7e35ab8 | 2015-05-10 01:00:23 +0900 | [diff] [blame] | 1032 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1033 | state, |
| 1034 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); |
| 1035 | |
| 1036 | #undef COND |
| 1037 | |
| 1038 | out: |
| 1039 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1040 | } |
| 1041 | |
| 1042 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 1043 | struct i915_power_well *power_well) |
| 1044 | { |
| 1045 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
| 1046 | } |
| 1047 | |
| 1048 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, |
| 1049 | struct i915_power_well *power_well) |
| 1050 | { |
| 1051 | WARN_ON_ONCE(power_well->data != PIPE_A && |
| 1052 | power_well->data != PIPE_B && |
| 1053 | power_well->data != PIPE_C); |
| 1054 | |
| 1055 | chv_set_pipe_power_well(dev_priv, power_well, true); |
Ville Syrjälä | afd6275 | 2014-10-30 19:43:03 +0200 | [diff] [blame] | 1056 | |
| 1057 | if (power_well->data == PIPE_A) { |
| 1058 | spin_lock_irq(&dev_priv->irq_lock); |
| 1059 | valleyview_enable_display_irqs(dev_priv); |
| 1060 | spin_unlock_irq(&dev_priv->irq_lock); |
| 1061 | |
| 1062 | /* |
| 1063 | * During driver initialization/resume we can avoid restoring the |
| 1064 | * part of the HW/SW state that will be inited anyway explicitly. |
| 1065 | */ |
| 1066 | if (dev_priv->power_domains.initializing) |
| 1067 | return; |
| 1068 | |
| 1069 | intel_hpd_init(dev_priv); |
| 1070 | |
| 1071 | i915_redisable_vga_power_on(dev_priv->dev); |
| 1072 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1073 | } |
| 1074 | |
| 1075 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, |
| 1076 | struct i915_power_well *power_well) |
| 1077 | { |
| 1078 | WARN_ON_ONCE(power_well->data != PIPE_A && |
| 1079 | power_well->data != PIPE_B && |
| 1080 | power_well->data != PIPE_C); |
| 1081 | |
Ville Syrjälä | afd6275 | 2014-10-30 19:43:03 +0200 | [diff] [blame] | 1082 | if (power_well->data == PIPE_A) { |
| 1083 | spin_lock_irq(&dev_priv->irq_lock); |
| 1084 | valleyview_disable_display_irqs(dev_priv); |
| 1085 | spin_unlock_irq(&dev_priv->irq_lock); |
| 1086 | } |
| 1087 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1088 | chv_set_pipe_power_well(dev_priv, power_well, false); |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 1089 | |
| 1090 | if (power_well->data == PIPE_A) |
| 1091 | vlv_power_sequencer_reset(dev_priv); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1092 | } |
| 1093 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1094 | /** |
| 1095 | * intel_display_power_get - grab a power domain reference |
| 1096 | * @dev_priv: i915 device instance |
| 1097 | * @domain: power domain to reference |
| 1098 | * |
| 1099 | * This function grabs a power domain reference for @domain and ensures that the |
| 1100 | * power domain and all its parents are powered up. Therefore users should only |
| 1101 | * grab a reference to the innermost power domain they need. |
| 1102 | * |
| 1103 | * Any power domain reference obtained by this function must have a symmetric |
| 1104 | * call to intel_display_power_put() to release the reference again. |
| 1105 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1106 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
| 1107 | enum intel_display_power_domain domain) |
| 1108 | { |
| 1109 | struct i915_power_domains *power_domains; |
| 1110 | struct i915_power_well *power_well; |
| 1111 | int i; |
| 1112 | |
| 1113 | intel_runtime_pm_get(dev_priv); |
| 1114 | |
| 1115 | power_domains = &dev_priv->power_domains; |
| 1116 | |
| 1117 | mutex_lock(&power_domains->lock); |
| 1118 | |
| 1119 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
| 1120 | if (!power_well->count++) { |
| 1121 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
| 1122 | power_well->ops->enable(dev_priv, power_well); |
| 1123 | power_well->hw_enabled = true; |
| 1124 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1125 | } |
| 1126 | |
| 1127 | power_domains->domain_use_count[domain]++; |
| 1128 | |
| 1129 | mutex_unlock(&power_domains->lock); |
| 1130 | } |
| 1131 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1132 | /** |
| 1133 | * intel_display_power_put - release a power domain reference |
| 1134 | * @dev_priv: i915 device instance |
| 1135 | * @domain: power domain to reference |
| 1136 | * |
| 1137 | * This function drops the power domain reference obtained by |
| 1138 | * intel_display_power_get() and might power down the corresponding hardware |
| 1139 | * block right away if this is the last reference. |
| 1140 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1141 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
| 1142 | enum intel_display_power_domain domain) |
| 1143 | { |
| 1144 | struct i915_power_domains *power_domains; |
| 1145 | struct i915_power_well *power_well; |
| 1146 | int i; |
| 1147 | |
| 1148 | power_domains = &dev_priv->power_domains; |
| 1149 | |
| 1150 | mutex_lock(&power_domains->lock); |
| 1151 | |
| 1152 | WARN_ON(!power_domains->domain_use_count[domain]); |
| 1153 | power_domains->domain_use_count[domain]--; |
| 1154 | |
| 1155 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 1156 | WARN_ON(!power_well->count); |
| 1157 | |
| 1158 | if (!--power_well->count && i915.disable_power_well) { |
| 1159 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
| 1160 | power_well->hw_enabled = false; |
| 1161 | power_well->ops->disable(dev_priv, power_well); |
| 1162 | } |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1163 | } |
| 1164 | |
| 1165 | mutex_unlock(&power_domains->lock); |
| 1166 | |
| 1167 | intel_runtime_pm_put(dev_priv); |
| 1168 | } |
| 1169 | |
| 1170 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 1171 | |
| 1172 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 1173 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 1174 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
| 1175 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 1176 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 1177 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 1178 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 1179 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 1180 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 1181 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 1182 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 1183 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
| 1184 | BIT(POWER_DOMAIN_PLLS) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1185 | BIT(POWER_DOMAIN_AUX_A) | \ |
| 1186 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 1187 | BIT(POWER_DOMAIN_AUX_C) | \ |
| 1188 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1189 | BIT(POWER_DOMAIN_INIT)) |
| 1190 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
| 1191 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 1192 | BIT(POWER_DOMAIN_INIT)) |
| 1193 | |
| 1194 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 1195 | HSW_ALWAYS_ON_POWER_DOMAINS | \ |
| 1196 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
| 1197 | #define BDW_DISPLAY_POWER_DOMAINS ( \ |
| 1198 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 1199 | BIT(POWER_DOMAIN_INIT)) |
| 1200 | |
| 1201 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
| 1202 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK |
| 1203 | |
| 1204 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 1205 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 1206 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 1207 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 1208 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 1209 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1210 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 1211 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1212 | BIT(POWER_DOMAIN_INIT)) |
| 1213 | |
| 1214 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
| 1215 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 1216 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1217 | BIT(POWER_DOMAIN_AUX_B) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1218 | BIT(POWER_DOMAIN_INIT)) |
| 1219 | |
| 1220 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
| 1221 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1222 | BIT(POWER_DOMAIN_AUX_B) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1223 | BIT(POWER_DOMAIN_INIT)) |
| 1224 | |
| 1225 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
| 1226 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 1227 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1228 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1229 | BIT(POWER_DOMAIN_INIT)) |
| 1230 | |
| 1231 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
| 1232 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1233 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1234 | BIT(POWER_DOMAIN_INIT)) |
| 1235 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1236 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 1237 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 1238 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 1239 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 1240 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1241 | BIT(POWER_DOMAIN_AUX_B) | \ |
| 1242 | BIT(POWER_DOMAIN_AUX_C) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1243 | BIT(POWER_DOMAIN_INIT)) |
| 1244 | |
| 1245 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ |
| 1246 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 1247 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame] | 1248 | BIT(POWER_DOMAIN_AUX_D) | \ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1249 | BIT(POWER_DOMAIN_INIT)) |
| 1250 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1251 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
| 1252 | .sync_hw = i9xx_always_on_power_well_noop, |
| 1253 | .enable = i9xx_always_on_power_well_noop, |
| 1254 | .disable = i9xx_always_on_power_well_noop, |
| 1255 | .is_enabled = i9xx_always_on_power_well_enabled, |
| 1256 | }; |
| 1257 | |
| 1258 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { |
| 1259 | .sync_hw = chv_pipe_power_well_sync_hw, |
| 1260 | .enable = chv_pipe_power_well_enable, |
| 1261 | .disable = chv_pipe_power_well_disable, |
| 1262 | .is_enabled = chv_pipe_power_well_enabled, |
| 1263 | }; |
| 1264 | |
| 1265 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { |
| 1266 | .sync_hw = vlv_power_well_sync_hw, |
| 1267 | .enable = chv_dpio_cmn_power_well_enable, |
| 1268 | .disable = chv_dpio_cmn_power_well_disable, |
| 1269 | .is_enabled = vlv_power_well_enabled, |
| 1270 | }; |
| 1271 | |
| 1272 | static struct i915_power_well i9xx_always_on_power_well[] = { |
| 1273 | { |
| 1274 | .name = "always-on", |
| 1275 | .always_on = 1, |
| 1276 | .domains = POWER_DOMAIN_MASK, |
| 1277 | .ops = &i9xx_always_on_power_well_ops, |
| 1278 | }, |
| 1279 | }; |
| 1280 | |
| 1281 | static const struct i915_power_well_ops hsw_power_well_ops = { |
| 1282 | .sync_hw = hsw_power_well_sync_hw, |
| 1283 | .enable = hsw_power_well_enable, |
| 1284 | .disable = hsw_power_well_disable, |
| 1285 | .is_enabled = hsw_power_well_enabled, |
| 1286 | }; |
| 1287 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1288 | static const struct i915_power_well_ops skl_power_well_ops = { |
| 1289 | .sync_hw = skl_power_well_sync_hw, |
| 1290 | .enable = skl_power_well_enable, |
| 1291 | .disable = skl_power_well_disable, |
| 1292 | .is_enabled = skl_power_well_enabled, |
| 1293 | }; |
| 1294 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1295 | static struct i915_power_well hsw_power_wells[] = { |
| 1296 | { |
| 1297 | .name = "always-on", |
| 1298 | .always_on = 1, |
| 1299 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, |
| 1300 | .ops = &i9xx_always_on_power_well_ops, |
| 1301 | }, |
| 1302 | { |
| 1303 | .name = "display", |
| 1304 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
| 1305 | .ops = &hsw_power_well_ops, |
| 1306 | }, |
| 1307 | }; |
| 1308 | |
| 1309 | static struct i915_power_well bdw_power_wells[] = { |
| 1310 | { |
| 1311 | .name = "always-on", |
| 1312 | .always_on = 1, |
| 1313 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, |
| 1314 | .ops = &i9xx_always_on_power_well_ops, |
| 1315 | }, |
| 1316 | { |
| 1317 | .name = "display", |
| 1318 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
| 1319 | .ops = &hsw_power_well_ops, |
| 1320 | }, |
| 1321 | }; |
| 1322 | |
| 1323 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
| 1324 | .sync_hw = vlv_power_well_sync_hw, |
| 1325 | .enable = vlv_display_power_well_enable, |
| 1326 | .disable = vlv_display_power_well_disable, |
| 1327 | .is_enabled = vlv_power_well_enabled, |
| 1328 | }; |
| 1329 | |
| 1330 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { |
| 1331 | .sync_hw = vlv_power_well_sync_hw, |
| 1332 | .enable = vlv_dpio_cmn_power_well_enable, |
| 1333 | .disable = vlv_dpio_cmn_power_well_disable, |
| 1334 | .is_enabled = vlv_power_well_enabled, |
| 1335 | }; |
| 1336 | |
| 1337 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
| 1338 | .sync_hw = vlv_power_well_sync_hw, |
| 1339 | .enable = vlv_power_well_enable, |
| 1340 | .disable = vlv_power_well_disable, |
| 1341 | .is_enabled = vlv_power_well_enabled, |
| 1342 | }; |
| 1343 | |
| 1344 | static struct i915_power_well vlv_power_wells[] = { |
| 1345 | { |
| 1346 | .name = "always-on", |
| 1347 | .always_on = 1, |
| 1348 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 1349 | .ops = &i9xx_always_on_power_well_ops, |
| 1350 | }, |
| 1351 | { |
| 1352 | .name = "display", |
| 1353 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 1354 | .data = PUNIT_POWER_WELL_DISP2D, |
| 1355 | .ops = &vlv_display_power_well_ops, |
| 1356 | }, |
| 1357 | { |
| 1358 | .name = "dpio-tx-b-01", |
| 1359 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1360 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1361 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1362 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1363 | .ops = &vlv_dpio_power_well_ops, |
| 1364 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 1365 | }, |
| 1366 | { |
| 1367 | .name = "dpio-tx-b-23", |
| 1368 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1369 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1370 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1371 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1372 | .ops = &vlv_dpio_power_well_ops, |
| 1373 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 1374 | }, |
| 1375 | { |
| 1376 | .name = "dpio-tx-c-01", |
| 1377 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1378 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1379 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1380 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1381 | .ops = &vlv_dpio_power_well_ops, |
| 1382 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 1383 | }, |
| 1384 | { |
| 1385 | .name = "dpio-tx-c-23", |
| 1386 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 1387 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 1388 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 1389 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 1390 | .ops = &vlv_dpio_power_well_ops, |
| 1391 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 1392 | }, |
| 1393 | { |
| 1394 | .name = "dpio-common", |
| 1395 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, |
| 1396 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 1397 | .ops = &vlv_dpio_cmn_power_well_ops, |
| 1398 | }, |
| 1399 | }; |
| 1400 | |
| 1401 | static struct i915_power_well chv_power_wells[] = { |
| 1402 | { |
| 1403 | .name = "always-on", |
| 1404 | .always_on = 1, |
| 1405 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 1406 | .ops = &i9xx_always_on_power_well_ops, |
| 1407 | }, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1408 | { |
| 1409 | .name = "display", |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 1410 | /* |
Ville Syrjälä | fde61e4 | 2015-05-26 20:22:39 +0300 | [diff] [blame^] | 1411 | * Pipe A power well is the new disp2d well. Pipe B and C |
| 1412 | * power wells don't actually exist. Pipe A power well is |
| 1413 | * required for any pipe to work. |
Ville Syrjälä | baa4e57 | 2014-10-27 16:07:32 +0200 | [diff] [blame] | 1414 | */ |
Ville Syrjälä | fde61e4 | 2015-05-26 20:22:39 +0300 | [diff] [blame^] | 1415 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1416 | .data = PIPE_A, |
| 1417 | .ops = &chv_pipe_power_well_ops, |
| 1418 | }, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1419 | { |
| 1420 | .name = "dpio-common-bc", |
Ville Syrjälä | 71849b6 | 2015-04-10 18:21:29 +0300 | [diff] [blame] | 1421 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1422 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 1423 | .ops = &chv_dpio_cmn_power_well_ops, |
| 1424 | }, |
| 1425 | { |
| 1426 | .name = "dpio-common-d", |
Ville Syrjälä | 71849b6 | 2015-04-10 18:21:29 +0300 | [diff] [blame] | 1427 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1428 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
| 1429 | .ops = &chv_dpio_cmn_power_well_ops, |
| 1430 | }, |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1431 | }; |
| 1432 | |
| 1433 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 1434 | int power_well_id) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1435 | { |
| 1436 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1437 | struct i915_power_well *power_well; |
| 1438 | int i; |
| 1439 | |
| 1440 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
| 1441 | if (power_well->data == power_well_id) |
| 1442 | return power_well; |
| 1443 | } |
| 1444 | |
| 1445 | return NULL; |
| 1446 | } |
| 1447 | |
Suketu Shah | 5aefb23 | 2015-04-16 14:22:10 +0530 | [diff] [blame] | 1448 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
| 1449 | int power_well_id) |
| 1450 | { |
| 1451 | struct i915_power_well *power_well; |
| 1452 | bool ret; |
| 1453 | |
| 1454 | power_well = lookup_power_well(dev_priv, power_well_id); |
| 1455 | ret = power_well->ops->is_enabled(dev_priv, power_well); |
| 1456 | |
| 1457 | return ret; |
| 1458 | } |
| 1459 | |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1460 | static struct i915_power_well skl_power_wells[] = { |
| 1461 | { |
| 1462 | .name = "always-on", |
| 1463 | .always_on = 1, |
| 1464 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, |
| 1465 | .ops = &i9xx_always_on_power_well_ops, |
| 1466 | }, |
| 1467 | { |
| 1468 | .name = "power well 1", |
| 1469 | .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, |
| 1470 | .ops = &skl_power_well_ops, |
| 1471 | .data = SKL_DISP_PW_1, |
| 1472 | }, |
| 1473 | { |
| 1474 | .name = "MISC IO power well", |
| 1475 | .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, |
| 1476 | .ops = &skl_power_well_ops, |
| 1477 | .data = SKL_DISP_PW_MISC_IO, |
| 1478 | }, |
| 1479 | { |
| 1480 | .name = "power well 2", |
| 1481 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, |
| 1482 | .ops = &skl_power_well_ops, |
| 1483 | .data = SKL_DISP_PW_2, |
| 1484 | }, |
| 1485 | { |
| 1486 | .name = "DDI A/E power well", |
| 1487 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, |
| 1488 | .ops = &skl_power_well_ops, |
| 1489 | .data = SKL_DISP_PW_DDI_A_E, |
| 1490 | }, |
| 1491 | { |
| 1492 | .name = "DDI B power well", |
| 1493 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, |
| 1494 | .ops = &skl_power_well_ops, |
| 1495 | .data = SKL_DISP_PW_DDI_B, |
| 1496 | }, |
| 1497 | { |
| 1498 | .name = "DDI C power well", |
| 1499 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, |
| 1500 | .ops = &skl_power_well_ops, |
| 1501 | .data = SKL_DISP_PW_DDI_C, |
| 1502 | }, |
| 1503 | { |
| 1504 | .name = "DDI D power well", |
| 1505 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, |
| 1506 | .ops = &skl_power_well_ops, |
| 1507 | .data = SKL_DISP_PW_DDI_D, |
| 1508 | }, |
| 1509 | }; |
| 1510 | |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 1511 | static struct i915_power_well bxt_power_wells[] = { |
| 1512 | { |
| 1513 | .name = "always-on", |
| 1514 | .always_on = 1, |
| 1515 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, |
| 1516 | .ops = &i9xx_always_on_power_well_ops, |
| 1517 | }, |
| 1518 | { |
| 1519 | .name = "power well 1", |
| 1520 | .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, |
| 1521 | .ops = &skl_power_well_ops, |
| 1522 | .data = SKL_DISP_PW_1, |
| 1523 | }, |
| 1524 | { |
| 1525 | .name = "power well 2", |
| 1526 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, |
| 1527 | .ops = &skl_power_well_ops, |
| 1528 | .data = SKL_DISP_PW_2, |
| 1529 | } |
| 1530 | }; |
| 1531 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1532 | #define set_power_wells(power_domains, __power_wells) ({ \ |
| 1533 | (power_domains)->power_wells = (__power_wells); \ |
| 1534 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ |
| 1535 | }) |
| 1536 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1537 | /** |
| 1538 | * intel_power_domains_init - initializes the power domain structures |
| 1539 | * @dev_priv: i915 device instance |
| 1540 | * |
| 1541 | * Initializes the power domain structures for @dev_priv depending upon the |
| 1542 | * supported platform. |
| 1543 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1544 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
| 1545 | { |
| 1546 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1547 | |
| 1548 | mutex_init(&power_domains->lock); |
| 1549 | |
| 1550 | /* |
| 1551 | * The enabling order will be from lower to higher indexed wells, |
| 1552 | * the disabling order is reversed. |
| 1553 | */ |
| 1554 | if (IS_HASWELL(dev_priv->dev)) { |
| 1555 | set_power_wells(power_domains, hsw_power_wells); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1556 | } else if (IS_BROADWELL(dev_priv->dev)) { |
| 1557 | set_power_wells(power_domains, bdw_power_wells); |
Satheeshakrishna M | 94dd513 | 2015-02-04 13:57:44 +0000 | [diff] [blame] | 1558 | } else if (IS_SKYLAKE(dev_priv->dev)) { |
| 1559 | set_power_wells(power_domains, skl_power_wells); |
Satheeshakrishna M | 0b4a2a3 | 2014-07-11 14:51:13 +0530 | [diff] [blame] | 1560 | } else if (IS_BROXTON(dev_priv->dev)) { |
| 1561 | set_power_wells(power_domains, bxt_power_wells); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1562 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1563 | set_power_wells(power_domains, chv_power_wells); |
| 1564 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 1565 | set_power_wells(power_domains, vlv_power_wells); |
| 1566 | } else { |
| 1567 | set_power_wells(power_domains, i9xx_always_on_power_well); |
| 1568 | } |
| 1569 | |
| 1570 | return 0; |
| 1571 | } |
| 1572 | |
Daniel Vetter | 41373cd | 2014-09-30 10:56:41 +0200 | [diff] [blame] | 1573 | static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) |
| 1574 | { |
| 1575 | struct drm_device *dev = dev_priv->dev; |
| 1576 | struct device *device = &dev->pdev->dev; |
| 1577 | |
| 1578 | if (!HAS_RUNTIME_PM(dev)) |
| 1579 | return; |
| 1580 | |
| 1581 | if (!intel_enable_rc6(dev)) |
| 1582 | return; |
| 1583 | |
| 1584 | /* Make sure we're not suspended first. */ |
| 1585 | pm_runtime_get_sync(device); |
| 1586 | pm_runtime_disable(device); |
| 1587 | } |
| 1588 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1589 | /** |
| 1590 | * intel_power_domains_fini - finalizes the power domain structures |
| 1591 | * @dev_priv: i915 device instance |
| 1592 | * |
| 1593 | * Finalizes the power domain structures for @dev_priv depending upon the |
| 1594 | * supported platform. This function also disables runtime pm and ensures that |
| 1595 | * the device stays powered up so that the driver can be reloaded. |
| 1596 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1597 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1598 | { |
Daniel Vetter | 41373cd | 2014-09-30 10:56:41 +0200 | [diff] [blame] | 1599 | intel_runtime_pm_disable(dev_priv); |
| 1600 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1601 | /* The i915.ko module is still not prepared to be loaded when |
| 1602 | * the power well is not enabled, so just enable it in case |
| 1603 | * we're going to unload/reload. */ |
| 1604 | intel_display_set_init_power(dev_priv, true); |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1605 | } |
| 1606 | |
| 1607 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
| 1608 | { |
| 1609 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1610 | struct i915_power_well *power_well; |
| 1611 | int i; |
| 1612 | |
| 1613 | mutex_lock(&power_domains->lock); |
| 1614 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
| 1615 | power_well->ops->sync_hw(dev_priv, power_well); |
| 1616 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, |
| 1617 | power_well); |
| 1618 | } |
| 1619 | mutex_unlock(&power_domains->lock); |
| 1620 | } |
| 1621 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 1622 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
| 1623 | { |
| 1624 | struct i915_power_well *cmn_bc = |
| 1625 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 1626 | struct i915_power_well *cmn_d = |
| 1627 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); |
| 1628 | |
| 1629 | /* |
| 1630 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a |
| 1631 | * workaround never ever read DISPLAY_PHY_CONTROL, and |
| 1632 | * instead maintain a shadow copy ourselves. Use the actual |
| 1633 | * power well state to reconstruct the expected initial |
| 1634 | * value. |
| 1635 | */ |
| 1636 | dev_priv->chv_phy_control = |
Ville Syrjälä | bc28454 | 2015-05-26 20:22:38 +0300 | [diff] [blame] | 1637 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
| 1638 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 1639 | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | |
| 1640 | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | |
| 1641 | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); |
| 1642 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) |
| 1643 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); |
| 1644 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) |
| 1645 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); |
| 1646 | } |
| 1647 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1648 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
| 1649 | { |
| 1650 | struct i915_power_well *cmn = |
| 1651 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 1652 | struct i915_power_well *disp2d = |
| 1653 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); |
| 1654 | |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1655 | /* If the display might be already active skip this */ |
Ville Syrjälä | 5d93a6e | 2014-10-16 20:52:33 +0300 | [diff] [blame] | 1656 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
| 1657 | disp2d->ops->is_enabled(dev_priv, disp2d) && |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1658 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
| 1659 | return; |
| 1660 | |
| 1661 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); |
| 1662 | |
| 1663 | /* cmnlane needs DPLL registers */ |
| 1664 | disp2d->ops->enable(dev_priv, disp2d); |
| 1665 | |
| 1666 | /* |
| 1667 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: |
| 1668 | * Need to assert and de-assert PHY SB reset by gating the |
| 1669 | * common lane power, then un-gating it. |
| 1670 | * Simply ungating isn't enough to reset the PHY enough to get |
| 1671 | * ports and lanes running. |
| 1672 | */ |
| 1673 | cmn->ops->disable(dev_priv, cmn); |
| 1674 | } |
| 1675 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1676 | /** |
| 1677 | * intel_power_domains_init_hw - initialize hardware power domain state |
| 1678 | * @dev_priv: i915 device instance |
| 1679 | * |
| 1680 | * This function initializes the hardware power domain state and enables all |
| 1681 | * power domains using intel_display_set_init_power(). |
| 1682 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1683 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
| 1684 | { |
| 1685 | struct drm_device *dev = dev_priv->dev; |
| 1686 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 1687 | |
| 1688 | power_domains->initializing = true; |
| 1689 | |
Ville Syrjälä | 7072246 | 2015-04-10 18:21:28 +0300 | [diff] [blame] | 1690 | if (IS_CHERRYVIEW(dev)) { |
| 1691 | chv_phy_control_init(dev_priv); |
| 1692 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1693 | mutex_lock(&power_domains->lock); |
| 1694 | vlv_cmnlane_wa(dev_priv); |
| 1695 | mutex_unlock(&power_domains->lock); |
| 1696 | } |
| 1697 | |
| 1698 | /* For now, we need the power well to be always enabled. */ |
| 1699 | intel_display_set_init_power(dev_priv, true); |
| 1700 | intel_power_domains_resume(dev_priv); |
| 1701 | power_domains->initializing = false; |
| 1702 | } |
| 1703 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1704 | /** |
Geert Uytterhoeven | ca2b140 | 2015-03-09 21:21:08 +0100 | [diff] [blame] | 1705 | * intel_aux_display_runtime_get - grab an auxiliary power domain reference |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1706 | * @dev_priv: i915 device instance |
| 1707 | * |
| 1708 | * This function grabs a power domain reference for the auxiliary power domain |
| 1709 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its |
| 1710 | * parents are powered up. Therefore users should only grab a reference to the |
| 1711 | * innermost power domain they need. |
| 1712 | * |
| 1713 | * Any power domain reference obtained by this function must have a symmetric |
| 1714 | * call to intel_aux_display_runtime_put() to release the reference again. |
| 1715 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1716 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
| 1717 | { |
| 1718 | intel_runtime_pm_get(dev_priv); |
| 1719 | } |
| 1720 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1721 | /** |
Geert Uytterhoeven | ca2b140 | 2015-03-09 21:21:08 +0100 | [diff] [blame] | 1722 | * intel_aux_display_runtime_put - release an auxiliary power domain reference |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1723 | * @dev_priv: i915 device instance |
| 1724 | * |
Geert Uytterhoeven | ca2b140 | 2015-03-09 21:21:08 +0100 | [diff] [blame] | 1725 | * This function drops the auxiliary power domain reference obtained by |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1726 | * intel_aux_display_runtime_get() and might power down the corresponding |
| 1727 | * hardware block right away if this is the last reference. |
| 1728 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1729 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
| 1730 | { |
| 1731 | intel_runtime_pm_put(dev_priv); |
| 1732 | } |
| 1733 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1734 | /** |
| 1735 | * intel_runtime_pm_get - grab a runtime pm reference |
| 1736 | * @dev_priv: i915 device instance |
| 1737 | * |
| 1738 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
| 1739 | * code to ensure the GTT or GT is on) and ensures that it is powered up. |
| 1740 | * |
| 1741 | * Any runtime pm reference obtained by this function must have a symmetric |
| 1742 | * call to intel_runtime_pm_put() to release the reference again. |
| 1743 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1744 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
| 1745 | { |
| 1746 | struct drm_device *dev = dev_priv->dev; |
| 1747 | struct device *device = &dev->pdev->dev; |
| 1748 | |
| 1749 | if (!HAS_RUNTIME_PM(dev)) |
| 1750 | return; |
| 1751 | |
| 1752 | pm_runtime_get_sync(device); |
| 1753 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); |
| 1754 | } |
| 1755 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1756 | /** |
| 1757 | * intel_runtime_pm_get_noresume - grab a runtime pm reference |
| 1758 | * @dev_priv: i915 device instance |
| 1759 | * |
| 1760 | * This function grabs a device-level runtime pm reference (mostly used for GEM |
| 1761 | * code to ensure the GTT or GT is on). |
| 1762 | * |
| 1763 | * It will _not_ power up the device but instead only check that it's powered |
| 1764 | * on. Therefore it is only valid to call this functions from contexts where |
| 1765 | * the device is known to be powered up and where trying to power it up would |
| 1766 | * result in hilarity and deadlocks. That pretty much means only the system |
| 1767 | * suspend/resume code where this is used to grab runtime pm references for |
| 1768 | * delayed setup down in work items. |
| 1769 | * |
| 1770 | * Any runtime pm reference obtained by this function must have a symmetric |
| 1771 | * call to intel_runtime_pm_put() to release the reference again. |
| 1772 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1773 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
| 1774 | { |
| 1775 | struct drm_device *dev = dev_priv->dev; |
| 1776 | struct device *device = &dev->pdev->dev; |
| 1777 | |
| 1778 | if (!HAS_RUNTIME_PM(dev)) |
| 1779 | return; |
| 1780 | |
| 1781 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); |
| 1782 | pm_runtime_get_noresume(device); |
| 1783 | } |
| 1784 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1785 | /** |
| 1786 | * intel_runtime_pm_put - release a runtime pm reference |
| 1787 | * @dev_priv: i915 device instance |
| 1788 | * |
| 1789 | * This function drops the device-level runtime pm reference obtained by |
| 1790 | * intel_runtime_pm_get() and might power down the corresponding |
| 1791 | * hardware block right away if this is the last reference. |
| 1792 | */ |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1793 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
| 1794 | { |
| 1795 | struct drm_device *dev = dev_priv->dev; |
| 1796 | struct device *device = &dev->pdev->dev; |
| 1797 | |
| 1798 | if (!HAS_RUNTIME_PM(dev)) |
| 1799 | return; |
| 1800 | |
| 1801 | pm_runtime_mark_last_busy(device); |
| 1802 | pm_runtime_put_autosuspend(device); |
| 1803 | } |
| 1804 | |
Daniel Vetter | e4e7684 | 2014-09-30 10:56:42 +0200 | [diff] [blame] | 1805 | /** |
| 1806 | * intel_runtime_pm_enable - enable runtime pm |
| 1807 | * @dev_priv: i915 device instance |
| 1808 | * |
| 1809 | * This function enables runtime pm at the end of the driver load sequence. |
| 1810 | * |
| 1811 | * Note that this function does currently not enable runtime pm for the |
| 1812 | * subordinate display power domains. That is only done on the first modeset |
| 1813 | * using intel_display_set_init_power(). |
| 1814 | */ |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1815 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
Daniel Vetter | 9c065a7 | 2014-09-30 10:56:38 +0200 | [diff] [blame] | 1816 | { |
| 1817 | struct drm_device *dev = dev_priv->dev; |
| 1818 | struct device *device = &dev->pdev->dev; |
| 1819 | |
| 1820 | if (!HAS_RUNTIME_PM(dev)) |
| 1821 | return; |
| 1822 | |
| 1823 | pm_runtime_set_active(device); |
| 1824 | |
| 1825 | /* |
| 1826 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
| 1827 | * requirement. |
| 1828 | */ |
| 1829 | if (!intel_enable_rc6(dev)) { |
| 1830 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
| 1831 | return; |
| 1832 | } |
| 1833 | |
| 1834 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
| 1835 | pm_runtime_mark_last_busy(device); |
| 1836 | pm_runtime_use_autosuspend(device); |
| 1837 | |
| 1838 | pm_runtime_put_autosuspend(device); |
| 1839 | } |
| 1840 | |