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Grant Likelyc103de22011-06-04 18:38:28 -06001/*
David Cohena0bbf032014-01-17 07:30:01 -08002 * Intel MID GPIO driver
Grant Likelyc103de22011-06-04 18:38:28 -06003 *
Andy Shevchenko3cabe872016-07-06 12:50:13 +03004 * Copyright (c) 2008-2014,2016 Intel Corporation.
Alek Du8bf02612009-09-22 16:46:36 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Alek Du8bf02612009-09-22 16:46:36 -070014 */
15
16/* Supports:
17 * Moorestown platform Langwell chip.
Alek Du8081c842010-05-26 14:42:25 -070018 * Medfield platform Penwell chip.
David Cohenf89a7682013-10-04 13:01:42 -070019 * Clovertrail platform Cloverview chip.
Alek Du8bf02612009-09-22 16:46:36 -070020 */
21
Andy Shevchenko3cabe872016-07-06 12:50:13 +030022#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/gpio/driver.h>
27#include <linux/kernel.h>
Alek Du8bf02612009-09-22 16:46:36 -070028#include <linux/module.h>
29#include <linux/pci.h>
Alan Cox72b43792010-10-27 15:33:23 -070030#include <linux/platform_device.h>
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010031#include <linux/pm_runtime.h>
Andy Shevchenko3cabe872016-07-06 12:50:13 +030032#include <linux/slab.h>
33#include <linux/stddef.h>
Alek Du8bf02612009-09-22 16:46:36 -070034
David Cohenf89a7682013-10-04 13:01:42 -070035#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
36#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
David Cohend56d6b32013-10-04 13:01:40 -070037
Alek Du8081c842010-05-26 14:42:25 -070038/*
39 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
40 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
41 * registers to control them, so we only define the order here instead of a
42 * structure, to get a bit offset for a pin (use GPDR as an example):
43 *
44 * nreg = ngpio / 32;
45 * reg = offset / 32;
46 * bit = offset % 32;
47 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
48 *
49 * so the bit of reg_addr is to control pin offset's GPDR feature
50*/
51
52enum GPIO_REG {
53 GPLR = 0, /* pin level read-only */
54 GPDR, /* pin direction */
55 GPSR, /* pin set */
56 GPCR, /* pin clear */
57 GRER, /* rising edge detect */
58 GFER, /* falling edge detect */
59 GEDR, /* edge detect result */
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030060 GAFR, /* alt function */
Alek Du8bf02612009-09-22 16:46:36 -070061};
62
David Cohenf89a7682013-10-04 13:01:42 -070063/* intel_mid gpio driver data */
64struct intel_mid_gpio_ddata {
David Cohend56d6b32013-10-04 13:01:40 -070065 u16 ngpio; /* number of gpio pins */
David Cohend56d6b32013-10-04 13:01:40 -070066 u32 chip_irq_type; /* chip interrupt type */
67};
68
David Cohenf89a7682013-10-04 13:01:42 -070069struct intel_mid_gpio {
Alek Du8bf02612009-09-22 16:46:36 -070070 struct gpio_chip chip;
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +030071 void __iomem *reg_base;
Alek Du8bf02612009-09-22 16:46:36 -070072 spinlock_t lock;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010073 struct pci_dev *pdev;
Alek Du8bf02612009-09-22 16:46:36 -070074};
75
Alek Du8081c842010-05-26 14:42:25 -070076static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
Andy Shevchenko611a4852013-05-22 13:20:14 +030077 enum GPIO_REG reg_type)
Alek Du8bf02612009-09-22 16:46:36 -070078{
Linus Walleij5c77c022015-12-06 10:55:28 +010079 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
Alek Du8081c842010-05-26 14:42:25 -070080 unsigned nreg = chip->ngpio / 32;
Alek Du8bf02612009-09-22 16:46:36 -070081 u8 reg = offset / 32;
Alek Du8bf02612009-09-22 16:46:36 -070082
David Cohenf89a7682013-10-04 13:01:42 -070083 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Alek Du8081c842010-05-26 14:42:25 -070084}
85
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030086static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
87 enum GPIO_REG reg_type)
88{
Linus Walleij5c77c022015-12-06 10:55:28 +010089 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030090 unsigned nreg = chip->ngpio / 32;
91 u8 reg = offset / 16;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030092
David Cohenf89a7682013-10-04 13:01:42 -070093 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030094}
95
David Cohenf89a7682013-10-04 13:01:42 -070096static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030097{
98 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
99 u32 value = readl(gafr);
100 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
101
102 if (af) {
103 value &= ~(3 << shift);
104 writel(value, gafr);
105 }
106 return 0;
107}
108
David Cohenf89a7682013-10-04 13:01:42 -0700109static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
Alek Du8081c842010-05-26 14:42:25 -0700110{
111 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
112
Linus Walleij4c628f32015-12-21 11:00:56 +0100113 return !!(readl(gplr) & BIT(offset % 32));
Alek Du8bf02612009-09-22 16:46:36 -0700114}
115
David Cohenf89a7682013-10-04 13:01:42 -0700116static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
Alek Du8bf02612009-09-22 16:46:36 -0700117{
Alek Du8bf02612009-09-22 16:46:36 -0700118 void __iomem *gpsr, *gpcr;
119
120 if (value) {
Alek Du8081c842010-05-26 14:42:25 -0700121 gpsr = gpio_reg(chip, offset, GPSR);
Alek Du8bf02612009-09-22 16:46:36 -0700122 writel(BIT(offset % 32), gpsr);
123 } else {
Alek Du8081c842010-05-26 14:42:25 -0700124 gpcr = gpio_reg(chip, offset, GPCR);
Alek Du8bf02612009-09-22 16:46:36 -0700125 writel(BIT(offset % 32), gpcr);
126 }
127}
128
David Cohenf89a7682013-10-04 13:01:42 -0700129static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
Alek Du8bf02612009-09-22 16:46:36 -0700130{
Linus Walleij5c77c022015-12-06 10:55:28 +0100131 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
Alek Du8081c842010-05-26 14:42:25 -0700132 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700133 u32 value;
134 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700135
David Cohenf89a7682013-10-04 13:01:42 -0700136 if (priv->pdev)
137 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100138
David Cohenf89a7682013-10-04 13:01:42 -0700139 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700140 value = readl(gpdr);
141 value &= ~BIT(offset % 32);
142 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700143 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100144
David Cohenf89a7682013-10-04 13:01:42 -0700145 if (priv->pdev)
146 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100147
Alek Du8bf02612009-09-22 16:46:36 -0700148 return 0;
149}
150
David Cohenf89a7682013-10-04 13:01:42 -0700151static int intel_gpio_direction_output(struct gpio_chip *chip,
Alek Du8bf02612009-09-22 16:46:36 -0700152 unsigned offset, int value)
153{
Linus Walleij5c77c022015-12-06 10:55:28 +0100154 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
Alek Du8081c842010-05-26 14:42:25 -0700155 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700156 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700157
David Cohenf89a7682013-10-04 13:01:42 -0700158 intel_gpio_set(chip, offset, value);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100159
David Cohenf89a7682013-10-04 13:01:42 -0700160 if (priv->pdev)
161 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100162
David Cohenf89a7682013-10-04 13:01:42 -0700163 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700164 value = readl(gpdr);
Justin P. Mattock6eab04a2011-04-08 19:49:08 -0700165 value |= BIT(offset % 32);
Alek Du8bf02612009-09-22 16:46:36 -0700166 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700167 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100168
David Cohenf89a7682013-10-04 13:01:42 -0700169 if (priv->pdev)
170 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100171
Alek Du8bf02612009-09-22 16:46:36 -0700172 return 0;
173}
174
David Cohenf89a7682013-10-04 13:01:42 -0700175static int intel_mid_irq_type(struct irq_data *d, unsigned type)
Alek Du8bf02612009-09-22 16:46:36 -0700176{
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleij5c77c022015-12-06 10:55:28 +0100178 struct intel_mid_gpio *priv = gpiochip_get_data(gc);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300179 u32 gpio = irqd_to_hwirq(d);
Alek Du8bf02612009-09-22 16:46:36 -0700180 unsigned long flags;
181 u32 value;
David Cohenf89a7682013-10-04 13:01:42 -0700182 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
183 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
Alek Du8bf02612009-09-22 16:46:36 -0700184
David Cohenf89a7682013-10-04 13:01:42 -0700185 if (gpio >= priv->chip.ngpio)
Alek Du8bf02612009-09-22 16:46:36 -0700186 return -EINVAL;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100187
David Cohenf89a7682013-10-04 13:01:42 -0700188 if (priv->pdev)
189 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100190
David Cohenf89a7682013-10-04 13:01:42 -0700191 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700192 if (type & IRQ_TYPE_EDGE_RISING)
193 value = readl(grer) | BIT(gpio % 32);
194 else
195 value = readl(grer) & (~BIT(gpio % 32));
196 writel(value, grer);
197
198 if (type & IRQ_TYPE_EDGE_FALLING)
199 value = readl(gfer) | BIT(gpio % 32);
200 else
201 value = readl(gfer) & (~BIT(gpio % 32));
202 writel(value, gfer);
David Cohenf89a7682013-10-04 13:01:42 -0700203 spin_unlock_irqrestore(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700204
David Cohenf89a7682013-10-04 13:01:42 -0700205 if (priv->pdev)
206 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100207
Alek Du8bf02612009-09-22 16:46:36 -0700208 return 0;
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700209}
Alek Du8bf02612009-09-22 16:46:36 -0700210
David Cohenf89a7682013-10-04 13:01:42 -0700211static void intel_mid_irq_unmask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700212{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700213}
Alek Du8bf02612009-09-22 16:46:36 -0700214
David Cohenf89a7682013-10-04 13:01:42 -0700215static void intel_mid_irq_mask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700216{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700217}
Alek Du8bf02612009-09-22 16:46:36 -0700218
David Cohenf89a7682013-10-04 13:01:42 -0700219static struct irq_chip intel_mid_irqchip = {
220 .name = "INTEL_MID-GPIO",
221 .irq_mask = intel_mid_irq_mask,
222 .irq_unmask = intel_mid_irq_unmask,
223 .irq_set_type = intel_mid_irq_type,
Alek Du8bf02612009-09-22 16:46:36 -0700224};
225
David Cohenf89a7682013-10-04 13:01:42 -0700226static const struct intel_mid_gpio_ddata gpio_lincroft = {
David Cohend56d6b32013-10-04 13:01:40 -0700227 .ngpio = 64,
228};
229
David Cohenf89a7682013-10-04 13:01:42 -0700230static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700231 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700232 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700233};
234
David Cohenf89a7682013-10-04 13:01:42 -0700235static const struct intel_mid_gpio_ddata gpio_penwell_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700236 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700237 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700238};
239
David Cohenf89a7682013-10-04 13:01:42 -0700240static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700241 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700242 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
David Cohend56d6b32013-10-04 13:01:40 -0700243};
244
David Cohenf89a7682013-10-04 13:01:42 -0700245static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700246 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700247 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700248};
249
Jingoo Han14f4a882013-12-03 08:08:45 +0900250static const struct pci_device_id intel_gpio_ids[] = {
David Cohend56d6b32013-10-04 13:01:40 -0700251 {
252 /* Lincroft */
253 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
254 .driver_data = (kernel_ulong_t)&gpio_lincroft,
255 },
256 {
257 /* Penwell AON */
258 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
259 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
260 },
261 {
262 /* Penwell Core */
263 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
264 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
265 },
266 {
267 /* Cloverview Aon */
268 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
269 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
270 },
271 {
272 /* Cloverview Core */
273 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
274 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
275 },
David Cohend56d6b32013-10-04 13:01:40 -0700276 { 0 }
Alek Du8bf02612009-09-22 16:46:36 -0700277};
David Cohenf89a7682013-10-04 13:01:42 -0700278MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
Alek Du8bf02612009-09-22 16:46:36 -0700279
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200280static void intel_mid_irq_handler(struct irq_desc *desc)
Alek Du8bf02612009-09-22 16:46:36 -0700281{
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200282 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
Linus Walleij5c77c022015-12-06 10:55:28 +0100283 struct intel_mid_gpio *priv = gpiochip_get_data(gc);
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000284 struct irq_data *data = irq_desc_get_irq_data(desc);
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000285 struct irq_chip *chip = irq_data_get_irq_chip(data);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000286 u32 base, gpio, mask;
Thomas Gleixner732063b2011-03-17 19:32:55 +0000287 unsigned long pending;
Alek Du8bf02612009-09-22 16:46:36 -0700288 void __iomem *gedr;
Alek Du8bf02612009-09-22 16:46:36 -0700289
290 /* check GPIO controller to check which pin triggered the interrupt */
David Cohenf89a7682013-10-04 13:01:42 -0700291 for (base = 0; base < priv->chip.ngpio; base += 32) {
292 gedr = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergc8f925b2012-05-10 13:01:22 +0300293 while ((pending = readl(gedr))) {
Mathias Nyman2345b202011-07-08 10:02:18 +0100294 gpio = __ffs(pending);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000295 mask = BIT(gpio);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000296 /* Clear before handling so we can't lose an edge */
297 writel(mask, gedr);
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200298 generic_handle_irq(irq_find_mapping(gc->irqdomain,
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300299 base + gpio));
Thomas Gleixner732063b2011-03-17 19:32:55 +0000300 }
Alek Du8bf02612009-09-22 16:46:36 -0700301 }
Feng Tang0766d202011-01-25 15:07:15 -0800302
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000303 chip->irq_eoi(data);
Alek Du8bf02612009-09-22 16:46:36 -0700304}
305
David Cohenf89a7682013-10-04 13:01:42 -0700306static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
Mika Westerbergf5f93112012-04-05 12:15:17 +0300307{
308 void __iomem *reg;
309 unsigned base;
310
David Cohenf89a7682013-10-04 13:01:42 -0700311 for (base = 0; base < priv->chip.ngpio; base += 32) {
Mika Westerbergf5f93112012-04-05 12:15:17 +0300312 /* Clear the rising-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700313 reg = gpio_reg(&priv->chip, base, GRER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300314 writel(0, reg);
315 /* Clear the falling-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700316 reg = gpio_reg(&priv->chip, base, GFER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300317 writel(0, reg);
318 /* Clear the edge detect status register */
David Cohenf89a7682013-10-04 13:01:42 -0700319 reg = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300320 writel(~0, reg);
321 }
322}
323
David Cohenf89a7682013-10-04 13:01:42 -0700324static int intel_gpio_runtime_idle(struct device *dev)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100325{
xinhui.pan84a34572014-01-31 13:08:01 -0800326 int err = pm_schedule_suspend(dev, 500);
327 return err ?: -EBUSY;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100328}
329
David Cohenf89a7682013-10-04 13:01:42 -0700330static const struct dev_pm_ops intel_gpio_pm_ops = {
331 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100332};
333
David Cohenf89a7682013-10-04 13:01:42 -0700334static int intel_gpio_probe(struct pci_dev *pdev,
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300335 const struct pci_device_id *id)
Alek Du8bf02612009-09-22 16:46:36 -0700336{
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300337 void __iomem *base;
David Cohenf89a7682013-10-04 13:01:42 -0700338 struct intel_mid_gpio *priv;
Alek Du8bf02612009-09-22 16:46:36 -0700339 u32 gpio_base;
David Cohen2519f9a2013-05-06 16:11:03 -0700340 u32 irq_base;
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200341 int retval;
David Cohenf89a7682013-10-04 13:01:42 -0700342 struct intel_mid_gpio_ddata *ddata =
343 (struct intel_mid_gpio_ddata *)id->driver_data;
Alek Du8bf02612009-09-22 16:46:36 -0700344
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300345 retval = pcim_enable_device(pdev);
Alek Du8bf02612009-09-22 16:46:36 -0700346 if (retval)
Mika Westerberg8302c742012-04-05 12:15:15 +0300347 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700348
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300349 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
Alek Du8bf02612009-09-22 16:46:36 -0700350 if (retval) {
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300351 dev_err(&pdev->dev, "I/O memory mapping error\n");
352 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700353 }
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300354
355 base = pcim_iomap_table(pdev)[1];
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300356
357 irq_base = readl(base);
358 gpio_base = readl(sizeof(u32) + base);
359
Alek Du8bf02612009-09-22 16:46:36 -0700360 /* release the IO mapping, since we already get the info from bar1 */
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300361 pcim_iounmap_regions(pdev, 1 << 1);
Alek Du8bf02612009-09-22 16:46:36 -0700362
David Cohenf89a7682013-10-04 13:01:42 -0700363 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
364 if (!priv) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300365 dev_err(&pdev->dev, "can't allocate chip data\n");
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300366 return -ENOMEM;
Alek Du8bf02612009-09-22 16:46:36 -0700367 }
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300368
David Cohenf89a7682013-10-04 13:01:42 -0700369 priv->reg_base = pcim_iomap_table(pdev)[0];
370 priv->chip.label = dev_name(&pdev->dev);
Linus Walleij58383c72015-11-04 09:56:26 +0100371 priv->chip.parent = &pdev->dev;
David Cohenf89a7682013-10-04 13:01:42 -0700372 priv->chip.request = intel_gpio_request;
373 priv->chip.direction_input = intel_gpio_direction_input;
374 priv->chip.direction_output = intel_gpio_direction_output;
375 priv->chip.get = intel_gpio_get;
376 priv->chip.set = intel_gpio_set;
David Cohenf89a7682013-10-04 13:01:42 -0700377 priv->chip.base = gpio_base;
378 priv->chip.ngpio = ddata->ngpio;
Linus Walleij9fb1f392013-12-04 14:42:46 +0100379 priv->chip.can_sleep = false;
David Cohenf89a7682013-10-04 13:01:42 -0700380 priv->pdev = pdev;
David Cohen2519f9a2013-05-06 16:11:03 -0700381
David Cohenf89a7682013-10-04 13:01:42 -0700382 spin_lock_init(&priv->lock);
Andy Shevchenkoaeb168f2013-05-22 13:20:10 +0300383
David Cohenf89a7682013-10-04 13:01:42 -0700384 pci_set_drvdata(pdev, priv);
Andy Shevchenkodd3b2042016-06-19 23:49:57 +0300385 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
Alek Du8bf02612009-09-22 16:46:36 -0700386 if (retval) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300387 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300388 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700389 }
Mika Westerbergf5f93112012-04-05 12:15:17 +0300390
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200391 retval = gpiochip_irqchip_add(&priv->chip,
392 &intel_mid_irqchip,
393 irq_base,
394 handle_simple_irq,
395 IRQ_TYPE_NONE);
396 if (retval) {
397 dev_err(&pdev->dev,
398 "could not connect irqchip to gpiochip\n");
399 return retval;
400 }
401
David Cohenf89a7682013-10-04 13:01:42 -0700402 intel_mid_irq_init_hw(priv);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300403
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200404 gpiochip_set_chained_irqchip(&priv->chip,
405 &intel_mid_irqchip,
406 pdev->irq,
407 intel_mid_irq_handler);
Alek Du8bf02612009-09-22 16:46:36 -0700408
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100409 pm_runtime_put_noidle(&pdev->dev);
410 pm_runtime_allow(&pdev->dev);
411
Mika Westerberg8302c742012-04-05 12:15:15 +0300412 return 0;
Alek Du8bf02612009-09-22 16:46:36 -0700413}
414
David Cohenf89a7682013-10-04 13:01:42 -0700415static struct pci_driver intel_gpio_driver = {
416 .name = "intel_mid_gpio",
417 .id_table = intel_gpio_ids,
418 .probe = intel_gpio_probe,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100419 .driver = {
David Cohenf89a7682013-10-04 13:01:42 -0700420 .pm = &intel_gpio_pm_ops,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100421 },
Alek Du8bf02612009-09-22 16:46:36 -0700422};
423
David Cohenf89a7682013-10-04 13:01:42 -0700424static int __init intel_gpio_init(void)
Alek Du8bf02612009-09-22 16:46:36 -0700425{
David Cohenf89a7682013-10-04 13:01:42 -0700426 return pci_register_driver(&intel_gpio_driver);
Alek Du8bf02612009-09-22 16:46:36 -0700427}
428
David Cohenf89a7682013-10-04 13:01:42 -0700429device_initcall(intel_gpio_init);