Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3-specific clock framework functions |
| 3 | * |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
Paul Walmsley | da4d290 | 2010-01-26 20:13:10 -0700 | [diff] [blame^] | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 6 | * |
Paul Walmsley | da4d290 | 2010-01-26 20:13:10 -0700 | [diff] [blame^] | 7 | * Paul Walmsley |
| 8 | * Jouni Högander |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 9 | * |
| 10 | * Parts of this code are based on code written by |
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | #undef DEBUG |
| 18 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 19 | #include <linux/kernel.h> |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 20 | #include <linux/errno.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> |
| 24 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 25 | #include <plat/cpu.h> |
| 26 | #include <plat/clock.h> |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 27 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 28 | #include "clock.h" |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 29 | #include "clock34xx.h" |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 30 | #include "prm.h" |
| 31 | #include "prm-regbits-34xx.h" |
| 32 | #include "cm.h" |
| 33 | #include "cm-regbits-34xx.h" |
| 34 | |
Rajendra Nayak | 7a66a39 | 2009-10-05 13:31:44 -0700 | [diff] [blame] | 35 | /* |
| 36 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks |
| 37 | * that are sourced by DPLL5, and both of these require this clock |
| 38 | * to be at 120 MHz for proper operation. |
| 39 | */ |
| 40 | #define DPLL5_FREQ_FOR_USBHOST 120000000 |
| 41 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 42 | /* needed by omap3_core_dpll_m2_set_rate() */ |
| 43 | struct clk *sdrc_ick_p, *arm_fck_p; |
| 44 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 45 | /** |
Paul Walmsley | 3c82e22 | 2009-07-24 19:44:06 -0600 | [diff] [blame] | 46 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI |
| 47 | * @clk: struct clk * being enabled |
| 48 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
| 49 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
| 50 | * |
| 51 | * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift |
| 52 | * from the CM_{I,F}CLKEN bit. Pass back the correct info via |
| 53 | * @idlest_reg and @idlest_bit. No return value. |
| 54 | */ |
| 55 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, |
| 56 | void __iomem **idlest_reg, |
| 57 | u8 *idlest_bit) |
| 58 | { |
| 59 | u32 r; |
| 60 | |
| 61 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 62 | *idlest_reg = (__force void __iomem *)r; |
| 63 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; |
| 64 | } |
| 65 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 66 | const struct clkops clkops_omap3430es2_ssi_wait = { |
| 67 | .enable = omap2_dflt_clk_enable, |
| 68 | .disable = omap2_dflt_clk_disable, |
| 69 | .find_idlest = omap3430es2_clk_ssi_find_idlest, |
| 70 | .find_companion = omap2_clk_dflt_find_companion, |
| 71 | }; |
| 72 | |
Paul Walmsley | 3c82e22 | 2009-07-24 19:44:06 -0600 | [diff] [blame] | 73 | /** |
| 74 | * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST |
| 75 | * @clk: struct clk * being enabled |
| 76 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
| 77 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
| 78 | * |
| 79 | * Some OMAP modules on OMAP3 ES2+ chips have both initiator and |
| 80 | * target IDLEST bits. For our purposes, we are concerned with the |
| 81 | * target IDLEST bits, which exist at a different bit position than |
| 82 | * the *CLKEN bit position for these modules (DSS and USBHOST) (The |
| 83 | * default find_idlest code assumes that they are at the same |
| 84 | * position.) No return value. |
| 85 | */ |
| 86 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, |
| 87 | void __iomem **idlest_reg, |
| 88 | u8 *idlest_bit) |
| 89 | { |
| 90 | u32 r; |
| 91 | |
| 92 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 93 | *idlest_reg = (__force void __iomem *)r; |
| 94 | /* USBHOST_IDLE has same shift */ |
| 95 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; |
| 96 | } |
| 97 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 98 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { |
| 99 | .enable = omap2_dflt_clk_enable, |
| 100 | .disable = omap2_dflt_clk_disable, |
| 101 | .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, |
| 102 | .find_companion = omap2_clk_dflt_find_companion, |
| 103 | }; |
| 104 | |
Paul Walmsley | 3c82e22 | 2009-07-24 19:44:06 -0600 | [diff] [blame] | 105 | /** |
| 106 | * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB |
| 107 | * @clk: struct clk * being enabled |
| 108 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
| 109 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
| 110 | * |
| 111 | * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different |
| 112 | * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via |
| 113 | * @idlest_reg and @idlest_bit. No return value. |
| 114 | */ |
| 115 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, |
| 116 | void __iomem **idlest_reg, |
| 117 | u8 *idlest_bit) |
| 118 | { |
| 119 | u32 r; |
| 120 | |
| 121 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 122 | *idlest_reg = (__force void __iomem *)r; |
| 123 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; |
| 124 | } |
| 125 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 126 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { |
| 127 | .enable = omap2_dflt_clk_enable, |
| 128 | .disable = omap2_dflt_clk_disable, |
| 129 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, |
| 130 | .find_companion = omap2_clk_dflt_find_companion, |
| 131 | }; |
| 132 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 133 | const struct clkops clkops_noncore_dpll_ops = { |
| 134 | .enable = omap3_noncore_dpll_enable, |
| 135 | .disable = omap3_noncore_dpll_disable, |
| 136 | }; |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 137 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 138 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 139 | { |
| 140 | /* |
| 141 | * According to the 12-5 CDP code from TI, "Limitation 2.5" |
| 142 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers |
| 143 | * on DPLL4. |
| 144 | */ |
| 145 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
| 146 | printk(KERN_ERR "clock: DPLL4 cannot change rate due to " |
| 147 | "silicon 'Limitation 2.5' on 3430ES1.\n"); |
| 148 | return -EINVAL; |
| 149 | } |
| 150 | return omap3_noncore_dpll_set_rate(clk, rate); |
| 151 | } |
| 152 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 153 | /* Common clock code */ |
| 154 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 155 | /* |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 156 | * Set clocks for bypass mode for reboot to work. |
| 157 | */ |
| 158 | void omap2_clk_prepare_for_reboot(void) |
| 159 | { |
| 160 | /* REVISIT: Not ready for 343x */ |
| 161 | #if 0 |
| 162 | u32 rate; |
| 163 | |
| 164 | if (vclk == NULL || sclk == NULL) |
| 165 | return; |
| 166 | |
| 167 | rate = clk_get_rate(sclk); |
| 168 | clk_set_rate(vclk, rate); |
| 169 | #endif |
| 170 | } |
| 171 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 172 | void omap3_clk_lock_dpll5(void) |
Rajendra Nayak | 7a66a39 | 2009-10-05 13:31:44 -0700 | [diff] [blame] | 173 | { |
| 174 | struct clk *dpll5_clk; |
| 175 | struct clk *dpll5_m2_clk; |
| 176 | |
| 177 | dpll5_clk = clk_get(NULL, "dpll5_ck"); |
| 178 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); |
| 179 | clk_enable(dpll5_clk); |
| 180 | |
| 181 | /* Enable autoidle to allow it to enter low power bypass */ |
| 182 | omap3_dpll_allow_idle(dpll5_clk); |
| 183 | |
| 184 | /* Program dpll5_m2_clk divider for no division */ |
| 185 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); |
| 186 | clk_enable(dpll5_m2_clk); |
| 187 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); |
| 188 | |
| 189 | clk_disable(dpll5_m2_clk); |
| 190 | clk_disable(dpll5_clk); |
| 191 | return; |
| 192 | } |
| 193 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 194 | /* REVISIT: Move this init stuff out into clock.c */ |
| 195 | |
| 196 | /* |
| 197 | * Switch the MPU rate if specified on cmdline. |
| 198 | * We cannot do this early until cmdline is parsed. |
| 199 | */ |
Paul Walmsley | 4680c29 | 2010-01-26 20:13:09 -0700 | [diff] [blame] | 200 | static int __init omap3xxx_clk_arch_init(void) |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 201 | { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 202 | struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; |
| 203 | unsigned long osc_sys_rate; |
| 204 | |
Paul Walmsley | 4680c29 | 2010-01-26 20:13:09 -0700 | [diff] [blame] | 205 | if (!cpu_is_omap34xx()) |
| 206 | return 0; |
| 207 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 208 | if (!mpurate) |
| 209 | return -EINVAL; |
| 210 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 211 | /* XXX test these for success */ |
| 212 | dpll1_ck = clk_get(NULL, "dpll1_ck"); |
| 213 | arm_fck = clk_get(NULL, "arm_fck"); |
| 214 | core_ck = clk_get(NULL, "core_ck"); |
| 215 | osc_sys_ck = clk_get(NULL, "osc_sys_ck"); |
| 216 | |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 217 | /* REVISIT: not yet ready for 343x */ |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 218 | if (clk_set_rate(dpll1_ck, mpurate)) |
Sanjeev Premi | 11b6638 | 2009-09-03 20:13:58 +0300 | [diff] [blame] | 219 | printk(KERN_ERR "*** Unable to set MPU rate\n"); |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 220 | |
| 221 | recalculate_root_clocks(); |
| 222 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 223 | osc_sys_rate = clk_get_rate(osc_sys_ck); |
| 224 | |
| 225 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " |
| 226 | "%ld.%01ld/%ld/%ld MHz\n", |
| 227 | (osc_sys_rate / 1000000), |
| 228 | ((osc_sys_rate / 100000) % 10), |
| 229 | (clk_get_rate(core_ck) / 1000000), |
| 230 | (clk_get_rate(arm_fck) / 1000000)); |
Sanjeev Premi | 11b6638 | 2009-09-03 20:13:58 +0300 | [diff] [blame] | 231 | |
| 232 | calibrate_delay(); |
Paul Walmsley | 02e19a9 | 2008-03-18 15:09:51 +0200 | [diff] [blame] | 233 | |
| 234 | return 0; |
| 235 | } |
Paul Walmsley | 4680c29 | 2010-01-26 20:13:09 -0700 | [diff] [blame] | 236 | arch_initcall(omap3xxx_clk_arch_init); |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 237 | |
| 238 | |