Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 28 | #include <linux/firmware.h> |
| 29 | #include <linux/platform_device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | #include "drmP.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 33 | #include "radeon_asic.h" |
Dave Airlie | 4153e58 | 2009-09-18 18:41:24 +1000 | [diff] [blame] | 34 | #include "radeon_drm.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 35 | #include "rv770d.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 36 | #include "atom.h" |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 37 | #include "avivod.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 39 | #define R700_PFP_UCODE_SIZE 848 |
| 40 | #define R700_PM4_UCODE_SIZE 1360 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 42 | static void rv770_gpu_init(struct radeon_device *rdev); |
| 43 | void rv770_fini(struct radeon_device *rdev); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 45 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 46 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
| 47 | { |
| 48 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
| 49 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); |
| 50 | |
| 51 | /* Lock the graphics update lock */ |
| 52 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
| 53 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
| 54 | |
| 55 | /* update the scanout addresses */ |
| 56 | if (radeon_crtc->crtc_id) { |
| 57 | WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 58 | WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 59 | } else { |
| 60 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 61 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 62 | } |
| 63 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 64 | (u32)crtc_base); |
| 65 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 66 | (u32)crtc_base); |
| 67 | |
| 68 | /* Wait for update_pending to go high. */ |
| 69 | while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); |
| 70 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
| 71 | |
| 72 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
| 73 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
| 74 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
| 75 | |
| 76 | /* Return current update_pending status: */ |
| 77 | return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; |
| 78 | } |
| 79 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 80 | /* get temperature in millidegrees */ |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 81 | int rv770_get_temp(struct radeon_device *rdev) |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 82 | { |
| 83 | u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> |
| 84 | ASIC_T_SHIFT; |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 85 | int actual_temp; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 86 | |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 87 | if (temp & 0x400) |
| 88 | actual_temp = -256; |
| 89 | else if (temp & 0x200) |
| 90 | actual_temp = 255; |
| 91 | else if (temp & 0x100) { |
| 92 | actual_temp = temp & 0x1ff; |
| 93 | actual_temp |= ~0x1ff; |
| 94 | } else |
| 95 | actual_temp = temp & 0xff; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 96 | |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 97 | return (actual_temp * 1000) / 2; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 98 | } |
| 99 | |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 100 | void rv770_pm_misc(struct radeon_device *rdev) |
| 101 | { |
Rafał Miłecki | a081a9d | 2010-06-07 18:20:25 -0400 | [diff] [blame] | 102 | int req_ps_idx = rdev->pm.requested_power_state_index; |
| 103 | int req_cm_idx = rdev->pm.requested_clock_mode_index; |
| 104 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
| 105 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 106 | |
| 107 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
Alex Deucher | a377e18 | 2011-06-20 13:00:31 -0400 | [diff] [blame] | 108 | /* 0xff01 is a flag rather then an actual voltage */ |
| 109 | if (voltage->voltage == 0xff01) |
| 110 | return; |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 111 | if (voltage->voltage != rdev->pm.current_vddc) { |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 112 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 113 | rdev->pm.current_vddc = voltage->voltage; |
Rafał Miłecki | 0fcbe94 | 2010-06-07 18:25:21 -0400 | [diff] [blame] | 114 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 115 | } |
| 116 | } |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 117 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 118 | |
| 119 | /* |
| 120 | * GART |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 121 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 122 | int rv770_pcie_gart_enable(struct radeon_device *rdev) |
| 123 | { |
| 124 | u32 tmp; |
| 125 | int r, i; |
| 126 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 127 | if (rdev->gart.table.vram.robj == NULL) { |
| 128 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 129 | return -EINVAL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 130 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 131 | r = radeon_gart_table_vram_pin(rdev); |
| 132 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 133 | return r; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 134 | radeon_gart_restore(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 135 | /* Setup L2 cache */ |
| 136 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 137 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 138 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 139 | WREG32(VM_L2_CNTL2, 0); |
| 140 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
| 141 | /* Setup TLB control */ |
| 142 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 143 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 144 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
| 145 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
| 146 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
| 147 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
| 148 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
| 149 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 150 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
| 151 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
| 152 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
| 153 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 154 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 155 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| 156 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
| 157 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
| 158 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| 159 | (u32)(rdev->dummy_page.addr >> 12)); |
| 160 | for (i = 1; i < 7; i++) |
| 161 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 162 | |
| 163 | r600_pcie_gart_tlb_flush(rdev); |
| 164 | rdev->gart.ready = true; |
| 165 | return 0; |
| 166 | } |
| 167 | |
| 168 | void rv770_pcie_gart_disable(struct radeon_device *rdev) |
| 169 | { |
| 170 | u32 tmp; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 171 | int i, r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 172 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 173 | /* Disable all tables */ |
| 174 | for (i = 0; i < 7; i++) |
| 175 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 176 | |
| 177 | /* Setup L2 cache */ |
| 178 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
| 179 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 180 | WREG32(VM_L2_CNTL2, 0); |
| 181 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
| 182 | /* Setup TLB control */ |
| 183 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
| 184 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
| 185 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
| 186 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
| 187 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 188 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
| 189 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
| 190 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 191 | if (rdev->gart.table.vram.robj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 192 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
| 193 | if (likely(r == 0)) { |
| 194 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
| 195 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
| 196 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
| 197 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 198 | } |
| 199 | } |
| 200 | |
| 201 | void rv770_pcie_gart_fini(struct radeon_device *rdev) |
| 202 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 203 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 204 | rv770_pcie_gart_disable(rdev); |
| 205 | radeon_gart_table_vram_free(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 206 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 207 | |
| 208 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 209 | void rv770_agp_enable(struct radeon_device *rdev) |
| 210 | { |
| 211 | u32 tmp; |
| 212 | int i; |
| 213 | |
| 214 | /* Setup L2 cache */ |
| 215 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 216 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 217 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 218 | WREG32(VM_L2_CNTL2, 0); |
| 219 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
| 220 | /* Setup TLB control */ |
| 221 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 222 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 223 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
| 224 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
| 225 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
| 226 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
| 227 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
| 228 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 229 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
| 230 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
| 231 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
| 232 | for (i = 0; i < 7; i++) |
| 233 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 234 | } |
| 235 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 236 | static void rv770_mc_program(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 238 | struct rv515_mc_save save; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 239 | u32 tmp; |
| 240 | int i, j; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 241 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 242 | /* Initialize HDP */ |
| 243 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 244 | WREG32((0x2c14 + j), 0x00000000); |
| 245 | WREG32((0x2c18 + j), 0x00000000); |
| 246 | WREG32((0x2c1c + j), 0x00000000); |
| 247 | WREG32((0x2c20 + j), 0x00000000); |
| 248 | WREG32((0x2c24 + j), 0x00000000); |
| 249 | } |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 250 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
| 251 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL |
| 252 | */ |
| 253 | tmp = RREG32(HDP_DEBUG1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 254 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 255 | rv515_mc_stop(rdev, &save); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 256 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 257 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 259 | /* Lockout access through VGA aperture*/ |
| 260 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 261 | /* Update configuration */ |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 262 | if (rdev->flags & RADEON_IS_AGP) { |
| 263 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
| 264 | /* VRAM before AGP */ |
| 265 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 266 | rdev->mc.vram_start >> 12); |
| 267 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 268 | rdev->mc.gtt_end >> 12); |
| 269 | } else { |
| 270 | /* VRAM after AGP */ |
| 271 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 272 | rdev->mc.gtt_start >> 12); |
| 273 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 274 | rdev->mc.vram_end >> 12); |
| 275 | } |
| 276 | } else { |
| 277 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 278 | rdev->mc.vram_start >> 12); |
| 279 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 280 | rdev->mc.vram_end >> 12); |
| 281 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 282 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 283 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 284 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
| 285 | WREG32(MC_VM_FB_LOCATION, tmp); |
| 286 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
| 287 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
Jerome Glisse | 46fcd2b | 2010-06-03 19:34:48 +0200 | [diff] [blame] | 288 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 289 | if (rdev->flags & RADEON_IS_AGP) { |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 290 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 291 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
| 292 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
| 293 | } else { |
| 294 | WREG32(MC_VM_AGP_BASE, 0); |
| 295 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
| 296 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
| 297 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 298 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 299 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 300 | } |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 301 | rv515_mc_resume(rdev, &save); |
Dave Airlie | 698443d | 2009-09-18 14:16:38 +1000 | [diff] [blame] | 302 | /* we need to own VRAM, so turn off the VGA renderer here |
| 303 | * to stop it overwriting our objects */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 304 | rv515_vga_render_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | |
| 308 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 309 | * CP. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 311 | void r700_cp_stop(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 312 | { |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 313 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 314 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 315 | WREG32(SCRATCH_UMSK, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 316 | } |
| 317 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 318 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 319 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 320 | const __be32 *fw_data; |
| 321 | int i; |
| 322 | |
| 323 | if (!rdev->me_fw || !rdev->pfp_fw) |
| 324 | return -EINVAL; |
| 325 | |
| 326 | r700_cp_stop(rdev); |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 327 | WREG32(CP_RB_CNTL, |
| 328 | #ifdef __BIG_ENDIAN |
| 329 | BUF_SWAP_32BIT | |
| 330 | #endif |
| 331 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 332 | |
| 333 | /* Reset cp */ |
| 334 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
| 335 | RREG32(GRBM_SOFT_RESET); |
| 336 | mdelay(15); |
| 337 | WREG32(GRBM_SOFT_RESET, 0); |
| 338 | |
| 339 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
| 340 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 341 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
| 342 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 343 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 344 | |
| 345 | fw_data = (const __be32 *)rdev->me_fw->data; |
| 346 | WREG32(CP_ME_RAM_WADDR, 0); |
| 347 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
| 348 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
| 349 | |
| 350 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 351 | WREG32(CP_ME_RAM_WADDR, 0); |
| 352 | WREG32(CP_ME_RAM_RADDR, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 353 | return 0; |
| 354 | } |
| 355 | |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 356 | void r700_cp_fini(struct radeon_device *rdev) |
| 357 | { |
| 358 | r700_cp_stop(rdev); |
| 359 | radeon_ring_fini(rdev); |
| 360 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 361 | |
| 362 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 363 | * Core functions |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 364 | */ |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 365 | static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
| 366 | u32 num_tile_pipes, |
| 367 | u32 num_backends, |
| 368 | u32 backend_disable_mask) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 369 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 370 | u32 backend_map = 0; |
| 371 | u32 enabled_backends_mask; |
| 372 | u32 enabled_backends_count; |
| 373 | u32 cur_pipe; |
| 374 | u32 swizzle_pipe[R7XX_MAX_PIPES]; |
| 375 | u32 cur_backend; |
| 376 | u32 i; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 377 | bool force_no_swizzle; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 378 | |
| 379 | if (num_tile_pipes > R7XX_MAX_PIPES) |
| 380 | num_tile_pipes = R7XX_MAX_PIPES; |
| 381 | if (num_tile_pipes < 1) |
| 382 | num_tile_pipes = 1; |
| 383 | if (num_backends > R7XX_MAX_BACKENDS) |
| 384 | num_backends = R7XX_MAX_BACKENDS; |
| 385 | if (num_backends < 1) |
| 386 | num_backends = 1; |
| 387 | |
| 388 | enabled_backends_mask = 0; |
| 389 | enabled_backends_count = 0; |
| 390 | for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { |
| 391 | if (((backend_disable_mask >> i) & 1) == 0) { |
| 392 | enabled_backends_mask |= (1 << i); |
| 393 | ++enabled_backends_count; |
| 394 | } |
| 395 | if (enabled_backends_count == num_backends) |
| 396 | break; |
| 397 | } |
| 398 | |
| 399 | if (enabled_backends_count == 0) { |
| 400 | enabled_backends_mask = 1; |
| 401 | enabled_backends_count = 1; |
| 402 | } |
| 403 | |
| 404 | if (enabled_backends_count != num_backends) |
| 405 | num_backends = enabled_backends_count; |
| 406 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 407 | switch (rdev->family) { |
| 408 | case CHIP_RV770: |
| 409 | case CHIP_RV730: |
| 410 | force_no_swizzle = false; |
| 411 | break; |
| 412 | case CHIP_RV710: |
| 413 | case CHIP_RV740: |
| 414 | default: |
| 415 | force_no_swizzle = true; |
| 416 | break; |
| 417 | } |
| 418 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 419 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); |
| 420 | switch (num_tile_pipes) { |
| 421 | case 1: |
| 422 | swizzle_pipe[0] = 0; |
| 423 | break; |
| 424 | case 2: |
| 425 | swizzle_pipe[0] = 0; |
| 426 | swizzle_pipe[1] = 1; |
| 427 | break; |
| 428 | case 3: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 429 | if (force_no_swizzle) { |
| 430 | swizzle_pipe[0] = 0; |
| 431 | swizzle_pipe[1] = 1; |
| 432 | swizzle_pipe[2] = 2; |
| 433 | } else { |
| 434 | swizzle_pipe[0] = 0; |
| 435 | swizzle_pipe[1] = 2; |
| 436 | swizzle_pipe[2] = 1; |
| 437 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 438 | break; |
| 439 | case 4: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 440 | if (force_no_swizzle) { |
| 441 | swizzle_pipe[0] = 0; |
| 442 | swizzle_pipe[1] = 1; |
| 443 | swizzle_pipe[2] = 2; |
| 444 | swizzle_pipe[3] = 3; |
| 445 | } else { |
| 446 | swizzle_pipe[0] = 0; |
| 447 | swizzle_pipe[1] = 2; |
| 448 | swizzle_pipe[2] = 3; |
| 449 | swizzle_pipe[3] = 1; |
| 450 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 451 | break; |
| 452 | case 5: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 453 | if (force_no_swizzle) { |
| 454 | swizzle_pipe[0] = 0; |
| 455 | swizzle_pipe[1] = 1; |
| 456 | swizzle_pipe[2] = 2; |
| 457 | swizzle_pipe[3] = 3; |
| 458 | swizzle_pipe[4] = 4; |
| 459 | } else { |
| 460 | swizzle_pipe[0] = 0; |
| 461 | swizzle_pipe[1] = 2; |
| 462 | swizzle_pipe[2] = 4; |
| 463 | swizzle_pipe[3] = 1; |
| 464 | swizzle_pipe[4] = 3; |
| 465 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 466 | break; |
| 467 | case 6: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 468 | if (force_no_swizzle) { |
| 469 | swizzle_pipe[0] = 0; |
| 470 | swizzle_pipe[1] = 1; |
| 471 | swizzle_pipe[2] = 2; |
| 472 | swizzle_pipe[3] = 3; |
| 473 | swizzle_pipe[4] = 4; |
| 474 | swizzle_pipe[5] = 5; |
| 475 | } else { |
| 476 | swizzle_pipe[0] = 0; |
| 477 | swizzle_pipe[1] = 2; |
| 478 | swizzle_pipe[2] = 4; |
| 479 | swizzle_pipe[3] = 5; |
| 480 | swizzle_pipe[4] = 3; |
| 481 | swizzle_pipe[5] = 1; |
| 482 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 483 | break; |
| 484 | case 7: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 485 | if (force_no_swizzle) { |
| 486 | swizzle_pipe[0] = 0; |
| 487 | swizzle_pipe[1] = 1; |
| 488 | swizzle_pipe[2] = 2; |
| 489 | swizzle_pipe[3] = 3; |
| 490 | swizzle_pipe[4] = 4; |
| 491 | swizzle_pipe[5] = 5; |
| 492 | swizzle_pipe[6] = 6; |
| 493 | } else { |
| 494 | swizzle_pipe[0] = 0; |
| 495 | swizzle_pipe[1] = 2; |
| 496 | swizzle_pipe[2] = 4; |
| 497 | swizzle_pipe[3] = 6; |
| 498 | swizzle_pipe[4] = 3; |
| 499 | swizzle_pipe[5] = 1; |
| 500 | swizzle_pipe[6] = 5; |
| 501 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 502 | break; |
| 503 | case 8: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 504 | if (force_no_swizzle) { |
| 505 | swizzle_pipe[0] = 0; |
| 506 | swizzle_pipe[1] = 1; |
| 507 | swizzle_pipe[2] = 2; |
| 508 | swizzle_pipe[3] = 3; |
| 509 | swizzle_pipe[4] = 4; |
| 510 | swizzle_pipe[5] = 5; |
| 511 | swizzle_pipe[6] = 6; |
| 512 | swizzle_pipe[7] = 7; |
| 513 | } else { |
| 514 | swizzle_pipe[0] = 0; |
| 515 | swizzle_pipe[1] = 2; |
| 516 | swizzle_pipe[2] = 4; |
| 517 | swizzle_pipe[3] = 6; |
| 518 | swizzle_pipe[4] = 3; |
| 519 | swizzle_pipe[5] = 1; |
| 520 | swizzle_pipe[6] = 7; |
| 521 | swizzle_pipe[7] = 5; |
| 522 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 523 | break; |
| 524 | } |
| 525 | |
| 526 | cur_backend = 0; |
| 527 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
| 528 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
| 529 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; |
| 530 | |
| 531 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); |
| 532 | |
| 533 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; |
| 534 | } |
| 535 | |
| 536 | return backend_map; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 537 | } |
| 538 | |
Alex Deucher | 9535ab7 | 2010-11-22 17:56:18 -0500 | [diff] [blame] | 539 | static void rv770_program_channel_remap(struct radeon_device *rdev) |
| 540 | { |
| 541 | u32 tcp_chan_steer, mc_shared_chremap, tmp; |
| 542 | bool force_no_swizzle; |
| 543 | |
| 544 | switch (rdev->family) { |
| 545 | case CHIP_RV770: |
| 546 | case CHIP_RV730: |
| 547 | force_no_swizzle = false; |
| 548 | break; |
| 549 | case CHIP_RV710: |
| 550 | case CHIP_RV740: |
| 551 | default: |
| 552 | force_no_swizzle = true; |
| 553 | break; |
| 554 | } |
| 555 | |
| 556 | tmp = RREG32(MC_SHARED_CHMAP); |
| 557 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 558 | case 0: |
| 559 | case 1: |
| 560 | default: |
| 561 | /* default mapping */ |
| 562 | mc_shared_chremap = 0x00fac688; |
| 563 | break; |
| 564 | case 2: |
| 565 | case 3: |
| 566 | if (force_no_swizzle) |
| 567 | mc_shared_chremap = 0x00fac688; |
| 568 | else |
| 569 | mc_shared_chremap = 0x00bbc298; |
| 570 | break; |
| 571 | } |
| 572 | |
| 573 | if (rdev->family == CHIP_RV740) |
| 574 | tcp_chan_steer = 0x00ef2a60; |
| 575 | else |
| 576 | tcp_chan_steer = 0x00fac688; |
| 577 | |
Alex Deucher | daf54f1 | 2011-06-30 08:59:55 -0400 | [diff] [blame^] | 578 | /* RV770 CE has special chremap setup */ |
| 579 | if (rdev->pdev->device == 0x944e) { |
| 580 | tcp_chan_steer = 0x00b08b08; |
| 581 | mc_shared_chremap = 0x00b08b08; |
| 582 | } |
| 583 | |
Alex Deucher | 9535ab7 | 2010-11-22 17:56:18 -0500 | [diff] [blame] | 584 | WREG32(TCP_CHAN_STEER, tcp_chan_steer); |
| 585 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); |
| 586 | } |
| 587 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 588 | static void rv770_gpu_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 589 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 590 | int i, j, num_qd_pipes; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 591 | u32 ta_aux_cntl; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 592 | u32 sx_debug_1; |
| 593 | u32 smx_dc_ctl0; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 594 | u32 db_debug3; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 595 | u32 num_gs_verts_per_thread; |
| 596 | u32 vgt_gs_per_es; |
| 597 | u32 gs_prim_buffer_depth = 0; |
| 598 | u32 sq_ms_fifo_sizes; |
| 599 | u32 sq_config; |
| 600 | u32 sq_thread_resource_mgmt; |
| 601 | u32 hdp_host_path_cntl; |
| 602 | u32 sq_dyn_gpr_size_simd_ab_0; |
| 603 | u32 backend_map; |
| 604 | u32 gb_tiling_config = 0; |
| 605 | u32 cc_rb_backend_disable = 0; |
| 606 | u32 cc_gc_shader_pipe_config = 0; |
| 607 | u32 mc_arb_ramcfg; |
| 608 | u32 db_debug4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 609 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 610 | /* setup chip specs */ |
| 611 | switch (rdev->family) { |
| 612 | case CHIP_RV770: |
| 613 | rdev->config.rv770.max_pipes = 4; |
| 614 | rdev->config.rv770.max_tile_pipes = 8; |
| 615 | rdev->config.rv770.max_simds = 10; |
| 616 | rdev->config.rv770.max_backends = 4; |
| 617 | rdev->config.rv770.max_gprs = 256; |
| 618 | rdev->config.rv770.max_threads = 248; |
| 619 | rdev->config.rv770.max_stack_entries = 512; |
| 620 | rdev->config.rv770.max_hw_contexts = 8; |
| 621 | rdev->config.rv770.max_gs_threads = 16 * 2; |
| 622 | rdev->config.rv770.sx_max_export_size = 128; |
| 623 | rdev->config.rv770.sx_max_export_pos_size = 16; |
| 624 | rdev->config.rv770.sx_max_export_smx_size = 112; |
| 625 | rdev->config.rv770.sq_num_cf_insts = 2; |
| 626 | |
| 627 | rdev->config.rv770.sx_num_of_sets = 7; |
| 628 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
| 629 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 630 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 631 | break; |
| 632 | case CHIP_RV730: |
| 633 | rdev->config.rv770.max_pipes = 2; |
| 634 | rdev->config.rv770.max_tile_pipes = 4; |
| 635 | rdev->config.rv770.max_simds = 8; |
| 636 | rdev->config.rv770.max_backends = 2; |
| 637 | rdev->config.rv770.max_gprs = 128; |
| 638 | rdev->config.rv770.max_threads = 248; |
| 639 | rdev->config.rv770.max_stack_entries = 256; |
| 640 | rdev->config.rv770.max_hw_contexts = 8; |
| 641 | rdev->config.rv770.max_gs_threads = 16 * 2; |
| 642 | rdev->config.rv770.sx_max_export_size = 256; |
| 643 | rdev->config.rv770.sx_max_export_pos_size = 32; |
| 644 | rdev->config.rv770.sx_max_export_smx_size = 224; |
| 645 | rdev->config.rv770.sq_num_cf_insts = 2; |
| 646 | |
| 647 | rdev->config.rv770.sx_num_of_sets = 7; |
| 648 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
| 649 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 650 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 651 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
| 652 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
| 653 | rdev->config.rv770.sx_max_export_smx_size += 16; |
| 654 | } |
| 655 | break; |
| 656 | case CHIP_RV710: |
| 657 | rdev->config.rv770.max_pipes = 2; |
| 658 | rdev->config.rv770.max_tile_pipes = 2; |
| 659 | rdev->config.rv770.max_simds = 2; |
| 660 | rdev->config.rv770.max_backends = 1; |
| 661 | rdev->config.rv770.max_gprs = 256; |
| 662 | rdev->config.rv770.max_threads = 192; |
| 663 | rdev->config.rv770.max_stack_entries = 256; |
| 664 | rdev->config.rv770.max_hw_contexts = 4; |
| 665 | rdev->config.rv770.max_gs_threads = 8 * 2; |
| 666 | rdev->config.rv770.sx_max_export_size = 128; |
| 667 | rdev->config.rv770.sx_max_export_pos_size = 16; |
| 668 | rdev->config.rv770.sx_max_export_smx_size = 112; |
| 669 | rdev->config.rv770.sq_num_cf_insts = 1; |
| 670 | |
| 671 | rdev->config.rv770.sx_num_of_sets = 7; |
| 672 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
| 673 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 674 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 675 | break; |
| 676 | case CHIP_RV740: |
| 677 | rdev->config.rv770.max_pipes = 4; |
| 678 | rdev->config.rv770.max_tile_pipes = 4; |
| 679 | rdev->config.rv770.max_simds = 8; |
| 680 | rdev->config.rv770.max_backends = 4; |
| 681 | rdev->config.rv770.max_gprs = 256; |
| 682 | rdev->config.rv770.max_threads = 248; |
| 683 | rdev->config.rv770.max_stack_entries = 512; |
| 684 | rdev->config.rv770.max_hw_contexts = 8; |
| 685 | rdev->config.rv770.max_gs_threads = 16 * 2; |
| 686 | rdev->config.rv770.sx_max_export_size = 256; |
| 687 | rdev->config.rv770.sx_max_export_pos_size = 32; |
| 688 | rdev->config.rv770.sx_max_export_smx_size = 224; |
| 689 | rdev->config.rv770.sq_num_cf_insts = 2; |
| 690 | |
| 691 | rdev->config.rv770.sx_num_of_sets = 7; |
| 692 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
| 693 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 694 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 695 | |
| 696 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
| 697 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
| 698 | rdev->config.rv770.sx_max_export_smx_size += 16; |
| 699 | } |
| 700 | break; |
| 701 | default: |
| 702 | break; |
| 703 | } |
| 704 | |
| 705 | /* Initialize HDP */ |
| 706 | j = 0; |
| 707 | for (i = 0; i < 32; i++) { |
| 708 | WREG32((0x2c14 + j), 0x00000000); |
| 709 | WREG32((0x2c18 + j), 0x00000000); |
| 710 | WREG32((0x2c1c + j), 0x00000000); |
| 711 | WREG32((0x2c20 + j), 0x00000000); |
| 712 | WREG32((0x2c24 + j), 0x00000000); |
| 713 | j += 0x18; |
| 714 | } |
| 715 | |
| 716 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
| 717 | |
| 718 | /* setup tiling, simd, pipe config */ |
| 719 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
| 720 | |
| 721 | switch (rdev->config.rv770.max_tile_pipes) { |
| 722 | case 1: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 723 | default: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 724 | gb_tiling_config |= PIPE_TILING(0); |
| 725 | break; |
| 726 | case 2: |
| 727 | gb_tiling_config |= PIPE_TILING(1); |
| 728 | break; |
| 729 | case 4: |
| 730 | gb_tiling_config |= PIPE_TILING(2); |
| 731 | break; |
| 732 | case 8: |
| 733 | gb_tiling_config |= PIPE_TILING(3); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 734 | break; |
| 735 | } |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 736 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 737 | |
| 738 | if (rdev->family == CHIP_RV770) |
| 739 | gb_tiling_config |= BANK_TILING(1); |
| 740 | else |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 741 | gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
Jerome Glisse | 961fb59 | 2010-02-10 22:30:05 +0000 | [diff] [blame] | 742 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
Alex Deucher | 881fe6c | 2010-10-18 23:54:56 -0400 | [diff] [blame] | 743 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
| 744 | if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) |
| 745 | rdev->config.rv770.tiling_group_size = 512; |
| 746 | else |
| 747 | rdev->config.rv770.tiling_group_size = 256; |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 748 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 749 | gb_tiling_config |= ROW_TILING(3); |
| 750 | gb_tiling_config |= SAMPLE_SPLIT(3); |
| 751 | } else { |
| 752 | gb_tiling_config |= |
| 753 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
| 754 | gb_tiling_config |= |
| 755 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
| 756 | } |
| 757 | |
| 758 | gb_tiling_config |= BANK_SWAPS(1); |
| 759 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 760 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
| 761 | cc_rb_backend_disable |= |
| 762 | BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 763 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 764 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
| 765 | cc_gc_shader_pipe_config |= |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 766 | INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); |
| 767 | cc_gc_shader_pipe_config |= |
| 768 | INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); |
| 769 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 770 | if (rdev->family == CHIP_RV740) |
| 771 | backend_map = 0x28; |
| 772 | else |
| 773 | backend_map = r700_get_tile_pipe_to_backend_map(rdev, |
| 774 | rdev->config.rv770.max_tile_pipes, |
| 775 | (R7XX_MAX_BACKENDS - |
| 776 | r600_count_pipe_bits((cc_rb_backend_disable & |
| 777 | R7XX_MAX_BACKENDS_MASK) >> 16)), |
| 778 | (cc_rb_backend_disable >> 16)); |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 779 | |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 780 | rdev->config.rv770.tile_config = gb_tiling_config; |
| 781 | gb_tiling_config |= BACKEND_MAP(backend_map); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 782 | |
| 783 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
| 784 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 785 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 786 | |
Alex Deucher | 9535ab7 | 2010-11-22 17:56:18 -0500 | [diff] [blame] | 787 | rv770_program_channel_remap(rdev); |
| 788 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 789 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
| 790 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
Alex Deucher | f867c60d | 2010-03-05 14:50:37 -0500 | [diff] [blame] | 791 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 792 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 793 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 794 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
| 795 | WREG32(CGTS_TCC_DISABLE, 0); |
Alex Deucher | f867c60d | 2010-03-05 14:50:37 -0500 | [diff] [blame] | 796 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
| 797 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 798 | |
| 799 | num_qd_pipes = |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 800 | R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 801 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
| 802 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
| 803 | |
| 804 | /* set HW defaults for 3D engine */ |
| 805 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 806 | ROQ_IB2_START(0x2b))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 807 | |
| 808 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
| 809 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 810 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
| 811 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 812 | |
| 813 | sx_debug_1 = RREG32(SX_DEBUG_1); |
| 814 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
| 815 | WREG32(SX_DEBUG_1, sx_debug_1); |
| 816 | |
| 817 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
| 818 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
| 819 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
| 820 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
| 821 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 822 | if (rdev->family != CHIP_RV740) |
| 823 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
| 824 | GS_FLUSH_CTL(4) | |
| 825 | ACK_FLUSH_CTL(3) | |
| 826 | SYNC_FLUSH_CTL)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 827 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 828 | db_debug3 = RREG32(DB_DEBUG3); |
| 829 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
| 830 | switch (rdev->family) { |
| 831 | case CHIP_RV770: |
| 832 | case CHIP_RV740: |
| 833 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
| 834 | break; |
| 835 | case CHIP_RV710: |
| 836 | case CHIP_RV730: |
| 837 | default: |
| 838 | db_debug3 |= DB_CLK_OFF_DELAY(2); |
| 839 | break; |
| 840 | } |
| 841 | WREG32(DB_DEBUG3, db_debug3); |
| 842 | |
| 843 | if (rdev->family != CHIP_RV770) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 844 | db_debug4 = RREG32(DB_DEBUG4); |
| 845 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
| 846 | WREG32(DB_DEBUG4, db_debug4); |
| 847 | } |
| 848 | |
| 849 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 850 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
| 851 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 852 | |
| 853 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 854 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
| 855 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 856 | |
| 857 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 858 | |
| 859 | WREG32(VGT_NUM_INSTANCES, 1); |
| 860 | |
| 861 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); |
| 862 | |
| 863 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
| 864 | |
| 865 | WREG32(CP_PERFMON_CNTL, 0); |
| 866 | |
| 867 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
| 868 | DONE_FIFO_HIWATER(0xe0) | |
| 869 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
| 870 | switch (rdev->family) { |
| 871 | case CHIP_RV770: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 872 | case CHIP_RV730: |
| 873 | case CHIP_RV710: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 874 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
| 875 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 876 | case CHIP_RV740: |
| 877 | default: |
| 878 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
| 879 | break; |
| 880 | } |
| 881 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
| 882 | |
| 883 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
| 884 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
| 885 | */ |
| 886 | sq_config = RREG32(SQ_CONFIG); |
| 887 | sq_config &= ~(PS_PRIO(3) | |
| 888 | VS_PRIO(3) | |
| 889 | GS_PRIO(3) | |
| 890 | ES_PRIO(3)); |
| 891 | sq_config |= (DX9_CONSTS | |
| 892 | VC_ENABLE | |
| 893 | EXPORT_SRC_C | |
| 894 | PS_PRIO(0) | |
| 895 | VS_PRIO(1) | |
| 896 | GS_PRIO(2) | |
| 897 | ES_PRIO(3)); |
| 898 | if (rdev->family == CHIP_RV710) |
| 899 | /* no vertex cache */ |
| 900 | sq_config &= ~VC_ENABLE; |
| 901 | |
| 902 | WREG32(SQ_CONFIG, sq_config); |
| 903 | |
| 904 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 905 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
| 906 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 907 | |
| 908 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 909 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 910 | |
| 911 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
| 912 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
| 913 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
| 914 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
| 915 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
| 916 | else |
| 917 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
| 918 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
| 919 | |
| 920 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
| 921 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
| 922 | |
| 923 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
| 924 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
| 925 | |
| 926 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
| 927 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
| 928 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
| 929 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
| 930 | |
| 931 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
| 932 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
| 933 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
| 934 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
| 935 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
| 936 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
| 937 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
| 938 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
| 939 | |
| 940 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 941 | FORCE_EOV_MAX_REZ_CNT(255))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 942 | |
| 943 | if (rdev->family == CHIP_RV710) |
| 944 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 945 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 946 | else |
| 947 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 948 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 949 | |
| 950 | switch (rdev->family) { |
| 951 | case CHIP_RV770: |
| 952 | case CHIP_RV730: |
| 953 | case CHIP_RV740: |
| 954 | gs_prim_buffer_depth = 384; |
| 955 | break; |
| 956 | case CHIP_RV710: |
| 957 | gs_prim_buffer_depth = 128; |
| 958 | break; |
| 959 | default: |
| 960 | break; |
| 961 | } |
| 962 | |
| 963 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
| 964 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
| 965 | /* Max value for this is 256 */ |
| 966 | if (vgt_gs_per_es > 256) |
| 967 | vgt_gs_per_es = 256; |
| 968 | |
| 969 | WREG32(VGT_ES_PER_GS, 128); |
| 970 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
| 971 | WREG32(VGT_GS_PER_VS, 2); |
| 972 | |
| 973 | /* more default values. 2D/3D driver should adjust as needed */ |
| 974 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
| 975 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
| 976 | WREG32(VGT_STRMOUT_EN, 0); |
| 977 | WREG32(SX_MISC, 0); |
| 978 | WREG32(PA_SC_MODE_CNTL, 0); |
| 979 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
| 980 | WREG32(PA_SC_AA_CONFIG, 0); |
| 981 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
| 982 | WREG32(PA_SC_LINE_STIPPLE, 0); |
| 983 | WREG32(SPI_INPUT_Z, 0); |
| 984 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
| 985 | WREG32(CB_COLOR7_FRAG, 0); |
| 986 | |
| 987 | /* clear render buffer base addresses */ |
| 988 | WREG32(CB_COLOR0_BASE, 0); |
| 989 | WREG32(CB_COLOR1_BASE, 0); |
| 990 | WREG32(CB_COLOR2_BASE, 0); |
| 991 | WREG32(CB_COLOR3_BASE, 0); |
| 992 | WREG32(CB_COLOR4_BASE, 0); |
| 993 | WREG32(CB_COLOR5_BASE, 0); |
| 994 | WREG32(CB_COLOR6_BASE, 0); |
| 995 | WREG32(CB_COLOR7_BASE, 0); |
| 996 | |
| 997 | WREG32(TCP_CNTL, 0); |
| 998 | |
| 999 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
| 1000 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
| 1001 | |
| 1002 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1003 | |
| 1004 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
| 1005 | NUM_CLIP_SEQ(3))); |
| 1006 | |
| 1007 | } |
| 1008 | |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1009 | static int rv770_vram_scratch_init(struct radeon_device *rdev) |
| 1010 | { |
| 1011 | int r; |
| 1012 | u64 gpu_addr; |
| 1013 | |
| 1014 | if (rdev->vram_scratch.robj == NULL) { |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 1015 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 1016 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
| 1017 | &rdev->vram_scratch.robj); |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1018 | if (r) { |
| 1019 | return r; |
| 1020 | } |
| 1021 | } |
| 1022 | |
| 1023 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
| 1024 | if (unlikely(r != 0)) |
| 1025 | return r; |
| 1026 | r = radeon_bo_pin(rdev->vram_scratch.robj, |
| 1027 | RADEON_GEM_DOMAIN_VRAM, &gpu_addr); |
| 1028 | if (r) { |
| 1029 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1030 | return r; |
| 1031 | } |
| 1032 | r = radeon_bo_kmap(rdev->vram_scratch.robj, |
| 1033 | (void **)&rdev->vram_scratch.ptr); |
| 1034 | if (r) |
| 1035 | radeon_bo_unpin(rdev->vram_scratch.robj); |
| 1036 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1037 | |
| 1038 | return r; |
| 1039 | } |
| 1040 | |
| 1041 | static void rv770_vram_scratch_fini(struct radeon_device *rdev) |
| 1042 | { |
| 1043 | int r; |
| 1044 | |
| 1045 | if (rdev->vram_scratch.robj == NULL) { |
| 1046 | return; |
| 1047 | } |
| 1048 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
| 1049 | if (likely(r == 0)) { |
| 1050 | radeon_bo_kunmap(rdev->vram_scratch.robj); |
| 1051 | radeon_bo_unpin(rdev->vram_scratch.robj); |
| 1052 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1053 | } |
| 1054 | radeon_bo_unref(&rdev->vram_scratch.robj); |
| 1055 | } |
| 1056 | |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1057 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
| 1058 | { |
| 1059 | u64 size_bf, size_af; |
| 1060 | |
| 1061 | if (mc->mc_vram_size > 0xE0000000) { |
| 1062 | /* leave room for at least 512M GTT */ |
| 1063 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1064 | mc->real_vram_size = 0xE0000000; |
| 1065 | mc->mc_vram_size = 0xE0000000; |
| 1066 | } |
| 1067 | if (rdev->flags & RADEON_IS_AGP) { |
| 1068 | size_bf = mc->gtt_start; |
| 1069 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; |
| 1070 | if (size_bf > size_af) { |
| 1071 | if (mc->mc_vram_size > size_bf) { |
| 1072 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1073 | mc->real_vram_size = size_bf; |
| 1074 | mc->mc_vram_size = size_bf; |
| 1075 | } |
| 1076 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
| 1077 | } else { |
| 1078 | if (mc->mc_vram_size > size_af) { |
| 1079 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1080 | mc->real_vram_size = size_af; |
| 1081 | mc->mc_vram_size = size_af; |
| 1082 | } |
| 1083 | mc->vram_start = mc->gtt_end; |
| 1084 | } |
| 1085 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
| 1086 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
| 1087 | mc->mc_vram_size >> 20, mc->vram_start, |
| 1088 | mc->vram_end, mc->real_vram_size >> 20); |
| 1089 | } else { |
Alex Deucher | b4183e3 | 2010-12-15 11:04:10 -0500 | [diff] [blame] | 1090 | radeon_vram_location(rdev, &rdev->mc, 0); |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1091 | rdev->mc.gtt_base_align = 0; |
| 1092 | radeon_gtt_location(rdev, mc); |
| 1093 | } |
| 1094 | } |
| 1095 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1096 | int rv770_mc_init(struct radeon_device *rdev) |
| 1097 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1098 | u32 tmp; |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1099 | int chansize, numchan; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1100 | |
| 1101 | /* Get VRAM informations */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1102 | rdev->mc.vram_is_ddr = true; |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1103 | tmp = RREG32(MC_ARB_RAMCFG); |
| 1104 | if (tmp & CHANSIZE_OVERRIDE) { |
| 1105 | chansize = 16; |
| 1106 | } else if (tmp & CHANSIZE_MASK) { |
| 1107 | chansize = 64; |
| 1108 | } else { |
| 1109 | chansize = 32; |
| 1110 | } |
| 1111 | tmp = RREG32(MC_SHARED_CHMAP); |
| 1112 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 1113 | case 0: |
| 1114 | default: |
| 1115 | numchan = 1; |
| 1116 | break; |
| 1117 | case 1: |
| 1118 | numchan = 2; |
| 1119 | break; |
| 1120 | case 2: |
| 1121 | numchan = 4; |
| 1122 | break; |
| 1123 | case 3: |
| 1124 | numchan = 8; |
| 1125 | break; |
| 1126 | } |
| 1127 | rdev->mc.vram_width = numchan * chansize; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1128 | /* Could aper size report 0 ? */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 1129 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 1130 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1131 | /* Setup GPU memory space */ |
| 1132 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
| 1133 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 1134 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1135 | r700_vram_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1136 | radeon_update_bandwidth_info(rdev); |
| 1137 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1138 | return 0; |
| 1139 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1140 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1141 | static int rv770_startup(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1142 | { |
| 1143 | int r; |
| 1144 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1145 | /* enable pcie gen2 link */ |
| 1146 | rv770_pcie_gen2_enable(rdev); |
| 1147 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 1148 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
| 1149 | r = r600_init_microcode(rdev); |
| 1150 | if (r) { |
| 1151 | DRM_ERROR("Failed to load firmware!\n"); |
| 1152 | return r; |
| 1153 | } |
| 1154 | } |
| 1155 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1156 | rv770_mc_program(rdev); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1157 | if (rdev->flags & RADEON_IS_AGP) { |
| 1158 | rv770_agp_enable(rdev); |
| 1159 | } else { |
| 1160 | r = rv770_pcie_gart_enable(rdev); |
| 1161 | if (r) |
| 1162 | return r; |
| 1163 | } |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1164 | r = rv770_vram_scratch_init(rdev); |
| 1165 | if (r) |
| 1166 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1167 | rv770_gpu_init(rdev); |
Jerome Glisse | c38c7b6 | 2010-02-04 17:27:27 +0100 | [diff] [blame] | 1168 | r = r600_blit_init(rdev); |
| 1169 | if (r) { |
| 1170 | r600_blit_fini(rdev); |
| 1171 | rdev->asic->copy = NULL; |
| 1172 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| 1173 | } |
Alex Deucher | b70d6bb | 2010-08-06 21:36:58 -0400 | [diff] [blame] | 1174 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1175 | /* allocate wb buffer */ |
| 1176 | r = radeon_wb_init(rdev); |
| 1177 | if (r) |
| 1178 | return r; |
| 1179 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1180 | /* Enable IRQ */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1181 | r = r600_irq_init(rdev); |
| 1182 | if (r) { |
| 1183 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| 1184 | radeon_irq_kms_fini(rdev); |
| 1185 | return r; |
| 1186 | } |
| 1187 | r600_irq_set(rdev); |
| 1188 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1189 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| 1190 | if (r) |
| 1191 | return r; |
| 1192 | r = rv770_cp_load_microcode(rdev); |
| 1193 | if (r) |
| 1194 | return r; |
| 1195 | r = r600_cp_resume(rdev); |
| 1196 | if (r) |
| 1197 | return r; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1198 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1199 | return 0; |
| 1200 | } |
| 1201 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1202 | int rv770_resume(struct radeon_device *rdev) |
| 1203 | { |
| 1204 | int r; |
| 1205 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1206 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
| 1207 | * posting will perform necessary task to bring back GPU into good |
| 1208 | * shape. |
| 1209 | */ |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1210 | /* post card */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1211 | atom_asic_init(rdev->mode_info.atom_context); |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1212 | |
| 1213 | r = rv770_startup(rdev); |
| 1214 | if (r) { |
| 1215 | DRM_ERROR("r600 startup failed on resume\n"); |
| 1216 | return r; |
| 1217 | } |
| 1218 | |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 1219 | r = r600_ib_test(rdev); |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1220 | if (r) { |
Paul Bolle | ec4f2ac | 2011-01-28 23:32:04 +0100 | [diff] [blame] | 1221 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1222 | return r; |
| 1223 | } |
Rafał Miłecki | 8a8c6e7 | 2010-03-06 13:03:36 +0000 | [diff] [blame] | 1224 | |
| 1225 | r = r600_audio_init(rdev); |
| 1226 | if (r) { |
| 1227 | dev_err(rdev->dev, "radeon: audio init failed\n"); |
| 1228 | return r; |
| 1229 | } |
| 1230 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1231 | return r; |
| 1232 | |
| 1233 | } |
| 1234 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1235 | int rv770_suspend(struct radeon_device *rdev) |
| 1236 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1237 | int r; |
| 1238 | |
Rafał Miłecki | 8a8c6e7 | 2010-03-06 13:03:36 +0000 | [diff] [blame] | 1239 | r600_audio_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1240 | /* FIXME: we should wait for ring to be empty */ |
| 1241 | r700_cp_stop(rdev); |
Dave Airlie | 4153e58 | 2009-09-18 18:41:24 +1000 | [diff] [blame] | 1242 | rdev->cp.ready = false; |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 1243 | r600_irq_suspend(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1244 | radeon_wb_disable(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1245 | rv770_pcie_gart_disable(rdev); |
Dave Airlie | 4153e58 | 2009-09-18 18:41:24 +1000 | [diff] [blame] | 1246 | /* unpin shaders bo */ |
Jerome Glisse | 30d2d9a | 2010-01-13 10:29:27 +0100 | [diff] [blame] | 1247 | if (rdev->r600_blit.shader_obj) { |
| 1248 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 1249 | if (likely(r == 0)) { |
| 1250 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
| 1251 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 1252 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1253 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1254 | return 0; |
| 1255 | } |
| 1256 | |
| 1257 | /* Plan is to move initialization in that function and use |
| 1258 | * helper function so that radeon_device_init pretty much |
| 1259 | * do nothing more than calling asic specific function. This |
| 1260 | * should also allow to remove a bunch of callback function |
| 1261 | * like vram_info. |
| 1262 | */ |
| 1263 | int rv770_init(struct radeon_device *rdev) |
| 1264 | { |
| 1265 | int r; |
| 1266 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1267 | /* This don't do much */ |
| 1268 | r = radeon_gem_init(rdev); |
| 1269 | if (r) |
| 1270 | return r; |
| 1271 | /* Read BIOS */ |
| 1272 | if (!radeon_get_bios(rdev)) { |
| 1273 | if (ASIC_IS_AVIVO(rdev)) |
| 1274 | return -EINVAL; |
| 1275 | } |
| 1276 | /* Must be an ATOMBIOS */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1277 | if (!rdev->is_atom_bios) { |
| 1278 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1279 | return -EINVAL; |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1280 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1281 | r = radeon_atombios_init(rdev); |
| 1282 | if (r) |
| 1283 | return r; |
| 1284 | /* Post card if necessary */ |
Alex Deucher | fd909c3 | 2011-01-11 18:08:59 -0500 | [diff] [blame] | 1285 | if (!radeon_card_posted(rdev)) { |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1286 | if (!rdev->bios) { |
| 1287 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 1288 | return -EINVAL; |
| 1289 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1290 | DRM_INFO("GPU not posted. posting now...\n"); |
| 1291 | atom_asic_init(rdev->mode_info.atom_context); |
| 1292 | } |
| 1293 | /* Initialize scratch registers */ |
| 1294 | r600_scratch_init(rdev); |
| 1295 | /* Initialize surface registers */ |
| 1296 | radeon_surface_init(rdev); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1297 | /* Initialize clocks */ |
Michel Dänzer | 5e6dde7 | 2009-09-17 09:42:28 +0200 | [diff] [blame] | 1298 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1299 | /* Fence driver */ |
| 1300 | r = radeon_fence_driver_init(rdev); |
| 1301 | if (r) |
| 1302 | return r; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1303 | /* initialize AGP */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1304 | if (rdev->flags & RADEON_IS_AGP) { |
| 1305 | r = radeon_agp_init(rdev); |
| 1306 | if (r) |
| 1307 | radeon_agp_disable(rdev); |
| 1308 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1309 | r = rv770_mc_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 1310 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1311 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1312 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1313 | r = radeon_bo_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1314 | if (r) |
| 1315 | return r; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1316 | |
| 1317 | r = radeon_irq_kms_init(rdev); |
| 1318 | if (r) |
| 1319 | return r; |
| 1320 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1321 | rdev->cp.ring_obj = NULL; |
| 1322 | r600_ring_init(rdev, 1024 * 1024); |
| 1323 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1324 | rdev->ih.ring_obj = NULL; |
| 1325 | r600_ih_ring_init(rdev, 64 * 1024); |
| 1326 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1327 | r = r600_pcie_gart_init(rdev); |
| 1328 | if (r) |
| 1329 | return r; |
| 1330 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 1331 | rdev->accel_working = true; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1332 | r = rv770_startup(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1333 | if (r) { |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1334 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1335 | r700_cp_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1336 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1337 | radeon_wb_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1338 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 75c8129 | 2009-10-01 18:02:14 +0200 | [diff] [blame] | 1339 | rv770_pcie_gart_fini(rdev); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1340 | rdev->accel_working = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1341 | } |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1342 | if (rdev->accel_working) { |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1343 | r = radeon_ib_pool_init(rdev); |
| 1344 | if (r) { |
Jerome Glisse | db96380 | 2010-01-17 21:21:56 +0100 | [diff] [blame] | 1345 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1346 | rdev->accel_working = false; |
Jerome Glisse | db96380 | 2010-01-17 21:21:56 +0100 | [diff] [blame] | 1347 | } else { |
| 1348 | r = r600_ib_test(rdev); |
| 1349 | if (r) { |
| 1350 | dev_err(rdev->dev, "IB test failed (%d).\n", r); |
| 1351 | rdev->accel_working = false; |
| 1352 | } |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1353 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1354 | } |
Rafał Miłecki | 8a8c6e7 | 2010-03-06 13:03:36 +0000 | [diff] [blame] | 1355 | |
| 1356 | r = r600_audio_init(rdev); |
| 1357 | if (r) { |
| 1358 | dev_err(rdev->dev, "radeon: audio init failed\n"); |
| 1359 | return r; |
| 1360 | } |
| 1361 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | void rv770_fini(struct radeon_device *rdev) |
| 1366 | { |
| 1367 | r600_blit_fini(rdev); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1368 | r700_cp_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1369 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1370 | radeon_wb_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1371 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1372 | rv770_pcie_gart_fini(rdev); |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1373 | rv770_vram_scratch_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1374 | radeon_gem_fini(rdev); |
| 1375 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | d0269ed | 2010-01-07 16:08:32 +0100 | [diff] [blame] | 1376 | radeon_agp_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1377 | radeon_bo_fini(rdev); |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1378 | radeon_atombios_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1379 | kfree(rdev->bios); |
| 1380 | rdev->bios = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1381 | } |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1382 | |
| 1383 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
| 1384 | { |
| 1385 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
| 1386 | u16 link_cntl2; |
| 1387 | |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 1388 | if (radeon_pcie_gen2 == 0) |
| 1389 | return; |
| 1390 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1391 | if (rdev->flags & RADEON_IS_IGP) |
| 1392 | return; |
| 1393 | |
| 1394 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 1395 | return; |
| 1396 | |
| 1397 | /* x2 cards have a special sequence */ |
| 1398 | if (ASIC_IS_X2(rdev)) |
| 1399 | return; |
| 1400 | |
| 1401 | /* advertise upconfig capability */ |
| 1402 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 1403 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
| 1404 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 1405 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 1406 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
| 1407 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
| 1408 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
| 1409 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
| 1410 | link_width_cntl |= lanes | LC_RECONFIG_NOW | |
| 1411 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
| 1412 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 1413 | } else { |
| 1414 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 1415 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 1416 | } |
| 1417 | |
| 1418 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 1419 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
| 1420 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
| 1421 | |
| 1422 | tmp = RREG32(0x541c); |
| 1423 | WREG32(0x541c, tmp | 0x8); |
| 1424 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
| 1425 | link_cntl2 = RREG16(0x4088); |
| 1426 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
| 1427 | link_cntl2 |= 0x2; |
| 1428 | WREG16(0x4088, link_cntl2); |
| 1429 | WREG32(MM_CFGREGS_CNTL, 0); |
| 1430 | |
| 1431 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 1432 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
| 1433 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 1434 | |
| 1435 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 1436 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
| 1437 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 1438 | |
| 1439 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 1440 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
| 1441 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 1442 | |
| 1443 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 1444 | speed_cntl |= LC_GEN2_EN_STRAP; |
| 1445 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 1446 | |
| 1447 | } else { |
| 1448 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 1449 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
| 1450 | if (1) |
| 1451 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 1452 | else |
| 1453 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
| 1454 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 1455 | } |
| 1456 | } |