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Grant Likelyc103de22011-06-04 18:38:28 -06001/*
David Cohena0bbf032014-01-17 07:30:01 -08002 * Intel MID GPIO driver
Grant Likelyc103de22011-06-04 18:38:28 -06003 *
David Cohena0bbf032014-01-17 07:30:01 -08004 * Copyright (c) 2008-2014 Intel Corporation.
Alek Du8bf02612009-09-22 16:46:36 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Alek Du8bf02612009-09-22 16:46:36 -070014 */
15
16/* Supports:
17 * Moorestown platform Langwell chip.
Alek Du8081c842010-05-26 14:42:25 -070018 * Medfield platform Penwell chip.
David Cohenf89a7682013-10-04 13:01:42 -070019 * Clovertrail platform Cloverview chip.
20 * Merrifield platform Tangier chip.
Alek Du8bf02612009-09-22 16:46:36 -070021 */
22
23#include <linux/module.h>
24#include <linux/pci.h>
Alan Cox72b43792010-10-27 15:33:23 -070025#include <linux/platform_device.h>
Alek Du8bf02612009-09-22 16:46:36 -070026#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/stddef.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
Alek Du8bf02612009-09-22 16:46:36 -070031#include <linux/io.h>
Linus Walleij3f7dbfd2014-05-29 16:55:55 +020032#include <linux/gpio/driver.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010034#include <linux/pm_runtime.h>
Alek Du8bf02612009-09-22 16:46:36 -070035
David Cohenf89a7682013-10-04 13:01:42 -070036#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
37#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
David Cohend56d6b32013-10-04 13:01:40 -070038
Alek Du8081c842010-05-26 14:42:25 -070039/*
40 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
41 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
42 * registers to control them, so we only define the order here instead of a
43 * structure, to get a bit offset for a pin (use GPDR as an example):
44 *
45 * nreg = ngpio / 32;
46 * reg = offset / 32;
47 * bit = offset % 32;
48 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
49 *
50 * so the bit of reg_addr is to control pin offset's GPDR feature
51*/
52
53enum GPIO_REG {
54 GPLR = 0, /* pin level read-only */
55 GPDR, /* pin direction */
56 GPSR, /* pin set */
57 GPCR, /* pin clear */
58 GRER, /* rising edge detect */
59 GFER, /* falling edge detect */
60 GEDR, /* edge detect result */
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030061 GAFR, /* alt function */
Alek Du8bf02612009-09-22 16:46:36 -070062};
63
David Cohenf89a7682013-10-04 13:01:42 -070064/* intel_mid gpio driver data */
65struct intel_mid_gpio_ddata {
David Cohend56d6b32013-10-04 13:01:40 -070066 u16 ngpio; /* number of gpio pins */
67 u32 gplr_offset; /* offset of first GPLR register from base */
68 u32 flis_base; /* base address of FLIS registers */
69 u32 flis_len; /* length of FLIS registers */
70 u32 (*get_flis_offset)(int gpio);
71 u32 chip_irq_type; /* chip interrupt type */
72};
73
David Cohenf89a7682013-10-04 13:01:42 -070074struct intel_mid_gpio {
Alek Du8bf02612009-09-22 16:46:36 -070075 struct gpio_chip chip;
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +030076 void __iomem *reg_base;
Alek Du8bf02612009-09-22 16:46:36 -070077 spinlock_t lock;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010078 struct pci_dev *pdev;
Alek Du8bf02612009-09-22 16:46:36 -070079};
80
Linus Walleij3f7dbfd2014-05-29 16:55:55 +020081static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc)
82{
83 return container_of(gc, struct intel_mid_gpio, chip);
84}
David Cohen46ebfbc2012-12-20 14:45:51 -080085
Alek Du8081c842010-05-26 14:42:25 -070086static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
Andy Shevchenko611a4852013-05-22 13:20:14 +030087 enum GPIO_REG reg_type)
Alek Du8bf02612009-09-22 16:46:36 -070088{
David Cohenf89a7682013-10-04 13:01:42 -070089 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -070090 unsigned nreg = chip->ngpio / 32;
Alek Du8bf02612009-09-22 16:46:36 -070091 u8 reg = offset / 32;
Alek Du8bf02612009-09-22 16:46:36 -070092
David Cohenf89a7682013-10-04 13:01:42 -070093 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Alek Du8081c842010-05-26 14:42:25 -070094}
95
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030096static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
97 enum GPIO_REG reg_type)
98{
David Cohenf89a7682013-10-04 13:01:42 -070099 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300100 unsigned nreg = chip->ngpio / 32;
101 u8 reg = offset / 16;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300102
David Cohenf89a7682013-10-04 13:01:42 -0700103 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300104}
105
David Cohenf89a7682013-10-04 13:01:42 -0700106static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300107{
108 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
109 u32 value = readl(gafr);
110 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
111
112 if (af) {
113 value &= ~(3 << shift);
114 writel(value, gafr);
115 }
116 return 0;
117}
118
David Cohenf89a7682013-10-04 13:01:42 -0700119static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
Alek Du8081c842010-05-26 14:42:25 -0700120{
121 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
122
Alek Du8bf02612009-09-22 16:46:36 -0700123 return readl(gplr) & BIT(offset % 32);
124}
125
David Cohenf89a7682013-10-04 13:01:42 -0700126static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
Alek Du8bf02612009-09-22 16:46:36 -0700127{
Alek Du8bf02612009-09-22 16:46:36 -0700128 void __iomem *gpsr, *gpcr;
129
130 if (value) {
Alek Du8081c842010-05-26 14:42:25 -0700131 gpsr = gpio_reg(chip, offset, GPSR);
Alek Du8bf02612009-09-22 16:46:36 -0700132 writel(BIT(offset % 32), gpsr);
133 } else {
Alek Du8081c842010-05-26 14:42:25 -0700134 gpcr = gpio_reg(chip, offset, GPCR);
Alek Du8bf02612009-09-22 16:46:36 -0700135 writel(BIT(offset % 32), gpcr);
136 }
137}
138
David Cohenf89a7682013-10-04 13:01:42 -0700139static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
Alek Du8bf02612009-09-22 16:46:36 -0700140{
David Cohenf89a7682013-10-04 13:01:42 -0700141 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700142 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700143 u32 value;
144 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700145
David Cohenf89a7682013-10-04 13:01:42 -0700146 if (priv->pdev)
147 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100148
David Cohenf89a7682013-10-04 13:01:42 -0700149 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700150 value = readl(gpdr);
151 value &= ~BIT(offset % 32);
152 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700153 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100154
David Cohenf89a7682013-10-04 13:01:42 -0700155 if (priv->pdev)
156 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100157
Alek Du8bf02612009-09-22 16:46:36 -0700158 return 0;
159}
160
David Cohenf89a7682013-10-04 13:01:42 -0700161static int intel_gpio_direction_output(struct gpio_chip *chip,
Alek Du8bf02612009-09-22 16:46:36 -0700162 unsigned offset, int value)
163{
David Cohenf89a7682013-10-04 13:01:42 -0700164 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700165 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700166 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700167
David Cohenf89a7682013-10-04 13:01:42 -0700168 intel_gpio_set(chip, offset, value);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100169
David Cohenf89a7682013-10-04 13:01:42 -0700170 if (priv->pdev)
171 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100172
David Cohenf89a7682013-10-04 13:01:42 -0700173 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700174 value = readl(gpdr);
Justin P. Mattock6eab04a2011-04-08 19:49:08 -0700175 value |= BIT(offset % 32);
Alek Du8bf02612009-09-22 16:46:36 -0700176 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700177 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100178
David Cohenf89a7682013-10-04 13:01:42 -0700179 if (priv->pdev)
180 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100181
Alek Du8bf02612009-09-22 16:46:36 -0700182 return 0;
183}
184
David Cohenf89a7682013-10-04 13:01:42 -0700185static int intel_mid_irq_type(struct irq_data *d, unsigned type)
Alek Du8bf02612009-09-22 16:46:36 -0700186{
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200187 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
188 struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300189 u32 gpio = irqd_to_hwirq(d);
Alek Du8bf02612009-09-22 16:46:36 -0700190 unsigned long flags;
191 u32 value;
David Cohenf89a7682013-10-04 13:01:42 -0700192 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
193 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
Alek Du8bf02612009-09-22 16:46:36 -0700194
David Cohenf89a7682013-10-04 13:01:42 -0700195 if (gpio >= priv->chip.ngpio)
Alek Du8bf02612009-09-22 16:46:36 -0700196 return -EINVAL;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100197
David Cohenf89a7682013-10-04 13:01:42 -0700198 if (priv->pdev)
199 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100200
David Cohenf89a7682013-10-04 13:01:42 -0700201 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700202 if (type & IRQ_TYPE_EDGE_RISING)
203 value = readl(grer) | BIT(gpio % 32);
204 else
205 value = readl(grer) & (~BIT(gpio % 32));
206 writel(value, grer);
207
208 if (type & IRQ_TYPE_EDGE_FALLING)
209 value = readl(gfer) | BIT(gpio % 32);
210 else
211 value = readl(gfer) & (~BIT(gpio % 32));
212 writel(value, gfer);
David Cohenf89a7682013-10-04 13:01:42 -0700213 spin_unlock_irqrestore(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700214
David Cohenf89a7682013-10-04 13:01:42 -0700215 if (priv->pdev)
216 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100217
Alek Du8bf02612009-09-22 16:46:36 -0700218 return 0;
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700219}
Alek Du8bf02612009-09-22 16:46:36 -0700220
David Cohenf89a7682013-10-04 13:01:42 -0700221static void intel_mid_irq_unmask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700222{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700223}
Alek Du8bf02612009-09-22 16:46:36 -0700224
David Cohenf89a7682013-10-04 13:01:42 -0700225static void intel_mid_irq_mask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700226{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700227}
Alek Du8bf02612009-09-22 16:46:36 -0700228
David Cohenf89a7682013-10-04 13:01:42 -0700229static struct irq_chip intel_mid_irqchip = {
230 .name = "INTEL_MID-GPIO",
231 .irq_mask = intel_mid_irq_mask,
232 .irq_unmask = intel_mid_irq_unmask,
233 .irq_set_type = intel_mid_irq_type,
Alek Du8bf02612009-09-22 16:46:36 -0700234};
235
David Cohenf89a7682013-10-04 13:01:42 -0700236static const struct intel_mid_gpio_ddata gpio_lincroft = {
David Cohend56d6b32013-10-04 13:01:40 -0700237 .ngpio = 64,
238};
239
David Cohenf89a7682013-10-04 13:01:42 -0700240static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700241 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700242 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700243};
244
David Cohenf89a7682013-10-04 13:01:42 -0700245static const struct intel_mid_gpio_ddata gpio_penwell_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700246 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700247 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700248};
249
David Cohenf89a7682013-10-04 13:01:42 -0700250static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700251 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700252 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
David Cohend56d6b32013-10-04 13:01:40 -0700253};
254
David Cohenf89a7682013-10-04 13:01:42 -0700255static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700256 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700257 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700258};
259
David Cohenf89a7682013-10-04 13:01:42 -0700260static const struct intel_mid_gpio_ddata gpio_tangier = {
David Cohend56d6b32013-10-04 13:01:40 -0700261 .ngpio = 192,
262 .gplr_offset = 4,
263 .flis_base = 0xff0c0000,
264 .flis_len = 0x8000,
265 .get_flis_offset = NULL,
David Cohenf89a7682013-10-04 13:01:42 -0700266 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700267};
268
Jingoo Han14f4a882013-12-03 08:08:45 +0900269static const struct pci_device_id intel_gpio_ids[] = {
David Cohend56d6b32013-10-04 13:01:40 -0700270 {
271 /* Lincroft */
272 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
273 .driver_data = (kernel_ulong_t)&gpio_lincroft,
274 },
275 {
276 /* Penwell AON */
277 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
278 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
279 },
280 {
281 /* Penwell Core */
282 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
283 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
284 },
285 {
286 /* Cloverview Aon */
287 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
288 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
289 },
290 {
291 /* Cloverview Core */
292 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
293 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
294 },
295 {
296 /* Tangier */
297 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
298 .driver_data = (kernel_ulong_t)&gpio_tangier,
299 },
300 { 0 }
Alek Du8bf02612009-09-22 16:46:36 -0700301};
David Cohenf89a7682013-10-04 13:01:42 -0700302MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
Alek Du8bf02612009-09-22 16:46:36 -0700303
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200304static void intel_mid_irq_handler(struct irq_desc *desc)
Alek Du8bf02612009-09-22 16:46:36 -0700305{
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200306 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
307 struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000308 struct irq_data *data = irq_desc_get_irq_data(desc);
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000309 struct irq_chip *chip = irq_data_get_irq_chip(data);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000310 u32 base, gpio, mask;
Thomas Gleixner732063b2011-03-17 19:32:55 +0000311 unsigned long pending;
Alek Du8bf02612009-09-22 16:46:36 -0700312 void __iomem *gedr;
Alek Du8bf02612009-09-22 16:46:36 -0700313
314 /* check GPIO controller to check which pin triggered the interrupt */
David Cohenf89a7682013-10-04 13:01:42 -0700315 for (base = 0; base < priv->chip.ngpio; base += 32) {
316 gedr = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergc8f925b2012-05-10 13:01:22 +0300317 while ((pending = readl(gedr))) {
Mathias Nyman2345b202011-07-08 10:02:18 +0100318 gpio = __ffs(pending);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000319 mask = BIT(gpio);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000320 /* Clear before handling so we can't lose an edge */
321 writel(mask, gedr);
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200322 generic_handle_irq(irq_find_mapping(gc->irqdomain,
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300323 base + gpio));
Thomas Gleixner732063b2011-03-17 19:32:55 +0000324 }
Alek Du8bf02612009-09-22 16:46:36 -0700325 }
Feng Tang0766d202011-01-25 15:07:15 -0800326
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000327 chip->irq_eoi(data);
Alek Du8bf02612009-09-22 16:46:36 -0700328}
329
David Cohenf89a7682013-10-04 13:01:42 -0700330static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
Mika Westerbergf5f93112012-04-05 12:15:17 +0300331{
332 void __iomem *reg;
333 unsigned base;
334
David Cohenf89a7682013-10-04 13:01:42 -0700335 for (base = 0; base < priv->chip.ngpio; base += 32) {
Mika Westerbergf5f93112012-04-05 12:15:17 +0300336 /* Clear the rising-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700337 reg = gpio_reg(&priv->chip, base, GRER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300338 writel(0, reg);
339 /* Clear the falling-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700340 reg = gpio_reg(&priv->chip, base, GFER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300341 writel(0, reg);
342 /* Clear the edge detect status register */
David Cohenf89a7682013-10-04 13:01:42 -0700343 reg = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300344 writel(~0, reg);
345 }
346}
347
David Cohenf89a7682013-10-04 13:01:42 -0700348static int intel_gpio_runtime_idle(struct device *dev)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100349{
xinhui.pan84a34572014-01-31 13:08:01 -0800350 int err = pm_schedule_suspend(dev, 500);
351 return err ?: -EBUSY;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100352}
353
David Cohenf89a7682013-10-04 13:01:42 -0700354static const struct dev_pm_ops intel_gpio_pm_ops = {
355 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100356};
357
David Cohenf89a7682013-10-04 13:01:42 -0700358static int intel_gpio_probe(struct pci_dev *pdev,
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300359 const struct pci_device_id *id)
Alek Du8bf02612009-09-22 16:46:36 -0700360{
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300361 void __iomem *base;
David Cohenf89a7682013-10-04 13:01:42 -0700362 struct intel_mid_gpio *priv;
Alek Du8bf02612009-09-22 16:46:36 -0700363 u32 gpio_base;
David Cohen2519f9a2013-05-06 16:11:03 -0700364 u32 irq_base;
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200365 int retval;
David Cohenf89a7682013-10-04 13:01:42 -0700366 struct intel_mid_gpio_ddata *ddata =
367 (struct intel_mid_gpio_ddata *)id->driver_data;
Alek Du8bf02612009-09-22 16:46:36 -0700368
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300369 retval = pcim_enable_device(pdev);
Alek Du8bf02612009-09-22 16:46:36 -0700370 if (retval)
Mika Westerberg8302c742012-04-05 12:15:15 +0300371 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700372
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300373 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
Alek Du8bf02612009-09-22 16:46:36 -0700374 if (retval) {
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300375 dev_err(&pdev->dev, "I/O memory mapping error\n");
376 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700377 }
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300378
379 base = pcim_iomap_table(pdev)[1];
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300380
381 irq_base = readl(base);
382 gpio_base = readl(sizeof(u32) + base);
383
Alek Du8bf02612009-09-22 16:46:36 -0700384 /* release the IO mapping, since we already get the info from bar1 */
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300385 pcim_iounmap_regions(pdev, 1 << 1);
Alek Du8bf02612009-09-22 16:46:36 -0700386
David Cohenf89a7682013-10-04 13:01:42 -0700387 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
388 if (!priv) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300389 dev_err(&pdev->dev, "can't allocate chip data\n");
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300390 return -ENOMEM;
Alek Du8bf02612009-09-22 16:46:36 -0700391 }
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300392
David Cohenf89a7682013-10-04 13:01:42 -0700393 priv->reg_base = pcim_iomap_table(pdev)[0];
394 priv->chip.label = dev_name(&pdev->dev);
Linus Walleijaa6baa72013-11-20 15:24:32 +0100395 priv->chip.dev = &pdev->dev;
David Cohenf89a7682013-10-04 13:01:42 -0700396 priv->chip.request = intel_gpio_request;
397 priv->chip.direction_input = intel_gpio_direction_input;
398 priv->chip.direction_output = intel_gpio_direction_output;
399 priv->chip.get = intel_gpio_get;
400 priv->chip.set = intel_gpio_set;
David Cohenf89a7682013-10-04 13:01:42 -0700401 priv->chip.base = gpio_base;
402 priv->chip.ngpio = ddata->ngpio;
Linus Walleij9fb1f392013-12-04 14:42:46 +0100403 priv->chip.can_sleep = false;
David Cohenf89a7682013-10-04 13:01:42 -0700404 priv->pdev = pdev;
David Cohen2519f9a2013-05-06 16:11:03 -0700405
David Cohenf89a7682013-10-04 13:01:42 -0700406 spin_lock_init(&priv->lock);
Andy Shevchenkoaeb168f2013-05-22 13:20:10 +0300407
David Cohenf89a7682013-10-04 13:01:42 -0700408 pci_set_drvdata(pdev, priv);
409 retval = gpiochip_add(&priv->chip);
Alek Du8bf02612009-09-22 16:46:36 -0700410 if (retval) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300411 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300412 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700413 }
Mika Westerbergf5f93112012-04-05 12:15:17 +0300414
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200415 retval = gpiochip_irqchip_add(&priv->chip,
416 &intel_mid_irqchip,
417 irq_base,
418 handle_simple_irq,
419 IRQ_TYPE_NONE);
420 if (retval) {
421 dev_err(&pdev->dev,
422 "could not connect irqchip to gpiochip\n");
423 return retval;
424 }
425
David Cohenf89a7682013-10-04 13:01:42 -0700426 intel_mid_irq_init_hw(priv);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300427
Linus Walleij3f7dbfd2014-05-29 16:55:55 +0200428 gpiochip_set_chained_irqchip(&priv->chip,
429 &intel_mid_irqchip,
430 pdev->irq,
431 intel_mid_irq_handler);
Alek Du8bf02612009-09-22 16:46:36 -0700432
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100433 pm_runtime_put_noidle(&pdev->dev);
434 pm_runtime_allow(&pdev->dev);
435
Mika Westerberg8302c742012-04-05 12:15:15 +0300436 return 0;
Alek Du8bf02612009-09-22 16:46:36 -0700437}
438
David Cohenf89a7682013-10-04 13:01:42 -0700439static struct pci_driver intel_gpio_driver = {
440 .name = "intel_mid_gpio",
441 .id_table = intel_gpio_ids,
442 .probe = intel_gpio_probe,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100443 .driver = {
David Cohenf89a7682013-10-04 13:01:42 -0700444 .pm = &intel_gpio_pm_ops,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100445 },
Alek Du8bf02612009-09-22 16:46:36 -0700446};
447
David Cohenf89a7682013-10-04 13:01:42 -0700448static int __init intel_gpio_init(void)
Alek Du8bf02612009-09-22 16:46:36 -0700449{
David Cohenf89a7682013-10-04 13:01:42 -0700450 return pci_register_driver(&intel_gpio_driver);
Alek Du8bf02612009-09-22 16:46:36 -0700451}
452
David Cohenf89a7682013-10-04 13:01:42 -0700453device_initcall(intel_gpio_init);