Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
| 3 | * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | */ |
| 10 | |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 11 | #include <linux/clk-provider.h> |
| 12 | #include <linux/of.h> |
| 13 | |
| 14 | #include "clk.h" |
| 15 | #include <dt-bindings/clock/exynos7-clk.h> |
| 16 | |
| 17 | /* Register Offset definitions for CMU_TOPC (0x10570000) */ |
| 18 | #define CC_PLL_LOCK 0x0000 |
| 19 | #define BUS0_PLL_LOCK 0x0004 |
| 20 | #define BUS1_DPLL_LOCK 0x0008 |
| 21 | #define MFC_PLL_LOCK 0x000C |
| 22 | #define AUD_PLL_LOCK 0x0010 |
| 23 | #define CC_PLL_CON0 0x0100 |
| 24 | #define BUS0_PLL_CON0 0x0110 |
| 25 | #define BUS1_DPLL_CON0 0x0120 |
| 26 | #define MFC_PLL_CON0 0x0130 |
| 27 | #define AUD_PLL_CON0 0x0140 |
| 28 | #define MUX_SEL_TOPC0 0x0200 |
| 29 | #define MUX_SEL_TOPC1 0x0204 |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 30 | #define MUX_SEL_TOPC2 0x0208 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 31 | #define MUX_SEL_TOPC3 0x020C |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 32 | #define DIV_TOPC0 0x0600 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 33 | #define DIV_TOPC1 0x0604 |
| 34 | #define DIV_TOPC3 0x060C |
Tony K Nadackal | 49cab82 | 2014-12-17 13:03:37 +0530 | [diff] [blame] | 35 | #define ENABLE_ACLK_TOPC1 0x0804 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 36 | |
| 37 | static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 38 | FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 39 | FFACTOR(0, "ffac_topc_bus0_pll_div4", |
| 40 | "ffac_topc_bus0_pll_div2", 1, 2, 0), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 41 | FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), |
| 42 | FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), |
| 43 | FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | /* List of parent clocks for Muxes in CMU_TOPC */ |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 47 | PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; |
| 48 | PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; |
| 49 | PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; |
| 50 | PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; |
| 51 | PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 52 | |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 53 | PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", |
| 54 | "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", |
| 55 | "mout_topc_mfc_pll_half" }; |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 56 | |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 57 | PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 58 | "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 59 | PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 60 | "ffac_topc_bus1_pll_div2"}; |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 61 | PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 62 | "ffac_topc_cc_pll_div2"}; |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 63 | PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 64 | "ffac_topc_mfc_pll_div2"}; |
| 65 | |
| 66 | |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 67 | PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 68 | "ffac_topc_bus0_pll_div2"}; |
| 69 | |
| 70 | static unsigned long topc_clk_regs[] __initdata = { |
| 71 | CC_PLL_LOCK, |
| 72 | BUS0_PLL_LOCK, |
| 73 | BUS1_DPLL_LOCK, |
| 74 | MFC_PLL_LOCK, |
| 75 | AUD_PLL_LOCK, |
| 76 | CC_PLL_CON0, |
| 77 | BUS0_PLL_CON0, |
| 78 | BUS1_DPLL_CON0, |
| 79 | MFC_PLL_CON0, |
| 80 | AUD_PLL_CON0, |
| 81 | MUX_SEL_TOPC0, |
| 82 | MUX_SEL_TOPC1, |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 83 | MUX_SEL_TOPC2, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 84 | MUX_SEL_TOPC3, |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 85 | DIV_TOPC0, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 86 | DIV_TOPC1, |
| 87 | DIV_TOPC3, |
| 88 | }; |
| 89 | |
| 90 | static struct samsung_mux_clock topc_mux_clks[] __initdata = { |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 91 | MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, |
| 92 | MUX_SEL_TOPC0, 0, 1), |
| 93 | MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, |
| 94 | MUX_SEL_TOPC0, 4, 1), |
| 95 | MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, |
| 96 | MUX_SEL_TOPC0, 8, 1), |
| 97 | MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, |
| 98 | MUX_SEL_TOPC0, 12, 1), |
| 99 | MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 100 | MUX_SEL_TOPC0, 16, 2), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 101 | MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 102 | MUX_SEL_TOPC0, 20, 1), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 103 | MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 104 | MUX_SEL_TOPC0, 24, 1), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 105 | MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 106 | MUX_SEL_TOPC0, 28, 1), |
| 107 | |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 108 | MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, |
| 109 | MUX_SEL_TOPC1, 0, 1), |
| 110 | MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 111 | MUX_SEL_TOPC1, 16, 1), |
| 112 | |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 113 | MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), |
| 114 | |
Tony K Nadackal | 49cab82 | 2014-12-17 13:03:37 +0530 | [diff] [blame] | 115 | MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 116 | MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), |
| 117 | }; |
| 118 | |
| 119 | static struct samsung_div_clock topc_div_clks[] __initdata = { |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 120 | DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", |
| 121 | DIV_TOPC0, 4, 4), |
| 122 | |
Tony K Nadackal | 49cab82 | 2014-12-17 13:03:37 +0530 | [diff] [blame] | 123 | DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", |
| 124 | DIV_TOPC1, 20, 4), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 125 | DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", |
| 126 | DIV_TOPC1, 24, 4), |
| 127 | |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 128 | DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", |
Alim Akhtar | fa9f3a5 | 2015-08-26 09:00:41 +0530 | [diff] [blame] | 129 | DIV_TOPC3, 0, 4), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 130 | DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", |
Alim Akhtar | fa9f3a5 | 2015-08-26 09:00:41 +0530 | [diff] [blame] | 131 | DIV_TOPC3, 8, 4), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 132 | DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", |
Alim Akhtar | fa9f3a5 | 2015-08-26 09:00:41 +0530 | [diff] [blame] | 133 | DIV_TOPC3, 12, 4), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 134 | DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", |
Alim Akhtar | fa9f3a5 | 2015-08-26 09:00:41 +0530 | [diff] [blame] | 135 | DIV_TOPC3, 16, 4), |
Alim Akhtar | dc504b2 | 2015-09-10 14:14:26 +0530 | [diff] [blame^] | 136 | DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", |
Alim Akhtar | fa9f3a5 | 2015-08-26 09:00:41 +0530 | [diff] [blame] | 137 | DIV_TOPC3, 28, 4), |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { |
| 141 | PLL_36XX_RATE(491520000, 20, 1, 0, 31457), |
| 142 | {}, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 143 | }; |
| 144 | |
Tony K Nadackal | 49cab82 | 2014-12-17 13:03:37 +0530 | [diff] [blame] | 145 | static struct samsung_gate_clock topc_gate_clks[] __initdata = { |
| 146 | GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", |
| 147 | ENABLE_ACLK_TOPC1, 20, 0, 0), |
| 148 | }; |
| 149 | |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 150 | static struct samsung_pll_clock topc_pll_clks[] __initdata = { |
| 151 | PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, |
| 152 | BUS0_PLL_CON0, NULL), |
| 153 | PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, |
| 154 | CC_PLL_CON0, NULL), |
| 155 | PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, |
| 156 | BUS1_DPLL_CON0, NULL), |
| 157 | PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, |
| 158 | MFC_PLL_CON0, NULL), |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 159 | PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, |
| 160 | AUD_PLL_CON0, pll1460x_24mhz_tbl), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | static struct samsung_cmu_info topc_cmu_info __initdata = { |
| 164 | .pll_clks = topc_pll_clks, |
| 165 | .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), |
| 166 | .mux_clks = topc_mux_clks, |
| 167 | .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), |
| 168 | .div_clks = topc_div_clks, |
| 169 | .nr_div_clks = ARRAY_SIZE(topc_div_clks), |
Tony K Nadackal | 49cab82 | 2014-12-17 13:03:37 +0530 | [diff] [blame] | 170 | .gate_clks = topc_gate_clks, |
| 171 | .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 172 | .fixed_factor_clks = topc_fixed_factor_clks, |
| 173 | .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), |
| 174 | .nr_clk_ids = TOPC_NR_CLK, |
| 175 | .clk_regs = topc_clk_regs, |
| 176 | .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), |
| 177 | }; |
| 178 | |
| 179 | static void __init exynos7_clk_topc_init(struct device_node *np) |
| 180 | { |
| 181 | samsung_cmu_register_one(np, &topc_cmu_info); |
| 182 | } |
| 183 | |
| 184 | CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", |
| 185 | exynos7_clk_topc_init); |
| 186 | |
| 187 | /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ |
| 188 | #define MUX_SEL_TOP00 0x0200 |
| 189 | #define MUX_SEL_TOP01 0x0204 |
| 190 | #define MUX_SEL_TOP03 0x020C |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 191 | #define MUX_SEL_TOP0_PERIC0 0x0230 |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 192 | #define MUX_SEL_TOP0_PERIC1 0x0234 |
| 193 | #define MUX_SEL_TOP0_PERIC2 0x0238 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 194 | #define MUX_SEL_TOP0_PERIC3 0x023C |
| 195 | #define DIV_TOP03 0x060C |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 196 | #define DIV_TOP0_PERIC0 0x0630 |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 197 | #define DIV_TOP0_PERIC1 0x0634 |
| 198 | #define DIV_TOP0_PERIC2 0x0638 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 199 | #define DIV_TOP0_PERIC3 0x063C |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 200 | #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 201 | #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 |
| 202 | #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 203 | #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C |
| 204 | |
| 205 | /* List of parent clocks for Muxes in CMU_TOP0 */ |
| 206 | PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; |
| 207 | PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; |
| 208 | PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; |
| 209 | PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 210 | PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" }; |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 211 | |
| 212 | PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", |
| 213 | "ffac_top0_bus0_pll_div2"}; |
| 214 | PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", |
| 215 | "ffac_top0_bus1_pll_div2"}; |
| 216 | PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", |
| 217 | "ffac_top0_cc_pll_div2"}; |
| 218 | PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", |
| 219 | "ffac_top0_mfc_pll_div2"}; |
| 220 | |
| 221 | PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", |
| 222 | "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", |
| 223 | "mout_top0_half_mfc_pll"}; |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 224 | PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", |
| 225 | "ioclk_audiocdclk1", "ioclk_spdif_extclk", |
| 226 | "mout_top0_aud_pll", "mout_top0_half_bus0_pll", |
| 227 | "mout_top0_half_bus1_pll"}; |
| 228 | PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll", |
| 229 | "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"}; |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 230 | |
| 231 | static unsigned long top0_clk_regs[] __initdata = { |
| 232 | MUX_SEL_TOP00, |
| 233 | MUX_SEL_TOP01, |
| 234 | MUX_SEL_TOP03, |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 235 | MUX_SEL_TOP0_PERIC0, |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 236 | MUX_SEL_TOP0_PERIC1, |
| 237 | MUX_SEL_TOP0_PERIC2, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 238 | MUX_SEL_TOP0_PERIC3, |
| 239 | DIV_TOP03, |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 240 | DIV_TOP0_PERIC0, |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 241 | DIV_TOP0_PERIC1, |
| 242 | DIV_TOP0_PERIC2, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 243 | DIV_TOP0_PERIC3, |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 244 | ENABLE_SCLK_TOP0_PERIC0, |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 245 | ENABLE_SCLK_TOP0_PERIC1, |
| 246 | ENABLE_SCLK_TOP0_PERIC2, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 247 | ENABLE_SCLK_TOP0_PERIC3, |
| 248 | }; |
| 249 | |
| 250 | static struct samsung_mux_clock top0_mux_clks[] __initdata = { |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 251 | MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 252 | MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), |
| 253 | MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), |
| 254 | MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), |
| 255 | MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), |
| 256 | |
| 257 | MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, |
| 258 | MUX_SEL_TOP01, 4, 1), |
| 259 | MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, |
| 260 | MUX_SEL_TOP01, 8, 1), |
| 261 | MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, |
| 262 | MUX_SEL_TOP01, 12, 1), |
| 263 | MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, |
| 264 | MUX_SEL_TOP01, 16, 1), |
| 265 | |
| 266 | MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), |
| 267 | MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), |
| 268 | |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 269 | MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), |
| 270 | MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), |
| 271 | MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), |
| 272 | |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 273 | MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), |
| 274 | MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), |
| 275 | |
| 276 | MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), |
| 277 | MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 278 | MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), |
| 279 | MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), |
| 280 | MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), |
| 281 | MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 282 | MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 283 | }; |
| 284 | |
| 285 | static struct samsung_div_clock top0_div_clks[] __initdata = { |
| 286 | DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", |
| 287 | DIV_TOP03, 12, 6), |
| 288 | DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", |
| 289 | DIV_TOP03, 20, 6), |
| 290 | |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 291 | DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), |
| 292 | DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), |
| 293 | DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), |
| 294 | |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 295 | DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), |
| 296 | DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), |
| 297 | |
| 298 | DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), |
| 299 | DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), |
| 300 | |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 301 | DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), |
| 302 | DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), |
| 303 | DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), |
| 304 | DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 305 | DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 306 | }; |
| 307 | |
| 308 | static struct samsung_gate_clock top0_gate_clks[] __initdata = { |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 309 | GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", |
| 310 | ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), |
| 311 | GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", |
| 312 | ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), |
| 313 | GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", |
| 314 | ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), |
| 315 | |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 316 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", |
| 317 | ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), |
| 318 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", |
| 319 | ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), |
| 320 | |
| 321 | GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", |
| 322 | ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), |
| 323 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", |
| 324 | ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 325 | GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", |
| 326 | ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), |
| 327 | GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", |
| 328 | ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), |
| 329 | GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", |
| 330 | ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), |
| 331 | GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", |
| 332 | ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 333 | GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", |
| 334 | ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 335 | }; |
| 336 | |
| 337 | static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { |
| 338 | FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), |
| 339 | FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), |
| 340 | FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), |
| 341 | FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), |
| 342 | }; |
| 343 | |
| 344 | static struct samsung_cmu_info top0_cmu_info __initdata = { |
| 345 | .mux_clks = top0_mux_clks, |
| 346 | .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), |
| 347 | .div_clks = top0_div_clks, |
| 348 | .nr_div_clks = ARRAY_SIZE(top0_div_clks), |
| 349 | .gate_clks = top0_gate_clks, |
| 350 | .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), |
| 351 | .fixed_factor_clks = top0_fixed_factor_clks, |
| 352 | .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), |
| 353 | .nr_clk_ids = TOP0_NR_CLK, |
| 354 | .clk_regs = top0_clk_regs, |
| 355 | .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), |
| 356 | }; |
| 357 | |
| 358 | static void __init exynos7_clk_top0_init(struct device_node *np) |
| 359 | { |
| 360 | samsung_cmu_register_one(np, &top0_cmu_info); |
| 361 | } |
| 362 | |
| 363 | CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", |
| 364 | exynos7_clk_top0_init); |
| 365 | |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 366 | /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ |
| 367 | #define MUX_SEL_TOP10 0x0200 |
| 368 | #define MUX_SEL_TOP11 0x0204 |
| 369 | #define MUX_SEL_TOP13 0x020C |
| 370 | #define MUX_SEL_TOP1_FSYS0 0x0224 |
| 371 | #define MUX_SEL_TOP1_FSYS1 0x0228 |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 372 | #define MUX_SEL_TOP1_FSYS11 0x022C |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 373 | #define DIV_TOP13 0x060C |
| 374 | #define DIV_TOP1_FSYS0 0x0624 |
| 375 | #define DIV_TOP1_FSYS1 0x0628 |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 376 | #define DIV_TOP1_FSYS11 0x062C |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 377 | #define ENABLE_ACLK_TOP13 0x080C |
| 378 | #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 |
| 379 | #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 380 | #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 381 | |
| 382 | /* List of parent clocks for Muxes in CMU_TOP1 */ |
| 383 | PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; |
| 384 | PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; |
| 385 | PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; |
| 386 | PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; |
| 387 | |
| 388 | PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", |
| 389 | "ffac_top1_bus0_pll_div2"}; |
| 390 | PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", |
| 391 | "ffac_top1_bus1_pll_div2"}; |
| 392 | PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", |
| 393 | "ffac_top1_cc_pll_div2"}; |
| 394 | PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", |
| 395 | "ffac_top1_mfc_pll_div2"}; |
| 396 | |
| 397 | PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", |
| 398 | "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", |
| 399 | "mout_top1_half_mfc_pll"}; |
| 400 | |
| 401 | static unsigned long top1_clk_regs[] __initdata = { |
| 402 | MUX_SEL_TOP10, |
| 403 | MUX_SEL_TOP11, |
| 404 | MUX_SEL_TOP13, |
| 405 | MUX_SEL_TOP1_FSYS0, |
| 406 | MUX_SEL_TOP1_FSYS1, |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 407 | MUX_SEL_TOP1_FSYS11, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 408 | DIV_TOP13, |
| 409 | DIV_TOP1_FSYS0, |
| 410 | DIV_TOP1_FSYS1, |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 411 | DIV_TOP1_FSYS11, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 412 | ENABLE_ACLK_TOP13, |
| 413 | ENABLE_SCLK_TOP1_FSYS0, |
| 414 | ENABLE_SCLK_TOP1_FSYS1, |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 415 | ENABLE_SCLK_TOP1_FSYS11, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 416 | }; |
| 417 | |
| 418 | static struct samsung_mux_clock top1_mux_clks[] __initdata = { |
| 419 | MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), |
| 420 | MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), |
| 421 | MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, |
| 422 | MUX_SEL_TOP10, 12, 1), |
| 423 | MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, |
| 424 | MUX_SEL_TOP10, 16, 1), |
| 425 | |
| 426 | MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, |
| 427 | MUX_SEL_TOP11, 4, 1), |
| 428 | MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, |
| 429 | MUX_SEL_TOP11, 8, 1), |
| 430 | MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, |
| 431 | MUX_SEL_TOP11, 12, 1), |
| 432 | MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, |
| 433 | MUX_SEL_TOP11, 16, 1), |
| 434 | |
| 435 | MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), |
| 436 | MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), |
| 437 | |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 438 | MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 439 | MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, |
| 440 | MUX_SEL_TOP1_FSYS0, 28, 2), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 441 | |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 442 | MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), |
| 443 | MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 444 | }; |
| 445 | |
| 446 | static struct samsung_div_clock top1_div_clks[] __initdata = { |
| 447 | DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", |
| 448 | DIV_TOP13, 24, 4), |
| 449 | DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", |
| 450 | DIV_TOP13, 28, 4), |
| 451 | |
| 452 | DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 453 | DIV_TOP1_FSYS0, 16, 10), |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 454 | DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", |
| 455 | DIV_TOP1_FSYS0, 28, 4), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 456 | |
| 457 | DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 458 | DIV_TOP1_FSYS11, 0, 10), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 459 | DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 460 | DIV_TOP1_FSYS11, 12, 10), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 461 | }; |
| 462 | |
| 463 | static struct samsung_gate_clock top1_gate_clks[] __initdata = { |
| 464 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 465 | ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 466 | GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", |
| 467 | ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 468 | |
| 469 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 470 | ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 471 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", |
Alim Akhtar | cfc7588 | 2015-08-26 09:00:42 +0530 | [diff] [blame] | 472 | ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 473 | }; |
| 474 | |
| 475 | static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { |
| 476 | FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), |
| 477 | FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), |
| 478 | FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), |
| 479 | FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), |
| 480 | }; |
| 481 | |
| 482 | static struct samsung_cmu_info top1_cmu_info __initdata = { |
| 483 | .mux_clks = top1_mux_clks, |
| 484 | .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), |
| 485 | .div_clks = top1_div_clks, |
| 486 | .nr_div_clks = ARRAY_SIZE(top1_div_clks), |
| 487 | .gate_clks = top1_gate_clks, |
| 488 | .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), |
| 489 | .fixed_factor_clks = top1_fixed_factor_clks, |
| 490 | .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), |
| 491 | .nr_clk_ids = TOP1_NR_CLK, |
| 492 | .clk_regs = top1_clk_regs, |
| 493 | .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), |
| 494 | }; |
| 495 | |
| 496 | static void __init exynos7_clk_top1_init(struct device_node *np) |
| 497 | { |
| 498 | samsung_cmu_register_one(np, &top1_cmu_info); |
| 499 | } |
| 500 | |
| 501 | CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", |
| 502 | exynos7_clk_top1_init); |
| 503 | |
Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 504 | /* Register Offset definitions for CMU_CCORE (0x105B0000) */ |
| 505 | #define MUX_SEL_CCORE 0x0200 |
| 506 | #define DIV_CCORE 0x0600 |
| 507 | #define ENABLE_ACLK_CCORE0 0x0800 |
| 508 | #define ENABLE_ACLK_CCORE1 0x0804 |
| 509 | #define ENABLE_PCLK_CCORE 0x0900 |
| 510 | |
| 511 | /* |
| 512 | * List of parent clocks for Muxes in CMU_CCORE |
| 513 | */ |
| 514 | PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; |
| 515 | |
| 516 | static unsigned long ccore_clk_regs[] __initdata = { |
| 517 | MUX_SEL_CCORE, |
| 518 | ENABLE_PCLK_CCORE, |
| 519 | }; |
| 520 | |
| 521 | static struct samsung_mux_clock ccore_mux_clks[] __initdata = { |
| 522 | MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, |
| 523 | MUX_SEL_CCORE, 1, 1), |
| 524 | }; |
| 525 | |
| 526 | static struct samsung_gate_clock ccore_gate_clks[] __initdata = { |
| 527 | GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", |
| 528 | ENABLE_PCLK_CCORE, 8, 0, 0), |
| 529 | }; |
| 530 | |
| 531 | static struct samsung_cmu_info ccore_cmu_info __initdata = { |
| 532 | .mux_clks = ccore_mux_clks, |
| 533 | .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), |
| 534 | .gate_clks = ccore_gate_clks, |
| 535 | .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), |
| 536 | .nr_clk_ids = CCORE_NR_CLK, |
| 537 | .clk_regs = ccore_clk_regs, |
| 538 | .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), |
| 539 | }; |
| 540 | |
| 541 | static void __init exynos7_clk_ccore_init(struct device_node *np) |
| 542 | { |
| 543 | samsung_cmu_register_one(np, &ccore_cmu_info); |
| 544 | } |
| 545 | |
| 546 | CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", |
| 547 | exynos7_clk_ccore_init); |
| 548 | |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 549 | /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ |
| 550 | #define MUX_SEL_PERIC0 0x0200 |
| 551 | #define ENABLE_PCLK_PERIC0 0x0900 |
| 552 | #define ENABLE_SCLK_PERIC0 0x0A00 |
| 553 | |
| 554 | /* List of parent clocks for Muxes in CMU_PERIC0 */ |
| 555 | PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; |
| 556 | PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; |
| 557 | |
| 558 | static unsigned long peric0_clk_regs[] __initdata = { |
| 559 | MUX_SEL_PERIC0, |
| 560 | ENABLE_PCLK_PERIC0, |
| 561 | ENABLE_SCLK_PERIC0, |
| 562 | }; |
| 563 | |
| 564 | static struct samsung_mux_clock peric0_mux_clks[] __initdata = { |
| 565 | MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, |
| 566 | MUX_SEL_PERIC0, 0, 1), |
| 567 | MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, |
| 568 | MUX_SEL_PERIC0, 16, 1), |
| 569 | }; |
| 570 | |
| 571 | static struct samsung_gate_clock peric0_gate_clks[] __initdata = { |
Naveen Krishna Ch | 57a2b48 | 2014-10-21 11:13:51 +0530 | [diff] [blame] | 572 | GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", |
| 573 | ENABLE_PCLK_PERIC0, 8, 0, 0), |
| 574 | GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", |
| 575 | ENABLE_PCLK_PERIC0, 9, 0, 0), |
| 576 | GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", |
| 577 | ENABLE_PCLK_PERIC0, 10, 0, 0), |
| 578 | GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", |
| 579 | ENABLE_PCLK_PERIC0, 11, 0, 0), |
| 580 | GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", |
| 581 | ENABLE_PCLK_PERIC0, 12, 0, 0), |
| 582 | GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", |
| 583 | ENABLE_PCLK_PERIC0, 13, 0, 0), |
| 584 | GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", |
| 585 | ENABLE_PCLK_PERIC0, 14, 0, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 586 | GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", |
| 587 | ENABLE_PCLK_PERIC0, 16, 0, 0), |
Abhilash Kesavan | 932e982 | 2014-10-28 16:48:55 +0530 | [diff] [blame] | 588 | GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", |
| 589 | ENABLE_PCLK_PERIC0, 20, 0, 0), |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 590 | GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", |
| 591 | ENABLE_PCLK_PERIC0, 21, 0, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 592 | |
| 593 | GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", |
| 594 | ENABLE_SCLK_PERIC0, 16, 0, 0), |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 595 | GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 596 | }; |
| 597 | |
| 598 | static struct samsung_cmu_info peric0_cmu_info __initdata = { |
| 599 | .mux_clks = peric0_mux_clks, |
| 600 | .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), |
| 601 | .gate_clks = peric0_gate_clks, |
| 602 | .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), |
| 603 | .nr_clk_ids = PERIC0_NR_CLK, |
| 604 | .clk_regs = peric0_clk_regs, |
| 605 | .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), |
| 606 | }; |
| 607 | |
| 608 | static void __init exynos7_clk_peric0_init(struct device_node *np) |
| 609 | { |
| 610 | samsung_cmu_register_one(np, &peric0_cmu_info); |
| 611 | } |
| 612 | |
| 613 | /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ |
| 614 | #define MUX_SEL_PERIC10 0x0200 |
| 615 | #define MUX_SEL_PERIC11 0x0204 |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 616 | #define MUX_SEL_PERIC12 0x0208 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 617 | #define ENABLE_PCLK_PERIC1 0x0900 |
| 618 | #define ENABLE_SCLK_PERIC10 0x0A00 |
| 619 | |
| 620 | CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", |
| 621 | exynos7_clk_peric0_init); |
| 622 | |
| 623 | /* List of parent clocks for Muxes in CMU_PERIC1 */ |
| 624 | PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; |
| 625 | PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; |
| 626 | PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; |
| 627 | PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 628 | PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; |
| 629 | PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; |
| 630 | PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; |
| 631 | PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; |
| 632 | PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 633 | |
| 634 | static unsigned long peric1_clk_regs[] __initdata = { |
| 635 | MUX_SEL_PERIC10, |
| 636 | MUX_SEL_PERIC11, |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 637 | MUX_SEL_PERIC12, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 638 | ENABLE_PCLK_PERIC1, |
| 639 | ENABLE_SCLK_PERIC10, |
| 640 | }; |
| 641 | |
| 642 | static struct samsung_mux_clock peric1_mux_clks[] __initdata = { |
| 643 | MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, |
| 644 | MUX_SEL_PERIC10, 0, 1), |
| 645 | |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 646 | MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, |
| 647 | MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), |
| 648 | MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, |
| 649 | MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), |
| 650 | MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, |
| 651 | MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), |
| 652 | MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, |
| 653 | MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), |
| 654 | MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, |
| 655 | MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 656 | MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, |
| 657 | MUX_SEL_PERIC11, 20, 1), |
| 658 | MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, |
| 659 | MUX_SEL_PERIC11, 24, 1), |
| 660 | MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, |
| 661 | MUX_SEL_PERIC11, 28, 1), |
| 662 | }; |
| 663 | |
| 664 | static struct samsung_gate_clock peric1_gate_clks[] __initdata = { |
Naveen Krishna Ch | 57a2b48 | 2014-10-21 11:13:51 +0530 | [diff] [blame] | 665 | GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", |
| 666 | ENABLE_PCLK_PERIC1, 4, 0, 0), |
| 667 | GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", |
| 668 | ENABLE_PCLK_PERIC1, 5, 0, 0), |
| 669 | GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", |
| 670 | ENABLE_PCLK_PERIC1, 6, 0, 0), |
| 671 | GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", |
| 672 | ENABLE_PCLK_PERIC1, 7, 0, 0), |
| 673 | GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", |
| 674 | ENABLE_PCLK_PERIC1, 8, 0, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 675 | GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", |
| 676 | ENABLE_PCLK_PERIC1, 9, 0, 0), |
| 677 | GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", |
| 678 | ENABLE_PCLK_PERIC1, 10, 0, 0), |
| 679 | GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", |
| 680 | ENABLE_PCLK_PERIC1, 11, 0, 0), |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 681 | GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", |
| 682 | ENABLE_PCLK_PERIC1, 12, 0, 0), |
| 683 | GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", |
| 684 | ENABLE_PCLK_PERIC1, 13, 0, 0), |
| 685 | GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", |
| 686 | ENABLE_PCLK_PERIC1, 14, 0, 0), |
| 687 | GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", |
| 688 | ENABLE_PCLK_PERIC1, 15, 0, 0), |
| 689 | GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", |
| 690 | ENABLE_PCLK_PERIC1, 16, 0, 0), |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 691 | GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", |
| 692 | ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), |
| 693 | GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", |
| 694 | ENABLE_PCLK_PERIC1, 18, 0, 0), |
| 695 | GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", |
| 696 | ENABLE_PCLK_PERIC1, 19, 0, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 697 | |
| 698 | GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", |
| 699 | ENABLE_SCLK_PERIC10, 9, 0, 0), |
| 700 | GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", |
| 701 | ENABLE_SCLK_PERIC10, 10, 0, 0), |
| 702 | GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", |
| 703 | ENABLE_SCLK_PERIC10, 11, 0, 0), |
Padmavathi Venna | ee74b56 | 2015-01-13 16:57:41 +0530 | [diff] [blame] | 704 | GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", |
| 705 | ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), |
| 706 | GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", |
| 707 | ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), |
| 708 | GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", |
| 709 | ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), |
| 710 | GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", |
| 711 | ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), |
| 712 | GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", |
| 713 | ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 714 | GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", |
| 715 | ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), |
| 716 | GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", |
| 717 | ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), |
| 718 | GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", |
| 719 | ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 720 | }; |
| 721 | |
| 722 | static struct samsung_cmu_info peric1_cmu_info __initdata = { |
| 723 | .mux_clks = peric1_mux_clks, |
| 724 | .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), |
| 725 | .gate_clks = peric1_gate_clks, |
| 726 | .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), |
| 727 | .nr_clk_ids = PERIC1_NR_CLK, |
| 728 | .clk_regs = peric1_clk_regs, |
| 729 | .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), |
| 730 | }; |
| 731 | |
| 732 | static void __init exynos7_clk_peric1_init(struct device_node *np) |
| 733 | { |
| 734 | samsung_cmu_register_one(np, &peric1_cmu_info); |
| 735 | } |
| 736 | |
| 737 | CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", |
| 738 | exynos7_clk_peric1_init); |
| 739 | |
| 740 | /* Register Offset definitions for CMU_PERIS (0x10040000) */ |
| 741 | #define MUX_SEL_PERIS 0x0200 |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 742 | #define ENABLE_PCLK_PERIS 0x0900 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 743 | #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 744 | #define ENABLE_SCLK_PERIS 0x0A00 |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 745 | #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 |
| 746 | |
| 747 | /* List of parent clocks for Muxes in CMU_PERIS */ |
| 748 | PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; |
| 749 | |
| 750 | static unsigned long peris_clk_regs[] __initdata = { |
| 751 | MUX_SEL_PERIS, |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 752 | ENABLE_PCLK_PERIS, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 753 | ENABLE_PCLK_PERIS_SECURE_CHIPID, |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 754 | ENABLE_SCLK_PERIS, |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 755 | ENABLE_SCLK_PERIS_SECURE_CHIPID, |
| 756 | }; |
| 757 | |
| 758 | static struct samsung_mux_clock peris_mux_clks[] __initdata = { |
| 759 | MUX(0, "mout_aclk_peris_66_user", |
| 760 | mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), |
| 761 | }; |
| 762 | |
| 763 | static struct samsung_gate_clock peris_gate_clks[] __initdata = { |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 764 | GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", |
| 765 | ENABLE_PCLK_PERIS, 6, 0, 0), |
| 766 | GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", |
| 767 | ENABLE_PCLK_PERIS, 10, 0, 0), |
| 768 | |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 769 | GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", |
| 770 | ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), |
| 771 | GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", |
| 772 | ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), |
Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 773 | |
| 774 | GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), |
Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 775 | }; |
| 776 | |
| 777 | static struct samsung_cmu_info peris_cmu_info __initdata = { |
| 778 | .mux_clks = peris_mux_clks, |
| 779 | .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), |
| 780 | .gate_clks = peris_gate_clks, |
| 781 | .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), |
| 782 | .nr_clk_ids = PERIS_NR_CLK, |
| 783 | .clk_regs = peris_clk_regs, |
| 784 | .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), |
| 785 | }; |
| 786 | |
| 787 | static void __init exynos7_clk_peris_init(struct device_node *np) |
| 788 | { |
| 789 | samsung_cmu_register_one(np, &peris_cmu_info); |
| 790 | } |
| 791 | |
| 792 | CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", |
| 793 | exynos7_clk_peris_init); |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 794 | |
| 795 | /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ |
| 796 | #define MUX_SEL_FSYS00 0x0200 |
| 797 | #define MUX_SEL_FSYS01 0x0204 |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 798 | #define MUX_SEL_FSYS02 0x0208 |
| 799 | #define ENABLE_ACLK_FSYS00 0x0800 |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 800 | #define ENABLE_ACLK_FSYS01 0x0804 |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 801 | #define ENABLE_SCLK_FSYS01 0x0A04 |
| 802 | #define ENABLE_SCLK_FSYS02 0x0A08 |
| 803 | #define ENABLE_SCLK_FSYS04 0x0A10 |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 804 | |
| 805 | /* |
| 806 | * List of parent clocks for Muxes in CMU_FSYS0 |
| 807 | */ |
| 808 | PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; |
| 809 | PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; |
| 810 | |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 811 | PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; |
| 812 | PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", |
| 813 | "phyclk_usbdrd300_udrd30_phyclock" }; |
| 814 | PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", |
| 815 | "phyclk_usbdrd300_udrd30_pipe_pclk" }; |
| 816 | |
| 817 | /* fixed rate clocks used in the FSYS0 block */ |
| 818 | struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { |
| 819 | FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, |
| 820 | CLK_IS_ROOT, 60000000), |
| 821 | FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, |
| 822 | CLK_IS_ROOT, 125000000), |
| 823 | }; |
| 824 | |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 825 | static unsigned long fsys0_clk_regs[] __initdata = { |
| 826 | MUX_SEL_FSYS00, |
| 827 | MUX_SEL_FSYS01, |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 828 | MUX_SEL_FSYS02, |
| 829 | ENABLE_ACLK_FSYS00, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 830 | ENABLE_ACLK_FSYS01, |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 831 | ENABLE_SCLK_FSYS01, |
| 832 | ENABLE_SCLK_FSYS02, |
| 833 | ENABLE_SCLK_FSYS04, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 834 | }; |
| 835 | |
| 836 | static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { |
| 837 | MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, |
| 838 | MUX_SEL_FSYS00, 24, 1), |
| 839 | |
| 840 | MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 841 | MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p, |
| 842 | MUX_SEL_FSYS01, 28, 1), |
| 843 | |
| 844 | MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", |
| 845 | mout_phyclk_usbdrd300_udrd30_pipe_pclk_p, |
| 846 | MUX_SEL_FSYS02, 24, 1), |
| 847 | MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", |
| 848 | mout_phyclk_usbdrd300_udrd30_phyclk_p, |
| 849 | MUX_SEL_FSYS02, 28, 1), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 850 | }; |
| 851 | |
| 852 | static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { |
Padmavathi Venna | 9cc2a0c9 | 2015-01-13 16:57:40 +0530 | [diff] [blame] | 853 | GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", |
| 854 | ENABLE_ACLK_FSYS00, 3, 0, 0), |
| 855 | GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", |
| 856 | ENABLE_ACLK_FSYS00, 4, 0, 0), |
Alim Akhtar | 7cca2e0 | 2015-08-26 09:00:43 +0530 | [diff] [blame] | 857 | GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", |
| 858 | "mout_aclk_fsys0_200_user", |
| 859 | ENABLE_ACLK_FSYS00, 19, 0, 0), |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 860 | |
| 861 | GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", |
| 862 | ENABLE_ACLK_FSYS01, 29, 0, 0), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 863 | GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", |
| 864 | ENABLE_ACLK_FSYS01, 31, 0, 0), |
Vivek Gautam | 83f191a | 2014-11-21 19:05:51 +0530 | [diff] [blame] | 865 | |
| 866 | GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", |
| 867 | "mout_sclk_usbdrd300_user", |
| 868 | ENABLE_SCLK_FSYS01, 4, 0, 0), |
| 869 | GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", |
| 870 | ENABLE_SCLK_FSYS01, 8, 0, 0), |
| 871 | |
| 872 | GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, |
| 873 | "phyclk_usbdrd300_udrd30_pipe_pclk_user", |
| 874 | "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", |
| 875 | ENABLE_SCLK_FSYS02, 24, 0, 0), |
| 876 | GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, |
| 877 | "phyclk_usbdrd300_udrd30_phyclk_user", |
| 878 | "mout_phyclk_usbdrd300_udrd30_phyclk_user", |
| 879 | ENABLE_SCLK_FSYS02, 28, 0, 0), |
| 880 | |
| 881 | GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", |
| 882 | "fin_pll", |
| 883 | ENABLE_SCLK_FSYS04, 28, 0, 0), |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 884 | }; |
| 885 | |
| 886 | static struct samsung_cmu_info fsys0_cmu_info __initdata = { |
| 887 | .mux_clks = fsys0_mux_clks, |
| 888 | .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), |
| 889 | .gate_clks = fsys0_gate_clks, |
| 890 | .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), |
Alim Akhtar | 7cca2e0 | 2015-08-26 09:00:43 +0530 | [diff] [blame] | 891 | .nr_clk_ids = FSYS0_NR_CLK, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 892 | .clk_regs = fsys0_clk_regs, |
| 893 | .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), |
| 894 | }; |
| 895 | |
| 896 | static void __init exynos7_clk_fsys0_init(struct device_node *np) |
| 897 | { |
| 898 | samsung_cmu_register_one(np, &fsys0_cmu_info); |
| 899 | } |
| 900 | |
| 901 | CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", |
| 902 | exynos7_clk_fsys0_init); |
| 903 | |
| 904 | /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ |
| 905 | #define MUX_SEL_FSYS10 0x0200 |
| 906 | #define MUX_SEL_FSYS11 0x0204 |
| 907 | #define ENABLE_ACLK_FSYS1 0x0800 |
| 908 | |
| 909 | /* |
| 910 | * List of parent clocks for Muxes in CMU_FSYS1 |
| 911 | */ |
| 912 | PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; |
| 913 | PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; |
| 914 | PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; |
| 915 | |
| 916 | static unsigned long fsys1_clk_regs[] __initdata = { |
| 917 | MUX_SEL_FSYS10, |
| 918 | MUX_SEL_FSYS11, |
| 919 | ENABLE_ACLK_FSYS1, |
| 920 | }; |
| 921 | |
| 922 | static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { |
| 923 | MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, |
| 924 | MUX_SEL_FSYS10, 28, 1), |
| 925 | |
| 926 | MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), |
| 927 | MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), |
| 928 | }; |
| 929 | |
| 930 | static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { |
| 931 | GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", |
| 932 | ENABLE_ACLK_FSYS1, 29, 0, 0), |
| 933 | GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", |
| 934 | ENABLE_ACLK_FSYS1, 30, 0, 0), |
| 935 | }; |
| 936 | |
| 937 | static struct samsung_cmu_info fsys1_cmu_info __initdata = { |
| 938 | .mux_clks = fsys1_mux_clks, |
| 939 | .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), |
| 940 | .gate_clks = fsys1_gate_clks, |
| 941 | .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), |
Alim Akhtar | 167c9e4 | 2015-08-26 09:00:44 +0530 | [diff] [blame] | 942 | .nr_clk_ids = FSYS1_NR_CLK, |
Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 943 | .clk_regs = fsys1_clk_regs, |
| 944 | .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), |
| 945 | }; |
| 946 | |
| 947 | static void __init exynos7_clk_fsys1_init(struct device_node *np) |
| 948 | { |
| 949 | samsung_cmu_register_one(np, &fsys1_cmu_info); |
| 950 | } |
| 951 | |
| 952 | CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", |
| 953 | exynos7_clk_fsys1_init); |
Tony K Nadackal | 49cab82 | 2014-12-17 13:03:37 +0530 | [diff] [blame] | 954 | |
| 955 | #define MUX_SEL_MSCL 0x0200 |
| 956 | #define DIV_MSCL 0x0600 |
| 957 | #define ENABLE_ACLK_MSCL 0x0800 |
| 958 | #define ENABLE_PCLK_MSCL 0x0900 |
| 959 | |
| 960 | /* List of parent clocks for Muxes in CMU_MSCL */ |
| 961 | PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; |
| 962 | |
| 963 | static unsigned long mscl_clk_regs[] __initdata = { |
| 964 | MUX_SEL_MSCL, |
| 965 | DIV_MSCL, |
| 966 | ENABLE_ACLK_MSCL, |
| 967 | ENABLE_PCLK_MSCL, |
| 968 | }; |
| 969 | |
| 970 | static struct samsung_mux_clock mscl_mux_clks[] __initdata = { |
| 971 | MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", |
| 972 | mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), |
| 973 | }; |
| 974 | static struct samsung_div_clock mscl_div_clks[] __initdata = { |
| 975 | DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", |
| 976 | DIV_MSCL, 0, 3), |
| 977 | }; |
| 978 | static struct samsung_gate_clock mscl_gate_clks[] __initdata = { |
| 979 | |
| 980 | GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", |
| 981 | ENABLE_ACLK_MSCL, 31, 0, 0), |
| 982 | GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", |
| 983 | ENABLE_ACLK_MSCL, 30, 0, 0), |
| 984 | GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", |
| 985 | ENABLE_ACLK_MSCL, 29, 0, 0), |
| 986 | GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", |
| 987 | ENABLE_ACLK_MSCL, 28, 0, 0), |
| 988 | GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", |
| 989 | "usermux_aclk_mscl_532", |
| 990 | ENABLE_ACLK_MSCL, 27, 0, 0), |
| 991 | GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", |
| 992 | "usermux_aclk_mscl_532", |
| 993 | ENABLE_ACLK_MSCL, 26, 0, 0), |
| 994 | GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", |
| 995 | ENABLE_ACLK_MSCL, 25, 0, 0), |
| 996 | GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", |
| 997 | ENABLE_ACLK_MSCL, 24, 0, 0), |
| 998 | GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", |
| 999 | "usermux_aclk_mscl_532", |
| 1000 | ENABLE_ACLK_MSCL, 23, 0, 0), |
| 1001 | GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", |
| 1002 | ENABLE_ACLK_MSCL, 22, 0, 0), |
| 1003 | GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", |
| 1004 | ENABLE_ACLK_MSCL, 21, 0, 0), |
| 1005 | GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", |
| 1006 | ENABLE_ACLK_MSCL, 20, 0, 0), |
| 1007 | GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", |
| 1008 | ENABLE_ACLK_MSCL, 19, 0, 0), |
| 1009 | GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", |
| 1010 | ENABLE_ACLK_MSCL, 18, 0, 0), |
| 1011 | GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", |
| 1012 | ENABLE_ACLK_MSCL, 17, 0, 0), |
| 1013 | GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", |
| 1014 | ENABLE_ACLK_MSCL, 16, 0, 0), |
| 1015 | GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", |
| 1016 | "usermux_aclk_mscl_532", |
| 1017 | ENABLE_ACLK_MSCL, 15, 0, 0), |
| 1018 | GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", |
| 1019 | "usermux_aclk_mscl_532", |
| 1020 | ENABLE_ACLK_MSCL, 14, 0, 0), |
| 1021 | |
| 1022 | GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", |
| 1023 | ENABLE_PCLK_MSCL, 31, 0, 0), |
| 1024 | GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", |
| 1025 | ENABLE_PCLK_MSCL, 30, 0, 0), |
| 1026 | GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", |
| 1027 | ENABLE_PCLK_MSCL, 29, 0, 0), |
| 1028 | GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", |
| 1029 | ENABLE_PCLK_MSCL, 28, 0, 0), |
| 1030 | GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", |
| 1031 | ENABLE_PCLK_MSCL, 27, 0, 0), |
| 1032 | GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", |
| 1033 | ENABLE_PCLK_MSCL, 26, 0, 0), |
| 1034 | GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", |
| 1035 | ENABLE_PCLK_MSCL, 25, 0, 0), |
| 1036 | GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", |
| 1037 | ENABLE_PCLK_MSCL, 24, 0, 0), |
| 1038 | GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", |
| 1039 | ENABLE_PCLK_MSCL, 23, 0, 0), |
| 1040 | GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", |
| 1041 | ENABLE_PCLK_MSCL, 22, 0, 0), |
| 1042 | GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", |
| 1043 | ENABLE_PCLK_MSCL, 21, 0, 0), |
| 1044 | GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", |
| 1045 | ENABLE_PCLK_MSCL, 20, 0, 0), |
| 1046 | }; |
| 1047 | |
| 1048 | static struct samsung_cmu_info mscl_cmu_info __initdata = { |
| 1049 | .mux_clks = mscl_mux_clks, |
| 1050 | .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), |
| 1051 | .div_clks = mscl_div_clks, |
| 1052 | .nr_div_clks = ARRAY_SIZE(mscl_div_clks), |
| 1053 | .gate_clks = mscl_gate_clks, |
| 1054 | .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), |
| 1055 | .nr_clk_ids = MSCL_NR_CLK, |
| 1056 | .clk_regs = mscl_clk_regs, |
| 1057 | .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), |
| 1058 | }; |
| 1059 | |
| 1060 | static void __init exynos7_clk_mscl_init(struct device_node *np) |
| 1061 | { |
| 1062 | samsung_cmu_register_one(np, &mscl_cmu_info); |
| 1063 | } |
| 1064 | |
| 1065 | CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", |
| 1066 | exynos7_clk_mscl_init); |
Padmavathi Venna | 9f930a3 | 2015-01-13 16:57:42 +0530 | [diff] [blame] | 1067 | |
| 1068 | /* Register Offset definitions for CMU_AUD (0x114C0000) */ |
| 1069 | #define MUX_SEL_AUD 0x0200 |
| 1070 | #define DIV_AUD0 0x0600 |
| 1071 | #define DIV_AUD1 0x0604 |
| 1072 | #define ENABLE_ACLK_AUD 0x0800 |
| 1073 | #define ENABLE_PCLK_AUD 0x0900 |
| 1074 | #define ENABLE_SCLK_AUD 0x0A00 |
| 1075 | |
| 1076 | /* |
| 1077 | * List of parent clocks for Muxes in CMU_AUD |
| 1078 | */ |
| 1079 | PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; |
| 1080 | PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; |
| 1081 | |
| 1082 | static unsigned long aud_clk_regs[] __initdata = { |
| 1083 | MUX_SEL_AUD, |
| 1084 | DIV_AUD0, |
| 1085 | DIV_AUD1, |
| 1086 | ENABLE_ACLK_AUD, |
| 1087 | ENABLE_PCLK_AUD, |
| 1088 | ENABLE_SCLK_AUD, |
| 1089 | }; |
| 1090 | |
| 1091 | static struct samsung_mux_clock aud_mux_clks[] __initdata = { |
| 1092 | MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), |
| 1093 | MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), |
| 1094 | MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), |
| 1095 | }; |
| 1096 | |
| 1097 | static struct samsung_div_clock aud_div_clks[] __initdata = { |
| 1098 | DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), |
| 1099 | DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), |
| 1100 | DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), |
| 1101 | |
| 1102 | DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), |
| 1103 | DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), |
| 1104 | DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), |
| 1105 | DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), |
| 1106 | DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), |
| 1107 | }; |
| 1108 | |
| 1109 | static struct samsung_gate_clock aud_gate_clks[] __initdata = { |
| 1110 | GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", |
| 1111 | ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), |
| 1112 | GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", |
| 1113 | ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), |
| 1114 | GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), |
| 1115 | GATE(0, "sclk_slimbus", "dout_sclk_slimbus", |
| 1116 | ENABLE_SCLK_AUD, 30, 0, 0), |
| 1117 | |
| 1118 | GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), |
| 1119 | GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), |
| 1120 | GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), |
| 1121 | GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), |
| 1122 | GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), |
| 1123 | GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), |
| 1124 | GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", |
| 1125 | ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), |
| 1126 | GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", |
| 1127 | ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), |
| 1128 | GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), |
| 1129 | GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), |
| 1130 | |
| 1131 | GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), |
| 1132 | GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", |
| 1133 | ENABLE_ACLK_AUD, 28, 0, 0), |
| 1134 | GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), |
| 1135 | }; |
| 1136 | |
| 1137 | static struct samsung_cmu_info aud_cmu_info __initdata = { |
| 1138 | .mux_clks = aud_mux_clks, |
| 1139 | .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), |
| 1140 | .div_clks = aud_div_clks, |
| 1141 | .nr_div_clks = ARRAY_SIZE(aud_div_clks), |
| 1142 | .gate_clks = aud_gate_clks, |
| 1143 | .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), |
| 1144 | .nr_clk_ids = AUD_NR_CLK, |
| 1145 | .clk_regs = aud_clk_regs, |
| 1146 | .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), |
| 1147 | }; |
| 1148 | |
| 1149 | static void __init exynos7_clk_aud_init(struct device_node *np) |
| 1150 | { |
| 1151 | samsung_cmu_register_one(np, &aud_cmu_info); |
| 1152 | } |
| 1153 | |
| 1154 | CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", |
| 1155 | exynos7_clk_aud_init); |