blob: 8338353e505b291ecacf7382423f517382064219 [file] [log] [blame]
Dave Airlief26c4732006-01-02 17:18:39 +11001/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
Alex Deucher45e51902008-05-28 13:28:59 +10005 * Copyright 2007 Advanced Micro Devices, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32#include "drmP.h"
33#include "drm.h"
Dave Airlie7c1c2872008-11-28 14:22:24 +100034#include "drm_sarea.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include "radeon_drm.h"
36#include "radeon_drv.h"
Dave Airlie414ed532005-08-16 20:43:16 +100037#include "r300_reg.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Alex Deucher9f184092008-05-28 11:21:25 +100039#include "radeon_microcode.h"
40
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#define RADEON_FIFO_DEBUG 0
42
Dave Airlie84b1fd12007-07-11 15:53:27 +100043static int radeon_do_cleanup_cp(struct drm_device * dev);
Jerome Glisse54f961a2008-08-13 09:46:31 +100044static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
David Millerb07fa022009-02-12 02:15:37 -080046static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
47{
48 u32 val;
49
50 if (dev_priv->flags & RADEON_IS_AGP) {
51 val = DRM_READ32(dev_priv->ring_rptr, off);
52 } else {
53 val = *(((volatile u32 *)
54 dev_priv->ring_rptr->handle) +
55 (off / sizeof(u32)));
56 val = le32_to_cpu(val);
57 }
58 return val;
59}
60
61u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
62{
63 if (dev_priv->writeback_works)
64 return radeon_read_ring_rptr(dev_priv, 0);
65 else
66 return RADEON_READ(RADEON_CP_RB_RPTR);
67}
68
69static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
70{
71 if (dev_priv->flags & RADEON_IS_AGP)
72 DRM_WRITE32(dev_priv->ring_rptr, off, val);
73 else
74 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
75 (off / sizeof(u32))) = cpu_to_le32(val);
76}
77
78void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
79{
80 radeon_write_ring_rptr(dev_priv, 0, val);
81}
82
83u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
84{
85 if (dev_priv->writeback_works)
86 return radeon_read_ring_rptr(dev_priv,
87 RADEON_SCRATCHOFF(index));
88 else
89 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
90}
91
Alex Deucher45e51902008-05-28 13:28:59 +100092static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
Dave Airlie3d5e2c12008-02-07 15:01:05 +100093{
94 u32 ret;
95 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
96 ret = RADEON_READ(R520_MC_IND_DATA);
97 RADEON_WRITE(R520_MC_IND_INDEX, 0);
98 return ret;
99}
100
Alex Deucher45e51902008-05-28 13:28:59 +1000101static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
102{
103 u32 ret;
104 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
105 ret = RADEON_READ(RS480_NB_MC_DATA);
106 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
107 return ret;
108}
109
Maciej Cencora60f92682008-02-19 21:32:45 +1000110static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
111{
Alex Deucher45e51902008-05-28 13:28:59 +1000112 u32 ret;
Maciej Cencora60f92682008-02-19 21:32:45 +1000113 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
Alex Deucher45e51902008-05-28 13:28:59 +1000114 ret = RADEON_READ(RS690_MC_DATA);
115 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
116 return ret;
117}
118
119static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
120{
Alex Deucherf0738e92008-10-16 17:12:02 +1000121 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
122 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Alex Deucher45e51902008-05-28 13:28:59 +1000123 return RS690_READ_MCIND(dev_priv, addr);
124 else
125 return RS480_READ_MCIND(dev_priv, addr);
Maciej Cencora60f92682008-02-19 21:32:45 +1000126}
127
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000128u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
129{
130
131 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000132 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
Alex Deucherf0738e92008-10-16 17:12:02 +1000133 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
134 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Maciej Cencora60f92682008-02-19 21:32:45 +1000135 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000136 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000137 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000138 else
139 return RADEON_READ(RADEON_MC_FB_LOCATION);
140}
141
142static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
143{
144 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000145 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
Alex Deucherf0738e92008-10-16 17:12:02 +1000146 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
147 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Maciej Cencora60f92682008-02-19 21:32:45 +1000148 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000149 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000150 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000151 else
152 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
153}
154
155static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
156{
157 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000158 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
Alex Deucherf0738e92008-10-16 17:12:02 +1000159 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
160 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Maciej Cencora60f92682008-02-19 21:32:45 +1000161 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000162 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000163 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000164 else
165 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
166}
167
Dave Airlie70b13d52008-06-19 11:40:44 +1000168static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
169{
170 u32 agp_base_hi = upper_32_bits(agp_base);
171 u32 agp_base_lo = agp_base & 0xffffffff;
172
173 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
174 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
175 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
Alex Deucherf0738e92008-10-16 17:12:02 +1000176 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
Dave Airlie70b13d52008-06-19 11:40:44 +1000178 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
179 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
180 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
181 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
182 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000183 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
184 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
Alex Deucher5cfb6952008-06-19 12:38:29 +1000185 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000186 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
Dave Airlie70b13d52008-06-19 11:40:44 +1000187 } else {
188 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
190 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
191 }
192}
193
Dave Airliedd8d7cb2009-02-20 13:28:59 +1000194static void radeon_enable_bm(struct drm_radeon_private *dev_priv)
195{
196 u32 tmp;
197 /* Turn on bus mastering */
198 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
199 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
200 /* rs600/rs690/rs740 */
201 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
202 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
203 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
204 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
205 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
206 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
207 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
208 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
209 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
210 } /* PCIE cards appears to not need this */
211}
212
Dave Airlie84b1fd12007-07-11 15:53:27 +1000213static int RADEON_READ_PLL(struct drm_device * dev, int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214{
215 drm_radeon_private_t *dev_priv = dev->dev_private;
216
217 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
218 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
219}
220
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000221static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222{
Dave Airlieea98a922005-09-11 20:28:11 +1000223 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
224 return RADEON_READ(RADEON_PCIE_DATA);
225}
226
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000228static void radeon_status(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
Harvey Harrisonbf9d8922008-04-30 00:55:10 -0700230 printk("%s:\n", __func__);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000231 printk("RBBM_STATUS = 0x%08x\n",
232 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
233 printk("CP_RB_RTPR = 0x%08x\n",
234 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
235 printk("CP_RB_WTPR = 0x%08x\n",
236 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
237 printk("AIC_CNTL = 0x%08x\n",
238 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
239 printk("AIC_STAT = 0x%08x\n",
240 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
241 printk("AIC_PT_BASE = 0x%08x\n",
242 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
243 printk("TLB_ADDR = 0x%08x\n",
244 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
245 printk("TLB_DATA = 0x%08x\n",
246 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247}
248#endif
249
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250/* ================================================================
251 * Engine, FIFO control
252 */
253
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000254static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255{
256 u32 tmp;
257 int i;
258
259 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
260
Alex Deucher259434a2008-05-28 11:51:12 +1000261 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
262 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
263 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
264 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
Alex Deucher259434a2008-05-28 11:51:12 +1000266 for (i = 0; i < dev_priv->usec_timeout; i++) {
267 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
268 & RADEON_RB3D_DC_BUSY)) {
269 return 0;
270 }
271 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 }
Alex Deucher259434a2008-05-28 11:51:12 +1000273 } else {
Jerome Glisse54f961a2008-08-13 09:46:31 +1000274 /* don't flush or purge cache here or lockup */
275 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 }
277
278#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000279 DRM_ERROR("failed!\n");
280 radeon_status(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281#endif
Eric Anholt20caafa2007-08-25 19:22:43 +1000282 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283}
284
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000285static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286{
287 int i;
288
289 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
290
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000291 for (i = 0; i < dev_priv->usec_timeout; i++) {
292 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
293 & RADEON_RBBM_FIFOCNT_MASK);
294 if (slots >= entries)
295 return 0;
296 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 }
Dave Airlie6c7be292008-09-01 08:51:52 +1000298 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
Jerome Glisse54f961a2008-08-13 09:46:31 +1000299 RADEON_READ(RADEON_RBBM_STATUS),
300 RADEON_READ(R300_VAP_CNTL_STATUS));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
302#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000303 DRM_ERROR("failed!\n");
304 radeon_status(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305#endif
Eric Anholt20caafa2007-08-25 19:22:43 +1000306 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307}
308
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000309static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310{
311 int i, ret;
312
313 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
314
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000315 ret = radeon_do_wait_for_fifo(dev_priv, 64);
316 if (ret)
317 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000319 for (i = 0; i < dev_priv->usec_timeout; i++) {
320 if (!(RADEON_READ(RADEON_RBBM_STATUS)
321 & RADEON_RBBM_ACTIVE)) {
322 radeon_do_pixcache_flush(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 return 0;
324 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000325 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 }
Dave Airlie6c7be292008-09-01 08:51:52 +1000327 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
Jerome Glisse54f961a2008-08-13 09:46:31 +1000328 RADEON_READ(RADEON_RBBM_STATUS),
329 RADEON_READ(R300_VAP_CNTL_STATUS));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
331#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000332 DRM_ERROR("failed!\n");
333 radeon_status(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334#endif
Eric Anholt20caafa2007-08-25 19:22:43 +1000335 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336}
337
Alex Deucher5b92c402008-05-28 11:57:40 +1000338static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
339{
340 uint32_t gb_tile_config, gb_pipe_sel = 0;
341
342 /* RS4xx/RS6xx/R4xx/R5xx */
343 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
344 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
345 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
346 } else {
347 /* R3xx */
348 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
349 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
350 dev_priv->num_gb_pipes = 2;
351 } else {
352 /* R3Vxx */
353 dev_priv->num_gb_pipes = 1;
354 }
355 }
356 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
357
358 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
359
360 switch (dev_priv->num_gb_pipes) {
361 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
362 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
363 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
364 default:
365 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
366 }
367
368 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
369 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
370 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
371 }
372 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
373 radeon_do_wait_for_idle(dev_priv);
374 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
375 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
376 R300_DC_AUTOFLUSH_ENABLE |
377 R300_DC_DC_DISABLE_IGNORE_PE));
378
379
380}
381
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382/* ================================================================
383 * CP control, initialization
384 */
385
386/* Load the microcode for the CP */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000387static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388{
389 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000390 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000392 radeon_do_wait_for_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000394 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
Alex Deucher9f184092008-05-28 11:21:25 +1000395 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
396 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
397 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
398 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
399 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
400 DRM_INFO("Loading R100 Microcode\n");
401 for (i = 0; i < 256; i++) {
402 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
403 R100_cp_microcode[i][1]);
404 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
405 R100_cp_microcode[i][0]);
406 }
407 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
408 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
409 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
410 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 DRM_INFO("Loading R200 Microcode\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000412 for (i = 0; i < 256; i++) {
413 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
414 R200_cp_microcode[i][1]);
415 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
416 R200_cp_microcode[i][0]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 }
Alex Deucher9f184092008-05-28 11:21:25 +1000418 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
419 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
420 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
421 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000422 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
Alex Deucher45e51902008-05-28 13:28:59 +1000423 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 DRM_INFO("Loading R300 Microcode\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000425 for (i = 0; i < 256; i++) {
426 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
427 R300_cp_microcode[i][1]);
428 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
429 R300_cp_microcode[i][0]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 }
Alex Deucher9f184092008-05-28 11:21:25 +1000431 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
Alex Deucheredc6f382008-10-17 09:21:45 +1000432 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
Alex Deucher9f184092008-05-28 11:21:25 +1000433 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
434 DRM_INFO("Loading R400 Microcode\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000435 for (i = 0; i < 256; i++) {
436 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
Alex Deucher9f184092008-05-28 11:21:25 +1000437 R420_cp_microcode[i][1]);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000438 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
Alex Deucher9f184092008-05-28 11:21:25 +1000439 R420_cp_microcode[i][0]);
440 }
Alex Deucherf0738e92008-10-16 17:12:02 +1000441 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
442 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
443 DRM_INFO("Loading RS690/RS740 Microcode\n");
Alex Deucher9f184092008-05-28 11:21:25 +1000444 for (i = 0; i < 256; i++) {
445 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
446 RS690_cp_microcode[i][1]);
447 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
448 RS690_cp_microcode[i][0]);
449 }
450 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
451 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
452 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
453 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
454 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
455 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
456 DRM_INFO("Loading R500 Microcode\n");
457 for (i = 0; i < 256; i++) {
458 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
459 R520_cp_microcode[i][1]);
460 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
461 R520_cp_microcode[i][0]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 }
463 }
464}
465
466/* Flush any pending commands to the CP. This should only be used just
467 * prior to a wait for idle, as it informs the engine that the command
468 * stream is ending.
469 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000470static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000472 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473#if 0
474 u32 tmp;
475
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000476 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
477 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478#endif
479}
480
481/* Wait for the CP to go idle.
482 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000483int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484{
485 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000486 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000488 BEGIN_RING(6);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489
490 RADEON_PURGE_CACHE();
491 RADEON_PURGE_ZCACHE();
492 RADEON_WAIT_UNTIL_IDLE();
493
494 ADVANCE_RING();
495 COMMIT_RING();
496
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000497 return radeon_do_wait_for_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498}
499
500/* Start the Command Processor.
501 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000502static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503{
504 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000505 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000507 radeon_do_wait_for_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000509 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510
511 dev_priv->cp_running = 1;
512
Jerome Glisse54f961a2008-08-13 09:46:31 +1000513 BEGIN_RING(8);
514 /* isync can only be written through cp on r5xx write it here */
515 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
516 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
517 RADEON_ISYNC_ANY3D_IDLE2D |
518 RADEON_ISYNC_WAIT_IDLEGUI |
519 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520 RADEON_PURGE_CACHE();
521 RADEON_PURGE_ZCACHE();
522 RADEON_WAIT_UNTIL_IDLE();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 ADVANCE_RING();
524 COMMIT_RING();
Jerome Glisse54f961a2008-08-13 09:46:31 +1000525
526 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527}
528
529/* Reset the Command Processor. This will not flush any pending
530 * commands, so you must wait for the CP command stream to complete
531 * before calling this routine.
532 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000533static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534{
535 u32 cur_read_ptr;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000536 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000538 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
539 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
540 SET_RING_HEAD(dev_priv, cur_read_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 dev_priv->ring.tail = cur_read_ptr;
542}
543
544/* Stop the Command Processor. This will not flush any pending
545 * commands, so you must flush the command stream and wait for the CP
546 * to go idle before calling this routine.
547 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000548static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000550 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000552 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553
554 dev_priv->cp_running = 0;
555}
556
557/* Reset the engine. This will stop the CP if it is running.
558 */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000559static int radeon_do_engine_reset(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560{
561 drm_radeon_private_t *dev_priv = dev->dev_private;
Alex Deucherd396db32008-05-28 11:54:06 +1000562 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000563 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000565 radeon_do_pixcache_flush(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566
Alex Deucherd396db32008-05-28 11:54:06 +1000567 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
568 /* may need something similar for newer chips */
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000569 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
570 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000572 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
573 RADEON_FORCEON_MCLKA |
574 RADEON_FORCEON_MCLKB |
575 RADEON_FORCEON_YCLKA |
576 RADEON_FORCEON_YCLKB |
577 RADEON_FORCEON_MC |
578 RADEON_FORCEON_AIC));
Alex Deucherd396db32008-05-28 11:54:06 +1000579 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
Alex Deucherd396db32008-05-28 11:54:06 +1000581 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582
Alex Deucherd396db32008-05-28 11:54:06 +1000583 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
584 RADEON_SOFT_RESET_CP |
585 RADEON_SOFT_RESET_HI |
586 RADEON_SOFT_RESET_SE |
587 RADEON_SOFT_RESET_RE |
588 RADEON_SOFT_RESET_PP |
589 RADEON_SOFT_RESET_E2 |
590 RADEON_SOFT_RESET_RB));
591 RADEON_READ(RADEON_RBBM_SOFT_RESET);
592 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
593 ~(RADEON_SOFT_RESET_CP |
594 RADEON_SOFT_RESET_HI |
595 RADEON_SOFT_RESET_SE |
596 RADEON_SOFT_RESET_RE |
597 RADEON_SOFT_RESET_PP |
598 RADEON_SOFT_RESET_E2 |
599 RADEON_SOFT_RESET_RB)));
600 RADEON_READ(RADEON_RBBM_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601
Alex Deucherd396db32008-05-28 11:54:06 +1000602 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000603 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
604 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
605 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
606 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607
Alex Deucher5b92c402008-05-28 11:57:40 +1000608 /* setup the raster pipes */
609 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
610 radeon_init_pipes(dev_priv);
611
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612 /* Reset the CP ring */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000613 radeon_do_cp_reset(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614
615 /* The CP is no longer running after an engine reset */
616 dev_priv->cp_running = 0;
617
618 /* Reset any pending vertex, indirect buffers */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000619 radeon_freelist_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620
621 return 0;
622}
623
Dave Airlie84b1fd12007-07-11 15:53:27 +1000624static void radeon_cp_init_ring_buffer(struct drm_device * dev,
etienne3d161182009-02-20 09:44:45 +1000625 drm_radeon_private_t *dev_priv,
626 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627{
etienne3d161182009-02-20 09:44:45 +1000628 struct drm_radeon_master_private *master_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 u32 ring_start, cur_read_ptr;
Dave Airliebc5f4522007-11-05 12:50:58 +1000630
Dave Airlied5ea7022006-03-19 19:37:55 +1100631 /* Initialize the memory controller. With new memory map, the fb location
632 * is not changed, it should have been properly initialized already. Part
633 * of the problem is that the code below is bogus, assuming the GART is
634 * always appended to the fb which is not necessarily the case
635 */
636 if (!dev_priv->new_memmap)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000637 radeon_write_fb_location(dev_priv,
Dave Airlied5ea7022006-03-19 19:37:55 +1100638 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
639 | (dev_priv->fb_location >> 16));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640
641#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +1000642 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlie70b13d52008-06-19 11:40:44 +1000643 radeon_write_agp_base(dev_priv, dev->agp->base);
644
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000645 radeon_write_agp_location(dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000646 (((dev_priv->gart_vm_start - 1 +
647 dev_priv->gart_size) & 0xffff0000) |
648 (dev_priv->gart_vm_start >> 16)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649
650 ring_start = (dev_priv->cp_ring->offset
651 - dev->agp->base
652 + dev_priv->gart_vm_start);
Ivan Kokshayskyb0917bd2005-10-26 11:05:25 +0100653 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654#endif
655 ring_start = (dev_priv->cp_ring->offset
Ivan Kokshayskyb0917bd2005-10-26 11:05:25 +0100656 - (unsigned long)dev->sg->virtual
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 + dev_priv->gart_vm_start);
658
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000659 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
661 /* Set the write pointer delay */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000662 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
664 /* Initialize the ring buffer's read and write pointers */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000665 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
666 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
667 SET_RING_HEAD(dev_priv, cur_read_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 dev_priv->ring.tail = cur_read_ptr;
669
670#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +1000671 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000672 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
673 dev_priv->ring_rptr->offset
674 - dev->agp->base + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 } else
676#endif
677 {
David Millere8a89432009-02-12 02:15:44 -0800678 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
679 dev_priv->ring_rptr->offset
680 - ((unsigned long) dev->sg->virtual)
681 + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 }
683
Dave Airlied5ea7022006-03-19 19:37:55 +1100684 /* Set ring buffer size */
685#ifdef __BIG_ENDIAN
686 RADEON_WRITE(RADEON_CP_RB_CNTL,
Roland Scheidegger576cc452008-02-07 14:59:24 +1000687 RADEON_BUF_SWAP_32BIT |
688 (dev_priv->ring.fetch_size_l2ow << 18) |
689 (dev_priv->ring.rptr_update_l2qw << 8) |
690 dev_priv->ring.size_l2qw);
Dave Airlied5ea7022006-03-19 19:37:55 +1100691#else
Roland Scheidegger576cc452008-02-07 14:59:24 +1000692 RADEON_WRITE(RADEON_CP_RB_CNTL,
693 (dev_priv->ring.fetch_size_l2ow << 18) |
694 (dev_priv->ring.rptr_update_l2qw << 8) |
695 dev_priv->ring.size_l2qw);
Dave Airlied5ea7022006-03-19 19:37:55 +1100696#endif
697
Dave Airlied5ea7022006-03-19 19:37:55 +1100698
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 /* Initialize the scratch register pointer. This will cause
700 * the scratch register values to be written out to memory
701 * whenever they are updated.
702 *
703 * We simply put this behind the ring read pointer, this works
704 * with PCI GART as well as (whatever kind of) AGP GART
705 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000706 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
707 + RADEON_SCRATCH_REG_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000709 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710
Dave Airliedd8d7cb2009-02-20 13:28:59 +1000711 radeon_enable_bm(dev_priv);
Dave Airlied5ea7022006-03-19 19:37:55 +1100712
David Millerb07fa022009-02-12 02:15:37 -0800713 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000714 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
Dave Airlied5ea7022006-03-19 19:37:55 +1100715
David Millerb07fa022009-02-12 02:15:37 -0800716 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000717 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
Dave Airlied5ea7022006-03-19 19:37:55 +1100718
David Millerb07fa022009-02-12 02:15:37 -0800719 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000720 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
Dave Airlied5ea7022006-03-19 19:37:55 +1100721
etienne3d161182009-02-20 09:44:45 +1000722 /* reset sarea copies of these */
723 master_priv = file_priv->master->driver_priv;
724 if (master_priv->sarea_priv) {
725 master_priv->sarea_priv->last_frame = 0;
726 master_priv->sarea_priv->last_dispatch = 0;
727 master_priv->sarea_priv->last_clear = 0;
728 }
729
Dave Airlied5ea7022006-03-19 19:37:55 +1100730 radeon_do_wait_for_idle(dev_priv);
731
732 /* Sync everything up */
733 RADEON_WRITE(RADEON_ISYNC_CNTL,
734 (RADEON_ISYNC_ANY2D_IDLE3D |
735 RADEON_ISYNC_ANY3D_IDLE2D |
736 RADEON_ISYNC_WAIT_IDLEGUI |
737 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
738
739}
740
741static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
742{
743 u32 tmp;
744
Dave Airlie6b79d522008-09-02 10:10:16 +1000745 /* Start with assuming that writeback doesn't work */
746 dev_priv->writeback_works = 0;
747
Dave Airlied5ea7022006-03-19 19:37:55 +1100748 /* Writeback doesn't seem to work everywhere, test it here and possibly
749 * enable it if it appears to work
750 */
David Millerb07fa022009-02-12 02:15:37 -0800751 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
752
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000753 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000755 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
David Millerb07fa022009-02-12 02:15:37 -0800756 u32 val;
757
758 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
759 if (val == 0xdeadbeef)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 break;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000761 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762 }
763
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000764 if (tmp < dev_priv->usec_timeout) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 dev_priv->writeback_works = 1;
Dave Airlied5ea7022006-03-19 19:37:55 +1100766 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767 } else {
768 dev_priv->writeback_works = 0;
Dave Airlied5ea7022006-03-19 19:37:55 +1100769 DRM_INFO("writeback test failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 }
Dave Airlie689b9d72005-09-30 17:09:07 +1000771 if (radeon_no_wb == 1) {
772 dev_priv->writeback_works = 0;
Dave Airlied5ea7022006-03-19 19:37:55 +1100773 DRM_INFO("writeback forced off\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 }
Michel Dänzerae1b1a482006-08-07 20:37:46 +1000775
776 if (!dev_priv->writeback_works) {
777 /* Disable writeback to avoid unnecessary bus master transfer */
778 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
779 RADEON_RB_NO_UPDATE);
780 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
781 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782}
783
Dave Airlief2b04cd2007-05-08 15:19:23 +1000784/* Enable or disable IGP GART on the chip */
785static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
786{
Maciej Cencora60f92682008-02-19 21:32:45 +1000787 u32 temp;
788
789 if (on) {
Alex Deucher45e51902008-05-28 13:28:59 +1000790 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
Maciej Cencora60f92682008-02-19 21:32:45 +1000791 dev_priv->gart_vm_start,
792 (long)dev_priv->gart_info.bus_addr,
793 dev_priv->gart_size);
794
Alex Deucher45e51902008-05-28 13:28:59 +1000795 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
Alex Deucherf0738e92008-10-16 17:12:02 +1000796 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
797 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Alex Deucher45e51902008-05-28 13:28:59 +1000798 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
799 RS690_BLOCK_GFX_D3_EN));
800 else
801 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
Maciej Cencora60f92682008-02-19 21:32:45 +1000802
Alex Deucher45e51902008-05-28 13:28:59 +1000803 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
804 RS480_VA_SIZE_32MB));
Maciej Cencora60f92682008-02-19 21:32:45 +1000805
Alex Deucher45e51902008-05-28 13:28:59 +1000806 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
807 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
808 RS480_TLB_ENABLE |
809 RS480_GTW_LAC_EN |
810 RS480_1LEVEL_GART));
Maciej Cencora60f92682008-02-19 21:32:45 +1000811
Dave Airliefa0d71b2008-05-28 11:27:01 +1000812 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
813 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
Alex Deucher45e51902008-05-28 13:28:59 +1000814 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
Maciej Cencora60f92682008-02-19 21:32:45 +1000815
Alex Deucher45e51902008-05-28 13:28:59 +1000816 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
817 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
818 RS480_REQ_TYPE_SNOOP_DIS));
Maciej Cencora60f92682008-02-19 21:32:45 +1000819
Alex Deucher5cfb6952008-06-19 12:38:29 +1000820 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
Dave Airlie3722bfc2008-05-28 11:28:27 +1000821
Maciej Cencora60f92682008-02-19 21:32:45 +1000822 dev_priv->gart_size = 32*1024*1024;
823 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
824 0xffff0000) | (dev_priv->gart_vm_start >> 16));
825
Alex Deucher45e51902008-05-28 13:28:59 +1000826 radeon_write_agp_location(dev_priv, temp);
Maciej Cencora60f92682008-02-19 21:32:45 +1000827
Alex Deucher45e51902008-05-28 13:28:59 +1000828 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
829 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
830 RS480_VA_SIZE_32MB));
Maciej Cencora60f92682008-02-19 21:32:45 +1000831
832 do {
Alex Deucher45e51902008-05-28 13:28:59 +1000833 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
834 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
Maciej Cencora60f92682008-02-19 21:32:45 +1000835 break;
836 DRM_UDELAY(1);
837 } while (1);
838
Alex Deucher45e51902008-05-28 13:28:59 +1000839 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
840 RS480_GART_CACHE_INVALIDATE);
Alex Deucher27359772008-05-28 12:54:16 +1000841
Maciej Cencora60f92682008-02-19 21:32:45 +1000842 do {
Alex Deucher45e51902008-05-28 13:28:59 +1000843 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
844 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
Maciej Cencora60f92682008-02-19 21:32:45 +1000845 break;
846 DRM_UDELAY(1);
847 } while (1);
848
Alex Deucher45e51902008-05-28 13:28:59 +1000849 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
Maciej Cencora60f92682008-02-19 21:32:45 +1000850 } else {
Alex Deucher45e51902008-05-28 13:28:59 +1000851 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
Maciej Cencora60f92682008-02-19 21:32:45 +1000852 }
853}
854
Dave Airlieea98a922005-09-11 20:28:11 +1000855static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856{
Dave Airlieea98a922005-09-11 20:28:11 +1000857 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
858 if (on) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859
Dave Airlieea98a922005-09-11 20:28:11 +1000860 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000861 dev_priv->gart_vm_start,
862 (long)dev_priv->gart_info.bus_addr,
Dave Airlieea98a922005-09-11 20:28:11 +1000863 dev_priv->gart_size);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000864 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
865 dev_priv->gart_vm_start);
866 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
867 dev_priv->gart_info.bus_addr);
868 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
869 dev_priv->gart_vm_start);
870 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
871 dev_priv->gart_vm_start +
872 dev_priv->gart_size - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000874 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000876 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
877 RADEON_PCIE_TX_GART_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 } else {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000879 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
880 tmp & ~RADEON_PCIE_TX_GART_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 }
882}
883
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884/* Enable or disable PCI GART on the chip */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000885static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886{
Dave Airlied985c102006-01-02 21:32:48 +1100887 u32 tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888
Alex Deucher45e51902008-05-28 13:28:59 +1000889 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
Alex Deucherf0738e92008-10-16 17:12:02 +1000890 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
Alex Deucher45e51902008-05-28 13:28:59 +1000891 (dev_priv->flags & RADEON_IS_IGPGART)) {
Dave Airlief2b04cd2007-05-08 15:19:23 +1000892 radeon_set_igpgart(dev_priv, on);
893 return;
894 }
895
Dave Airlie54a56ac2006-09-22 04:25:09 +1000896 if (dev_priv->flags & RADEON_IS_PCIE) {
Dave Airlieea98a922005-09-11 20:28:11 +1000897 radeon_set_pciegart(dev_priv, on);
898 return;
899 }
900
Dave Airliebc5f4522007-11-05 12:50:58 +1000901 tmp = RADEON_READ(RADEON_AIC_CNTL);
Dave Airlied985c102006-01-02 21:32:48 +1100902
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000903 if (on) {
904 RADEON_WRITE(RADEON_AIC_CNTL,
905 tmp | RADEON_PCIGART_TRANSLATE_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906
907 /* set PCI GART page-table base address
908 */
Dave Airlieea98a922005-09-11 20:28:11 +1000909 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910
911 /* set address range for PCI address translate
912 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000913 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
914 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
915 + dev_priv->gart_size - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916
917 /* Turn off AGP aperture -- is this required for PCI GART?
918 */
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000919 radeon_write_agp_location(dev_priv, 0xffffffc0);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000920 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921 } else {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000922 RADEON_WRITE(RADEON_AIC_CNTL,
923 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 }
925}
926
David Miller6abf6bb2009-02-14 01:51:07 -0800927static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
928{
929 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
930 struct radeon_virt_surface *vp;
931 int i;
932
933 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
934 if (!dev_priv->virt_surfaces[i].file_priv ||
935 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
936 break;
937 }
938 if (i >= 2 * RADEON_MAX_SURFACES)
939 return -ENOMEM;
940 vp = &dev_priv->virt_surfaces[i];
941
942 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
943 struct radeon_surface *sp = &dev_priv->surfaces[i];
944 if (sp->refcount)
945 continue;
946
947 vp->surface_index = i;
948 vp->lower = gart_info->bus_addr;
949 vp->upper = vp->lower + gart_info->table_size;
950 vp->flags = 0;
951 vp->file_priv = PCIGART_FILE_PRIV;
952
953 sp->refcount = 1;
954 sp->lower = vp->lower;
955 sp->upper = vp->upper;
956 sp->flags = 0;
957
958 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
959 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
960 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
961 return 0;
962 }
963
964 return -ENOMEM;
965}
966
Dave Airlie7c1c2872008-11-28 14:22:24 +1000967static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
968 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969{
Dave Airlied985c102006-01-02 21:32:48 +1100970 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000971 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
Dave Airlied985c102006-01-02 21:32:48 +1100972
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000973 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974
Dave Airlief3dd5c32006-03-25 18:09:46 +1100975 /* if we require new memory map but we don't have it fail */
Dave Airlie54a56ac2006-09-22 04:25:09 +1000976 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
Dave Airlieb15ec362006-08-19 17:43:52 +1000977 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
Dave Airlief3dd5c32006-03-25 18:09:46 +1100978 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +1000979 return -EINVAL;
Dave Airlief3dd5c32006-03-25 18:09:46 +1100980 }
981
Dave Airlie54a56ac2006-09-22 04:25:09 +1000982 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
Dave Airlied985c102006-01-02 21:32:48 +1100983 DRM_DEBUG("Forcing AGP card to PCI mode\n");
Dave Airlie54a56ac2006-09-22 04:25:09 +1000984 dev_priv->flags &= ~RADEON_IS_AGP;
985 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
Dave Airlieb15ec362006-08-19 17:43:52 +1000986 && !init->is_pci) {
987 DRM_DEBUG("Restoring AGP flag\n");
Dave Airlie54a56ac2006-09-22 04:25:09 +1000988 dev_priv->flags |= RADEON_IS_AGP;
Dave Airlied985c102006-01-02 21:32:48 +1100989 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990
Dave Airlie54a56ac2006-09-22 04:25:09 +1000991 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000992 DRM_ERROR("PCI GART memory not allocated!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +1000994 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 }
996
997 dev_priv->usec_timeout = init->usec_timeout;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000998 if (dev_priv->usec_timeout < 1 ||
999 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1000 DRM_DEBUG("TIMEOUT problem!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001002 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 }
1004
Dave Airlieddbee332007-07-11 12:16:01 +10001005 /* Enable vblank on CRTC1 for older X servers
1006 */
1007 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1008
Dave Airlied985c102006-01-02 21:32:48 +11001009 switch(init->func) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 case RADEON_INIT_R200_CP:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001011 dev_priv->microcode_version = UCODE_R200;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 break;
1013 case RADEON_INIT_R300_CP:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001014 dev_priv->microcode_version = UCODE_R300;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 break;
1016 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001017 dev_priv->microcode_version = UCODE_R100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001019
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 dev_priv->do_boxes = 0;
1021 dev_priv->cp_mode = init->cp_mode;
1022
1023 /* We don't support anything other than bus-mastering ring mode,
1024 * but the ring can be in either AGP or PCI space for the ring
1025 * read pointer.
1026 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001027 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1028 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1029 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001031 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032 }
1033
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001034 switch (init->fb_bpp) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035 case 16:
1036 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1037 break;
1038 case 32:
1039 default:
1040 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1041 break;
1042 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001043 dev_priv->front_offset = init->front_offset;
1044 dev_priv->front_pitch = init->front_pitch;
1045 dev_priv->back_offset = init->back_offset;
1046 dev_priv->back_pitch = init->back_pitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001048 switch (init->depth_bpp) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049 case 16:
1050 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1051 break;
1052 case 32:
1053 default:
1054 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1055 break;
1056 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001057 dev_priv->depth_offset = init->depth_offset;
1058 dev_priv->depth_pitch = init->depth_pitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059
1060 /* Hardware state for depth clears. Remove this if/when we no
1061 * longer clear the depth buffer with a 3D rectangle. Hard-code
1062 * all values to prevent unwanted 3D state from slipping through
1063 * and screwing with the clear operation.
1064 */
1065 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1066 (dev_priv->color_fmt << 10) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001067 (dev_priv->microcode_version ==
1068 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001070 dev_priv->depth_clear.rb3d_zstencilcntl =
1071 (dev_priv->depth_fmt |
1072 RADEON_Z_TEST_ALWAYS |
1073 RADEON_STENCIL_TEST_ALWAYS |
1074 RADEON_STENCIL_S_FAIL_REPLACE |
1075 RADEON_STENCIL_ZPASS_REPLACE |
1076 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077
1078 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1079 RADEON_BFACE_SOLID |
1080 RADEON_FFACE_SOLID |
1081 RADEON_FLAT_SHADE_VTX_LAST |
1082 RADEON_DIFFUSE_SHADE_FLAT |
1083 RADEON_ALPHA_SHADE_FLAT |
1084 RADEON_SPECULAR_SHADE_FLAT |
1085 RADEON_FOG_SHADE_FLAT |
1086 RADEON_VTX_PIX_CENTER_OGL |
1087 RADEON_ROUND_MODE_TRUNC |
1088 RADEON_ROUND_PREC_8TH_PIX);
1089
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091 dev_priv->ring_offset = init->ring_offset;
1092 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1093 dev_priv->buffers_offset = init->buffers_offset;
1094 dev_priv->gart_textures_offset = init->gart_textures_offset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001095
Dave Airlie7c1c2872008-11-28 14:22:24 +10001096 master_priv->sarea = drm_getsarea(dev);
1097 if (!master_priv->sarea) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098 DRM_ERROR("could not find sarea!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001100 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101 }
1102
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001104 if (!dev_priv->cp_ring) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 DRM_ERROR("could not find cp ring region!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001107 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108 }
1109 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001110 if (!dev_priv->ring_rptr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 DRM_ERROR("could not find ring read pointer!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001113 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 }
Dave Airlied1f2b552005-08-05 22:11:22 +10001115 dev->agp_buffer_token = init->buffers_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001117 if (!dev->agp_buffer_map) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 DRM_ERROR("could not find dma buffer region!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001120 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 }
1122
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001123 if (init->gart_textures_offset) {
1124 dev_priv->gart_textures =
1125 drm_core_findmap(dev, init->gart_textures_offset);
1126 if (!dev_priv->gart_textures) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127 DRM_ERROR("could not find GART texture region!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001129 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130 }
1131 }
1132
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001134 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlie9b8d5a12009-02-07 11:15:41 +10001135 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1136 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1137 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001138 if (!dev_priv->cp_ring->handle ||
1139 !dev_priv->ring_rptr->handle ||
1140 !dev->agp_buffer_map->handle) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 DRM_ERROR("could not find ioremap agp regions!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001143 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144 }
1145 } else
1146#endif
1147 {
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001148 dev_priv->cp_ring->handle =
1149 (void *)(unsigned long)dev_priv->cp_ring->offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150 dev_priv->ring_rptr->handle =
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001151 (void *)(unsigned long)dev_priv->ring_rptr->offset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001152 dev->agp_buffer_map->handle =
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001153 (void *)(unsigned long)dev->agp_buffer_map->offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001155 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1156 dev_priv->cp_ring->handle);
1157 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1158 dev_priv->ring_rptr->handle);
1159 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1160 dev->agp_buffer_map->handle);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161 }
1162
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001163 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
Dave Airliebc5f4522007-11-05 12:50:58 +10001164 dev_priv->fb_size =
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001165 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
Dave Airlied5ea7022006-03-19 19:37:55 +11001166 - dev_priv->fb_location;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001168 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1169 ((dev_priv->front_offset
1170 + dev_priv->fb_location) >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001172 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1173 ((dev_priv->back_offset
1174 + dev_priv->fb_location) >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001176 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1177 ((dev_priv->depth_offset
1178 + dev_priv->fb_location) >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179
1180 dev_priv->gart_size = init->gart_size;
Dave Airlied5ea7022006-03-19 19:37:55 +11001181
1182 /* New let's set the memory map ... */
1183 if (dev_priv->new_memmap) {
1184 u32 base = 0;
1185
1186 DRM_INFO("Setting GART location based on new memory map\n");
1187
1188 /* If using AGP, try to locate the AGP aperture at the same
1189 * location in the card and on the bus, though we have to
1190 * align it down.
1191 */
1192#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001193 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlied5ea7022006-03-19 19:37:55 +11001194 base = dev->agp->base;
1195 /* Check if valid */
Michel Dänzer80b2c382007-02-18 18:03:21 +11001196 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1197 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
Dave Airlied5ea7022006-03-19 19:37:55 +11001198 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1199 dev->agp->base);
1200 base = 0;
1201 }
1202 }
1203#endif
1204 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1205 if (base == 0) {
1206 base = dev_priv->fb_location + dev_priv->fb_size;
Michel Dänzer80b2c382007-02-18 18:03:21 +11001207 if (base < dev_priv->fb_location ||
1208 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
Dave Airlied5ea7022006-03-19 19:37:55 +11001209 base = dev_priv->fb_location
1210 - dev_priv->gart_size;
Dave Airliebc5f4522007-11-05 12:50:58 +10001211 }
Dave Airlied5ea7022006-03-19 19:37:55 +11001212 dev_priv->gart_vm_start = base & 0xffc00000u;
1213 if (dev_priv->gart_vm_start != base)
1214 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1215 base, dev_priv->gart_vm_start);
1216 } else {
1217 DRM_INFO("Setting GART location based on old memory map\n");
1218 dev_priv->gart_vm_start = dev_priv->fb_location +
1219 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1220 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221
1222#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001223 if (dev_priv->flags & RADEON_IS_AGP)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001225 - dev->agp->base
1226 + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 else
1228#endif
1229 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
Ivan Kokshayskyb0917bd2005-10-26 11:05:25 +01001230 - (unsigned long)dev->sg->virtual
1231 + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001233 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1234 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1235 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1236 dev_priv->gart_buffers_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001238 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1239 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 + init->ring_size / sizeof(u32));
1241 dev_priv->ring.size = init->ring_size;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001242 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243
Roland Scheidegger576cc452008-02-07 14:59:24 +10001244 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1245 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1246
1247 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1248 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001249 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250
1251 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1252
1253#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001254 if (dev_priv->flags & RADEON_IS_AGP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255 /* Turn off PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001256 radeon_set_pcigart(dev_priv, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257 } else
1258#endif
1259 {
David Miller6abf6bb2009-02-14 01:51:07 -08001260 u32 sctrl;
1261 int ret;
1262
Dave Airlieb05c2382008-03-17 10:24:24 +10001263 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
Dave Airlieea98a922005-09-11 20:28:11 +10001264 /* if we have an offset set from userspace */
Dave Airlief2b04cd2007-05-08 15:19:23 +10001265 if (dev_priv->pcigart_offset_set) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001266 dev_priv->gart_info.bus_addr =
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001267 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
Dave Airlief26c4732006-01-02 17:18:39 +11001268 dev_priv->gart_info.mapping.offset =
Dave Airlie7fc86862007-11-05 10:45:27 +10001269 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
Dave Airlief26c4732006-01-02 17:18:39 +11001270 dev_priv->gart_info.mapping.size =
Dave Airlief2b04cd2007-05-08 15:19:23 +10001271 dev_priv->gart_info.table_size;
Dave Airlief26c4732006-01-02 17:18:39 +11001272
Dave Airlie242e3df2008-07-15 15:48:05 +10001273 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001274 dev_priv->gart_info.addr =
Dave Airlief26c4732006-01-02 17:18:39 +11001275 dev_priv->gart_info.mapping.handle;
Dave Airlieea98a922005-09-11 20:28:11 +10001276
Dave Airlief2b04cd2007-05-08 15:19:23 +10001277 if (dev_priv->flags & RADEON_IS_PCIE)
1278 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1279 else
1280 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001281 dev_priv->gart_info.gart_table_location =
1282 DRM_ATI_GART_FB;
1283
Dave Airlief26c4732006-01-02 17:18:39 +11001284 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001285 dev_priv->gart_info.addr,
1286 dev_priv->pcigart_offset);
1287 } else {
Dave Airlief2b04cd2007-05-08 15:19:23 +10001288 if (dev_priv->flags & RADEON_IS_IGPGART)
1289 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1290 else
1291 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001292 dev_priv->gart_info.gart_table_location =
1293 DRM_ATI_GART_MAIN;
Dave Airlief26c4732006-01-02 17:18:39 +11001294 dev_priv->gart_info.addr = NULL;
1295 dev_priv->gart_info.bus_addr = 0;
Dave Airlie54a56ac2006-09-22 04:25:09 +10001296 if (dev_priv->flags & RADEON_IS_PCIE) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001297 DRM_ERROR
1298 ("Cannot use PCI Express without GART in FB memory\n");
Dave Airlieea98a922005-09-11 20:28:11 +10001299 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001300 return -EINVAL;
Dave Airlieea98a922005-09-11 20:28:11 +10001301 }
1302 }
1303
David Miller6abf6bb2009-02-14 01:51:07 -08001304 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1305 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1306 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1307 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1308
1309 if (!ret) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001310 DRM_ERROR("failed to init PCI GART!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001312 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313 }
1314
David Miller6abf6bb2009-02-14 01:51:07 -08001315 ret = radeon_setup_pcigart_surface(dev_priv);
1316 if (ret) {
1317 DRM_ERROR("failed to setup GART surface!\n");
1318 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1319 radeon_do_cleanup_cp(dev);
1320 return ret;
1321 }
1322
Linus Torvalds1da177e2005-04-16 15:20:36 -07001323 /* Turn on PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001324 radeon_set_pcigart(dev_priv, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325 }
1326
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001327 radeon_cp_load_microcode(dev_priv);
etienne3d161182009-02-20 09:44:45 +10001328 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329
1330 dev_priv->last_buf = 0;
1331
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001332 radeon_do_engine_reset(dev);
Dave Airlied5ea7022006-03-19 19:37:55 +11001333 radeon_test_writeback(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334
1335 return 0;
1336}
1337
Dave Airlie84b1fd12007-07-11 15:53:27 +10001338static int radeon_do_cleanup_cp(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339{
1340 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001341 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342
1343 /* Make sure interrupts are disabled here because the uninstall ioctl
1344 * may not have been called from userspace and after dev_private
1345 * is freed, it's too late.
1346 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001347 if (dev->irq_enabled)
1348 drm_irq_uninstall(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349
1350#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001351 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlied985c102006-01-02 21:32:48 +11001352 if (dev_priv->cp_ring != NULL) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001353 drm_core_ioremapfree(dev_priv->cp_ring, dev);
Dave Airlied985c102006-01-02 21:32:48 +11001354 dev_priv->cp_ring = NULL;
1355 }
1356 if (dev_priv->ring_rptr != NULL) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001357 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
Dave Airlied985c102006-01-02 21:32:48 +11001358 dev_priv->ring_rptr = NULL;
1359 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001360 if (dev->agp_buffer_map != NULL) {
1361 drm_core_ioremapfree(dev->agp_buffer_map, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 dev->agp_buffer_map = NULL;
1363 }
1364 } else
1365#endif
1366 {
Dave Airlied985c102006-01-02 21:32:48 +11001367
1368 if (dev_priv->gart_info.bus_addr) {
1369 /* Turn off PCI GART */
1370 radeon_set_pcigart(dev_priv, 0);
Dave Airlieea98a922005-09-11 20:28:11 +10001371 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1372 DRM_ERROR("failed to cleanup PCI GART!\n");
Dave Airlied985c102006-01-02 21:32:48 +11001373 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001374
Dave Airlied985c102006-01-02 21:32:48 +11001375 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1376 {
Dave Airlief26c4732006-01-02 17:18:39 +11001377 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
Dave Airlief2b04cd2007-05-08 15:19:23 +10001378 dev_priv->gart_info.addr = 0;
Dave Airlieea98a922005-09-11 20:28:11 +10001379 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001381 /* only clear to the start of flags */
1382 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1383
1384 return 0;
1385}
1386
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001387/* This code will reinit the Radeon CP hardware after a resume from disc.
1388 * AFAIK, it would be very difficult to pickle the state at suspend time, so
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389 * here we make sure that all Radeon hardware initialisation is re-done without
1390 * affecting running applications.
1391 *
1392 * Charl P. Botha <http://cpbotha.net>
1393 */
etienne3d161182009-02-20 09:44:45 +10001394static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395{
1396 drm_radeon_private_t *dev_priv = dev->dev_private;
1397
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001398 if (!dev_priv) {
1399 DRM_ERROR("Called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001400 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401 }
1402
1403 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1404
1405#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001406 if (dev_priv->flags & RADEON_IS_AGP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 /* Turn off PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001408 radeon_set_pcigart(dev_priv, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409 } else
1410#endif
1411 {
1412 /* Turn on PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001413 radeon_set_pcigart(dev_priv, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414 }
1415
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001416 radeon_cp_load_microcode(dev_priv);
etienne3d161182009-02-20 09:44:45 +10001417 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001419 radeon_do_engine_reset(dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001420 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421
1422 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1423
1424 return 0;
1425}
1426
Eric Anholtc153f452007-09-03 12:06:45 +10001427int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428{
Eric Anholtc153f452007-09-03 12:06:45 +10001429 drm_radeon_init_t *init = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430
Eric Anholt6c340ea2007-08-25 20:23:09 +10001431 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432
Eric Anholtc153f452007-09-03 12:06:45 +10001433 if (init->func == RADEON_INIT_R300_CP)
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001434 r300_init_reg_flags(dev);
Dave Airlie414ed532005-08-16 20:43:16 +10001435
Eric Anholtc153f452007-09-03 12:06:45 +10001436 switch (init->func) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437 case RADEON_INIT_CP:
1438 case RADEON_INIT_R200_CP:
1439 case RADEON_INIT_R300_CP:
Dave Airlie7c1c2872008-11-28 14:22:24 +10001440 return radeon_do_init_cp(dev, init, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441 case RADEON_CLEANUP_CP:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001442 return radeon_do_cleanup_cp(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443 }
1444
Eric Anholt20caafa2007-08-25 19:22:43 +10001445 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446}
1447
Eric Anholtc153f452007-09-03 12:06:45 +10001448int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001451 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452
Eric Anholt6c340ea2007-08-25 20:23:09 +10001453 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001455 if (dev_priv->cp_running) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001456 DRM_DEBUG("while CP running\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 return 0;
1458 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001459 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001460 DRM_DEBUG("called with bogus CP mode (%d)\n",
1461 dev_priv->cp_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 return 0;
1463 }
1464
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001465 radeon_do_cp_start(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466
1467 return 0;
1468}
1469
1470/* Stop the CP. The engine must have been idled before calling this
1471 * routine.
1472 */
Eric Anholtc153f452007-09-03 12:06:45 +10001473int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001474{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001476 drm_radeon_cp_stop_t *stop = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477 int ret;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001478 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479
Eric Anholt6c340ea2007-08-25 20:23:09 +10001480 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 if (!dev_priv->cp_running)
1483 return 0;
1484
1485 /* Flush any pending CP commands. This ensures any outstanding
1486 * commands are exectuted by the engine before we turn it off.
1487 */
Eric Anholtc153f452007-09-03 12:06:45 +10001488 if (stop->flush) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001489 radeon_do_cp_flush(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490 }
1491
1492 /* If we fail to make the engine go idle, we return an error
1493 * code so that the DRM ioctl wrapper can try again.
1494 */
Eric Anholtc153f452007-09-03 12:06:45 +10001495 if (stop->idle) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001496 ret = radeon_do_cp_idle(dev_priv);
1497 if (ret)
1498 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499 }
1500
1501 /* Finally, we can turn off the CP. If the engine isn't idle,
1502 * we will get some dropped triangles as they won't be fully
1503 * rendered before the CP is shut down.
1504 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001505 radeon_do_cp_stop(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506
1507 /* Reset the engine */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001508 radeon_do_engine_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509
1510 return 0;
1511}
1512
Dave Airlie84b1fd12007-07-11 15:53:27 +10001513void radeon_do_release(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001514{
1515 drm_radeon_private_t *dev_priv = dev->dev_private;
1516 int i, ret;
1517
1518 if (dev_priv) {
1519 if (dev_priv->cp_running) {
1520 /* Stop the cp */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001521 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1523#ifdef __linux__
1524 schedule();
1525#else
1526 tsleep(&ret, PZERO, "rdnrel", 1);
1527#endif
1528 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001529 radeon_do_cp_stop(dev_priv);
1530 radeon_do_engine_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531 }
1532
1533 /* Disable *all* interrupts */
1534 if (dev_priv->mmio) /* remove this after permanent addmaps */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001535 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001537 if (dev_priv->mmio) { /* remove all surfaces */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001539 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1540 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1541 16 * i, 0);
1542 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1543 16 * i, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 }
1545 }
1546
1547 /* Free memory heap structures */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001548 radeon_mem_takedown(&(dev_priv->gart_heap));
1549 radeon_mem_takedown(&(dev_priv->fb_heap));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550
1551 /* deallocate kernel resources */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001552 radeon_do_cleanup_cp(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 }
1554}
1555
1556/* Just reset the CP ring. Called as part of an X Server engine reset.
1557 */
Eric Anholtc153f452007-09-03 12:06:45 +10001558int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001561 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562
Eric Anholt6c340ea2007-08-25 20:23:09 +10001563 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001565 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001566 DRM_DEBUG("called before init done\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001567 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568 }
1569
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001570 radeon_do_cp_reset(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571
1572 /* The CP is no longer running after an engine reset */
1573 dev_priv->cp_running = 0;
1574
1575 return 0;
1576}
1577
Eric Anholtc153f452007-09-03 12:06:45 +10001578int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001580 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001581 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582
Eric Anholt6c340ea2007-08-25 20:23:09 +10001583 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001585 return radeon_do_cp_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586}
1587
1588/* Added by Charl P. Botha to call radeon_do_resume_cp().
1589 */
Eric Anholtc153f452007-09-03 12:06:45 +10001590int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591{
etienne3d161182009-02-20 09:44:45 +10001592 return radeon_do_resume_cp(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593}
1594
Eric Anholtc153f452007-09-03 12:06:45 +10001595int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596{
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001597 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598
Eric Anholt6c340ea2007-08-25 20:23:09 +10001599 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001600
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001601 return radeon_do_engine_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602}
1603
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604/* ================================================================
1605 * Fullscreen mode
1606 */
1607
1608/* KW: Deprecated to say the least:
1609 */
Eric Anholtc153f452007-09-03 12:06:45 +10001610int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611{
1612 return 0;
1613}
1614
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615/* ================================================================
1616 * Freelist management
1617 */
1618
1619/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1620 * bufs until freelist code is used. Note this hides a problem with
1621 * the scratch register * (used to keep track of last buffer
1622 * completed) being written to before * the last buffer has actually
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001623 * completed rendering.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624 *
1625 * KW: It's also a good way to find free buffers quickly.
1626 *
1627 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1628 * sleep. However, bugs in older versions of radeon_accel.c mean that
1629 * we essentially have to do this, else old clients will break.
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001630 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631 * However, it does leave open a potential deadlock where all the
1632 * buffers are held by other clients, which can't release them because
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001633 * they can't get the lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001634 */
1635
Dave Airlie056219e2007-07-11 16:17:42 +10001636struct drm_buf *radeon_freelist_get(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637{
Dave Airliecdd55a22007-07-11 16:32:08 +10001638 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001639 drm_radeon_private_t *dev_priv = dev->dev_private;
1640 drm_radeon_buf_priv_t *buf_priv;
Dave Airlie056219e2007-07-11 16:17:42 +10001641 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642 int i, t;
1643 int start;
1644
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001645 if (++dev_priv->last_buf >= dma->buf_count)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646 dev_priv->last_buf = 0;
1647
1648 start = dev_priv->last_buf;
1649
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001650 for (t = 0; t < dev_priv->usec_timeout; t++) {
David Millerb07fa022009-02-12 02:15:37 -08001651 u32 done_age = GET_SCRATCH(dev_priv, 1);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001652 DRM_DEBUG("done_age = %d\n", done_age);
1653 for (i = start; i < dma->buf_count; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654 buf = dma->buflist[i];
1655 buf_priv = buf->dev_private;
Eric Anholt6c340ea2007-08-25 20:23:09 +10001656 if (buf->file_priv == NULL || (buf->pending &&
1657 buf_priv->age <=
1658 done_age)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 dev_priv->stats.requested_bufs++;
1660 buf->pending = 0;
1661 return buf;
1662 }
1663 start = 0;
1664 }
1665
1666 if (t) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001667 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001668 dev_priv->stats.freelist_loops++;
1669 }
1670 }
1671
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001672 DRM_DEBUG("returning NULL!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673 return NULL;
1674}
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001675
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676#if 0
Dave Airlie056219e2007-07-11 16:17:42 +10001677struct drm_buf *radeon_freelist_get(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678{
Dave Airliecdd55a22007-07-11 16:32:08 +10001679 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001680 drm_radeon_private_t *dev_priv = dev->dev_private;
1681 drm_radeon_buf_priv_t *buf_priv;
Dave Airlie056219e2007-07-11 16:17:42 +10001682 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 int i, t;
1684 int start;
David Millerb07fa022009-02-12 02:15:37 -08001685 u32 done_age;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686
David Millerb07fa022009-02-12 02:15:37 -08001687 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001688 if (++dev_priv->last_buf >= dma->buf_count)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689 dev_priv->last_buf = 0;
1690
1691 start = dev_priv->last_buf;
1692 dev_priv->stats.freelist_loops++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001693
1694 for (t = 0; t < 2; t++) {
1695 for (i = start; i < dma->buf_count; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696 buf = dma->buflist[i];
1697 buf_priv = buf->dev_private;
Eric Anholt6c340ea2007-08-25 20:23:09 +10001698 if (buf->file_priv == 0 || (buf->pending &&
1699 buf_priv->age <=
1700 done_age)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701 dev_priv->stats.requested_bufs++;
1702 buf->pending = 0;
1703 return buf;
1704 }
1705 }
1706 start = 0;
1707 }
1708
1709 return NULL;
1710}
1711#endif
1712
Dave Airlie84b1fd12007-07-11 15:53:27 +10001713void radeon_freelist_reset(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714{
Dave Airliecdd55a22007-07-11 16:32:08 +10001715 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716 drm_radeon_private_t *dev_priv = dev->dev_private;
1717 int i;
1718
1719 dev_priv->last_buf = 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001720 for (i = 0; i < dma->buf_count; i++) {
Dave Airlie056219e2007-07-11 16:17:42 +10001721 struct drm_buf *buf = dma->buflist[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1723 buf_priv->age = 0;
1724 }
1725}
1726
Linus Torvalds1da177e2005-04-16 15:20:36 -07001727/* ================================================================
1728 * CP command submission
1729 */
1730
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001731int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732{
1733 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1734 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001735 u32 last_head = GET_RING_HEAD(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001736
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001737 for (i = 0; i < dev_priv->usec_timeout; i++) {
1738 u32 head = GET_RING_HEAD(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739
1740 ring->space = (head - ring->tail) * sizeof(u32);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001741 if (ring->space <= 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001742 ring->space += ring->size;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001743 if (ring->space > n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744 return 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001745
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1747
1748 if (head != last_head)
1749 i = 0;
1750 last_head = head;
1751
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001752 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001753 }
1754
1755 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1756#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001757 radeon_status(dev_priv);
1758 DRM_ERROR("failed!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759#endif
Eric Anholt20caafa2007-08-25 19:22:43 +10001760 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761}
1762
Eric Anholt6c340ea2007-08-25 20:23:09 +10001763static int radeon_cp_get_buffers(struct drm_device *dev,
1764 struct drm_file *file_priv,
Dave Airliec60ce622007-07-11 15:27:12 +10001765 struct drm_dma * d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766{
1767 int i;
Dave Airlie056219e2007-07-11 16:17:42 +10001768 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001770 for (i = d->granted_count; i < d->request_count; i++) {
1771 buf = radeon_freelist_get(dev);
1772 if (!buf)
Eric Anholt20caafa2007-08-25 19:22:43 +10001773 return -EBUSY; /* NOTE: broken client */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774
Eric Anholt6c340ea2007-08-25 20:23:09 +10001775 buf->file_priv = file_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001776
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001777 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1778 sizeof(buf->idx)))
Eric Anholt20caafa2007-08-25 19:22:43 +10001779 return -EFAULT;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001780 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1781 sizeof(buf->total)))
Eric Anholt20caafa2007-08-25 19:22:43 +10001782 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783
1784 d->granted_count++;
1785 }
1786 return 0;
1787}
1788
Eric Anholtc153f452007-09-03 12:06:45 +10001789int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001790{
Dave Airliecdd55a22007-07-11 16:32:08 +10001791 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792 int ret = 0;
Eric Anholtc153f452007-09-03 12:06:45 +10001793 struct drm_dma *d = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001794
Eric Anholt6c340ea2007-08-25 20:23:09 +10001795 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797 /* Please don't send us buffers.
1798 */
Eric Anholtc153f452007-09-03 12:06:45 +10001799 if (d->send_count != 0) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001800 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
Eric Anholtc153f452007-09-03 12:06:45 +10001801 DRM_CURRENTPID, d->send_count);
Eric Anholt20caafa2007-08-25 19:22:43 +10001802 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803 }
1804
1805 /* We'll send you buffers.
1806 */
Eric Anholtc153f452007-09-03 12:06:45 +10001807 if (d->request_count < 0 || d->request_count > dma->buf_count) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001808 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
Eric Anholtc153f452007-09-03 12:06:45 +10001809 DRM_CURRENTPID, d->request_count, dma->buf_count);
Eric Anholt20caafa2007-08-25 19:22:43 +10001810 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811 }
1812
Eric Anholtc153f452007-09-03 12:06:45 +10001813 d->granted_count = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
Eric Anholtc153f452007-09-03 12:06:45 +10001815 if (d->request_count) {
1816 ret = radeon_cp_get_buffers(dev, file_priv, d);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001817 }
1818
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819 return ret;
1820}
1821
Dave Airlie22eae942005-11-10 22:16:34 +11001822int radeon_driver_load(struct drm_device *dev, unsigned long flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823{
1824 drm_radeon_private_t *dev_priv;
1825 int ret = 0;
1826
1827 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1828 if (dev_priv == NULL)
Eric Anholt20caafa2007-08-25 19:22:43 +10001829 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001830
1831 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1832 dev->dev_private = (void *)dev_priv;
1833 dev_priv->flags = flags;
1834
Dave Airlie54a56ac2006-09-22 04:25:09 +10001835 switch (flags & RADEON_FAMILY_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836 case CHIP_R100:
1837 case CHIP_RV200:
1838 case CHIP_R200:
1839 case CHIP_R300:
Dave Airlieb15ec362006-08-19 17:43:52 +10001840 case CHIP_R350:
Dave Airlie414ed532005-08-16 20:43:16 +10001841 case CHIP_R420:
Alex Deucheredc6f382008-10-17 09:21:45 +10001842 case CHIP_R423:
Dave Airlieb15ec362006-08-19 17:43:52 +10001843 case CHIP_RV410:
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001844 case CHIP_RV515:
1845 case CHIP_R520:
1846 case CHIP_RV570:
1847 case CHIP_R580:
Dave Airlie54a56ac2006-09-22 04:25:09 +10001848 dev_priv->flags |= RADEON_HAS_HIERZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849 break;
1850 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001851 /* all other chips have no hierarchical z buffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001852 break;
1853 }
Dave Airlie414ed532005-08-16 20:43:16 +10001854
1855 if (drm_device_is_agp(dev))
Dave Airlie54a56ac2006-09-22 04:25:09 +10001856 dev_priv->flags |= RADEON_IS_AGP;
Dave Airlieb15ec362006-08-19 17:43:52 +10001857 else if (drm_device_is_pcie(dev))
Dave Airlie54a56ac2006-09-22 04:25:09 +10001858 dev_priv->flags |= RADEON_IS_PCIE;
Dave Airlieb15ec362006-08-19 17:43:52 +10001859 else
Dave Airlie54a56ac2006-09-22 04:25:09 +10001860 dev_priv->flags |= RADEON_IS_PCI;
Dave Airlieea98a922005-09-11 20:28:11 +10001861
Dave Airlie78538bf2008-11-11 17:56:16 +10001862 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1863 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1864 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1865 if (ret != 0)
1866 return ret;
1867
Keith Packard52440212008-11-18 09:30:25 -08001868 ret = drm_vblank_init(dev, 2);
1869 if (ret) {
1870 radeon_driver_unload(dev);
1871 return ret;
1872 }
1873
Dave Airlie414ed532005-08-16 20:43:16 +10001874 DRM_DEBUG("%s card detected\n",
Dave Airlie54a56ac2006-09-22 04:25:09 +10001875 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001876 return ret;
1877}
1878
Dave Airlie7c1c2872008-11-28 14:22:24 +10001879int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1880{
1881 struct drm_radeon_master_private *master_priv;
1882 unsigned long sareapage;
1883 int ret;
1884
1885 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1886 if (!master_priv)
1887 return -ENOMEM;
1888
1889 /* prebuild the SAREA */
Dave Airliebdf539a2008-12-18 16:56:11 +10001890 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001891 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1892 &master_priv->sarea);
1893 if (ret) {
1894 DRM_ERROR("SAREA setup failed\n");
1895 return ret;
1896 }
1897 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1898 master_priv->sarea_priv->pfCurrentPage = 0;
1899
1900 master->driver_priv = master_priv;
1901 return 0;
1902}
1903
1904void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1905{
1906 struct drm_radeon_master_private *master_priv = master->driver_priv;
1907
1908 if (!master_priv)
1909 return;
1910
1911 if (master_priv->sarea_priv &&
1912 master_priv->sarea_priv->pfCurrentPage != 0)
1913 radeon_cp_dispatch_flip(dev, master);
1914
1915 master_priv->sarea_priv = NULL;
1916 if (master_priv->sarea)
Dave Airlie4e74f362008-12-19 10:23:14 +11001917 drm_rmmap_locked(dev, master_priv->sarea);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001918
1919 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1920
1921 master->driver_priv = NULL;
1922}
1923
Dave Airlie22eae942005-11-10 22:16:34 +11001924/* Create mappings for registers and framebuffer so userland doesn't necessarily
1925 * have to find them.
1926 */
1927int radeon_driver_firstopen(struct drm_device *dev)
Dave Airlie836cf042005-07-10 19:27:04 +10001928{
1929 int ret;
1930 drm_local_map_t *map;
1931 drm_radeon_private_t *dev_priv = dev->dev_private;
1932
Dave Airlief2b04cd2007-05-08 15:19:23 +10001933 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1934
Dave Airlie7fc86862007-11-05 10:45:27 +10001935 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1936 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
Dave Airlie836cf042005-07-10 19:27:04 +10001937 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1938 _DRM_WRITE_COMBINING, &map);
1939 if (ret != 0)
1940 return ret;
1941
1942 return 0;
1943}
1944
Dave Airlie22eae942005-11-10 22:16:34 +11001945int radeon_driver_unload(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001946{
1947 drm_radeon_private_t *dev_priv = dev->dev_private;
1948
1949 DRM_DEBUG("\n");
Dave Airlie78538bf2008-11-11 17:56:16 +10001950
1951 drm_rmmap(dev, dev_priv->mmio);
1952
Linus Torvalds1da177e2005-04-16 15:20:36 -07001953 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1954
1955 dev->dev_private = NULL;
1956 return 0;
1957}
Dave Airlie4247ca92009-02-20 13:28:34 +10001958
1959void radeon_commit_ring(drm_radeon_private_t *dev_priv)
1960{
1961 int i;
1962 u32 *ring;
1963 int tail_aligned;
1964
1965 /* check if the ring is padded out to 16-dword alignment */
1966
1967 tail_aligned = dev_priv->ring.tail & 0xf;
1968 if (tail_aligned) {
1969 int num_p2 = 16 - tail_aligned;
1970
1971 ring = dev_priv->ring.start;
1972 /* pad with some CP_PACKET2 */
1973 for (i = 0; i < num_p2; i++)
1974 ring[dev_priv->ring.tail + i] = CP_PACKET2();
1975
1976 dev_priv->ring.tail += i;
1977
1978 dev_priv->ring.space -= num_p2 * sizeof(u32);
1979 }
1980
1981 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
1982
1983 DRM_MEMORYBARRIER();
1984 GET_RING_HEAD( dev_priv );
1985
1986 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );
1987 /* read from PCI bus to ensure correct posting */
1988 RADEON_READ( RADEON_CP_RB_RPTR );
1989}