blob: 5c5614f9eb17354aa1bba3b20998391cbb8d0a4c [file] [log] [blame]
Andy Fleming2654d632006-08-18 18:04:34 -05001/*
2 * MPC8555 CDS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -05004 * Copyright 2006, 2008 Freescale Semiconductor Inc.
Andy Fleming2654d632006-08-18 18:04:34 -05005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -050012/dts-v1/;
Andy Fleming2654d632006-08-18 18:04:34 -050013
14/ {
15 model = "MPC8555CDS";
Kumar Gala52094872007-02-17 16:04:23 -060016 compatible = "MPC8555CDS", "MPC85xxCDS";
Andy Fleming2654d632006-08-18 18:04:34 -050017 #address-cells = <1>;
18 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -050019
Kumar Galaea082fa2007-12-12 01:46:12 -060020 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
28
Andy Fleming2654d632006-08-18 18:04:34 -050029 cpus {
Andy Fleming2654d632006-08-18 18:04:34 -050030 #address-cells = <1>;
31 #size-cells = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -050032
33 PowerPC,8555@0 {
34 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -050035 reg = <0x0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
Andy Fleming2654d632006-08-18 18:04:34 -050040 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
Kumar Galac0540652008-05-30 13:43:43 -050043 next-level-cache = <&L2>;
Andy Fleming2654d632006-08-18 18:04:34 -050044 };
45 };
46
47 memory {
48 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -050049 reg = <0x0 0x8000000>; // 128M at 0x0
Andy Fleming2654d632006-08-18 18:04:34 -050050 };
51
52 soc8555@e0000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -050055 device_type = "soc";
Kim Phillipscf0d19f2008-07-29 15:29:24 -050056 compatible = "simple-bus";
Kumar Gala32f960e2008-04-17 01:28:15 -050057 ranges = <0x0 0xe0000000 0x100000>;
Andy Fleming2654d632006-08-18 18:04:34 -050058 bus-frequency = <0>;
59
Kumar Galae1a22892009-04-22 13:17:42 -050060 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
72
Kumar Gala4da421d2007-05-15 13:20:05 -050073 memory-controller@2000 {
Bradley Hughes8a4ab212010-07-21 12:04:06 +000074 compatible = "fsl,mpc8555-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -050075 reg = <0x2000 0x1000>;
Kumar Gala4da421d2007-05-15 13:20:05 -050076 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -050077 interrupts = <18 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -050078 };
79
Kumar Galac0540652008-05-30 13:43:43 -050080 L2: l2-cache-controller@20000 {
Bradley Hughes8a4ab212010-07-21 12:04:06 +000081 compatible = "fsl,mpc8555-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -050082 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K
Kumar Gala4da421d2007-05-15 13:20:05 -050085 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -050086 interrupts = <16 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -050087 };
88
Andy Fleming2654d632006-08-18 18:04:34 -050089 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -060090 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -050093 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -050094 reg = <0x3000 0x100>;
95 interrupts = <43 2>;
Kumar Gala52094872007-02-17 16:04:23 -060096 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -050097 dfsrr;
98 };
99
Kumar Galadee80552008-06-27 13:45:19 -0500100 dma@21300 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
104 reg = <0x21300 0x4>;
105 ranges = <0x0 0x21100 0x200>;
106 cell-index = <0>;
107 dma-channel@0 {
108 compatible = "fsl,mpc8555-dma-channel",
109 "fsl,eloplus-dma-channel";
110 reg = <0x0 0x80>;
111 cell-index = <0>;
112 interrupt-parent = <&mpic>;
113 interrupts = <20 2>;
114 };
115 dma-channel@80 {
116 compatible = "fsl,mpc8555-dma-channel",
117 "fsl,eloplus-dma-channel";
118 reg = <0x80 0x80>;
119 cell-index = <1>;
120 interrupt-parent = <&mpic>;
121 interrupts = <21 2>;
122 };
123 dma-channel@100 {
124 compatible = "fsl,mpc8555-dma-channel",
125 "fsl,eloplus-dma-channel";
126 reg = <0x100 0x80>;
127 cell-index = <2>;
128 interrupt-parent = <&mpic>;
129 interrupts = <22 2>;
130 };
131 dma-channel@180 {
132 compatible = "fsl,mpc8555-dma-channel",
133 "fsl,eloplus-dma-channel";
134 reg = <0x180 0x80>;
135 cell-index = <3>;
136 interrupt-parent = <&mpic>;
137 interrupts = <23 2>;
138 };
139 };
140
Kumar Galae77b28e2007-12-12 00:28:35 -0600141 enet0: ethernet@24000 {
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300142 #address-cells = <1>;
143 #size-cells = <1>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600144 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500145 device_type = "network";
146 model = "TSEC";
147 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500148 reg = <0x24000 0x1000>;
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300149 ranges = <0x0 0x24000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500150 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500151 interrupts = <29 2 30 2 34 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600152 interrupt-parent = <&mpic>;
Andy Flemingb31a1d82008-12-16 15:29:15 -0800153 tbi-handle = <&tbi0>;
Kumar Gala52094872007-02-17 16:04:23 -0600154 phy-handle = <&phy0>;
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300155
156 mdio@520 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,gianfar-mdio";
160 reg = <0x520 0x20>;
161
162 phy0: ethernet-phy@0 {
163 interrupt-parent = <&mpic>;
164 interrupts = <5 1>;
165 reg = <0x0>;
166 device_type = "ethernet-phy";
167 };
168 phy1: ethernet-phy@1 {
169 interrupt-parent = <&mpic>;
170 interrupts = <5 1>;
171 reg = <0x1>;
172 device_type = "ethernet-phy";
173 };
174 tbi0: tbi-phy@11 {
175 reg = <0x11>;
176 device_type = "tbi-phy";
177 };
178 };
Andy Fleming2654d632006-08-18 18:04:34 -0500179 };
180
Kumar Galae77b28e2007-12-12 00:28:35 -0600181 enet1: ethernet@25000 {
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300182 #address-cells = <1>;
183 #size-cells = <1>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600184 cell-index = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500185 device_type = "network";
186 model = "TSEC";
187 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500188 reg = <0x25000 0x1000>;
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300189 ranges = <0x0 0x25000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500190 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500191 interrupts = <35 2 36 2 40 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600192 interrupt-parent = <&mpic>;
Andy Flemingb31a1d82008-12-16 15:29:15 -0800193 tbi-handle = <&tbi1>;
Kumar Gala52094872007-02-17 16:04:23 -0600194 phy-handle = <&phy1>;
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300195
196 mdio@520 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,gianfar-tbi";
200 reg = <0x520 0x20>;
201
202 tbi1: tbi-phy@11 {
203 reg = <0x11>;
204 device_type = "tbi-phy";
205 };
206 };
Andy Fleming2654d632006-08-18 18:04:34 -0500207 };
208
Kumar Galaea082fa2007-12-12 01:46:12 -0600209 serial0: serial@4500 {
210 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500211 device_type = "serial";
212 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500213 reg = <0x4500 0x100>; // reg base, size
Andy Fleming2654d632006-08-18 18:04:34 -0500214 clock-frequency = <0>; // should we fill in in uboot?
Kumar Gala32f960e2008-04-17 01:28:15 -0500215 interrupts = <42 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600216 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500217 };
218
Kumar Galaea082fa2007-12-12 01:46:12 -0600219 serial1: serial@4600 {
220 cell-index = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500221 device_type = "serial";
222 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500223 reg = <0x4600 0x100>; // reg base, size
Andy Fleming2654d632006-08-18 18:04:34 -0500224 clock-frequency = <0>; // should we fill in in uboot?
Kumar Gala32f960e2008-04-17 01:28:15 -0500225 interrupts = <42 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600226 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500227 };
228
Kim Phillips3fd44732008-07-08 19:13:33 -0500229 crypto@30000 {
230 compatible = "fsl,sec2.0";
231 reg = <0x30000 0x10000>;
232 interrupts = <45 2>;
233 interrupt-parent = <&mpic>;
234 fsl,num-channels = <4>;
235 fsl,channel-fifo-len = <24>;
236 fsl,exec-units-mask = <0x7e>;
237 fsl,descriptor-types-mask = <0x01010ebf>;
238 };
239
Kumar Gala52094872007-02-17 16:04:23 -0600240 mpic: pic@40000 {
Andy Fleming2654d632006-08-18 18:04:34 -0500241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500244 reg = <0x40000 0x40000>;
Andy Fleming2654d632006-08-18 18:04:34 -0500245 compatible = "chrp,open-pic";
246 device_type = "open-pic";
Andy Fleming2654d632006-08-18 18:04:34 -0500247 };
Scott Woodab9683c2007-10-08 16:08:52 -0500248
249 cpm@919c0 {
250 #address-cells = <1>;
251 #size-cells = <1>;
252 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
Kumar Gala32f960e2008-04-17 01:28:15 -0500253 reg = <0x919c0 0x30>;
Scott Woodab9683c2007-10-08 16:08:52 -0500254 ranges;
255
256 muram@80000 {
257 #address-cells = <1>;
258 #size-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500259 ranges = <0x0 0x80000 0x10000>;
Scott Woodab9683c2007-10-08 16:08:52 -0500260
261 data@0 {
262 compatible = "fsl,cpm-muram-data";
Kumar Gala32f960e2008-04-17 01:28:15 -0500263 reg = <0x0 0x2000 0x9000 0x1000>;
Scott Woodab9683c2007-10-08 16:08:52 -0500264 };
265 };
266
267 brg@919f0 {
268 compatible = "fsl,mpc8555-brg",
269 "fsl,cpm2-brg",
270 "fsl,cpm-brg";
Kumar Gala32f960e2008-04-17 01:28:15 -0500271 reg = <0x919f0 0x10 0x915f0 0x10>;
Scott Woodab9683c2007-10-08 16:08:52 -0500272 };
273
274 cpmpic: pic@90c00 {
275 interrupt-controller;
276 #address-cells = <0>;
277 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500278 interrupts = <46 2>;
Scott Woodab9683c2007-10-08 16:08:52 -0500279 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500280 reg = <0x90c00 0x80>;
Scott Woodab9683c2007-10-08 16:08:52 -0500281 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
282 };
283 };
Andy Fleming2654d632006-08-18 18:04:34 -0500284 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500285
Kumar Galaea082fa2007-12-12 01:46:12 -0600286 pci0: pci@e0008000 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500287 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500288 interrupt-map = <
289
290 /* IDSEL 0x10 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500291 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
292 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
293 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
294 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500295
296 /* IDSEL 0x11 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500297 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
298 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
299 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
300 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500301
302 /* IDSEL 0x12 (Slot 1) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500303 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
304 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
305 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
306 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500307
308 /* IDSEL 0x13 (Slot 2) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500309 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
310 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
311 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
312 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500313
314 /* IDSEL 0x14 (Slot 3) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500315 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
316 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
317 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
318 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500319
320 /* IDSEL 0x15 (Slot 4) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500321 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
322 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
323 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
324 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500325
326 /* Bus 1 (Tundra Bridge) */
327 /* IDSEL 0x12 (ISA bridge) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500328 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
329 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
330 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
331 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500332 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500333 interrupts = <24 2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500334 bus-range = <0 0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500335 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
336 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
337 clock-frequency = <66666666>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500338 #interrupt-cells = <1>;
339 #size-cells = <2>;
340 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500341 reg = <0xe0008000 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500342 compatible = "fsl,mpc8540-pci";
343 device_type = "pci";
344
345 i8259@19000 {
346 interrupt-controller;
347 device_type = "interrupt-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500348 reg = <0x19000 0x0 0x0 0x0 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500349 #address-cells = <0>;
350 #interrupt-cells = <2>;
351 compatible = "chrp,iic";
352 interrupts = <1>;
Kumar Galaea082fa2007-12-12 01:46:12 -0600353 interrupt-parent = <&pci0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500354 };
355 };
356
Kumar Galaea082fa2007-12-12 01:46:12 -0600357 pci1: pci@e0009000 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500358 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500359 interrupt-map = <
360
361 /* IDSEL 0x15 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500362 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
363 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
364 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
365 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500366 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500367 interrupts = <25 2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500368 bus-range = <0 0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500369 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
370 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
371 clock-frequency = <66666666>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500372 #interrupt-cells = <1>;
373 #size-cells = <2>;
374 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500375 reg = <0xe0009000 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500376 compatible = "fsl,mpc8540-pci";
377 device_type = "pci";
378 };
Andy Fleming2654d632006-08-18 18:04:34 -0500379};