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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * I2O kernel space accessible structures/APIs
3 *
4 * (c) Copyright 1999, 2000 Red Hat Software
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 *************************************************************************
12 *
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
15 *
16 */
17
18#ifndef _I2O_H
19#define _I2O_H
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/i2o-dev.h>
22
23/* How many different OSM's are we allowing */
24#define I2O_MAX_DRIVERS 8
25
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/pci.h>
27#include <linux/dma-mapping.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080028#include <linux/string.h>
29#include <linux/slab.h>
30#include <linux/workqueue.h> /* work_struct */
Markus Lidela1a5ea72006-01-06 00:19:29 -080031#include <linux/mempool.h>
Matthias Kaehlcke9ac16252007-07-15 23:39:49 -070032#include <linux/mutex.h>
Jens Axboeba2da2f2007-07-24 14:42:11 +020033#include <linux/scatterlist.h>
Matthew Wilcox6188e102008-04-18 22:21:05 -040034#include <linux/semaphore.h> /* Needed for MUTEX init macros */
Tim Schmielau4e57b682005-10-30 15:03:48 -080035
36#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38/* message queue empty */
39#define I2O_QUEUE_EMPTY 0xffffffff
40
41/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 * Cache strategies
43 */
44
45/* The NULL strategy leaves everything up to the controller. This tends to be a
46 * pessimal but functional choice.
47 */
48#define CACHE_NULL 0
49/* Prefetch data when reading. We continually attempt to load the next 32 sectors
50 * into the controller cache.
51 */
52#define CACHE_PREFETCH 1
53/* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
54 * into the controller cache. When an I/O is less <= 8K we assume its probably
55 * not sequential and don't prefetch (default)
56 */
57#define CACHE_SMARTFETCH 2
58/* Data is written to the cache and then out on to the disk. The I/O must be
59 * physically on the medium before the write is acknowledged (default without
60 * NVRAM)
61 */
62#define CACHE_WRITETHROUGH 17
63/* Data is written to the cache and then out on to the disk. The controller
64 * is permitted to write back the cache any way it wants. (default if battery
65 * backed NVRAM is present). It can be useful to set this for swap regardless of
66 * battery state.
67 */
68#define CACHE_WRITEBACK 18
69/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
70 * write large I/O's directly to disk bypassing the cache to avoid the extra
71 * memory copy hits. Small writes are writeback cached
72 */
73#define CACHE_SMARTBACK 19
74/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
75 * write large I/O's directly to disk bypassing the cache to avoid the extra
76 * memory copy hits. Small writes are writethrough cached. Suitable for devices
77 * lacking battery backup
78 */
79#define CACHE_SMARTTHROUGH 20
80
81/*
82 * Ioctl structures
83 */
84
85#define BLKI2OGRSTRAT _IOR('2', 1, int)
86#define BLKI2OGWSTRAT _IOR('2', 2, int)
87#define BLKI2OSRSTRAT _IOW('2', 3, int)
88#define BLKI2OSWSTRAT _IOW('2', 4, int)
89
90/*
91 * I2O Function codes
92 */
93
94/*
95 * Executive Class
96 */
97#define I2O_CMD_ADAPTER_ASSIGN 0xB3
98#define I2O_CMD_ADAPTER_READ 0xB2
99#define I2O_CMD_ADAPTER_RELEASE 0xB5
100#define I2O_CMD_BIOS_INFO_SET 0xA5
101#define I2O_CMD_BOOT_DEVICE_SET 0xA7
102#define I2O_CMD_CONFIG_VALIDATE 0xBB
103#define I2O_CMD_CONN_SETUP 0xCA
104#define I2O_CMD_DDM_DESTROY 0xB1
105#define I2O_CMD_DDM_ENABLE 0xD5
106#define I2O_CMD_DDM_QUIESCE 0xC7
107#define I2O_CMD_DDM_RESET 0xD9
108#define I2O_CMD_DDM_SUSPEND 0xAF
109#define I2O_CMD_DEVICE_ASSIGN 0xB7
110#define I2O_CMD_DEVICE_RELEASE 0xB9
111#define I2O_CMD_HRT_GET 0xA8
112#define I2O_CMD_ADAPTER_CLEAR 0xBE
113#define I2O_CMD_ADAPTER_CONNECT 0xC9
114#define I2O_CMD_ADAPTER_RESET 0xBD
115#define I2O_CMD_LCT_NOTIFY 0xA2
116#define I2O_CMD_OUTBOUND_INIT 0xA1
117#define I2O_CMD_PATH_ENABLE 0xD3
118#define I2O_CMD_PATH_QUIESCE 0xC5
119#define I2O_CMD_PATH_RESET 0xD7
120#define I2O_CMD_STATIC_MF_CREATE 0xDD
121#define I2O_CMD_STATIC_MF_RELEASE 0xDF
122#define I2O_CMD_STATUS_GET 0xA0
123#define I2O_CMD_SW_DOWNLOAD 0xA9
124#define I2O_CMD_SW_UPLOAD 0xAB
125#define I2O_CMD_SW_REMOVE 0xAD
126#define I2O_CMD_SYS_ENABLE 0xD1
127#define I2O_CMD_SYS_MODIFY 0xC1
128#define I2O_CMD_SYS_QUIESCE 0xC3
129#define I2O_CMD_SYS_TAB_SET 0xA3
130
131/*
132 * Utility Class
133 */
134#define I2O_CMD_UTIL_NOP 0x00
135#define I2O_CMD_UTIL_ABORT 0x01
136#define I2O_CMD_UTIL_CLAIM 0x09
137#define I2O_CMD_UTIL_RELEASE 0x0B
138#define I2O_CMD_UTIL_PARAMS_GET 0x06
139#define I2O_CMD_UTIL_PARAMS_SET 0x05
140#define I2O_CMD_UTIL_EVT_REGISTER 0x13
141#define I2O_CMD_UTIL_EVT_ACK 0x14
142#define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
143#define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
144#define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
145#define I2O_CMD_UTIL_LOCK 0x17
146#define I2O_CMD_UTIL_LOCK_RELEASE 0x19
147#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
148
149/*
150 * SCSI Host Bus Adapter Class
151 */
152#define I2O_CMD_SCSI_EXEC 0x81
153#define I2O_CMD_SCSI_ABORT 0x83
154#define I2O_CMD_SCSI_BUSRESET 0x27
155
156/*
Markus Lidelf10378f2005-06-23 22:02:16 -0700157 * Bus Adapter Class
158 */
159#define I2O_CMD_BUS_ADAPTER_RESET 0x85
160#define I2O_CMD_BUS_RESET 0x87
161#define I2O_CMD_BUS_SCAN 0x89
162#define I2O_CMD_BUS_QUIESCE 0x8b
163
164/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 * Random Block Storage Class
166 */
167#define I2O_CMD_BLOCK_READ 0x30
168#define I2O_CMD_BLOCK_WRITE 0x31
169#define I2O_CMD_BLOCK_CFLUSH 0x37
170#define I2O_CMD_BLOCK_MLOCK 0x49
171#define I2O_CMD_BLOCK_MUNLOCK 0x4B
172#define I2O_CMD_BLOCK_MMOUNT 0x41
173#define I2O_CMD_BLOCK_MEJECT 0x43
174#define I2O_CMD_BLOCK_POWER 0x70
175
Markus Lidelb2aaee32005-06-23 22:02:19 -0700176#define I2O_CMD_PRIVATE 0xFF
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177
178/* Command status values */
179
180#define I2O_CMD_IN_PROGRESS 0x01
181#define I2O_CMD_REJECTED 0x02
182#define I2O_CMD_FAILED 0x03
183#define I2O_CMD_COMPLETED 0x04
184
185/* I2O API function return values */
186
187#define I2O_RTN_NO_ERROR 0
188#define I2O_RTN_NOT_INIT 1
189#define I2O_RTN_FREE_Q_EMPTY 2
190#define I2O_RTN_TCB_ERROR 3
191#define I2O_RTN_TRANSACTION_ERROR 4
192#define I2O_RTN_ADAPTER_ALREADY_INIT 5
193#define I2O_RTN_MALLOC_ERROR 6
194#define I2O_RTN_ADPTR_NOT_REGISTERED 7
195#define I2O_RTN_MSG_REPLY_TIMEOUT 8
196#define I2O_RTN_NO_STATUS 9
197#define I2O_RTN_NO_FIRM_VER 10
198#define I2O_RTN_NO_LINK_SPEED 11
199
200/* Reply message status defines for all messages */
201
202#define I2O_REPLY_STATUS_SUCCESS 0x00
203#define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
204#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
205#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
206#define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
207#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
208#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
209#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
210#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
211#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
212#define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
213#define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
214
215/* Status codes and Error Information for Parameter functions */
216
217#define I2O_PARAMS_STATUS_SUCCESS 0x00
218#define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
219#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
220#define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
221#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
222#define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
223#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
224#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
225#define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
226#define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
227#define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
228#define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
229#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
230#define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
231#define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
232#define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
233#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
234
235/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
236 * messages: Table 3-2 Detailed Status Codes.*/
237
238#define I2O_DSC_SUCCESS 0x0000
239#define I2O_DSC_BAD_KEY 0x0002
240#define I2O_DSC_TCL_ERROR 0x0003
241#define I2O_DSC_REPLY_BUFFER_FULL 0x0004
242#define I2O_DSC_NO_SUCH_PAGE 0x0005
243#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
244#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
245#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
246#define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
247#define I2O_DSC_DEVICE_LOCKED 0x000B
248#define I2O_DSC_DEVICE_RESET 0x000C
249#define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
250#define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
251#define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
252#define I2O_DSC_INVALID_OFFSET 0x0010
253#define I2O_DSC_INVALID_PARAMETER 0x0011
254#define I2O_DSC_INVALID_REQUEST 0x0012
255#define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
256#define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
257#define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
258#define I2O_DSC_MISSING_PARAMETER 0x0016
259#define I2O_DSC_TIMEOUT 0x0017
260#define I2O_DSC_UNKNOWN_ERROR 0x0018
261#define I2O_DSC_UNKNOWN_FUNCTION 0x0019
262#define I2O_DSC_UNSUPPORTED_VERSION 0x001A
263#define I2O_DSC_DEVICE_BUSY 0x001B
264#define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
265
266/* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
267 Status Codes.*/
268
269#define I2O_BSA_DSC_SUCCESS 0x0000
270#define I2O_BSA_DSC_MEDIA_ERROR 0x0001
271#define I2O_BSA_DSC_ACCESS_ERROR 0x0002
272#define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
273#define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
274#define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
275#define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
276#define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
277#define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
278#define I2O_BSA_DSC_BUS_FAILURE 0x0009
279#define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
280#define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
281#define I2O_BSA_DSC_DEVICE_RESET 0x000C
282#define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
283#define I2O_BSA_DSC_TIMEOUT 0x000E
284
285/* FailureStatusCodes, Table 3-3 Message Failure Codes */
286
287#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
288#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
289#define I2O_FSC_TRANSPORT_CONGESTION 0x83
290#define I2O_FSC_TRANSPORT_FAILURE 0x84
291#define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
292#define I2O_FSC_TRANSPORT_TIME_OUT 0x86
293#define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
294#define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
295#define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
296#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
297#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
298#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
299#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
300#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
301#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
302#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
303
304/* Device Claim Types */
305#define I2O_CLAIM_PRIMARY 0x01000000
306#define I2O_CLAIM_MANAGEMENT 0x02000000
307#define I2O_CLAIM_AUTHORIZED 0x03000000
308#define I2O_CLAIM_SECONDARY 0x04000000
309
310/* Message header defines for VersionOffset */
311#define I2OVER15 0x0001
312#define I2OVER20 0x0002
313
Markus Lidelf88e1192005-06-23 22:02:14 -0700314/* Default is 1.5 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315#define I2OVERSION I2OVER15
316
317#define SGL_OFFSET_0 I2OVERSION
318#define SGL_OFFSET_4 (0x0040 | I2OVERSION)
319#define SGL_OFFSET_5 (0x0050 | I2OVERSION)
320#define SGL_OFFSET_6 (0x0060 | I2OVERSION)
321#define SGL_OFFSET_7 (0x0070 | I2OVERSION)
322#define SGL_OFFSET_8 (0x0080 | I2OVERSION)
323#define SGL_OFFSET_9 (0x0090 | I2OVERSION)
324#define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
Markus Lidelb2aaee32005-06-23 22:02:19 -0700325#define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
326#define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
327#define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328
329/* Transaction Reply Lists (TRL) Control Word structure */
330#define TRL_SINGLE_FIXED_LENGTH 0x00
331#define TRL_SINGLE_VARIABLE_LENGTH 0x40
332#define TRL_MULTIPLE_FIXED_LENGTH 0x80
333
334 /* msg header defines for MsgFlags */
335#define MSG_STATIC 0x0100
336#define MSG_64BIT_CNTXT 0x0200
337#define MSG_MULTI_TRANS 0x1000
338#define MSG_FAIL 0x2000
339#define MSG_FINAL 0x4000
340#define MSG_REPLY 0x8000
341
342 /* minimum size msg */
343#define THREE_WORD_MSG_SIZE 0x00030000
344#define FOUR_WORD_MSG_SIZE 0x00040000
345#define FIVE_WORD_MSG_SIZE 0x00050000
346#define SIX_WORD_MSG_SIZE 0x00060000
347#define SEVEN_WORD_MSG_SIZE 0x00070000
348#define EIGHT_WORD_MSG_SIZE 0x00080000
349#define NINE_WORD_MSG_SIZE 0x00090000
350#define TEN_WORD_MSG_SIZE 0x000A0000
351#define ELEVEN_WORD_MSG_SIZE 0x000B0000
352#define I2O_MESSAGE_SIZE(x) ((x)<<16)
353
Markus Lidel9e875452005-06-23 22:02:21 -0700354/* special TID assignments */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355#define ADAPTER_TID 0
356#define HOST_TID 1
357
Markus Lidel9e875452005-06-23 22:02:21 -0700358/* outbound queue defines */
359#define I2O_MAX_OUTBOUND_MSG_FRAMES 128
360#define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
Markus Lidela1a5ea72006-01-06 00:19:29 -0800362/* inbound queue definitions */
363#define I2O_MSG_INPOOL_MIN 32
364#define I2O_INBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
365
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366#define I2O_POST_WAIT_OK 0
367#define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
368
369#define I2O_CONTEXT_LIST_MIN_LENGTH 15
370#define I2O_CONTEXT_LIST_USED 0x01
371#define I2O_CONTEXT_LIST_DELETED 0x02
372
373/* timeouts */
374#define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
375#define I2O_TIMEOUT_MESSAGE_GET 5
376#define I2O_TIMEOUT_RESET 30
377#define I2O_TIMEOUT_STATUS_GET 5
378#define I2O_TIMEOUT_LCT_GET 360
379#define I2O_TIMEOUT_SCSI_SCB_ABORT 240
380
381/* retries */
382#define I2O_HRT_GET_TRIES 3
383#define I2O_LCT_GET_TRIES 3
384
Markus Lidelb2aaee32005-06-23 22:02:19 -0700385/* defines for max_sectors and max_phys_segments */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386#define I2O_MAX_SECTORS 1024
Markus Lideldcceafe2006-01-06 00:19:32 -0800387#define I2O_MAX_SECTORS_LIMITED 128
Markus Lidelf10378f2005-06-23 22:02:16 -0700388#define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
Markus Lidela1a5ea72006-01-06 00:19:29 -0800390/*
391 * Message structures
392 */
393struct i2o_message {
394 union {
395 struct {
396 u8 version_offset;
397 u8 flags;
398 u16 size;
399 u32 target_tid:12;
400 u32 init_tid:12;
401 u32 function:8;
402 u32 icntxt; /* initiator context */
403 u32 tcntxt; /* transaction context */
404 } s;
405 u32 head[4];
406 } u;
407 /* List follows */
408 u32 body[0];
409};
410
411/* MFA and I2O message used by mempool */
412struct i2o_msg_mfa {
413 u32 mfa; /* MFA returned by the controller */
414 struct i2o_message msg; /* I2O message */
415};
416
417/*
418 * Each I2O device entity has one of these. There is one per device.
419 */
420struct i2o_device {
421 i2o_lct_entry lct_data; /* Device LCT information */
422
423 struct i2o_controller *iop; /* Controlling IOP */
424 struct list_head list; /* node in IOP devices list */
425
426 struct device device;
427
Matthias Kaehlcke9ac16252007-07-15 23:39:49 -0700428 struct mutex lock; /* device lock */
Markus Lidela1a5ea72006-01-06 00:19:29 -0800429};
430
431/*
432 * Event structure provided to the event handling function
433 */
434struct i2o_event {
435 struct work_struct work;
436 struct i2o_device *i2o_dev; /* I2O device pointer from which the
437 event reply was initiated */
438 u16 size; /* Size of data in 32-bit words */
439 u32 tcntxt; /* Transaction context used at
440 registration */
441 u32 event_indicator; /* Event indicator from reply */
442 u32 data[0]; /* Event data from reply */
443};
444
445/*
446 * I2O classes which could be handled by the OSM
447 */
448struct i2o_class_id {
449 u16 class_id:12;
450};
451
452/*
453 * I2O driver structure for OSMs
454 */
455struct i2o_driver {
456 char *name; /* OSM name */
457 int context; /* Low 8 bits of the transaction info */
458 struct i2o_class_id *classes; /* I2O classes that this OSM handles */
459
460 /* Message reply handler */
461 int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
462
463 /* Event handler */
David Howellsc4028952006-11-22 14:57:56 +0000464 work_func_t event;
Markus Lidela1a5ea72006-01-06 00:19:29 -0800465
466 struct workqueue_struct *event_queue; /* Event queue */
467
468 struct device_driver driver;
469
470 /* notification of changes */
471 void (*notify_controller_add) (struct i2o_controller *);
472 void (*notify_controller_remove) (struct i2o_controller *);
473 void (*notify_device_add) (struct i2o_device *);
474 void (*notify_device_remove) (struct i2o_device *);
475
476 struct semaphore lock;
477};
478
479/*
480 * Contains DMA mapped address information
481 */
482struct i2o_dma {
483 void *virt;
484 dma_addr_t phys;
485 size_t len;
486};
487
488/*
489 * Contains slab cache and mempool information
490 */
491struct i2o_pool {
492 char *name;
Christoph Lametere18b8902006-12-06 20:33:20 -0800493 struct kmem_cache *slab;
Markus Lidela1a5ea72006-01-06 00:19:29 -0800494 mempool_t *mempool;
495};
496
497/*
498 * Contains IO mapped address information
499 */
500struct i2o_io {
501 void __iomem *virt;
502 unsigned long phys;
503 unsigned long len;
504};
505
506/*
507 * Context queue entry, used for 32-bit context on 64-bit systems
508 */
509struct i2o_context_list_element {
510 struct list_head list;
511 u32 context;
512 void *ptr;
513 unsigned long timestamp;
514};
515
516/*
517 * Each I2O controller has one of these objects
518 */
519struct i2o_controller {
520 char name[16];
521 int unit;
522 int type;
523
524 struct pci_dev *pdev; /* PCI device */
525
526 unsigned int promise:1; /* Promise controller */
527 unsigned int adaptec:1; /* DPT / Adaptec controller */
528 unsigned int raptor:1; /* split bar */
529 unsigned int no_quiesce:1; /* dont quiesce before reset */
530 unsigned int short_req:1; /* use small block sizes */
531 unsigned int limit_sectors:1; /* limit number of sectors / request */
532 unsigned int pae_support:1; /* controller has 64-bit SGL support */
533
534 struct list_head devices; /* list of I2O devices */
535 struct list_head list; /* Controller list */
536
537 void __iomem *in_port; /* Inbout port address */
538 void __iomem *out_port; /* Outbound port address */
539 void __iomem *irq_status; /* Interrupt status register address */
540 void __iomem *irq_mask; /* Interrupt mask register address */
541
542 struct i2o_dma status; /* IOP status block */
543
544 struct i2o_dma hrt; /* HW Resource Table */
545 i2o_lct *lct; /* Logical Config Table */
546 struct i2o_dma dlct; /* Temp LCT */
Matthias Kaehlcke9ac16252007-07-15 23:39:49 -0700547 struct mutex lct_lock; /* Lock for LCT updates */
Markus Lidela1a5ea72006-01-06 00:19:29 -0800548 struct i2o_dma status_block; /* IOP status block */
549
550 struct i2o_io base; /* controller messaging unit */
551 struct i2o_io in_queue; /* inbound message queue Host->IOP */
552 struct i2o_dma out_queue; /* outbound message queue IOP->Host */
553
554 struct i2o_pool in_msg; /* mempool for inbound messages */
555
556 unsigned int battery:1; /* Has a battery backup */
557 unsigned int io_alloc:1; /* An I/O resource was allocated */
558 unsigned int mem_alloc:1; /* A memory resource was allocated */
559
560 struct resource io_resource; /* I/O resource allocated to the IOP */
561 struct resource mem_resource; /* Mem resource allocated to the IOP */
562
563 struct device device;
Markus Lidela1a5ea72006-01-06 00:19:29 -0800564 struct i2o_device *exec; /* Executive */
565#if BITS_PER_LONG == 64
566 spinlock_t context_list_lock; /* lock for context_list */
567 atomic_t context_list_counter; /* needed for unique contexts */
568 struct list_head context_list; /* list of context id's
569 and pointers */
570#endif
571 spinlock_t lock; /* lock for controller
572 configuration */
573
574 void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */
575};
576
577/*
578 * I2O System table entry
579 *
580 * The system table contains information about all the IOPs in the
581 * system. It is sent to all IOPs so that they can create peer2peer
582 * connections between them.
583 */
584struct i2o_sys_tbl_entry {
585 u16 org_id;
586 u16 reserved1;
587 u32 iop_id:12;
588 u32 reserved2:20;
589 u16 seg_num:12;
590 u16 i2o_version:4;
591 u8 iop_state;
592 u8 msg_type;
593 u16 frame_size;
594 u16 reserved3;
595 u32 last_changed;
596 u32 iop_capabilities;
597 u32 inbound_low;
598 u32 inbound_high;
599};
600
601struct i2o_sys_tbl {
602 u8 num_entries;
603 u8 version;
604 u16 reserved1;
605 u32 change_ind;
606 u32 reserved2;
607 u32 reserved3;
608 struct i2o_sys_tbl_entry iops[0];
609};
610
611extern struct list_head i2o_controllers;
612
613/* Message functions */
Markus Lidela1a5ea72006-01-06 00:19:29 -0800614extern struct i2o_message *i2o_msg_get_wait(struct i2o_controller *, int);
Markus Lidela1a5ea72006-01-06 00:19:29 -0800615extern int i2o_msg_post_wait_mem(struct i2o_controller *, struct i2o_message *,
616 unsigned long, struct i2o_dma *);
Markus Lidela1a5ea72006-01-06 00:19:29 -0800617
618/* IOP functions */
619extern int i2o_status_get(struct i2o_controller *);
620
621extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int,
622 u32);
623extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16);
624extern struct i2o_controller *i2o_find_iop(int);
625
626/* Functions needed for handling 64-bit pointers in 32-bit context */
627#if BITS_PER_LONG == 64
628extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *);
629extern void *i2o_cntxt_list_get(struct i2o_controller *, u32);
630extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *);
631extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *);
632
633static inline u32 i2o_ptr_low(void *ptr)
634{
635 return (u32) (u64) ptr;
636};
637
638static inline u32 i2o_ptr_high(void *ptr)
639{
640 return (u32) ((u64) ptr >> 32);
641};
642
643static inline u32 i2o_dma_low(dma_addr_t dma_addr)
644{
645 return (u32) (u64) dma_addr;
646};
647
648static inline u32 i2o_dma_high(dma_addr_t dma_addr)
649{
650 return (u32) ((u64) dma_addr >> 32);
651};
652#else
653static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
654{
655 return (u32) ptr;
656};
657
658static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
659{
660 return (void *)context;
661};
662
663static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
664{
665 return (u32) ptr;
666};
667
668static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr)
669{
670 return (u32) ptr;
671};
672
673static inline u32 i2o_ptr_low(void *ptr)
674{
675 return (u32) ptr;
676};
677
678static inline u32 i2o_ptr_high(void *ptr)
679{
680 return 0;
681};
682
683static inline u32 i2o_dma_low(dma_addr_t dma_addr)
684{
685 return (u32) dma_addr;
686};
687
688static inline u32 i2o_dma_high(dma_addr_t dma_addr)
689{
690 return 0;
691};
692#endif
693
694/**
695 * i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
696 * @c: I2O controller for which the calculation should be done
697 * @body_size: maximum body size used for message in 32-bit words.
698 *
699 * Return the maximum number of SG elements in a SG list.
700 */
701static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
702{
703 i2o_status_block *sb = c->status_block.virt;
704 u16 sg_count =
705 (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
706 body_size;
707
708 if (c->pae_support) {
709 /*
710 * for 64-bit a SG attribute element must be added and each
711 * SG element needs 12 bytes instead of 8.
712 */
713 sg_count -= 2;
714 sg_count /= 3;
715 } else
716 sg_count /= 2;
717
718 if (c->short_req && (sg_count > 8))
719 sg_count = 8;
720
721 return sg_count;
722};
723
724/**
725 * i2o_dma_map_single - Map pointer to controller and fill in I2O message.
726 * @c: I2O controller
727 * @ptr: pointer to the data which should be mapped
728 * @size: size of data in bytes
729 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
730 * @sg_ptr: pointer to the SG list inside the I2O message
731 *
732 * This function does all necessary DMA handling and also writes the I2O
733 * SGL elements into the I2O message. For details on DMA handling see also
734 * dma_map_single(). The pointer sg_ptr will only be set to the end of the
735 * SG list if the allocation was successful.
736 *
737 * Returns DMA address which must be checked for failures using
738 * dma_mapping_error().
739 */
740static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
741 size_t size,
742 enum dma_data_direction direction,
743 u32 ** sg_ptr)
744{
745 u32 sg_flags;
746 u32 *mptr = *sg_ptr;
747 dma_addr_t dma_addr;
748
749 switch (direction) {
750 case DMA_TO_DEVICE:
751 sg_flags = 0xd4000000;
752 break;
753 case DMA_FROM_DEVICE:
754 sg_flags = 0xd0000000;
755 break;
756 default:
757 return 0;
758 }
759
760 dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700761 if (!dma_mapping_error(&c->pdev->dev, dma_addr)) {
Markus Lidela1a5ea72006-01-06 00:19:29 -0800762#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
763 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
764 *mptr++ = cpu_to_le32(0x7C020002);
765 *mptr++ = cpu_to_le32(PAGE_SIZE);
766 }
767#endif
768
769 *mptr++ = cpu_to_le32(sg_flags | size);
770 *mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
771#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
772 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
773 *mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
774#endif
775 *sg_ptr = mptr;
776 }
777 return dma_addr;
778};
779
780/**
781 * i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
782 * @c: I2O controller
783 * @sg: SG list to be mapped
784 * @sg_count: number of elements in the SG list
785 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
786 * @sg_ptr: pointer to the SG list inside the I2O message
787 *
788 * This function does all necessary DMA handling and also writes the I2O
789 * SGL elements into the I2O message. For details on DMA handling see also
790 * dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
791 * list if the allocation was successful.
792 *
793 * Returns 0 on failure or 1 on success.
794 */
795static inline int i2o_dma_map_sg(struct i2o_controller *c,
796 struct scatterlist *sg, int sg_count,
797 enum dma_data_direction direction,
798 u32 ** sg_ptr)
799{
800 u32 sg_flags;
801 u32 *mptr = *sg_ptr;
802
803 switch (direction) {
804 case DMA_TO_DEVICE:
805 sg_flags = 0x14000000;
806 break;
807 case DMA_FROM_DEVICE:
808 sg_flags = 0x10000000;
809 break;
810 default:
811 return 0;
812 }
813
814 sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
815 if (!sg_count)
816 return 0;
817
818#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
819 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
820 *mptr++ = cpu_to_le32(0x7C020002);
821 *mptr++ = cpu_to_le32(PAGE_SIZE);
822 }
823#endif
824
825 while (sg_count-- > 0) {
826 if (!sg_count)
827 sg_flags |= 0xC0000000;
828 *mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
829 *mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
830#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
831 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
832 *mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
833#endif
Jens Axboeba2da2f2007-07-24 14:42:11 +0200834 sg = sg_next(sg);
Markus Lidela1a5ea72006-01-06 00:19:29 -0800835 }
836 *sg_ptr = mptr;
837
838 return 1;
839};
840
841/**
842 * i2o_dma_alloc - Allocate DMA memory
843 * @dev: struct device pointer to the PCI device of the I2O controller
844 * @addr: i2o_dma struct which should get the DMA buffer
845 * @len: length of the new DMA memory
846 * @gfp_mask: GFP mask
847 *
848 * Allocate a coherent DMA memory and write the pointers into addr.
849 *
850 * Returns 0 on success or -ENOMEM on failure.
851 */
852static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
853 size_t len, gfp_t gfp_mask)
854{
855 struct pci_dev *pdev = to_pci_dev(dev);
856 int dma_64 = 0;
857
858 if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
859 dma_64 = 1;
860 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
861 return -ENOMEM;
862 }
863
864 addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
865
866 if ((sizeof(dma_addr_t) > 4) && dma_64)
867 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
868 printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
869
870 if (!addr->virt)
871 return -ENOMEM;
872
873 memset(addr->virt, 0, len);
874 addr->len = len;
875
876 return 0;
877};
878
879/**
880 * i2o_dma_free - Free DMA memory
881 * @dev: struct device pointer to the PCI device of the I2O controller
882 * @addr: i2o_dma struct which contains the DMA buffer
883 *
884 * Free a coherent DMA memory and set virtual address of addr to NULL.
885 */
886static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
887{
888 if (addr->virt) {
889 if (addr->phys)
890 dma_free_coherent(dev, addr->len, addr->virt,
891 addr->phys);
892 else
893 kfree(addr->virt);
894 addr->virt = NULL;
895 }
896};
897
898/**
899 * i2o_dma_realloc - Realloc DMA memory
900 * @dev: struct device pointer to the PCI device of the I2O controller
901 * @addr: pointer to a i2o_dma struct DMA buffer
902 * @len: new length of memory
903 * @gfp_mask: GFP mask
904 *
905 * If there was something allocated in the addr, free it first. If len > 0
906 * than try to allocate it and write the addresses back to the addr
907 * structure. If len == 0 set the virtual address to NULL.
908 *
909 * Returns the 0 on success or negative error code on failure.
910 */
911static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
912 size_t len, gfp_t gfp_mask)
913{
914 i2o_dma_free(dev, addr);
915
916 if (len)
917 return i2o_dma_alloc(dev, addr, len, gfp_mask);
918
919 return 0;
920};
921
922/*
923 * i2o_pool_alloc - Allocate an slab cache and mempool
924 * @mempool: pointer to struct i2o_pool to write data into.
925 * @name: name which is used to identify cache
926 * @size: size of each object
927 * @min_nr: minimum number of objects
928 *
929 * First allocates a slab cache with name and size. Then allocates a
930 * mempool which uses the slab cache for allocation and freeing.
931 *
932 * Returns 0 on success or negative error code on failure.
933 */
934static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
935 size_t size, int min_nr)
936{
937 pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
938 if (!pool->name)
939 goto exit;
940 strcpy(pool->name, name);
941
942 pool->slab =
Paul Mundt20c2df82007-07-20 10:11:58 +0900943 kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL);
Markus Lidela1a5ea72006-01-06 00:19:29 -0800944 if (!pool->slab)
945 goto free_name;
946
Matthew Dobson93d23412006-03-26 01:37:50 -0800947 pool->mempool = mempool_create_slab_pool(min_nr, pool->slab);
Markus Lidela1a5ea72006-01-06 00:19:29 -0800948 if (!pool->mempool)
949 goto free_slab;
950
951 return 0;
952
953 free_slab:
954 kmem_cache_destroy(pool->slab);
955
956 free_name:
957 kfree(pool->name);
958
959 exit:
960 return -ENOMEM;
961};
962
963/*
964 * i2o_pool_free - Free slab cache and mempool again
965 * @mempool: pointer to struct i2o_pool which should be freed
966 *
967 * Note that you have to return all objects to the mempool again before
968 * calling i2o_pool_free().
969 */
970static inline void i2o_pool_free(struct i2o_pool *pool)
971{
972 mempool_destroy(pool->mempool);
973 kmem_cache_destroy(pool->slab);
974 kfree(pool->name);
975};
976
977/* I2O driver (OSM) functions */
978extern int i2o_driver_register(struct i2o_driver *);
979extern void i2o_driver_unregister(struct i2o_driver *);
980
981/**
982 * i2o_driver_notify_controller_add - Send notification of added controller
Randy Dunlapd9489fb2006-12-06 20:38:43 -0800983 * @drv: I2O driver
984 * @c: I2O controller
Markus Lidela1a5ea72006-01-06 00:19:29 -0800985 *
986 * Send notification of added controller to a single registered driver.
987 */
988static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv,
989 struct i2o_controller *c)
990{
991 if (drv->notify_controller_add)
992 drv->notify_controller_add(c);
993};
994
995/**
Randy Dunlapd9489fb2006-12-06 20:38:43 -0800996 * i2o_driver_notify_controller_remove - Send notification of removed controller
997 * @drv: I2O driver
998 * @c: I2O controller
Markus Lidela1a5ea72006-01-06 00:19:29 -0800999 *
1000 * Send notification of removed controller to a single registered driver.
1001 */
1002static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv,
1003 struct i2o_controller *c)
1004{
1005 if (drv->notify_controller_remove)
1006 drv->notify_controller_remove(c);
1007};
1008
1009/**
Randy Dunlapd9489fb2006-12-06 20:38:43 -08001010 * i2o_driver_notify_device_add - Send notification of added device
1011 * @drv: I2O driver
1012 * @i2o_dev: the added i2o_device
Markus Lidela1a5ea72006-01-06 00:19:29 -08001013 *
1014 * Send notification of added device to a single registered driver.
1015 */
1016static inline void i2o_driver_notify_device_add(struct i2o_driver *drv,
1017 struct i2o_device *i2o_dev)
1018{
1019 if (drv->notify_device_add)
1020 drv->notify_device_add(i2o_dev);
1021};
1022
1023/**
1024 * i2o_driver_notify_device_remove - Send notification of removed device
Randy Dunlapd9489fb2006-12-06 20:38:43 -08001025 * @drv: I2O driver
1026 * @i2o_dev: the added i2o_device
Markus Lidela1a5ea72006-01-06 00:19:29 -08001027 *
1028 * Send notification of removed device to a single registered driver.
1029 */
1030static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv,
1031 struct i2o_device *i2o_dev)
1032{
1033 if (drv->notify_device_remove)
1034 drv->notify_device_remove(i2o_dev);
1035};
1036
1037extern void i2o_driver_notify_controller_add_all(struct i2o_controller *);
1038extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *);
1039extern void i2o_driver_notify_device_add_all(struct i2o_device *);
1040extern void i2o_driver_notify_device_remove_all(struct i2o_device *);
1041
1042/* I2O device functions */
1043extern int i2o_device_claim(struct i2o_device *);
1044extern int i2o_device_claim_release(struct i2o_device *);
1045
1046/* Exec OSM functions */
1047extern int i2o_exec_lct_get(struct i2o_controller *);
1048
1049/* device / driver / kobject conversion functions */
1050#define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
1051#define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
1052#define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
1053#define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
1054
1055/**
1056 * i2o_out_to_virt - Turn an I2O message to a virtual address
1057 * @c: controller
1058 * @m: message engine value
1059 *
1060 * Turn a receive message from an I2O controller bus address into
1061 * a Linux virtual address. The shared page frame is a linear block
1062 * so we simply have to shift the offset. This function does not
1063 * work for sender side messages as they are ioremap objects
1064 * provided by the I2O controller.
1065 */
1066static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
1067 u32 m)
1068{
1069 BUG_ON(m < c->out_queue.phys
1070 || m >= c->out_queue.phys + c->out_queue.len);
1071
1072 return c->out_queue.virt + (m - c->out_queue.phys);
1073};
1074
1075/**
1076 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address
1077 * @c: controller
1078 * @m: message engine value
1079 *
1080 * Turn a send message from an I2O controller bus address into
1081 * a Linux virtual address. The shared page frame is a linear block
1082 * so we simply have to shift the offset. This function does not
1083 * work for receive side messages as they are kmalloc objects
1084 * in a different pool.
1085 */
1086static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
1087 i2o_controller *c,
1088 u32 m)
1089{
1090 return c->in_queue.virt + m;
1091};
1092
1093/**
1094 * i2o_msg_get - obtain an I2O message from the IOP
1095 * @c: I2O controller
1096 *
1097 * This function tries to get a message frame. If no message frame is
1098 * available do not wait until one is availabe (see also i2o_msg_get_wait).
1099 * The returned pointer to the message frame is not in I/O memory, it is
1100 * allocated from a mempool. But because a MFA is allocated from the
1101 * controller too it is guaranteed that i2o_msg_post() will never fail.
1102 *
1103 * On a success a pointer to the message frame is returned. If the message
1104 * queue is empty -EBUSY is returned and if no memory is available -ENOMEM
1105 * is returned.
1106 */
1107static inline struct i2o_message *i2o_msg_get(struct i2o_controller *c)
1108{
1109 struct i2o_msg_mfa *mmsg = mempool_alloc(c->in_msg.mempool, GFP_ATOMIC);
1110 if (!mmsg)
1111 return ERR_PTR(-ENOMEM);
1112
1113 mmsg->mfa = readl(c->in_port);
Markus Lidel8b3e09e2006-02-03 03:04:29 -08001114 if (unlikely(mmsg->mfa >= c->in_queue.len)) {
Markus Lidel57a62fe2006-06-10 09:54:14 -07001115 u32 mfa = mmsg->mfa;
1116
Markus Lidela1a5ea72006-01-06 00:19:29 -08001117 mempool_free(mmsg, c->in_msg.mempool);
Markus Lidel57a62fe2006-06-10 09:54:14 -07001118
1119 if (mfa == I2O_QUEUE_EMPTY)
Markus Lidel8b3e09e2006-02-03 03:04:29 -08001120 return ERR_PTR(-EBUSY);
1121 return ERR_PTR(-EFAULT);
Markus Lidela1a5ea72006-01-06 00:19:29 -08001122 }
1123
1124 return &mmsg->msg;
1125};
1126
1127/**
1128 * i2o_msg_post - Post I2O message to I2O controller
1129 * @c: I2O controller to which the message should be send
1130 * @msg: message returned by i2o_msg_get()
1131 *
1132 * Post the message to the I2O controller and return immediately.
1133 */
1134static inline void i2o_msg_post(struct i2o_controller *c,
1135 struct i2o_message *msg)
1136{
1137 struct i2o_msg_mfa *mmsg;
1138
1139 mmsg = container_of(msg, struct i2o_msg_mfa, msg);
1140 memcpy_toio(i2o_msg_in_to_virt(c, mmsg->mfa), msg,
1141 (le32_to_cpu(msg->u.head[0]) >> 16) << 2);
1142 writel(mmsg->mfa, c->in_port);
1143 mempool_free(mmsg, c->in_msg.mempool);
1144};
1145
1146/**
1147 * i2o_msg_post_wait - Post and wait a message and wait until return
1148 * @c: controller
Randy Dunlapd9489fb2006-12-06 20:38:43 -08001149 * @msg: message to post
Markus Lidela1a5ea72006-01-06 00:19:29 -08001150 * @timeout: time in seconds to wait
1151 *
1152 * This API allows an OSM to post a message and then be told whether or
1153 * not the system received a successful reply. If the message times out
1154 * then the value '-ETIMEDOUT' is returned.
1155 *
1156 * Returns 0 on success or negative error code on failure.
1157 */
1158static inline int i2o_msg_post_wait(struct i2o_controller *c,
1159 struct i2o_message *msg,
1160 unsigned long timeout)
1161{
1162 return i2o_msg_post_wait_mem(c, msg, timeout, NULL);
1163};
1164
1165/**
1166 * i2o_msg_nop_mfa - Returns a fetched MFA back to the controller
1167 * @c: I2O controller from which the MFA was fetched
1168 * @mfa: MFA which should be returned
1169 *
1170 * This function must be used for preserved messages, because i2o_msg_nop()
1171 * also returns the allocated memory back to the msg_pool mempool.
1172 */
1173static inline void i2o_msg_nop_mfa(struct i2o_controller *c, u32 mfa)
1174{
1175 struct i2o_message __iomem *msg;
1176 u32 nop[3] = {
1177 THREE_WORD_MSG_SIZE | SGL_OFFSET_0,
1178 I2O_CMD_UTIL_NOP << 24 | HOST_TID << 12 | ADAPTER_TID,
1179 0x00000000
1180 };
1181
1182 msg = i2o_msg_in_to_virt(c, mfa);
1183 memcpy_toio(msg, nop, sizeof(nop));
1184 writel(mfa, c->in_port);
1185};
1186
1187/**
1188 * i2o_msg_nop - Returns a message which is not used
1189 * @c: I2O controller from which the message was created
1190 * @msg: message which should be returned
1191 *
1192 * If you fetch a message via i2o_msg_get, and can't use it, you must
1193 * return the message with this function. Otherwise the MFA is lost as well
1194 * as the allocated memory from the mempool.
1195 */
1196static inline void i2o_msg_nop(struct i2o_controller *c,
1197 struct i2o_message *msg)
1198{
1199 struct i2o_msg_mfa *mmsg;
1200 mmsg = container_of(msg, struct i2o_msg_mfa, msg);
1201
1202 i2o_msg_nop_mfa(c, mmsg->mfa);
1203 mempool_free(mmsg, c->in_msg.mempool);
1204};
1205
1206/**
1207 * i2o_flush_reply - Flush reply from I2O controller
1208 * @c: I2O controller
1209 * @m: the message identifier
1210 *
1211 * The I2O controller must be informed that the reply message is not needed
1212 * anymore. If you forget to flush the reply, the message frame can't be
1213 * used by the controller anymore and is therefore lost.
1214 */
1215static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
1216{
1217 writel(m, c->out_port);
1218};
1219
1220/*
1221 * Endian handling wrapped into the macro - keeps the core code
1222 * cleaner.
1223 */
1224
1225#define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
1226
1227extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int);
1228extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int,
1229 void *, int);
1230
1231/* debugging and troubleshooting/diagnostic helpers. */
1232#define osm_printk(level, format, arg...) \
1233 printk(level "%s: " format, OSM_NAME , ## arg)
1234
1235#ifdef DEBUG
1236#define osm_debug(format, arg...) \
1237 osm_printk(KERN_DEBUG, format , ## arg)
1238#else
1239#define osm_debug(format, arg...) \
1240 do { } while (0)
1241#endif
1242
1243#define osm_err(format, arg...) \
1244 osm_printk(KERN_ERR, format , ## arg)
1245#define osm_info(format, arg...) \
1246 osm_printk(KERN_INFO, format , ## arg)
1247#define osm_warn(format, arg...) \
1248 osm_printk(KERN_WARNING, format , ## arg)
1249
1250/* debugging functions */
1251extern void i2o_report_status(const char *, const char *, struct i2o_message *);
1252extern void i2o_dump_message(struct i2o_message *);
1253extern void i2o_dump_hrt(struct i2o_controller *c);
1254extern void i2o_debug_state(struct i2o_controller *c);
1255
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256#endif /* _I2O_H */