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Anant Golea6286ee2009-05-18 15:19:01 -07001/*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32/** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34 */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/string.h>
40#include <linux/timer.h>
41#include <linux/errno.h>
42#include <linux/in.h>
43#include <linux/ioport.h>
44#include <linux/slab.h>
45#include <linux/mm.h>
46#include <linux/interrupt.h>
47#include <linux/init.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/ethtool.h>
52#include <linux/highmem.h>
53#include <linux/proc_fs.h>
54#include <linux/ctype.h>
55#include <linux/version.h>
56#include <linux/spinlock.h>
57#include <linux/dma-mapping.h>
58#include <linux/clk.h>
59#include <linux/platform_device.h>
60#include <linux/semaphore.h>
61#include <linux/phy.h>
62#include <linux/bitops.h>
63#include <linux/io.h>
64#include <linux/uaccess.h>
65
66#include <asm/irq.h>
67#include <asm/page.h>
68
69#include <mach/emac.h>
70
71static int debug_level;
72module_param(debug_level, int, 0);
73MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
74
75/* Netif debug messages possible */
76#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR | \
84 NETIF_MSG_TX_QUEUED | \
85 NETIF_MSG_INTR | \
86 NETIF_MSG_TX_DONE | \
87 NETIF_MSG_RX_STATUS | \
88 NETIF_MSG_PKTDATA | \
89 NETIF_MSG_HW | \
90 NETIF_MSG_WOL)
91
92/* version info */
93#define EMAC_MAJOR_VERSION 6
94#define EMAC_MINOR_VERSION 1
95#define EMAC_MODULE_VERSION "6.1"
96MODULE_VERSION(EMAC_MODULE_VERSION);
97static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
98
99/* Configuration items */
100#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
101#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
102#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
103#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
104#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
105#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
106#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
107#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
108#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
109#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
110#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
111#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
112
113#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
114#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
115
116#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
117#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
118#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
119#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
120#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
121#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
122#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
123#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
124#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
125
126/* Buffer descriptor parameters */
127#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
128#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
129
130/* EMAC register related defines */
131#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
132#define EMAC_NUM_MULTICAST_BITS (64)
133#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
134#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
135#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
136#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
137#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
138#define EMAC_INT_MASK_CLEAR (0xFF)
139
140/* RX MBP register bit positions */
141#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
142#define EMAC_RXMBP_QOSEN_MASK BIT(29)
143#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
144#define EMAC_RXMBP_CMFEN_MASK BIT(24)
145#define EMAC_RXMBP_CSFEN_MASK BIT(23)
146#define EMAC_RXMBP_CEFEN_MASK BIT(22)
147#define EMAC_RXMBP_CAFEN_MASK BIT(21)
148#define EMAC_RXMBP_PROMCH_SHIFT (16)
149#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
150#define EMAC_RXMBP_BROADEN_MASK BIT(13)
151#define EMAC_RXMBP_BROADCH_SHIFT (8)
152#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
153#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
154#define EMAC_RXMBP_MULTICH_SHIFT (0)
155#define EMAC_RXMBP_MULTICH_MASK (0x7)
156#define EMAC_RXMBP_CHMASK (0x7)
157
158/* EMAC register definitions/bit maps used */
159# define EMAC_MBP_RXPROMISC (0x00200000)
160# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
161# define EMAC_MBP_RXBCAST (0x00002000)
162# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
163# define EMAC_MBP_RXMCAST (0x00000020)
164# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
165
166/* EMAC mac_control register */
167#define EMAC_MACCONTROL_TXPTYPE (0x200)
168#define EMAC_MACCONTROL_TXPACEEN (0x40)
169#define EMAC_MACCONTROL_MIIEN (0x20)
170#define EMAC_MACCONTROL_GIGABITEN (0x80)
171#define EMAC_MACCONTROL_GIGABITEN_SHIFT (7)
172#define EMAC_MACCONTROL_FULLDUPLEXEN (0x1)
173#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
174
175/* GIGABIT MODE related bits */
176#define EMAC_DM646X_MACCONTORL_GMIIEN BIT(5)
177#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
178#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
179
180/* EMAC mac_status register */
181#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
182#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
183#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
184#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
185#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
186#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
187#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
188#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
189
190/* EMAC RX register masks */
191#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
192#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
193
194/* MAC_IN_VECTOR (0x180) register bit fields */
195#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT (0x20000)
196#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT (0x10000)
197#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC (0x0100)
198#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC (0x01)
199
200/** NOTE:: For DM646x the IN_VECTOR has changed */
201#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
202#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
Sriram43c2ed82009-09-24 19:15:18 +0000203#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
204#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
205
Anant Golea6286ee2009-05-18 15:19:01 -0700206
207/* CPPI bit positions */
208#define EMAC_CPPI_SOP_BIT BIT(31)
209#define EMAC_CPPI_EOP_BIT BIT(30)
210#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
211#define EMAC_CPPI_EOQ_BIT BIT(28)
212#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
213#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
214#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
215#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
216#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
217
218/* Max hardware defines */
219#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
220#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
221
222/* EMAC Peripheral Device Register Memory Layout structure */
223#define EMAC_TXIDVER 0x0
224#define EMAC_TXCONTROL 0x4
225#define EMAC_TXTEARDOWN 0x8
226#define EMAC_RXIDVER 0x10
227#define EMAC_RXCONTROL 0x14
228#define EMAC_RXTEARDOWN 0x18
229#define EMAC_TXINTSTATRAW 0x80
230#define EMAC_TXINTSTATMASKED 0x84
231#define EMAC_TXINTMASKSET 0x88
232#define EMAC_TXINTMASKCLEAR 0x8C
233#define EMAC_MACINVECTOR 0x90
234
235#define EMAC_DM646X_MACEOIVECTOR 0x94
236
237#define EMAC_RXINTSTATRAW 0xA0
238#define EMAC_RXINTSTATMASKED 0xA4
239#define EMAC_RXINTMASKSET 0xA8
240#define EMAC_RXINTMASKCLEAR 0xAC
241#define EMAC_MACINTSTATRAW 0xB0
242#define EMAC_MACINTSTATMASKED 0xB4
243#define EMAC_MACINTMASKSET 0xB8
244#define EMAC_MACINTMASKCLEAR 0xBC
245
246#define EMAC_RXMBPENABLE 0x100
247#define EMAC_RXUNICASTSET 0x104
248#define EMAC_RXUNICASTCLEAR 0x108
249#define EMAC_RXMAXLEN 0x10C
250#define EMAC_RXBUFFEROFFSET 0x110
251#define EMAC_RXFILTERLOWTHRESH 0x114
252
253#define EMAC_MACCONTROL 0x160
254#define EMAC_MACSTATUS 0x164
255#define EMAC_EMCONTROL 0x168
256#define EMAC_FIFOCONTROL 0x16C
257#define EMAC_MACCONFIG 0x170
258#define EMAC_SOFTRESET 0x174
259#define EMAC_MACSRCADDRLO 0x1D0
260#define EMAC_MACSRCADDRHI 0x1D4
261#define EMAC_MACHASH1 0x1D8
262#define EMAC_MACHASH2 0x1DC
263#define EMAC_MACADDRLO 0x500
264#define EMAC_MACADDRHI 0x504
265#define EMAC_MACINDEX 0x508
266
267/* EMAC HDP and Completion registors */
268#define EMAC_TXHDP(ch) (0x600 + (ch * 4))
269#define EMAC_RXHDP(ch) (0x620 + (ch * 4))
270#define EMAC_TXCP(ch) (0x640 + (ch * 4))
271#define EMAC_RXCP(ch) (0x660 + (ch * 4))
272
273/* EMAC statistics registers */
274#define EMAC_RXGOODFRAMES 0x200
275#define EMAC_RXBCASTFRAMES 0x204
276#define EMAC_RXMCASTFRAMES 0x208
277#define EMAC_RXPAUSEFRAMES 0x20C
278#define EMAC_RXCRCERRORS 0x210
279#define EMAC_RXALIGNCODEERRORS 0x214
280#define EMAC_RXOVERSIZED 0x218
281#define EMAC_RXJABBER 0x21C
282#define EMAC_RXUNDERSIZED 0x220
283#define EMAC_RXFRAGMENTS 0x224
284#define EMAC_RXFILTERED 0x228
285#define EMAC_RXQOSFILTERED 0x22C
286#define EMAC_RXOCTETS 0x230
287#define EMAC_TXGOODFRAMES 0x234
288#define EMAC_TXBCASTFRAMES 0x238
289#define EMAC_TXMCASTFRAMES 0x23C
290#define EMAC_TXPAUSEFRAMES 0x240
291#define EMAC_TXDEFERRED 0x244
292#define EMAC_TXCOLLISION 0x248
293#define EMAC_TXSINGLECOLL 0x24C
294#define EMAC_TXMULTICOLL 0x250
295#define EMAC_TXEXCESSIVECOLL 0x254
296#define EMAC_TXLATECOLL 0x258
297#define EMAC_TXUNDERRUN 0x25C
298#define EMAC_TXCARRIERSENSE 0x260
299#define EMAC_TXOCTETS 0x264
300#define EMAC_NETOCTETS 0x280
301#define EMAC_RXSOFOVERRUNS 0x284
302#define EMAC_RXMOFOVERRUNS 0x288
303#define EMAC_RXDMAOVERRUNS 0x28C
304
305/* EMAC DM644x control registers */
306#define EMAC_CTRL_EWCTL (0x4)
307#define EMAC_CTRL_EWINTTCNT (0x8)
308
309/* EMAC MDIO related */
310/* Mask & Control defines */
311#define MDIO_CONTROL_CLKDIV (0xFF)
312#define MDIO_CONTROL_ENABLE BIT(30)
313#define MDIO_USERACCESS_GO BIT(31)
314#define MDIO_USERACCESS_WRITE BIT(30)
315#define MDIO_USERACCESS_READ (0)
316#define MDIO_USERACCESS_REGADR (0x1F << 21)
317#define MDIO_USERACCESS_PHYADR (0x1F << 16)
318#define MDIO_USERACCESS_DATA (0xFFFF)
319#define MDIO_USERPHYSEL_LINKSEL BIT(7)
320#define MDIO_VER_MODID (0xFFFF << 16)
321#define MDIO_VER_REVMAJ (0xFF << 8)
322#define MDIO_VER_REVMIN (0xFF)
323
324#define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
325#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
326#define MDIO_CONTROL (0x04)
327
328/* EMAC DM646X control module registers */
329#define EMAC_DM646X_CMRXINTEN (0x14)
330#define EMAC_DM646X_CMTXINTEN (0x18)
331
332/* EMAC EOI codes for C0 */
333#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
334#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
335
Sriram0fe74632009-10-07 02:44:30 +0000336/* EMAC Stats Clear Mask */
337#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
338
Anant Golea6286ee2009-05-18 15:19:01 -0700339/** net_buf_obj: EMAC network bufferdata structure
340 *
341 * EMAC network buffer data structure
342 */
343struct emac_netbufobj {
344 void *buf_token;
345 char *data_ptr;
346 int length;
347};
348
349/** net_pkt_obj: EMAC network packet data structure
350 *
351 * EMAC network packet data structure - supports buffer list (for future)
352 */
353struct emac_netpktobj {
354 void *pkt_token; /* data token may hold tx/rx chan id */
355 struct emac_netbufobj *buf_list; /* array of network buffer objects */
356 int num_bufs;
357 int pkt_length;
358};
359
360/** emac_tx_bd: EMAC TX Buffer descriptor data structure
361 *
362 * EMAC TX Buffer descriptor data structure
363 */
364struct emac_tx_bd {
365 int h_next;
366 int buff_ptr;
367 int off_b_len;
368 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
369 struct emac_tx_bd __iomem *next;
370 void *buf_token;
371};
372
373/** emac_txch: EMAC TX Channel data structure
374 *
375 * EMAC TX Channel data structure
376 */
377struct emac_txch {
378 /* Config related */
379 u32 num_bd;
380 u32 service_max;
381
382 /* CPPI specific */
383 u32 alloc_size;
384 void __iomem *bd_mem;
385 struct emac_tx_bd __iomem *bd_pool_head;
386 struct emac_tx_bd __iomem *active_queue_head;
387 struct emac_tx_bd __iomem *active_queue_tail;
388 struct emac_tx_bd __iomem *last_hw_bdprocessed;
389 u32 queue_active;
390 u32 teardown_pending;
391 u32 *tx_complete;
392
393 /** statistics */
394 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
395 u32 mis_queued_packets;
396 u32 queue_reinit;
397 u32 end_of_queue_add;
398 u32 out_of_tx_bd;
399 u32 no_active_pkts; /* IRQ when there were no packets to process */
400 u32 active_queue_count;
401};
402
403/** emac_rx_bd: EMAC RX Buffer descriptor data structure
404 *
405 * EMAC RX Buffer descriptor data structure
406 */
407struct emac_rx_bd {
408 int h_next;
409 int buff_ptr;
410 int off_b_len;
411 int mode;
412 struct emac_rx_bd __iomem *next;
413 void *data_ptr;
414 void *buf_token;
415};
416
417/** emac_rxch: EMAC RX Channel data structure
418 *
419 * EMAC RX Channel data structure
420 */
421struct emac_rxch {
422 /* configuration info */
423 u32 num_bd;
424 u32 service_max;
425 u32 buf_size;
426 char mac_addr[6];
427
428 /** CPPI specific */
429 u32 alloc_size;
430 void __iomem *bd_mem;
431 struct emac_rx_bd __iomem *bd_pool_head;
432 struct emac_rx_bd __iomem *active_queue_head;
433 struct emac_rx_bd __iomem *active_queue_tail;
434 u32 queue_active;
435 u32 teardown_pending;
436
437 /* packet and buffer objects */
438 struct emac_netpktobj pkt_queue;
439 struct emac_netbufobj buf_queue;
440
441 /** statistics */
442 u32 proc_count; /* number of times emac_rx_bdproc is called */
443 u32 processed_bd;
444 u32 recycled_bd;
445 u32 out_of_rx_bd;
446 u32 out_of_rx_buffers;
447 u32 queue_reinit;
448 u32 end_of_queue_add;
449 u32 end_of_queue;
450 u32 mis_queued_packets;
451};
452
453/* emac_priv: EMAC private data structure
454 *
455 * EMAC adapter private data structure
456 */
457struct emac_priv {
458 u32 msg_enable;
459 struct net_device *ndev;
460 struct platform_device *pdev;
461 struct napi_struct napi;
462 char mac_addr[6];
463 spinlock_t tx_lock;
464 spinlock_t rx_lock;
465 void __iomem *remap_addr;
466 u32 emac_base_phys;
467 void __iomem *emac_base;
468 void __iomem *ctrl_base;
469 void __iomem *emac_ctrl_ram;
470 u32 ctrl_ram_size;
471 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
472 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
473 u32 link; /* 1=link on, 0=link off */
474 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
475 u32 duplex; /* Link duplex: 0=Half, 1=Full */
476 u32 rx_buf_size;
477 u32 isr_count;
478 u8 rmii_en;
479 u8 version;
480 struct net_device_stats net_dev_stats;
481 u32 mac_hash1;
482 u32 mac_hash2;
483 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
484 u32 rx_addr_type;
485 /* periodic timer required for MDIO polling */
486 struct timer_list periodic_timer;
487 u32 periodic_ticks;
488 u32 timer_active;
489 u32 phy_mask;
490 /* mii_bus,phy members */
491 struct mii_bus *mii_bus;
492 struct phy_device *phydev;
493 spinlock_t lock;
494};
495
496/* clock frequency for EMAC */
497static struct clk *emac_clk;
498static unsigned long emac_bus_frequency;
499static unsigned long mdio_max_freq;
500
501/* EMAC internal utility function */
502static inline u32 emac_virt_to_phys(void __iomem *addr)
503{
504 return (u32 __force) io_v2p(addr);
505}
506
507/* Cache macros - Packet buffers would be from skb pool which is cached */
508#define EMAC_VIRT_NOCACHE(addr) (addr)
509#define EMAC_CACHE_INVALIDATE(addr, size) \
510 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
511#define EMAC_CACHE_WRITEBACK(addr, size) \
512 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
513#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
514 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
515
516/* DM644x does not have BD's in cached memory - so no cache functions */
517#define BD_CACHE_INVALIDATE(addr, size)
518#define BD_CACHE_WRITEBACK(addr, size)
519#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
520
521/* EMAC TX Host Error description strings */
522static char *emac_txhost_errcodes[16] = {
523 "No error", "SOP error", "Ownership bit not set in SOP buffer",
524 "Zero Next Buffer Descriptor Pointer Without EOP",
525 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
526 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
527 "Reserved", "Reserved", "Reserved", "Reserved"
528};
529
530/* EMAC RX Host Error description strings */
531static char *emac_rxhost_errcodes[16] = {
532 "No error", "Reserved", "Ownership bit not set in input buffer",
533 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
534 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
535 "Reserved", "Reserved", "Reserved", "Reserved"
536};
537
538/* Helper macros */
539#define emac_read(reg) ioread32(priv->emac_base + (reg))
540#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
541
542#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
543#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
544
545#define emac_mdio_read(reg) ioread32(bus->priv + (reg))
546#define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
547
548/**
549 * emac_dump_regs: Dump important EMAC registers to debug terminal
550 * @priv: The DaVinci EMAC private adapter structure
551 *
552 * Executes ethtool set cmd & sets phy mode
553 *
554 */
555static void emac_dump_regs(struct emac_priv *priv)
556{
557 struct device *emac_dev = &priv->ndev->dev;
558
559 /* Print important registers in EMAC */
560 dev_info(emac_dev, "EMAC Basic registers\n");
561 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
562 emac_ctrl_read(EMAC_CTRL_EWCTL),
563 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
564 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
565 emac_read(EMAC_TXIDVER),
566 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
567 emac_read(EMAC_RXIDVER),
568 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
569 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
570 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
571 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
572 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
573 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
574 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
575 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
576 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
577 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
578 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
579 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
580 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
581 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
582 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
583 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
584 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
585 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
586 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
587 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
588 dev_info(emac_dev, "EMAC Statistics\n");
589 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
590 emac_read(EMAC_RXGOODFRAMES));
591 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
592 emac_read(EMAC_RXBCASTFRAMES));
593 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
594 emac_read(EMAC_RXMCASTFRAMES));
595 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
596 emac_read(EMAC_RXPAUSEFRAMES));
597 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
598 emac_read(EMAC_RXCRCERRORS));
599 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
600 emac_read(EMAC_RXALIGNCODEERRORS));
601 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
602 emac_read(EMAC_RXOVERSIZED));
603 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
604 emac_read(EMAC_RXJABBER));
605 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
606 emac_read(EMAC_RXUNDERSIZED));
607 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
608 emac_read(EMAC_RXFRAGMENTS));
609 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
610 emac_read(EMAC_RXFILTERED));
611 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
612 emac_read(EMAC_RXQOSFILTERED));
613 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
614 emac_read(EMAC_RXOCTETS));
615 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
616 emac_read(EMAC_TXGOODFRAMES));
617 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
618 emac_read(EMAC_TXBCASTFRAMES));
619 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
620 emac_read(EMAC_TXMCASTFRAMES));
621 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
622 emac_read(EMAC_TXPAUSEFRAMES));
623 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
624 emac_read(EMAC_TXDEFERRED));
625 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
626 emac_read(EMAC_TXCOLLISION));
627 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
628 emac_read(EMAC_TXSINGLECOLL));
629 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
630 emac_read(EMAC_TXMULTICOLL));
631 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
632 emac_read(EMAC_TXEXCESSIVECOLL));
633 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
634 emac_read(EMAC_TXLATECOLL));
635 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
636 emac_read(EMAC_TXUNDERRUN));
637 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
638 emac_read(EMAC_TXCARRIERSENSE));
639 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
640 emac_read(EMAC_TXOCTETS));
641 dev_info(emac_dev, "EMAC: net_octets:%d\n",
642 emac_read(EMAC_NETOCTETS));
643 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
644 emac_read(EMAC_RXSOFOVERRUNS));
645 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
646 emac_read(EMAC_RXMOFOVERRUNS));
647 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
648 emac_read(EMAC_RXDMAOVERRUNS));
649}
650
651/*************************************************************************
652 * EMAC MDIO/Phy Functionality
653 *************************************************************************/
654/**
655 * emac_get_drvinfo: Get EMAC driver information
656 * @ndev: The DaVinci EMAC network adapter
657 * @info: ethtool info structure containing name and version
658 *
659 * Returns EMAC driver information (name and version)
660 *
661 */
662static void emac_get_drvinfo(struct net_device *ndev,
663 struct ethtool_drvinfo *info)
664{
665 strcpy(info->driver, emac_version_string);
666 strcpy(info->version, EMAC_MODULE_VERSION);
667}
668
669/**
670 * emac_get_settings: Get EMAC settings
671 * @ndev: The DaVinci EMAC network adapter
672 * @ecmd: ethtool command
673 *
674 * Executes ethool get command
675 *
676 */
677static int emac_get_settings(struct net_device *ndev,
678 struct ethtool_cmd *ecmd)
679{
680 struct emac_priv *priv = netdev_priv(ndev);
681 if (priv->phy_mask)
682 return phy_ethtool_gset(priv->phydev, ecmd);
683 else
684 return -EOPNOTSUPP;
685
686}
687
688/**
689 * emac_set_settings: Set EMAC settings
690 * @ndev: The DaVinci EMAC network adapter
691 * @ecmd: ethtool command
692 *
693 * Executes ethool set command
694 *
695 */
696static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
697{
698 struct emac_priv *priv = netdev_priv(ndev);
699 if (priv->phy_mask)
700 return phy_ethtool_sset(priv->phydev, ecmd);
701 else
702 return -EOPNOTSUPP;
703
704}
705
706/**
707 * ethtool_ops: DaVinci EMAC Ethtool structure
708 *
709 * Ethtool support for EMAC adapter
710 *
711 */
712static const struct ethtool_ops ethtool_ops = {
713 .get_drvinfo = emac_get_drvinfo,
714 .get_settings = emac_get_settings,
715 .set_settings = emac_set_settings,
716 .get_link = ethtool_op_get_link,
717};
718
719/**
720 * emac_update_phystatus: Update Phy status
721 * @priv: The DaVinci EMAC private adapter structure
722 *
723 * Updates phy status and takes action for network queue if required
724 * based upon link status
725 *
726 */
727static void emac_update_phystatus(struct emac_priv *priv)
728{
729 u32 mac_control;
730 u32 new_duplex;
731 u32 cur_duplex;
732 struct net_device *ndev = priv->ndev;
733
734 mac_control = emac_read(EMAC_MACCONTROL);
735 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
736 DUPLEX_FULL : DUPLEX_HALF;
737 if (priv->phy_mask)
738 new_duplex = priv->phydev->duplex;
739 else
740 new_duplex = DUPLEX_FULL;
741
742 /* We get called only if link has changed (speed/duplex/status) */
743 if ((priv->link) && (new_duplex != cur_duplex)) {
744 priv->duplex = new_duplex;
745 if (DUPLEX_FULL == priv->duplex)
746 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
747 else
748 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
749 }
750
751 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
752 mac_control = emac_read(EMAC_MACCONTROL);
753 mac_control |= (EMAC_DM646X_MACCONTORL_GMIIEN |
754 EMAC_DM646X_MACCONTORL_GIG |
755 EMAC_DM646X_MACCONTORL_GIGFORCE);
756 } else {
757 /* Clear the GIG bit and GIGFORCE bit */
758 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
759 EMAC_DM646X_MACCONTORL_GIG);
760
761 if (priv->rmii_en && (priv->speed == SPEED_100))
762 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
763 else
764 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
765 }
766
767 /* Update mac_control if changed */
768 emac_write(EMAC_MACCONTROL, mac_control);
769
770 if (priv->link) {
771 /* link ON */
772 if (!netif_carrier_ok(ndev))
773 netif_carrier_on(ndev);
774 /* reactivate the transmit queue if it is stopped */
775 if (netif_running(ndev) && netif_queue_stopped(ndev))
776 netif_wake_queue(ndev);
777 } else {
778 /* link OFF */
779 if (netif_carrier_ok(ndev))
780 netif_carrier_off(ndev);
781 if (!netif_queue_stopped(ndev))
782 netif_stop_queue(ndev);
783 }
784}
785
786/**
787 * hash_get: Calculate hash value from mac address
788 * @addr: mac address to delete from hash table
789 *
790 * Calculates hash value from mac address
791 *
792 */
793static u32 hash_get(u8 *addr)
794{
795 u32 hash;
796 u8 tmpval;
797 int cnt;
798 hash = 0;
799
800 for (cnt = 0; cnt < 2; cnt++) {
801 tmpval = *addr++;
802 hash ^= (tmpval >> 2) ^ (tmpval << 4);
803 tmpval = *addr++;
804 hash ^= (tmpval >> 4) ^ (tmpval << 2);
805 tmpval = *addr++;
806 hash ^= (tmpval >> 6) ^ (tmpval);
807 }
808
809 return hash & 0x3F;
810}
811
812/**
813 * hash_add: Hash function to add mac addr from hash table
814 * @priv: The DaVinci EMAC private adapter structure
815 * mac_addr: mac address to delete from hash table
816 *
817 * Adds mac address to the internal hash table
818 *
819 */
820static int hash_add(struct emac_priv *priv, u8 *mac_addr)
821{
822 struct device *emac_dev = &priv->ndev->dev;
823 u32 rc = 0;
824 u32 hash_bit;
825 u32 hash_value = hash_get(mac_addr);
826
827 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
828 if (netif_msg_drv(priv)) {
829 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
830 "Hash %08x, should not be greater than %08x",
831 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
832 }
833 return -1;
834 }
835
836 /* set the hash bit only if not previously set */
837 if (priv->multicast_hash_cnt[hash_value] == 0) {
838 rc = 1; /* hash value changed */
839 if (hash_value < 32) {
840 hash_bit = BIT(hash_value);
841 priv->mac_hash1 |= hash_bit;
842 } else {
843 hash_bit = BIT((hash_value - 32));
844 priv->mac_hash2 |= hash_bit;
845 }
846 }
847
848 /* incr counter for num of mcast addr's mapped to "this" hash bit */
849 ++priv->multicast_hash_cnt[hash_value];
850
851 return rc;
852}
853
854/**
855 * hash_del: Hash function to delete mac addr from hash table
856 * @priv: The DaVinci EMAC private adapter structure
857 * mac_addr: mac address to delete from hash table
858 *
859 * Removes mac address from the internal hash table
860 *
861 */
862static int hash_del(struct emac_priv *priv, u8 *mac_addr)
863{
864 u32 hash_value;
865 u32 hash_bit;
866
867 hash_value = hash_get(mac_addr);
868 if (priv->multicast_hash_cnt[hash_value] > 0) {
869 /* dec cntr for num of mcast addr's mapped to this hash bit */
870 --priv->multicast_hash_cnt[hash_value];
871 }
872
873 /* if counter still > 0, at least one multicast address refers
874 * to this hash bit. so return 0 */
875 if (priv->multicast_hash_cnt[hash_value] > 0)
876 return 0;
877
878 if (hash_value < 32) {
879 hash_bit = BIT(hash_value);
880 priv->mac_hash1 &= ~hash_bit;
881 } else {
882 hash_bit = BIT((hash_value - 32));
883 priv->mac_hash2 &= ~hash_bit;
884 }
885
886 /* return 1 to indicate change in mac_hash registers reqd */
887 return 1;
888}
889
890/* EMAC multicast operation */
891#define EMAC_MULTICAST_ADD 0
892#define EMAC_MULTICAST_DEL 1
893#define EMAC_ALL_MULTI_SET 2
894#define EMAC_ALL_MULTI_CLR 3
895
896/**
897 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
898 * @priv: The DaVinci EMAC private adapter structure
899 * @action: multicast operation to perform
900 * mac_addr: mac address to set
901 *
902 * Set multicast addresses in EMAC adapter - internal function
903 *
904 */
905static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
906{
907 struct device *emac_dev = &priv->ndev->dev;
908 int update = -1;
909
910 switch (action) {
911 case EMAC_MULTICAST_ADD:
912 update = hash_add(priv, mac_addr);
913 break;
914 case EMAC_MULTICAST_DEL:
915 update = hash_del(priv, mac_addr);
916 break;
917 case EMAC_ALL_MULTI_SET:
918 update = 1;
919 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
920 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
921 break;
922 case EMAC_ALL_MULTI_CLR:
923 update = 1;
924 priv->mac_hash1 = 0;
925 priv->mac_hash2 = 0;
926 memset(&(priv->multicast_hash_cnt[0]), 0,
927 sizeof(priv->multicast_hash_cnt[0]) *
928 EMAC_NUM_MULTICAST_BITS);
929 break;
930 default:
931 if (netif_msg_drv(priv))
932 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
933 ": bad operation %d", action);
934 break;
935 }
936
937 /* write to the hardware only if the register status chances */
938 if (update > 0) {
939 emac_write(EMAC_MACHASH1, priv->mac_hash1);
940 emac_write(EMAC_MACHASH2, priv->mac_hash2);
941 }
942}
943
944/**
945 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
946 * @ndev: The DaVinci EMAC network adapter
947 *
948 * Set multicast addresses in EMAC adapter
949 *
950 */
951static void emac_dev_mcast_set(struct net_device *ndev)
952{
953 u32 mbp_enable;
954 struct emac_priv *priv = netdev_priv(ndev);
955
956 mbp_enable = emac_read(EMAC_RXMBPENABLE);
957 if (ndev->flags & IFF_PROMISC) {
958 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
959 mbp_enable |= (EMAC_MBP_RXPROMISC);
960 } else {
961 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
962 if ((ndev->flags & IFF_ALLMULTI) ||
963 (ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) {
964 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
965 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
966 }
967 if (ndev->mc_count > 0) {
968 struct dev_mc_list *mc_ptr;
969 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
970 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
971 /* program multicast address list into EMAC hardware */
972 for (mc_ptr = ndev->mc_list; mc_ptr;
973 mc_ptr = mc_ptr->next) {
974 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
975 (u8 *)mc_ptr->dmi_addr);
976 }
977 } else {
978 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
979 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
980 }
981 }
982 /* Set mbp config register */
983 emac_write(EMAC_RXMBPENABLE, mbp_enable);
984}
985
986/*************************************************************************
987 * EMAC Hardware manipulation
988 *************************************************************************/
989
990/**
991 * emac_int_disable: Disable EMAC module interrupt (from adapter)
992 * @priv: The DaVinci EMAC private adapter structure
993 *
994 * Disable EMAC interrupt on the adapter
995 *
996 */
997static void emac_int_disable(struct emac_priv *priv)
998{
999 if (priv->version == EMAC_VERSION_2) {
1000 unsigned long flags;
1001
1002 local_irq_save(flags);
1003
1004 /* Program C0_Int_En to zero to turn off
1005 * interrupts to the CPU */
1006 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1007 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1008 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1009
1010 local_irq_restore(flags);
1011
1012 } else {
1013 /* Set DM644x control registers for interrupt control */
1014 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1015 }
1016}
1017
1018/**
1019 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1020 * @priv: The DaVinci EMAC private adapter structure
1021 *
1022 * Enable EMAC interrupt on the adapter
1023 *
1024 */
1025static void emac_int_enable(struct emac_priv *priv)
1026{
1027 if (priv->version == EMAC_VERSION_2) {
1028 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1029 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1030
1031 /* In addition to turning on interrupt Enable, we need
1032 * ack by writing appropriate values to the EOI
1033 * register */
1034
1035 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1036
1037 /* ack rxen only then a new pulse will be generated */
1038 emac_write(EMAC_DM646X_MACEOIVECTOR,
1039 EMAC_DM646X_MAC_EOI_C0_RXEN);
1040
1041 /* ack txen- only then a new pulse will be generated */
1042 emac_write(EMAC_DM646X_MACEOIVECTOR,
1043 EMAC_DM646X_MAC_EOI_C0_TXEN);
1044
1045 } else {
1046 /* Set DM644x control registers for interrupt control */
1047 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1048 }
1049}
1050
1051/**
1052 * emac_irq: EMAC interrupt handler
1053 * @irq: interrupt number
1054 * @dev_id: EMAC network adapter data structure ptr
1055 *
1056 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1057 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1058 *
1059 * Returns interrupt handled condition
1060 */
1061static irqreturn_t emac_irq(int irq, void *dev_id)
1062{
1063 struct net_device *ndev = (struct net_device *)dev_id;
1064 struct emac_priv *priv = netdev_priv(ndev);
1065
1066 ++priv->isr_count;
1067 if (likely(netif_running(priv->ndev))) {
1068 emac_int_disable(priv);
1069 napi_schedule(&priv->napi);
1070 } else {
1071 /* we are closing down, so dont process anything */
1072 }
1073 return IRQ_HANDLED;
1074}
1075
1076/** EMAC on-chip buffer descriptor memory
1077 *
1078 * WARNING: Please note that the on chip memory is used for both TX and RX
1079 * buffer descriptor queues and is equally divided between TX and RX desc's
1080 * If the number of TX or RX descriptors change this memory pointers need
1081 * to be adjusted. If external memory is allocated then these pointers can
1082 * pointer to the memory
1083 *
1084 */
1085#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1086#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1087 (((priv)->ctrl_ram_size) >> 1))
1088
1089/**
1090 * emac_init_txch: TX channel initialization
1091 * @priv: The DaVinci EMAC private adapter structure
1092 * @ch: RX channel number
1093 *
1094 * Called during device init to setup a TX channel (allocate buffer desc
1095 * create free pool and keep ready for transmission
1096 *
1097 * Returns success(0) or mem alloc failures error code
1098 */
1099static int emac_init_txch(struct emac_priv *priv, u32 ch)
1100{
1101 struct device *emac_dev = &priv->ndev->dev;
1102 u32 cnt, bd_size;
1103 void __iomem *mem;
1104 struct emac_tx_bd __iomem *curr_bd;
1105 struct emac_txch *txch = NULL;
1106
1107 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1108 if (NULL == txch) {
1109 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1110 return -ENOMEM;
1111 }
1112 priv->txch[ch] = txch;
1113 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1114 txch->active_queue_head = NULL;
1115 txch->active_queue_tail = NULL;
1116 txch->queue_active = 0;
1117 txch->teardown_pending = 0;
1118
1119 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1120 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1121 GFP_KERNEL);
1122 if (NULL == txch->tx_complete) {
1123 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1124 kfree(txch);
1125 return -ENOMEM;
1126 }
1127
1128 /* allocate buffer descriptor pool align every BD on four word
1129 * boundry for future requirements */
1130 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1131 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1132 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1133
1134 /* alloc TX BD memory */
1135 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1136 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1137
1138 /* initialize the BD linked list */
1139 mem = (void __force __iomem *)
1140 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1141 txch->bd_pool_head = NULL;
1142 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1143 curr_bd = mem + (cnt * bd_size);
1144 curr_bd->next = txch->bd_pool_head;
1145 txch->bd_pool_head = curr_bd;
1146 }
1147
1148 /* reset statistics counters */
1149 txch->out_of_tx_bd = 0;
1150 txch->no_active_pkts = 0;
1151 txch->active_queue_count = 0;
1152
1153 return 0;
1154}
1155
1156/**
1157 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1158 * @priv: The DaVinci EMAC private adapter structure
1159 * @ch: TX channel number
1160 *
1161 * Called to clean up TX channel resources
1162 *
1163 */
1164static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1165{
1166 struct emac_txch *txch = priv->txch[ch];
1167
1168 if (txch) {
1169 if (txch->bd_mem)
1170 txch->bd_mem = NULL;
1171 kfree(txch->tx_complete);
1172 kfree(txch);
1173 priv->txch[ch] = NULL;
1174 }
1175}
1176
1177/**
1178 * emac_net_tx_complete: TX packet completion function
1179 * @priv: The DaVinci EMAC private adapter structure
1180 * @net_data_tokens: packet token - skb pointer
1181 * @num_tokens: number of skb's to free
1182 * @ch: TX channel number
1183 *
1184 * Frees the skb once packet is transmitted
1185 *
1186 */
1187static int emac_net_tx_complete(struct emac_priv *priv,
1188 void **net_data_tokens,
1189 int num_tokens, u32 ch)
1190{
1191 u32 cnt;
1192
1193 if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1194 netif_start_queue(priv->ndev);
1195 for (cnt = 0; cnt < num_tokens; cnt++) {
1196 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1197 if (skb == NULL)
1198 continue;
1199 priv->net_dev_stats.tx_packets++;
1200 priv->net_dev_stats.tx_bytes += skb->len;
1201 dev_kfree_skb_any(skb);
1202 }
1203 return 0;
1204}
1205
1206/**
1207 * emac_txch_teardown: TX channel teardown
1208 * @priv: The DaVinci EMAC private adapter structure
1209 * @ch: TX channel number
1210 *
1211 * Called to teardown TX channel
1212 *
1213 */
1214static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1215{
1216 struct device *emac_dev = &priv->ndev->dev;
1217 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1218 struct emac_txch *txch = priv->txch[ch];
1219 struct emac_tx_bd __iomem *curr_bd;
1220
1221 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1222 EMAC_TEARDOWN_VALUE) {
1223 /* wait till tx teardown complete */
1224 cpu_relax(); /* TODO: check if this helps ... */
1225 --teardown_cnt;
1226 if (0 == teardown_cnt) {
1227 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1228 break;
1229 }
1230 }
1231 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1232
1233 /* process sent packets and return skb's to upper layer */
1234 if (1 == txch->queue_active) {
1235 curr_bd = txch->active_queue_head;
1236 while (curr_bd != NULL) {
1237 emac_net_tx_complete(priv, (void __force *)
1238 &curr_bd->buf_token, 1, ch);
1239 if (curr_bd != txch->active_queue_tail)
1240 curr_bd = curr_bd->next;
1241 else
1242 break;
1243 }
1244 txch->bd_pool_head = txch->active_queue_head;
1245 txch->active_queue_head =
1246 txch->active_queue_tail = NULL;
1247 }
1248}
1249
1250/**
1251 * emac_stop_txch: Stop TX channel operation
1252 * @priv: The DaVinci EMAC private adapter structure
1253 * @ch: TX channel number
1254 *
1255 * Called to stop TX channel operation
1256 *
1257 */
1258static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1259{
1260 struct emac_txch *txch = priv->txch[ch];
1261
1262 if (txch) {
1263 txch->teardown_pending = 1;
1264 emac_write(EMAC_TXTEARDOWN, 0);
1265 emac_txch_teardown(priv, ch);
1266 txch->teardown_pending = 0;
1267 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1268 }
1269}
1270
1271/**
1272 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1273 * @priv: The DaVinci EMAC private adapter structure
1274 * @ch: TX channel number to process buffer descriptors for
1275 * @budget: number of packets allowed to process
1276 * @pending: indication to caller that packets are pending to process
1277 *
1278 * Processes TX buffer descriptors after packets are transmitted - checks
1279 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1280 * the SKB buffer. Only "budget" number of packets are processed and
1281 * indication of pending packets provided to the caller
1282 *
1283 * Returns number of packets processed
1284 */
1285static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1286{
1287 struct device *emac_dev = &priv->ndev->dev;
1288 unsigned long flags;
1289 u32 frame_status;
1290 u32 pkts_processed = 0;
1291 u32 tx_complete_cnt = 0;
1292 struct emac_tx_bd __iomem *curr_bd;
1293 struct emac_txch *txch = priv->txch[ch];
1294 u32 *tx_complete_ptr = txch->tx_complete;
1295
1296 if (unlikely(1 == txch->teardown_pending)) {
1297 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1298 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1299 "teardown pending\n");
1300 }
1301 return 0; /* dont handle any pkt completions */
1302 }
1303
1304 ++txch->proc_count;
1305 spin_lock_irqsave(&priv->tx_lock, flags);
1306 curr_bd = txch->active_queue_head;
1307 if (NULL == curr_bd) {
1308 emac_write(EMAC_TXCP(ch),
1309 emac_virt_to_phys(txch->last_hw_bdprocessed));
1310 txch->no_active_pkts++;
1311 spin_unlock_irqrestore(&priv->tx_lock, flags);
1312 return 0;
1313 }
1314 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1315 frame_status = curr_bd->mode;
1316 while ((curr_bd) &&
1317 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1318 (pkts_processed < budget)) {
1319 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd));
1320 txch->active_queue_head = curr_bd->next;
1321 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1322 if (curr_bd->next) { /* misqueued packet */
1323 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1324 ++txch->mis_queued_packets;
1325 } else {
1326 txch->queue_active = 0; /* end of queue */
1327 }
1328 }
1329 *tx_complete_ptr = (u32) curr_bd->buf_token;
1330 ++tx_complete_ptr;
1331 ++tx_complete_cnt;
1332 curr_bd->next = txch->bd_pool_head;
1333 txch->bd_pool_head = curr_bd;
1334 --txch->active_queue_count;
1335 pkts_processed++;
1336 txch->last_hw_bdprocessed = curr_bd;
1337 curr_bd = txch->active_queue_head;
1338 if (curr_bd) {
1339 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1340 frame_status = curr_bd->mode;
1341 }
1342 } /* end of pkt processing loop */
1343
1344 emac_net_tx_complete(priv,
1345 (void *)&txch->tx_complete[0],
1346 tx_complete_cnt, ch);
1347 spin_unlock_irqrestore(&priv->tx_lock, flags);
1348 return pkts_processed;
1349}
1350
1351#define EMAC_ERR_TX_OUT_OF_BD -1
1352
1353/**
1354 * emac_send: EMAC Transmit function (internal)
1355 * @priv: The DaVinci EMAC private adapter structure
1356 * @pkt: packet pointer (contains skb ptr)
1357 * @ch: TX channel number
1358 *
1359 * Called by the transmit function to queue the packet in EMAC hardware queue
1360 *
1361 * Returns success(0) or error code (typically out of desc's)
1362 */
1363static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1364{
1365 unsigned long flags;
1366 struct emac_tx_bd __iomem *curr_bd;
1367 struct emac_txch *txch;
1368 struct emac_netbufobj *buf_list;
1369
1370 txch = priv->txch[ch];
1371 buf_list = pkt->buf_list; /* get handle to the buffer array */
1372
1373 /* check packet size and pad if short */
1374 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1375 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1376 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1377 }
1378
1379 spin_lock_irqsave(&priv->tx_lock, flags);
1380 curr_bd = txch->bd_pool_head;
1381 if (curr_bd == NULL) {
1382 txch->out_of_tx_bd++;
1383 spin_unlock_irqrestore(&priv->tx_lock, flags);
1384 return EMAC_ERR_TX_OUT_OF_BD;
1385 }
1386
1387 txch->bd_pool_head = curr_bd->next;
1388 curr_bd->buf_token = buf_list->buf_token;
1389 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1390 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1391 curr_bd->off_b_len = buf_list->length;
1392 curr_bd->h_next = 0;
1393 curr_bd->next = NULL;
1394 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1395 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1396
1397 /* flush the packet from cache if write back cache is present */
1398 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1399
1400 /* send the packet */
1401 if (txch->active_queue_head == NULL) {
1402 txch->active_queue_head = curr_bd;
1403 txch->active_queue_tail = curr_bd;
1404 if (1 != txch->queue_active) {
1405 emac_write(EMAC_TXHDP(ch),
1406 emac_virt_to_phys(curr_bd));
1407 txch->queue_active = 1;
1408 }
1409 ++txch->queue_reinit;
1410 } else {
1411 register struct emac_tx_bd __iomem *tail_bd;
1412 register u32 frame_status;
1413
1414 tail_bd = txch->active_queue_tail;
1415 tail_bd->next = curr_bd;
1416 txch->active_queue_tail = curr_bd;
1417 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1418 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd);
1419 frame_status = tail_bd->mode;
1420 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1421 emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd));
1422 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1423 tail_bd->mode = frame_status;
1424 ++txch->end_of_queue_add;
1425 }
1426 }
1427 txch->active_queue_count++;
1428 spin_unlock_irqrestore(&priv->tx_lock, flags);
1429 return 0;
1430}
1431
1432/**
1433 * emac_dev_xmit: EMAC Transmit function
1434 * @skb: SKB pointer
1435 * @ndev: The DaVinci EMAC network adapter
1436 *
1437 * Called by the system to transmit a packet - we queue the packet in
1438 * EMAC hardware transmit queue
1439 *
1440 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1441 */
1442static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1443{
1444 struct device *emac_dev = &ndev->dev;
1445 int ret_code;
1446 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1447 struct emac_netpktobj tx_packet; /* packet object */
1448 struct emac_priv *priv = netdev_priv(ndev);
1449
1450 /* If no link, return */
1451 if (unlikely(!priv->link)) {
1452 if (netif_msg_tx_err(priv) && net_ratelimit())
1453 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1454 return NETDEV_TX_BUSY;
1455 }
1456
1457 /* Build the buffer and packet objects - Since only single fragment is
1458 * supported, need not set length and token in both packet & object.
1459 * Doing so for completeness sake & to show that this needs to be done
1460 * in multifragment case
1461 */
1462 tx_packet.buf_list = &tx_buf;
1463 tx_packet.num_bufs = 1; /* only single fragment supported */
1464 tx_packet.pkt_length = skb->len;
1465 tx_packet.pkt_token = (void *)skb;
1466 tx_buf.length = skb->len;
1467 tx_buf.buf_token = (void *)skb;
1468 tx_buf.data_ptr = skb->data;
1469 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1470 ndev->trans_start = jiffies;
1471 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1472 if (unlikely(ret_code != 0)) {
1473 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1474 if (netif_msg_tx_err(priv) && net_ratelimit())
1475 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1476 " err. Out of TX BD's");
1477 netif_stop_queue(priv->ndev);
1478 }
1479 priv->net_dev_stats.tx_dropped++;
1480 return NETDEV_TX_BUSY;
1481 }
1482
1483 return NETDEV_TX_OK;
1484}
1485
1486/**
1487 * emac_dev_tx_timeout: EMAC Transmit timeout function
1488 * @ndev: The DaVinci EMAC network adapter
1489 *
1490 * Called when system detects that a skb timeout period has expired
1491 * potentially due to a fault in the adapter in not being able to send
1492 * it out on the wire. We teardown the TX channel assuming a hardware
1493 * error and re-initialize the TX channel for hardware operation
1494 *
1495 */
1496static void emac_dev_tx_timeout(struct net_device *ndev)
1497{
1498 struct emac_priv *priv = netdev_priv(ndev);
1499 struct device *emac_dev = &ndev->dev;
1500
1501 if (netif_msg_tx_err(priv))
1502 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1503
1504 priv->net_dev_stats.tx_errors++;
1505 emac_int_disable(priv);
1506 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1507 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1508 emac_init_txch(priv, EMAC_DEF_TX_CH);
1509 emac_write(EMAC_TXHDP(0), 0);
1510 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1511 emac_int_enable(priv);
1512}
1513
1514/**
1515 * emac_net_alloc_rx_buf: Allocate a skb for RX
1516 * @priv: The DaVinci EMAC private adapter structure
1517 * @buf_size: size of SKB data buffer to allocate
1518 * @data_token: data token returned (skb handle for storing in buffer desc)
1519 * @ch: RX channel number
1520 *
1521 * Called during RX channel setup - allocates skb buffer of required size
1522 * and provides the skb handle and allocated buffer data pointer to caller
1523 *
1524 * Returns skb data pointer or 0 on failure to alloc skb
1525 */
1526static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1527 void **data_token, u32 ch)
1528{
1529 struct net_device *ndev = priv->ndev;
1530 struct device *emac_dev = &ndev->dev;
1531 struct sk_buff *p_skb;
1532
1533 p_skb = dev_alloc_skb(buf_size);
1534 if (unlikely(NULL == p_skb)) {
1535 if (netif_msg_rx_err(priv) && net_ratelimit())
1536 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1537 return NULL;
1538 }
1539
1540 /* set device pointer in skb and reserve space for extra bytes */
1541 p_skb->dev = ndev;
1542 skb_reserve(p_skb, NET_IP_ALIGN);
1543 *data_token = (void *) p_skb;
1544 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1545 return p_skb->data;
1546}
1547
1548/**
1549 * emac_init_rxch: RX channel initialization
1550 * @priv: The DaVinci EMAC private adapter structure
1551 * @ch: RX channel number
1552 * @param: mac address for RX channel
1553 *
1554 * Called during device init to setup a RX channel (allocate buffers and
1555 * buffer descriptors, create queue and keep ready for reception
1556 *
1557 * Returns success(0) or mem alloc failures error code
1558 */
1559static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1560{
1561 struct device *emac_dev = &priv->ndev->dev;
1562 u32 cnt, bd_size;
1563 void __iomem *mem;
1564 struct emac_rx_bd __iomem *curr_bd;
1565 struct emac_rxch *rxch = NULL;
1566
1567 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1568 if (NULL == rxch) {
1569 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1570 return -ENOMEM;
1571 }
1572 priv->rxch[ch] = rxch;
1573 rxch->buf_size = priv->rx_buf_size;
1574 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1575 rxch->queue_active = 0;
1576 rxch->teardown_pending = 0;
1577
1578 /* save mac address */
1579 for (cnt = 0; cnt < 6; cnt++)
1580 rxch->mac_addr[cnt] = param[cnt];
1581
1582 /* allocate buffer descriptor pool align every BD on four word
1583 * boundry for future requirements */
1584 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1585 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1586 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1587 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1588 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1589 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1590
1591 /* allocate RX buffer and initialize the BD linked list */
1592 mem = (void __force __iomem *)
1593 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1594 rxch->active_queue_head = NULL;
1595 rxch->active_queue_tail = mem;
1596 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1597 curr_bd = mem + (cnt * bd_size);
1598 /* for future use the last parameter contains the BD ptr */
1599 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1600 rxch->buf_size,
1601 (void __force **)&curr_bd->buf_token,
1602 EMAC_DEF_RX_CH);
1603 if (curr_bd->data_ptr == NULL) {
1604 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1605 "failed for ch %d\n", ch);
1606 kfree(rxch);
1607 return -ENOMEM;
1608 }
1609
1610 /* populate the hardware descriptor */
1611 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head);
1612 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1613 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1614 curr_bd->off_b_len = rxch->buf_size;
1615 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1616
1617 /* write back to hardware memory */
1618 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1619 EMAC_BD_LENGTH_FOR_CACHE);
1620 curr_bd->next = rxch->active_queue_head;
1621 rxch->active_queue_head = curr_bd;
1622 }
1623
1624 /* At this point rxCppi->activeQueueHead points to the first
1625 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1626 points to the last RX BD
1627 */
1628 return 0;
1629}
1630
1631/**
1632 * emac_rxch_teardown: RX channel teardown
1633 * @priv: The DaVinci EMAC private adapter structure
1634 * @ch: RX channel number
1635 *
1636 * Called during device stop to teardown RX channel
1637 *
1638 */
1639static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1640{
1641 struct device *emac_dev = &priv->ndev->dev;
1642 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1643
1644 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1645 EMAC_TEARDOWN_VALUE) {
1646 /* wait till tx teardown complete */
1647 cpu_relax(); /* TODO: check if this helps ... */
1648 --teardown_cnt;
1649 if (0 == teardown_cnt) {
1650 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1651 break;
1652 }
1653 }
1654 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1655}
1656
1657/**
1658 * emac_stop_rxch: Stop RX channel operation
1659 * @priv: The DaVinci EMAC private adapter structure
1660 * @ch: RX channel number
1661 *
1662 * Called during device stop to stop RX channel operation
1663 *
1664 */
1665static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1666{
1667 struct emac_rxch *rxch = priv->rxch[ch];
1668
1669 if (rxch) {
1670 rxch->teardown_pending = 1;
1671 emac_write(EMAC_RXTEARDOWN, ch);
1672 /* wait for teardown complete */
1673 emac_rxch_teardown(priv, ch);
1674 rxch->teardown_pending = 0;
1675 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1676 }
1677}
1678
1679/**
1680 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1681 * @priv: The DaVinci EMAC private adapter structure
1682 * @ch: RX channel number
1683 *
1684 * Called during device stop to clean up RX channel resources
1685 *
1686 */
1687static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1688{
1689 struct emac_rxch *rxch = priv->rxch[ch];
1690 struct emac_rx_bd __iomem *curr_bd;
1691
1692 if (rxch) {
1693 /* free the receive buffers previously allocated */
1694 curr_bd = rxch->active_queue_head;
1695 while (curr_bd) {
1696 if (curr_bd->buf_token) {
1697 dev_kfree_skb_any((struct sk_buff *)\
1698 curr_bd->buf_token);
1699 }
1700 curr_bd = curr_bd->next;
1701 }
1702 if (rxch->bd_mem)
1703 rxch->bd_mem = NULL;
1704 kfree(rxch);
1705 priv->rxch[ch] = NULL;
1706 }
1707}
1708
1709/**
1710 * emac_set_type0addr: Set EMAC Type0 mac address
1711 * @priv: The DaVinci EMAC private adapter structure
1712 * @ch: RX channel number
1713 * @mac_addr: MAC address to set in device
1714 *
1715 * Called internally to set Type0 mac address of the adapter (Device)
1716 *
1717 * Returns success (0) or appropriate error code (none as of now)
1718 */
1719static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1720{
1721 u32 val;
1722 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1723 emac_write(EMAC_MACSRCADDRLO, val);
1724
1725 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1726 (mac_addr[1] << 8) | (mac_addr[0]));
1727 emac_write(EMAC_MACSRCADDRHI, val);
1728 val = emac_read(EMAC_RXUNICASTSET);
1729 val |= BIT(ch);
1730 emac_write(EMAC_RXUNICASTSET, val);
1731 val = emac_read(EMAC_RXUNICASTCLEAR);
1732 val &= ~BIT(ch);
1733 emac_write(EMAC_RXUNICASTCLEAR, val);
1734}
1735
1736/**
1737 * emac_set_type1addr: Set EMAC Type1 mac address
1738 * @priv: The DaVinci EMAC private adapter structure
1739 * @ch: RX channel number
1740 * @mac_addr: MAC address to set in device
1741 *
1742 * Called internally to set Type1 mac address of the adapter (Device)
1743 *
1744 * Returns success (0) or appropriate error code (none as of now)
1745 */
1746static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1747{
1748 u32 val;
1749 emac_write(EMAC_MACINDEX, ch);
1750 val = ((mac_addr[5] << 8) | mac_addr[4]);
1751 emac_write(EMAC_MACADDRLO, val);
1752 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1753 (mac_addr[1] << 8) | (mac_addr[0]));
1754 emac_write(EMAC_MACADDRHI, val);
1755 emac_set_type0addr(priv, ch, mac_addr);
1756}
1757
1758/**
1759 * emac_set_type2addr: Set EMAC Type2 mac address
1760 * @priv: The DaVinci EMAC private adapter structure
1761 * @ch: RX channel number
1762 * @mac_addr: MAC address to set in device
1763 * @index: index into RX address entries
1764 * @match: match parameter for RX address matching logic
1765 *
1766 * Called internally to set Type2 mac address of the adapter (Device)
1767 *
1768 * Returns success (0) or appropriate error code (none as of now)
1769 */
1770static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1771 char *mac_addr, int index, int match)
1772{
1773 u32 val;
1774 emac_write(EMAC_MACINDEX, index);
1775 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1776 (mac_addr[1] << 8) | (mac_addr[0]));
1777 emac_write(EMAC_MACADDRHI, val);
1778 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1779 (match << 19) | BIT(20));
1780 emac_write(EMAC_MACADDRLO, val);
1781 emac_set_type0addr(priv, ch, mac_addr);
1782}
1783
1784/**
1785 * emac_setmac: Set mac address in the adapter (internal function)
1786 * @priv: The DaVinci EMAC private adapter structure
1787 * @ch: RX channel number
1788 * @mac_addr: MAC address to set in device
1789 *
1790 * Called internally to set the mac address of the adapter (Device)
1791 *
1792 * Returns success (0) or appropriate error code (none as of now)
1793 */
1794static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1795{
1796 struct device *emac_dev = &priv->ndev->dev;
1797
1798 if (priv->rx_addr_type == 0) {
1799 emac_set_type0addr(priv, ch, mac_addr);
1800 } else if (priv->rx_addr_type == 1) {
1801 u32 cnt;
1802 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1803 emac_set_type1addr(priv, ch, mac_addr);
1804 } else if (priv->rx_addr_type == 2) {
1805 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1806 emac_set_type0addr(priv, ch, mac_addr);
1807 } else {
1808 if (netif_msg_drv(priv))
1809 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1810 }
1811}
1812
1813/**
1814 * emac_dev_setmac_addr: Set mac address in the adapter
1815 * @ndev: The DaVinci EMAC network adapter
1816 * @addr: MAC address to set in device
1817 *
1818 * Called by the system to set the mac address of the adapter (Device)
1819 *
1820 * Returns success (0) or appropriate error code (none as of now)
1821 */
1822static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1823{
1824 struct emac_priv *priv = netdev_priv(ndev);
1825 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1826 struct device *emac_dev = &priv->ndev->dev;
1827 struct sockaddr *sa = addr;
Anant Golea6286ee2009-05-18 15:19:01 -07001828
Pablo Bitton64c81652009-07-07 19:11:10 -07001829 if (!is_valid_ether_addr(sa->sa_data))
1830 return -EINVAL;
1831
Anant Golea6286ee2009-05-18 15:19:01 -07001832 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1833 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
Anant Golea6286ee2009-05-18 15:19:01 -07001834 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
Pablo Bitton64c81652009-07-07 19:11:10 -07001835
1836 /* If the interface is down - rxch is NULL. */
1837 /* MAC address is configured only after the interface is enabled. */
1838 if (netif_running(ndev)) {
1839 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1840 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1841 }
Anant Golea6286ee2009-05-18 15:19:01 -07001842
1843 if (netif_msg_drv(priv))
Chaithrika U S5c726162009-06-03 21:54:29 -07001844 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1845 priv->mac_addr);
Anant Golea6286ee2009-05-18 15:19:01 -07001846
1847 return 0;
1848}
1849
1850/**
1851 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1852 * @priv: The DaVinci EMAC private adapter structure
1853 * @ch: RX channel number to process buffer descriptors for
1854 * @curr_bd: current buffer descriptor
1855 * @buffer: buffer pointer for descriptor
1856 * @buf_token: buffer token (stores skb information)
1857 *
1858 * Prepares the recycled buffer descriptor and addes it to hardware
1859 * receive queue - if queue empty this descriptor becomes the head
1860 * else addes the descriptor to end of queue
1861 *
1862 */
1863static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1864 struct emac_rx_bd __iomem *curr_bd,
1865 char *buffer, void *buf_token)
1866{
1867 struct emac_rxch *rxch = priv->rxch[ch];
1868
1869 /* populate the hardware descriptor */
1870 curr_bd->h_next = 0;
1871 /* FIXME buff_ptr = dma_map_single(... buffer ...) */
1872 curr_bd->buff_ptr = virt_to_phys(buffer);
1873 curr_bd->off_b_len = rxch->buf_size;
1874 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1875 curr_bd->next = NULL;
1876 curr_bd->data_ptr = buffer;
1877 curr_bd->buf_token = buf_token;
1878
1879 /* write back */
1880 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1881 if (rxch->active_queue_head == NULL) {
1882 rxch->active_queue_head = curr_bd;
1883 rxch->active_queue_tail = curr_bd;
1884 if (0 != rxch->queue_active) {
1885 emac_write(EMAC_RXHDP(ch),
1886 emac_virt_to_phys(rxch->active_queue_head));
1887 rxch->queue_active = 1;
1888 }
1889 } else {
1890 struct emac_rx_bd __iomem *tail_bd;
1891 u32 frame_status;
1892
1893 tail_bd = rxch->active_queue_tail;
1894 rxch->active_queue_tail = curr_bd;
1895 tail_bd->next = curr_bd;
1896 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1897 tail_bd->h_next = emac_virt_to_phys(curr_bd);
1898 frame_status = tail_bd->mode;
1899 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1900 emac_write(EMAC_RXHDP(ch),
1901 emac_virt_to_phys(curr_bd));
1902 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1903 tail_bd->mode = frame_status;
1904 ++rxch->end_of_queue_add;
1905 }
1906 }
1907 ++rxch->recycled_bd;
1908}
1909
1910/**
1911 * emac_net_rx_cb: Prepares packet and sends to upper layer
1912 * @priv: The DaVinci EMAC private adapter structure
1913 * @net_pkt_list: Network packet list (received packets)
1914 *
1915 * Invalidates packet buffer memory and sends the received packet to upper
1916 * layer
1917 *
1918 * Returns success or appropriate error code (none as of now)
1919 */
1920static int emac_net_rx_cb(struct emac_priv *priv,
1921 struct emac_netpktobj *net_pkt_list)
1922{
1923 struct sk_buff *p_skb;
1924 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1925 /* set length of packet */
1926 skb_put(p_skb, net_pkt_list->pkt_length);
1927 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1928 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
Anant Golea6286ee2009-05-18 15:19:01 -07001929 netif_receive_skb(p_skb);
1930 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1931 priv->net_dev_stats.rx_packets++;
1932 return 0;
1933}
1934
1935/**
1936 * emac_rx_bdproc: RX buffer descriptor (packet) processing
1937 * @priv: The DaVinci EMAC private adapter structure
1938 * @ch: RX channel number to process buffer descriptors for
1939 * @budget: number of packets allowed to process
1940 * @pending: indication to caller that packets are pending to process
1941 *
1942 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
1943 * descriptor, sends the receive packet to upper layer, allocates a new SKB
1944 * and recycles the buffer descriptor (requeues it in hardware RX queue).
1945 * Only "budget" number of packets are processed and indication of pending
1946 * packets provided to the caller.
1947 *
1948 * Returns number of packets processed (and indication of pending packets)
1949 */
1950static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1951{
1952 unsigned long flags;
1953 u32 frame_status;
1954 u32 pkts_processed = 0;
1955 char *new_buffer;
1956 struct emac_rx_bd __iomem *curr_bd;
1957 struct emac_rx_bd __iomem *last_bd;
1958 struct emac_netpktobj *curr_pkt, pkt_obj;
1959 struct emac_netbufobj buf_obj;
1960 struct emac_netbufobj *rx_buf_obj;
1961 void *new_buf_token;
1962 struct emac_rxch *rxch = priv->rxch[ch];
1963
1964 if (unlikely(1 == rxch->teardown_pending))
1965 return 0;
1966 ++rxch->proc_count;
1967 spin_lock_irqsave(&priv->rx_lock, flags);
1968 pkt_obj.buf_list = &buf_obj;
1969 curr_pkt = &pkt_obj;
1970 curr_bd = rxch->active_queue_head;
1971 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1972 frame_status = curr_bd->mode;
1973
1974 while ((curr_bd) &&
1975 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1976 (pkts_processed < budget)) {
1977
1978 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1979 &new_buf_token, EMAC_DEF_RX_CH);
1980 if (unlikely(NULL == new_buffer)) {
1981 ++rxch->out_of_rx_buffers;
1982 goto end_emac_rx_bdproc;
1983 }
1984
1985 /* populate received packet data structure */
1986 rx_buf_obj = &curr_pkt->buf_list[0];
1987 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1988 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1989 rx_buf_obj->buf_token = curr_bd->buf_token;
1990 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1991 curr_pkt->num_bufs = 1;
1992 curr_pkt->pkt_length =
1993 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1994 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd));
1995 ++rxch->processed_bd;
1996 last_bd = curr_bd;
1997 curr_bd = last_bd->next;
1998 rxch->active_queue_head = curr_bd;
1999
2000 /* check if end of RX queue ? */
2001 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2002 if (curr_bd) {
2003 ++rxch->mis_queued_packets;
2004 emac_write(EMAC_RXHDP(ch),
2005 emac_virt_to_phys(curr_bd));
2006 } else {
2007 ++rxch->end_of_queue;
2008 rxch->queue_active = 0;
2009 }
2010 }
2011
2012 /* recycle BD */
2013 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2014 new_buf_token);
2015
2016 /* return the packet to the user - BD ptr passed in
2017 * last parameter for potential *future* use */
2018 spin_unlock_irqrestore(&priv->rx_lock, flags);
2019 emac_net_rx_cb(priv, curr_pkt);
2020 spin_lock_irqsave(&priv->rx_lock, flags);
2021 curr_bd = rxch->active_queue_head;
2022 if (curr_bd) {
2023 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2024 frame_status = curr_bd->mode;
2025 }
2026 ++pkts_processed;
2027 }
2028
2029end_emac_rx_bdproc:
2030 spin_unlock_irqrestore(&priv->rx_lock, flags);
2031 return pkts_processed;
2032}
2033
2034/**
2035 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2036 * @priv: The DaVinci EMAC private adapter structure
2037 *
2038 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2039 * for packet reception and enables device interrupts and then NAPI
2040 *
2041 * Returns success (0) or appropriate error code (none right now)
2042 */
2043static int emac_hw_enable(struct emac_priv *priv)
2044{
2045 u32 ch, val, mbp_enable, mac_control;
2046
2047 /* Soft reset */
2048 emac_write(EMAC_SOFTRESET, 1);
2049 while (emac_read(EMAC_SOFTRESET))
2050 cpu_relax();
2051
2052 /* Disable interrupt & Set pacing for more interrupts initially */
2053 emac_int_disable(priv);
2054
2055 /* Full duplex enable bit set when auto negotiation happens */
2056 mac_control =
2057 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2058 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2059 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2060 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2061 emac_write(EMAC_MACCONTROL, mac_control);
2062
2063 mbp_enable =
2064 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2065 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2066 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2067 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2068 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2069 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2070 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2071 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2072 EMAC_RXMBP_PROMCH_SHIFT) |
2073 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2074 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2075 EMAC_RXMBP_BROADCH_SHIFT) |
2076 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2077 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2078 EMAC_RXMBP_MULTICH_SHIFT));
2079 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2080 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2081 EMAC_RX_MAX_LEN_MASK));
2082 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2083 EMAC_RX_BUFFER_OFFSET_MASK));
2084 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2085 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2086 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2087
2088 val = emac_read(EMAC_TXCONTROL);
2089 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2090 emac_write(EMAC_TXCONTROL, val);
2091 val = emac_read(EMAC_RXCONTROL);
2092 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2093 emac_write(EMAC_RXCONTROL, val);
2094 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2095
2096 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2097 emac_write(EMAC_TXHDP(ch), 0);
2098 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2099 }
2100 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2101 struct emac_rxch *rxch = priv->rxch[ch];
2102 emac_setmac(priv, ch, rxch->mac_addr);
2103 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2104 rxch->queue_active = 1;
2105 emac_write(EMAC_RXHDP(ch),
2106 emac_virt_to_phys(rxch->active_queue_head));
2107 }
2108
2109 /* Enable MII */
2110 val = emac_read(EMAC_MACCONTROL);
2111 val |= (EMAC_MACCONTROL_MIIEN);
2112 emac_write(EMAC_MACCONTROL, val);
2113
2114 /* Enable NAPI and interrupts */
2115 napi_enable(&priv->napi);
2116 emac_int_enable(priv);
2117 return 0;
2118
2119}
2120
2121/**
2122 * emac_poll: EMAC NAPI Poll function
2123 * @ndev: The DaVinci EMAC network adapter
2124 * @budget: Number of receive packets to process (as told by NAPI layer)
2125 *
2126 * NAPI Poll function implemented to process packets as per budget. We check
2127 * the type of interrupt on the device and accordingly call the TX or RX
2128 * packet processing functions. We follow the budget for RX processing and
2129 * also put a cap on number of TX pkts processed through config param. The
2130 * NAPI schedule function is called if more packets pending.
2131 *
2132 * Returns number of packets received (in most cases; else TX pkts - rarely)
2133 */
2134static int emac_poll(struct napi_struct *napi, int budget)
2135{
2136 unsigned int mask;
2137 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2138 struct net_device *ndev = priv->ndev;
2139 struct device *emac_dev = &ndev->dev;
2140 u32 status = 0;
2141 u32 num_pkts = 0;
2142
2143 if (!netif_running(ndev))
2144 return 0;
2145
2146 /* Check interrupt vectors and call packet processing */
2147 status = emac_read(EMAC_MACINVECTOR);
2148
2149 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2150
2151 if (priv->version == EMAC_VERSION_2)
2152 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2153
2154 if (status & mask) {
2155 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2156 EMAC_DEF_TX_MAX_SERVICE);
2157 } /* TX processing */
2158
2159 if (num_pkts)
2160 return budget;
2161
2162 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2163
2164 if (priv->version == EMAC_VERSION_2)
2165 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2166
2167 if (status & mask) {
2168 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2169 } /* RX processing */
2170
2171 if (num_pkts < budget) {
2172 napi_complete(napi);
2173 emac_int_enable(priv);
2174 }
2175
Sriram43c2ed82009-09-24 19:15:18 +00002176 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2177 if (priv->version == EMAC_VERSION_2)
2178 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2179
2180 if (unlikely(status & mask)) {
Anant Golea6286ee2009-05-18 15:19:01 -07002181 u32 ch, cause;
2182 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2183 netif_stop_queue(ndev);
2184 napi_disable(&priv->napi);
2185
2186 status = emac_read(EMAC_MACSTATUS);
2187 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2188 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2189 if (cause) {
2190 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2191 EMAC_MACSTATUS_TXERRCH_SHIFT);
2192 if (net_ratelimit()) {
2193 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2194 &emac_txhost_errcodes[cause][0], ch);
2195 }
2196 }
2197 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2198 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2199 if (cause) {
2200 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2201 EMAC_MACSTATUS_RXERRCH_SHIFT);
2202 if (netif_msg_hw(priv) && net_ratelimit())
2203 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2204 &emac_rxhost_errcodes[cause][0], ch);
2205 }
2206 } /* Host error processing */
2207
2208 return num_pkts;
2209}
2210
2211#ifdef CONFIG_NET_POLL_CONTROLLER
2212/**
2213 * emac_poll_controller: EMAC Poll controller function
2214 * @ndev: The DaVinci EMAC network adapter
2215 *
2216 * Polled functionality used by netconsole and others in non interrupt mode
2217 *
2218 */
2219void emac_poll_controller(struct net_device *ndev)
2220{
2221 struct emac_priv *priv = netdev_priv(ndev);
2222
2223 emac_int_disable(priv);
2224 emac_irq(ndev->irq, priv);
2225 emac_int_enable(priv);
2226}
2227#endif
2228
2229/* PHY/MII bus related */
2230
2231/* Wait until mdio is ready for next command */
2232#define MDIO_WAIT_FOR_USER_ACCESS\
2233 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2234 MDIO_USERACCESS_GO) != 0)
2235
2236static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2237{
2238 unsigned int phy_data = 0;
2239 unsigned int phy_control;
2240
2241 /* Wait until mdio is ready for next command */
2242 MDIO_WAIT_FOR_USER_ACCESS;
2243
2244 phy_control = (MDIO_USERACCESS_GO |
2245 MDIO_USERACCESS_READ |
2246 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2247 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2248 (phy_data & MDIO_USERACCESS_DATA));
2249 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2250
2251 /* Wait until mdio is ready for next command */
2252 MDIO_WAIT_FOR_USER_ACCESS;
2253
2254 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2255
2256}
2257
2258static int emac_mii_write(struct mii_bus *bus, int phy_id,
2259 int phy_reg, u16 phy_data)
2260{
2261
2262 unsigned int control;
2263
2264 /* until mdio is ready for next command */
2265 MDIO_WAIT_FOR_USER_ACCESS;
2266
2267 control = (MDIO_USERACCESS_GO |
2268 MDIO_USERACCESS_WRITE |
2269 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2270 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2271 (phy_data & MDIO_USERACCESS_DATA));
2272 emac_mdio_write(MDIO_USERACCESS(0), control);
2273
2274 return 0;
2275}
2276
2277static int emac_mii_reset(struct mii_bus *bus)
2278{
2279 unsigned int clk_div;
2280 int mdio_bus_freq = emac_bus_frequency;
2281
2282 if (mdio_max_freq & mdio_bus_freq)
2283 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2284 else
2285 clk_div = 0xFF;
2286
2287 clk_div &= MDIO_CONTROL_CLKDIV;
2288
2289 /* Set enable and clock divider in MDIOControl */
2290 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2291
2292 return 0;
2293
2294}
2295
2296static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2297
2298/* emac_driver: EMAC MII bus structure */
2299
2300static struct mii_bus *emac_mii;
2301
2302static void emac_adjust_link(struct net_device *ndev)
2303{
2304 struct emac_priv *priv = netdev_priv(ndev);
2305 struct phy_device *phydev = priv->phydev;
2306 unsigned long flags;
2307 int new_state = 0;
2308
2309 spin_lock_irqsave(&priv->lock, flags);
2310
2311 if (phydev->link) {
2312 /* check the mode of operation - full/half duplex */
2313 if (phydev->duplex != priv->duplex) {
2314 new_state = 1;
2315 priv->duplex = phydev->duplex;
2316 }
2317 if (phydev->speed != priv->speed) {
2318 new_state = 1;
2319 priv->speed = phydev->speed;
2320 }
2321 if (!priv->link) {
2322 new_state = 1;
2323 priv->link = 1;
2324 }
2325
2326 } else if (priv->link) {
2327 new_state = 1;
2328 priv->link = 0;
2329 priv->speed = 0;
2330 priv->duplex = ~0;
2331 }
2332 if (new_state) {
2333 emac_update_phystatus(priv);
2334 phy_print_status(priv->phydev);
2335 }
2336
2337 spin_unlock_irqrestore(&priv->lock, flags);
2338}
2339
2340/*************************************************************************
2341 * Linux Driver Model
2342 *************************************************************************/
2343
2344/**
2345 * emac_devioctl: EMAC adapter ioctl
2346 * @ndev: The DaVinci EMAC network adapter
2347 * @ifrq: request parameter
2348 * @cmd: command parameter
2349 *
2350 * EMAC driver ioctl function
2351 *
2352 * Returns success(0) or appropriate error code
2353 */
2354static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2355{
2356 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2357
2358 if (!(netif_running(ndev)))
2359 return -EINVAL;
2360
2361 /* TODO: Add phy read and write and private statistics get feature */
2362
2363 return -EOPNOTSUPP;
2364}
2365
2366/**
2367 * emac_dev_open: EMAC device open
2368 * @ndev: The DaVinci EMAC network adapter
2369 *
2370 * Called when system wants to start the interface. We init TX/RX channels
2371 * and enable the hardware for packet reception/transmission and start the
2372 * network queue.
2373 *
2374 * Returns 0 for a successful open, or appropriate error code
2375 */
2376static int emac_dev_open(struct net_device *ndev)
2377{
2378 struct device *emac_dev = &ndev->dev;
2379 u32 rc, cnt, ch;
2380 int phy_addr;
2381 struct resource *res;
2382 int q, m;
2383 int i = 0;
2384 int k = 0;
2385 struct emac_priv *priv = netdev_priv(ndev);
2386
2387 netif_carrier_off(ndev);
2388 for (cnt = 0; cnt <= ETH_ALEN; cnt++)
2389 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2390
2391 /* Configuration items */
2392 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2393
2394 /* Clear basic hardware */
2395 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2396 emac_write(EMAC_TXHDP(ch), 0);
2397 emac_write(EMAC_RXHDP(ch), 0);
2398 emac_write(EMAC_RXHDP(ch), 0);
2399 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2400 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2401 }
2402 priv->mac_hash1 = 0;
2403 priv->mac_hash2 = 0;
2404 emac_write(EMAC_MACHASH1, 0);
2405 emac_write(EMAC_MACHASH2, 0);
2406
2407 /* multi ch not supported - open 1 TX, 1RX ch by default */
2408 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2409 if (0 != rc) {
2410 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2411 return rc;
2412 }
2413 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2414 if (0 != rc) {
2415 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2416 return rc;
2417 }
2418
2419 /* Request IRQ */
2420
2421 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2422 for (i = res->start; i <= res->end; i++) {
2423 if (request_irq(i, emac_irq, IRQF_DISABLED,
2424 ndev->name, ndev))
2425 goto rollback;
2426 }
2427 k++;
2428 }
2429
2430 /* Start/Enable EMAC hardware */
2431 emac_hw_enable(priv);
2432
2433 /* find the first phy */
2434 priv->phydev = NULL;
2435 if (priv->phy_mask) {
2436 emac_mii_reset(priv->mii_bus);
2437 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2438 if (priv->mii_bus->phy_map[phy_addr]) {
2439 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2440 break;
2441 }
2442 }
2443
2444 if (!priv->phydev) {
2445 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2446 return -1;
2447 }
2448
2449 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2450 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2451
2452 if (IS_ERR(priv->phydev)) {
2453 printk(KERN_ERR "%s: Could not attach to PHY\n",
2454 ndev->name);
2455 return PTR_ERR(priv->phydev);
2456 }
2457
2458 priv->link = 0;
2459 priv->speed = 0;
2460 priv->duplex = ~0;
2461
2462 printk(KERN_INFO "%s: attached PHY driver [%s] "
2463 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2464 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2465 priv->phydev->phy_id);
2466 } else{
2467 /* No PHY , fix the link, speed and duplex settings */
2468 priv->link = 1;
2469 priv->speed = SPEED_100;
2470 priv->duplex = DUPLEX_FULL;
2471 emac_update_phystatus(priv);
2472 }
2473
2474 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2475 emac_dump_regs(priv);
2476
2477 if (netif_msg_drv(priv))
2478 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2479
2480 if (priv->phy_mask)
2481 phy_start(priv->phydev);
2482
2483 return 0;
2484
2485rollback:
2486
2487 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2488
2489 for (q = k; k >= 0; k--) {
2490 for (m = i; m >= res->start; m--)
2491 free_irq(m, ndev);
2492 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2493 m = res->end;
2494 }
2495 return -EBUSY;
2496}
2497
2498/**
2499 * emac_dev_stop: EMAC device stop
2500 * @ndev: The DaVinci EMAC network adapter
2501 *
2502 * Called when system wants to stop or down the interface. We stop the network
2503 * queue, disable interrupts and cleanup TX/RX channels.
2504 *
2505 * We return the statistics in net_device_stats structure pulled from emac
2506 */
2507static int emac_dev_stop(struct net_device *ndev)
2508{
2509 struct resource *res;
2510 int i = 0;
2511 int irq_num;
2512 struct emac_priv *priv = netdev_priv(ndev);
2513 struct device *emac_dev = &ndev->dev;
2514
2515 /* inform the upper layers. */
2516 netif_stop_queue(ndev);
2517 napi_disable(&priv->napi);
2518
2519 netif_carrier_off(ndev);
2520 emac_int_disable(priv);
2521 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2522 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2523 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2524 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2525 emac_write(EMAC_SOFTRESET, 1);
2526
2527 if (priv->phydev)
2528 phy_disconnect(priv->phydev);
2529
2530 /* Free IRQ */
2531 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2532 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2533 free_irq(irq_num, priv->ndev);
2534 i++;
2535 }
2536
2537 if (netif_msg_drv(priv))
2538 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2539
2540 return 0;
2541}
2542
2543/**
2544 * emac_dev_getnetstats: EMAC get statistics function
2545 * @ndev: The DaVinci EMAC network adapter
2546 *
2547 * Called when system wants to get statistics from the device.
2548 *
2549 * We return the statistics in net_device_stats structure pulled from emac
2550 */
2551static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2552{
2553 struct emac_priv *priv = netdev_priv(ndev);
Sriram0fe74632009-10-07 02:44:30 +00002554 u32 mac_control;
2555 u32 stats_clear_mask;
Anant Golea6286ee2009-05-18 15:19:01 -07002556
2557 /* update emac hardware stats and reset the registers*/
2558
Sriram0fe74632009-10-07 02:44:30 +00002559 mac_control = emac_read(EMAC_MACCONTROL);
2560
2561 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2562 stats_clear_mask = EMAC_STATS_CLR_MASK;
2563 else
2564 stats_clear_mask = 0;
2565
Anant Golea6286ee2009-05-18 15:19:01 -07002566 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
Sriram0fe74632009-10-07 02:44:30 +00002567 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002568
2569 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2570 emac_read(EMAC_TXSINGLECOLL) +
2571 emac_read(EMAC_TXMULTICOLL));
Sriram0fe74632009-10-07 02:44:30 +00002572 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2573 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2574 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002575
2576 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2577 emac_read(EMAC_RXJABBER) +
2578 emac_read(EMAC_RXUNDERSIZED));
Sriram0fe74632009-10-07 02:44:30 +00002579 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2580 emac_write(EMAC_RXJABBER, stats_clear_mask);
2581 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002582
2583 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2584 emac_read(EMAC_RXMOFOVERRUNS));
Sriram0fe74632009-10-07 02:44:30 +00002585 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2586 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002587
2588 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
Sriram0fe74632009-10-07 02:44:30 +00002589 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002590
2591 priv->net_dev_stats.tx_carrier_errors +=
2592 emac_read(EMAC_TXCARRIERSENSE);
Sriram0fe74632009-10-07 02:44:30 +00002593 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002594
2595 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
Sriram0fe74632009-10-07 02:44:30 +00002596 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
Anant Golea6286ee2009-05-18 15:19:01 -07002597
2598 return &priv->net_dev_stats;
2599}
2600
2601static const struct net_device_ops emac_netdev_ops = {
2602 .ndo_open = emac_dev_open,
2603 .ndo_stop = emac_dev_stop,
2604 .ndo_start_xmit = emac_dev_xmit,
2605 .ndo_set_multicast_list = emac_dev_mcast_set,
2606 .ndo_set_mac_address = emac_dev_setmac_addr,
2607 .ndo_do_ioctl = emac_devioctl,
2608 .ndo_tx_timeout = emac_dev_tx_timeout,
2609 .ndo_get_stats = emac_dev_getnetstats,
2610#ifdef CONFIG_NET_POLL_CONTROLLER
2611 .ndo_poll_controller = emac_poll_controller,
2612#endif
2613};
2614
2615/**
2616 * davinci_emac_probe: EMAC device probe
2617 * @pdev: The DaVinci EMAC device that we are removing
2618 *
2619 * Called when probing for emac devicesr. We get details of instances and
2620 * resource information from platform init and register a network device
2621 * and allocate resources necessary for driver to perform
2622 */
2623static int __devinit davinci_emac_probe(struct platform_device *pdev)
2624{
2625 int rc = 0;
2626 struct resource *res;
2627 struct net_device *ndev;
2628 struct emac_priv *priv;
2629 unsigned long size;
2630 struct emac_platform_data *pdata;
2631 struct device *emac_dev;
2632
2633 /* obtain emac clock from kernel */
2634 emac_clk = clk_get(&pdev->dev, NULL);
2635 if (IS_ERR(emac_clk)) {
2636 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2637 return -EBUSY;
2638 }
2639 emac_bus_frequency = clk_get_rate(emac_clk);
2640 /* TODO: Probe PHY here if possible */
2641
2642 ndev = alloc_etherdev(sizeof(struct emac_priv));
2643 if (!ndev) {
2644 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2645 clk_put(emac_clk);
2646 return -ENOMEM;
2647 }
2648
2649 platform_set_drvdata(pdev, ndev);
2650 priv = netdev_priv(ndev);
2651 priv->pdev = pdev;
2652 priv->ndev = ndev;
2653 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2654
2655 spin_lock_init(&priv->tx_lock);
2656 spin_lock_init(&priv->rx_lock);
2657 spin_lock_init(&priv->lock);
2658
2659 pdata = pdev->dev.platform_data;
2660 if (!pdata) {
2661 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2662 return -ENODEV;
2663 }
2664
2665 /* MAC addr and PHY mask , RMII enable info from platform_data */
2666 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2667 priv->phy_mask = pdata->phy_mask;
2668 priv->rmii_en = pdata->rmii_en;
2669 priv->version = pdata->version;
2670 emac_dev = &ndev->dev;
2671 /* Get EMAC platform data */
2672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2673 if (!res) {
2674 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2675 rc = -ENOENT;
2676 goto probe_quit;
2677 }
2678
2679 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2680 size = res->end - res->start + 1;
2681 if (!request_mem_region(res->start, size, ndev->name)) {
2682 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \
2683 for regs\n");
2684 rc = -ENXIO;
2685 goto probe_quit;
2686 }
2687
2688 priv->remap_addr = ioremap(res->start, size);
2689 if (!priv->remap_addr) {
2690 dev_err(emac_dev, "Unable to map IO\n");
2691 rc = -ENOMEM;
2692 release_mem_region(res->start, size);
2693 goto probe_quit;
2694 }
2695 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2696 ndev->base_addr = (unsigned long)priv->remap_addr;
2697
2698 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2699 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2700 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2701
2702 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2703 if (!res) {
2704 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2705 rc = -ENOENT;
2706 goto no_irq_res;
2707 }
2708 ndev->irq = res->start;
2709
2710 if (!is_valid_ether_addr(priv->mac_addr)) {
Anant Golea6286ee2009-05-18 15:19:01 -07002711 /* Use random MAC if none passed */
2712 random_ether_addr(priv->mac_addr);
Chaithrika U S5c726162009-06-03 21:54:29 -07002713 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2714 __func__, priv->mac_addr);
Anant Golea6286ee2009-05-18 15:19:01 -07002715 }
2716
2717 ndev->netdev_ops = &emac_netdev_ops;
2718 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2719 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2720
2721 /* register the network device */
2722 SET_NETDEV_DEV(ndev, &pdev->dev);
2723 rc = register_netdev(ndev);
2724 if (rc) {
2725 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2726 rc = -ENODEV;
2727 goto netdev_reg_err;
2728 }
2729
2730 clk_enable(emac_clk);
2731
2732 /* MII/Phy intialisation, mdio bus registration */
2733 emac_mii = mdiobus_alloc();
2734 if (emac_mii == NULL) {
2735 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2736 rc = -ENOMEM;
2737 goto mdio_alloc_err;
2738 }
2739
2740 priv->mii_bus = emac_mii;
2741 emac_mii->name = "emac-mii",
2742 emac_mii->read = emac_mii_read,
2743 emac_mii->write = emac_mii_write,
2744 emac_mii->reset = emac_mii_reset,
2745 emac_mii->irq = mii_irqs,
2746 emac_mii->phy_mask = ~(priv->phy_mask);
2747 emac_mii->parent = &pdev->dev;
2748 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2749 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2750 mdio_max_freq = pdata->mdio_max_freq;
2751 emac_mii->reset(emac_mii);
2752
2753 /* Register the MII bus */
2754 rc = mdiobus_register(emac_mii);
2755 if (rc)
2756 goto mdiobus_quit;
2757
2758 if (netif_msg_probe(priv)) {
2759 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2760 "(regs: %p, irq: %d)\n",
2761 (void *)priv->emac_base_phys, ndev->irq);
2762 }
2763 return 0;
2764
2765mdiobus_quit:
2766 mdiobus_free(emac_mii);
2767
2768netdev_reg_err:
2769mdio_alloc_err:
2770no_irq_res:
2771 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2772 release_mem_region(res->start, res->end - res->start + 1);
2773 iounmap(priv->remap_addr);
2774
2775probe_quit:
2776 clk_put(emac_clk);
2777 free_netdev(ndev);
2778 return rc;
2779}
2780
2781/**
2782 * davinci_emac_remove: EMAC device remove
2783 * @pdev: The DaVinci EMAC device that we are removing
2784 *
2785 * Called when removing the device driver. We disable clock usage and release
2786 * the resources taken up by the driver and unregister network device
2787 */
2788static int __devexit davinci_emac_remove(struct platform_device *pdev)
2789{
2790 struct resource *res;
2791 struct net_device *ndev = platform_get_drvdata(pdev);
2792 struct emac_priv *priv = netdev_priv(ndev);
2793
2794 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2795
Anant Golea6286ee2009-05-18 15:19:01 -07002796 platform_set_drvdata(pdev, NULL);
2797 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2798 mdiobus_unregister(priv->mii_bus);
2799 mdiobus_free(priv->mii_bus);
2800
2801 release_mem_region(res->start, res->end - res->start + 1);
2802
2803 unregister_netdev(ndev);
2804 free_netdev(ndev);
2805 iounmap(priv->remap_addr);
2806
2807 clk_disable(emac_clk);
2808 clk_put(emac_clk);
2809
2810 return 0;
2811}
2812
2813/**
2814 * davinci_emac_driver: EMAC platform driver structure
2815 *
2816 * We implement only probe and remove functions - suspend/resume and
2817 * others not supported by this module
2818 */
2819static struct platform_driver davinci_emac_driver = {
2820 .driver = {
2821 .name = "davinci_emac",
2822 .owner = THIS_MODULE,
2823 },
2824 .probe = davinci_emac_probe,
2825 .remove = __devexit_p(davinci_emac_remove),
2826};
2827
2828/**
2829 * davinci_emac_init: EMAC driver module init
2830 *
2831 * Called when initializing the driver. We register the driver with
2832 * the platform.
2833 */
2834static int __init davinci_emac_init(void)
2835{
2836 return platform_driver_register(&davinci_emac_driver);
2837}
Rajashekhara, Sudhakar2db95172009-08-19 10:39:55 +00002838late_initcall(davinci_emac_init);
Anant Golea6286ee2009-05-18 15:19:01 -07002839
2840/**
2841 * davinci_emac_exit: EMAC driver module exit
2842 *
2843 * Called when exiting the driver completely. We unregister the driver with
2844 * the platform and exit
2845 */
2846static void __exit davinci_emac_exit(void)
2847{
2848 platform_driver_unregister(&davinci_emac_driver);
2849}
2850module_exit(davinci_emac_exit);
2851
2852MODULE_LICENSE("GPL");
2853MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2854MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2855MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");