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gerrit-public.fairphone.software / kernel / msm-4.9 / e1260beb70c0b679610b419f3e54b893374a5a47 / . / drivers / pci / host / pcie-designware.h
blob: a567ea288ee2f9fa7e12483e5feb64853029990b [file] [log] [blame]
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]1/*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
Seungwon Jeon18edf452013-10-09 09:12:21 -0600[diff] [blame]14#ifndef _PCIE_DESIGNWARE_H
15#define _PCIE_DESIGNWARE_H
16
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]17/*
18 * Maximum number of MSI IRQs can be 256 per controller. But keep
19 * it 32 as of now. Probably we will never need more than 32. If needed,
20 * then increment it in multiple of 32.
21 */
22#define MAX_MSI_IRQS 32
23#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
24
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]25struct pcie_port {
26 struct device *dev;
27 u8 root_bus_nr;
28 void __iomem *dbi_base;
29 u64 cfg0_base;
30 void __iomem *va_cfg0_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]31 u32 cfg0_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]32 u64 cfg1_base;
33 void __iomem *va_cfg1_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]34 u32 cfg1_size;
Zhou Wang0021d222015-10-29 19:57:06 -0500[diff] [blame]35 resource_size_t io_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]36 phys_addr_t io_bus_addr;
37 u32 io_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]38 u64 mem_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]39 phys_addr_t mem_bus_addr;
40 u32 mem_size;
Zhou Wang0021d222015-10-29 19:57:06 -0500[diff] [blame]41 struct resource *cfg;
42 struct resource *io;
43 struct resource *mem;
44 struct resource *busn;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]45 int irq;
46 u32 lanes;
Pratyush Anandfe48cb82016-07-04 21:44:42 +0530[diff] [blame]47 u32 num_viewport;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]48 struct pcie_host_ops *ops;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]49 int msi_irq;
Pratyush Anand904d0e72013-10-09 21:32:12 +0900[diff] [blame]50 struct irq_domain *irq_domain;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]51 unsigned long msi_data;
Joao Pintoa0601a42016-08-10 11:02:39 +0100[diff] [blame]52 u8 iatu_unroll_enabled;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]53 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]54};
55
56struct pcie_host_ops {
Bjorn Helgaas7e00dfd2016-10-06 13:25:46 -0500[diff] [blame]57 u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
Bjorn Helgaasad880212016-10-06 13:25:46 -0500[diff] [blame]58 void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]59 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
60 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
Murali Karicheria1c0ae92014-07-21 12:58:41 -0400[diff] [blame]61 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
62 unsigned int devfn, int where, int size, u32 *val);
63 int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
64 unsigned int devfn, int where, int size, u32 val);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]65 int (*link_up)(struct pcie_port *pp);
66 void (*host_init)(struct pcie_port *pp);
Murali Karicheri2f37c5a2014-07-21 12:58:42 -0400[diff] [blame]67 void (*msi_set_irq)(struct pcie_port *pp, int irq);
68 void (*msi_clear_irq)(struct pcie_port *pp, int irq);
Lucas Stach98a97e62015-09-18 13:58:35 -0500[diff] [blame]69 phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
Minghuan Lian24832b42014-09-23 22:28:59 +0800[diff] [blame]70 u32 (*get_msi_data)(struct pcie_port *pp, int pos);
Murali Karicherib14a3d12014-07-23 14:54:51 -0400[diff] [blame]71 void (*scan_bus)(struct pcie_port *pp);
Yijing Wangc2791b82014-11-11 17:45:45 -0700[diff] [blame]72 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]73};
74
Bjorn Helgaas8ad75012016-10-06 13:25:47 -0500[diff] [blame]75u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg);
76void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val);
Gabriele Paoloni4c458522015-10-08 14:27:48 -0500[diff] [blame]77int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
78int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
Lucas Stach7f4f16e2014-03-28 17:52:58 +0100[diff] [blame]79irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]80void dw_pcie_msi_init(struct pcie_port *pp);
Joao Pinto886bc5c2016-03-10 14:44:35 -0600[diff] [blame]81int dw_pcie_wait_for_link(struct pcie_port *pp);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]82int dw_pcie_link_up(struct pcie_port *pp);
83void dw_pcie_setup_rc(struct pcie_port *pp);
84int dw_pcie_host_init(struct pcie_port *pp);
Seungwon Jeon18edf452013-10-09 09:12:21 -0600[diff] [blame]85
86#endif /* _PCIE_DESIGNWARE_H */