Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Agere Systems Inc. |
| 3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs |
| 4 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 5 | * Copyright * 2005 Agere Systems Inc. |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 6 | * All rights reserved. |
| 7 | * http://www.agere.com |
| 8 | * |
| 9 | *------------------------------------------------------------------------------ |
| 10 | * |
| 11 | * et1310_phy.c - Routines for configuring and accessing the PHY |
| 12 | * |
| 13 | *------------------------------------------------------------------------------ |
| 14 | * |
| 15 | * SOFTWARE LICENSE |
| 16 | * |
| 17 | * This software is provided subject to the following terms and conditions, |
| 18 | * which you should read carefully before using the software. Using this |
| 19 | * software indicates your acceptance of these terms and conditions. If you do |
| 20 | * not agree with these terms and conditions, do not use the software. |
| 21 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 22 | * Copyright * 2005 Agere Systems Inc. |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 23 | * All rights reserved. |
| 24 | * |
| 25 | * Redistribution and use in source or binary forms, with or without |
| 26 | * modifications, are permitted provided that the following conditions are met: |
| 27 | * |
| 28 | * . Redistributions of source code must retain the above copyright notice, this |
| 29 | * list of conditions and the following Disclaimer as comments in the code as |
| 30 | * well as in the documentation and/or other materials provided with the |
| 31 | * distribution. |
| 32 | * |
| 33 | * . Redistributions in binary form must reproduce the above copyright notice, |
| 34 | * this list of conditions and the following Disclaimer in the documentation |
| 35 | * and/or other materials provided with the distribution. |
| 36 | * |
| 37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors |
| 38 | * may be used to endorse or promote products derived from this software |
| 39 | * without specific prior written permission. |
| 40 | * |
| 41 | * Disclaimer |
| 42 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
| 45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY |
| 46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN |
| 47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY |
| 48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT |
| 52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 54 | * DAMAGE. |
| 55 | * |
| 56 | */ |
| 57 | |
| 58 | #include "et131x_version.h" |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 59 | #include "et131x_defs.h" |
| 60 | |
| 61 | #include <linux/pci.h> |
| 62 | #include <linux/init.h> |
| 63 | #include <linux/module.h> |
| 64 | #include <linux/types.h> |
| 65 | #include <linux/kernel.h> |
| 66 | |
| 67 | #include <linux/sched.h> |
| 68 | #include <linux/ptrace.h> |
| 69 | #include <linux/slab.h> |
| 70 | #include <linux/ctype.h> |
| 71 | #include <linux/string.h> |
| 72 | #include <linux/timer.h> |
| 73 | #include <linux/interrupt.h> |
| 74 | #include <linux/in.h> |
| 75 | #include <linux/delay.h> |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 76 | #include <linux/io.h> |
| 77 | #include <linux/bitops.h> |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 78 | #include <asm/system.h> |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 79 | |
| 80 | #include <linux/netdevice.h> |
| 81 | #include <linux/etherdevice.h> |
| 82 | #include <linux/skbuff.h> |
| 83 | #include <linux/if_arp.h> |
| 84 | #include <linux/ioport.h> |
| 85 | #include <linux/random.h> |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 86 | |
| 87 | #include "et1310_phy.h" |
| 88 | #include "et1310_pm.h" |
| 89 | #include "et1310_jagcore.h" |
| 90 | |
| 91 | #include "et131x_adapter.h" |
| 92 | #include "et131x_netdev.h" |
| 93 | #include "et131x_initpci.h" |
| 94 | |
| 95 | #include "et1310_address_map.h" |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 96 | #include "et1310_tx.h" |
| 97 | #include "et1310_rx.h" |
| 98 | #include "et1310_mac.h" |
| 99 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 100 | /* Prototypes for functions with local scope */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 101 | static void et131x_xcvr_init(struct et131x_adapter *etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 102 | |
| 103 | /** |
| 104 | * PhyMiRead - Read from the PHY through the MII Interface on the MAC |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 105 | * @etdev: pointer to our private adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 106 | * @xcvrAddr: the address of the transciever |
| 107 | * @xcvrReg: the register to read |
| 108 | * @value: pointer to a 16-bit value in which the value will be stored |
| 109 | * |
| 110 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 111 | */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 112 | int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr, |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 113 | u8 xcvrReg, u16 *value) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 114 | { |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 115 | struct _MAC_t __iomem *mac = &etdev->regs->mac; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 116 | int status = 0; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 117 | u32 delay; |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 118 | u32 miiAddr; |
| 119 | u32 miiCmd; |
| 120 | u32 miiIndicator; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 121 | |
| 122 | /* Save a local copy of the registers we are dealing with so we can |
| 123 | * set them back |
| 124 | */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 125 | miiAddr = readl(&mac->mii_mgmt_addr); |
| 126 | miiCmd = readl(&mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 127 | |
| 128 | /* Stop the current operation */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 129 | writel(0, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 130 | |
| 131 | /* Set up the register we need to read from on the correct PHY */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 132 | writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 133 | |
| 134 | /* Kick the read cycle off */ |
| 135 | delay = 0; |
| 136 | |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 137 | writel(0x1, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 138 | |
| 139 | do { |
| 140 | udelay(50); |
| 141 | delay++; |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 142 | miiIndicator = readl(&mac->mii_mgmt_indicator); |
| 143 | } while ((miiIndicator & MGMT_WAIT) && delay < 50); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 144 | |
| 145 | /* If we hit the max delay, we could not read the register */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 146 | if (delay == 50) { |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 147 | dev_warn(&etdev->pdev->dev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 148 | "xcvrReg 0x%08x could not be read\n", xcvrReg); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 149 | dev_warn(&etdev->pdev->dev, "status is 0x%08x\n", |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 150 | miiIndicator); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 151 | |
| 152 | status = -EIO; |
| 153 | } |
| 154 | |
| 155 | /* If we hit here we were able to read the register and we need to |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 156 | * return the value to the caller */ |
| 157 | *value = readl(&mac->mii_mgmt_stat) & 0xFFFF; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 158 | |
| 159 | /* Stop the read operation */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 160 | writel(0, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 161 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 162 | /* set the registers we touched back to the state at which we entered |
| 163 | * this function |
| 164 | */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 165 | writel(miiAddr, &mac->mii_mgmt_addr); |
| 166 | writel(miiCmd, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 167 | |
| 168 | return status; |
| 169 | } |
| 170 | |
| 171 | /** |
| 172 | * MiWrite - Write to a PHY register through the MII interface of the MAC |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 173 | * @etdev: pointer to our private adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 174 | * @xcvrReg: the register to read |
| 175 | * @value: 16-bit value to write |
| 176 | * |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 177 | * FIXME: one caller in netdev still |
| 178 | * |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 179 | * Return 0 on success, errno on failure (as defined in errno.h) |
| 180 | */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 181 | int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 182 | { |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 183 | struct _MAC_t __iomem *mac = &etdev->regs->mac; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 184 | int status = 0; |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 185 | u8 xcvrAddr = etdev->Stats.xcvr_addr; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 186 | u32 delay; |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 187 | u32 miiAddr; |
| 188 | u32 miiCmd; |
| 189 | u32 miiIndicator; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 190 | |
| 191 | /* Save a local copy of the registers we are dealing with so we can |
| 192 | * set them back |
| 193 | */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 194 | miiAddr = readl(&mac->mii_mgmt_addr); |
| 195 | miiCmd = readl(&mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 196 | |
| 197 | /* Stop the current operation */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 198 | writel(0, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 199 | |
| 200 | /* Set up the register we need to write to on the correct PHY */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 201 | writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 202 | |
| 203 | /* Add the value to write to the registers to the mac */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 204 | writel(value, &mac->mii_mgmt_ctrl); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 205 | delay = 0; |
| 206 | |
| 207 | do { |
| 208 | udelay(50); |
| 209 | delay++; |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 210 | miiIndicator = readl(&mac->mii_mgmt_indicator); |
| 211 | } while ((miiIndicator & MGMT_BUSY) && delay < 100); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 212 | |
| 213 | /* If we hit the max delay, we could not write the register */ |
| 214 | if (delay == 100) { |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 215 | u16 TempValue; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 216 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 217 | dev_warn(&etdev->pdev->dev, |
Alan Cox | 1570003 | 2009-08-27 11:03:09 +0100 | [diff] [blame] | 218 | "xcvrReg 0x%08x could not be written", xcvrReg); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 219 | dev_warn(&etdev->pdev->dev, "status is 0x%08x\n", |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 220 | miiIndicator); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 221 | dev_warn(&etdev->pdev->dev, "command is 0x%08x\n", |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 222 | readl(&mac->mii_mgmt_cmd)); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 223 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 224 | MiRead(etdev, xcvrReg, &TempValue); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 225 | |
| 226 | status = -EIO; |
| 227 | } |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 228 | /* Stop the write operation */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 229 | writel(0, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 230 | |
| 231 | /* set the registers we touched back to the state at which we entered |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 232 | * this function |
| 233 | */ |
Alan Cox | 57aed3b | 2009-10-06 15:51:04 +0100 | [diff] [blame] | 234 | writel(miiAddr, &mac->mii_mgmt_addr); |
| 235 | writel(miiCmd, &mac->mii_mgmt_cmd); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 236 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 237 | return status; |
| 238 | } |
| 239 | |
| 240 | /** |
| 241 | * et131x_xcvr_find - Find the PHY ID |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 242 | * @etdev: pointer to our private adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 243 | * |
| 244 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 245 | */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 246 | int et131x_xcvr_find(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 247 | { |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 248 | u8 xcvr_addr; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 249 | MI_IDR1_t idr1; |
| 250 | MI_IDR2_t idr2; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 251 | u32 xcvr_id; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 252 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 253 | /* We need to get xcvr id and address we just get the first one */ |
| 254 | for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) { |
| 255 | /* Read the ID from the PHY */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 256 | PhyMiRead(etdev, xcvr_addr, |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 257 | (u8) offsetof(MI_REGS_t, idr1), |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 258 | &idr1.value); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 259 | PhyMiRead(etdev, xcvr_addr, |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 260 | (u8) offsetof(MI_REGS_t, idr2), |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 261 | &idr2.value); |
| 262 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 263 | xcvr_id = (u32) ((idr1.value << 16) | idr2.value); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 264 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 265 | if (idr1.value != 0 && idr1.value != 0xffff) { |
| 266 | etdev->Stats.xcvr_id = xcvr_id; |
| 267 | etdev->Stats.xcvr_addr = xcvr_addr; |
| 268 | return 0; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 269 | } |
| 270 | } |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 271 | return -ENODEV; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 272 | } |
| 273 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 274 | void ET1310_PhyReset(struct et131x_adapter *etdev) |
| 275 | { |
| 276 | MiWrite(etdev, PHY_CONTROL, 0x8000); |
| 277 | } |
| 278 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 279 | /** |
| 280 | * ET1310_PhyPowerDown - PHY power control |
| 281 | * @etdev: device to control |
| 282 | * @down: true for off/false for back on |
| 283 | * |
| 284 | * one hundred, ten, one thousand megs |
| 285 | * How would you like to have your LAN accessed |
| 286 | * Can't you see that this code processed |
| 287 | * Phy power, phy power.. |
| 288 | */ |
| 289 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 290 | void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down) |
| 291 | { |
| 292 | u16 data; |
| 293 | |
| 294 | MiRead(etdev, PHY_CONTROL, &data); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 295 | data &= ~0x0800; /* Power UP */ |
| 296 | if (down) /* Power DOWN */ |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 297 | data |= 0x0800; |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 298 | MiWrite(etdev, PHY_CONTROL, data); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 299 | } |
| 300 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 301 | /** |
| 302 | * ET130_PhyAutoNEg - autonegotiate control |
| 303 | * @etdev: device to control |
| 304 | * @enabe: autoneg on/off |
| 305 | * |
| 306 | * Set up the autonegotiation state according to whether we will be |
| 307 | * negotiating the state or forcing a speed. |
| 308 | */ |
| 309 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 310 | static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable) |
| 311 | { |
| 312 | u16 data; |
| 313 | |
| 314 | MiRead(etdev, PHY_CONTROL, &data); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 315 | data &= ~0x1000; /* Autonegotiation OFF */ |
| 316 | if (enable) |
| 317 | data |= 0x1000; /* Autonegotiation ON */ |
| 318 | MiWrite(etdev, PHY_CONTROL, data); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 319 | } |
| 320 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 321 | /** |
| 322 | * ET130_PhyDuplexMode - duplex control |
| 323 | * @etdev: device to control |
| 324 | * @duplex: duplex on/off |
| 325 | * |
| 326 | * Set up the duplex state on the PHY |
| 327 | */ |
| 328 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 329 | static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex) |
| 330 | { |
| 331 | u16 data; |
| 332 | |
| 333 | MiRead(etdev, PHY_CONTROL, &data); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 334 | data &= ~0x100; /* Set Half Duplex */ |
| 335 | if (duplex == TRUEPHY_DUPLEX_FULL) |
| 336 | data |= 0x100; /* Set Full Duplex */ |
| 337 | MiWrite(etdev, PHY_CONTROL, data); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 338 | } |
| 339 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 340 | /** |
| 341 | * ET130_PhySpeedSelect - speed control |
| 342 | * @etdev: device to control |
| 343 | * @duplex: duplex on/off |
| 344 | * |
| 345 | * Set the speed of our PHY. |
| 346 | */ |
| 347 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 348 | static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed) |
| 349 | { |
| 350 | u16 data; |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 351 | static const u16 bits[3]={0x0000, 0x2000, 0x0040}; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 352 | |
| 353 | /* Read the PHY control register */ |
| 354 | MiRead(etdev, PHY_CONTROL, &data); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 355 | /* Clear all Speed settings (Bits 6, 13) */ |
| 356 | data &= ~0x2040; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 357 | /* Write back the new speed */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 358 | MiWrite(etdev, PHY_CONTROL, data | bits[speed]); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 359 | } |
| 360 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 361 | /** |
| 362 | * ET1310_PhyLinkStatus - read link state |
| 363 | * @etdev: device to read |
| 364 | * @link_status: reported link state |
| 365 | * @autoneg: reported autonegotiation state (complete/incomplete/disabled) |
| 366 | * @linkspeed: returnedlink speed in use |
| 367 | * @duplex_mode: reported half/full duplex state |
| 368 | * @mdi_mdix: not yet working |
| 369 | * @masterslave: report whether we are master or slave |
| 370 | * @polarity: link polarity |
| 371 | * |
| 372 | * I can read your lan like a magazine |
| 373 | * I see if your up |
| 374 | * I know your link speed |
| 375 | * I see all the setting that you'd rather keep |
| 376 | */ |
| 377 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 378 | static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev, |
| 379 | u8 *link_status, |
| 380 | u32 *autoneg, |
| 381 | u32 *linkspeed, |
| 382 | u32 *duplex_mode, |
| 383 | u32 *mdi_mdix, |
| 384 | u32 *masterslave, u32 *polarity) |
| 385 | { |
| 386 | u16 mistatus = 0; |
| 387 | u16 is1000BaseT = 0; |
| 388 | u16 vmi_phystatus = 0; |
| 389 | u16 control = 0; |
| 390 | |
| 391 | MiRead(etdev, PHY_STATUS, &mistatus); |
| 392 | MiRead(etdev, PHY_1000_STATUS, &is1000BaseT); |
| 393 | MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus); |
| 394 | MiRead(etdev, PHY_CONTROL, &control); |
| 395 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 396 | *link_status = (vmi_phystatus & 0x0040) ? 1 : 0; |
| 397 | *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ? |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 398 | TRUEPHY_ANEG_COMPLETE : |
| 399 | TRUEPHY_ANEG_NOT_COMPLETE) : |
| 400 | TRUEPHY_ANEG_DISABLED; |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 401 | *linkspeed = (vmi_phystatus & 0x0300) >> 8; |
| 402 | *duplex_mode = (vmi_phystatus & 0x0080) >> 7; |
| 403 | /* NOTE: Need to complete this */ |
| 404 | *mdi_mdix = 0; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 405 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 406 | *masterslave = (is1000BaseT & 0x4000) ? |
| 407 | TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE; |
| 408 | *polarity = (vmi_phystatus & 0x0400) ? |
| 409 | TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 410 | } |
| 411 | |
| 412 | static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev, |
| 413 | u16 regnum, u16 andMask, u16 orMask) |
| 414 | { |
| 415 | u16 reg; |
| 416 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 417 | MiRead(etdev, regnum, ®); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 418 | reg &= andMask; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 419 | reg |= orMask; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 420 | MiWrite(etdev, regnum, reg); |
| 421 | } |
| 422 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 423 | /* Still used from _mac for BIT_READ */ |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 424 | void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action, |
| 425 | u16 regnum, u16 bitnum, u8 *value) |
| 426 | { |
| 427 | u16 reg; |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 428 | u16 mask = 0x0001 << bitnum; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 429 | |
| 430 | /* Read the requested register */ |
| 431 | MiRead(etdev, regnum, ®); |
| 432 | |
| 433 | switch (action) { |
| 434 | case TRUEPHY_BIT_READ: |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 435 | *value = (reg & mask) >> bitnum; |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 436 | break; |
| 437 | |
| 438 | case TRUEPHY_BIT_SET: |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 439 | MiWrite(etdev, regnum, reg | mask); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 440 | break; |
| 441 | |
| 442 | case TRUEPHY_BIT_CLEAR: |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 443 | MiWrite(etdev, regnum, reg & ~mask); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 444 | break; |
| 445 | |
| 446 | default: |
| 447 | break; |
| 448 | } |
| 449 | } |
| 450 | |
| 451 | void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev, |
| 452 | u16 duplex) |
| 453 | { |
| 454 | u16 data; |
| 455 | |
| 456 | /* Read the PHY 1000 Base-T Control Register */ |
| 457 | MiRead(etdev, PHY_1000_CONTROL, &data); |
| 458 | |
| 459 | /* Clear Bits 8,9 */ |
| 460 | data &= ~0x0300; |
| 461 | |
| 462 | switch (duplex) { |
| 463 | case TRUEPHY_ADV_DUPLEX_NONE: |
| 464 | /* Duplex already cleared, do nothing */ |
| 465 | break; |
| 466 | |
| 467 | case TRUEPHY_ADV_DUPLEX_FULL: |
| 468 | /* Set Bit 9 */ |
| 469 | data |= 0x0200; |
| 470 | break; |
| 471 | |
| 472 | case TRUEPHY_ADV_DUPLEX_HALF: |
| 473 | /* Set Bit 8 */ |
| 474 | data |= 0x0100; |
| 475 | break; |
| 476 | |
| 477 | case TRUEPHY_ADV_DUPLEX_BOTH: |
| 478 | default: |
| 479 | data |= 0x0300; |
| 480 | break; |
| 481 | } |
| 482 | |
| 483 | /* Write back advertisement */ |
| 484 | MiWrite(etdev, PHY_1000_CONTROL, data); |
| 485 | } |
| 486 | |
| 487 | static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev, |
| 488 | u16 duplex) |
| 489 | { |
| 490 | u16 data; |
| 491 | |
| 492 | /* Read the Autonegotiation Register (10/100) */ |
| 493 | MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data); |
| 494 | |
| 495 | /* Clear bits 7,8 */ |
| 496 | data &= ~0x0180; |
| 497 | |
| 498 | switch (duplex) { |
| 499 | case TRUEPHY_ADV_DUPLEX_NONE: |
| 500 | /* Duplex already cleared, do nothing */ |
| 501 | break; |
| 502 | |
| 503 | case TRUEPHY_ADV_DUPLEX_FULL: |
| 504 | /* Set Bit 8 */ |
| 505 | data |= 0x0100; |
| 506 | break; |
| 507 | |
| 508 | case TRUEPHY_ADV_DUPLEX_HALF: |
| 509 | /* Set Bit 7 */ |
| 510 | data |= 0x0080; |
| 511 | break; |
| 512 | |
| 513 | case TRUEPHY_ADV_DUPLEX_BOTH: |
| 514 | default: |
| 515 | /* Set Bits 7,8 */ |
| 516 | data |= 0x0180; |
| 517 | break; |
| 518 | } |
| 519 | |
| 520 | /* Write back advertisement */ |
| 521 | MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data); |
| 522 | } |
| 523 | |
| 524 | static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev, |
| 525 | u16 duplex) |
| 526 | { |
| 527 | u16 data; |
| 528 | |
| 529 | /* Read the Autonegotiation Register (10/100) */ |
| 530 | MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data); |
| 531 | |
| 532 | /* Clear bits 5,6 */ |
| 533 | data &= ~0x0060; |
| 534 | |
| 535 | switch (duplex) { |
| 536 | case TRUEPHY_ADV_DUPLEX_NONE: |
| 537 | /* Duplex already cleared, do nothing */ |
| 538 | break; |
| 539 | |
| 540 | case TRUEPHY_ADV_DUPLEX_FULL: |
| 541 | /* Set Bit 6 */ |
| 542 | data |= 0x0040; |
| 543 | break; |
| 544 | |
| 545 | case TRUEPHY_ADV_DUPLEX_HALF: |
| 546 | /* Set Bit 5 */ |
| 547 | data |= 0x0020; |
| 548 | break; |
| 549 | |
| 550 | case TRUEPHY_ADV_DUPLEX_BOTH: |
| 551 | default: |
| 552 | /* Set Bits 5,6 */ |
| 553 | data |= 0x0060; |
| 554 | break; |
| 555 | } |
| 556 | |
| 557 | /* Write back advertisement */ |
| 558 | MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data); |
| 559 | } |
| 560 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 561 | /** |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 562 | * et131x_setphy_normal - Set PHY for normal operation. |
| 563 | * @etdev: pointer to our private adapter structure |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 564 | * |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 565 | * Used by Power Management to force the PHY into 10 Base T half-duplex mode, |
| 566 | * when going to D3 in WOL mode. Also used during initialization to set the |
| 567 | * PHY for normal operation. |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 568 | */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 569 | void et131x_setphy_normal(struct et131x_adapter *etdev) |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 570 | { |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 571 | /* Make sure the PHY is powered up */ |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 572 | ET1310_PhyPowerDown(etdev, 0); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 573 | et131x_xcvr_init(etdev); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 574 | } |
| 575 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 576 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 577 | /** |
| 578 | * et131x_xcvr_init - Init the phy if we are setting it into force mode |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 579 | * @etdev: pointer to our private adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 580 | * |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 581 | */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 582 | static void et131x_xcvr_init(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 583 | { |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 584 | MI_IMR_t imr; |
| 585 | MI_ISR_t isr; |
| 586 | MI_LCR2_t lcr2; |
| 587 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 588 | /* Zero out the adapter structure variable representing BMSR */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 589 | etdev->Bmsr.value = 0; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 590 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 591 | MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value); |
| 592 | MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 593 | |
| 594 | /* Set the link status interrupt only. Bad behavior when link status |
| 595 | * and auto neg are set, we run into a nested interrupt problem |
| 596 | */ |
| 597 | imr.bits.int_en = 0x1; |
| 598 | imr.bits.link_status = 0x1; |
| 599 | imr.bits.autoneg_status = 0x1; |
| 600 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 601 | MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 602 | |
| 603 | /* Set the LED behavior such that LED 1 indicates speed (off = |
| 604 | * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates |
| 605 | * link and activity (on for link, blink off for activity). |
| 606 | * |
| 607 | * NOTE: Some customizations have been added here for specific |
| 608 | * vendors; The LED behavior is now determined by vendor data in the |
| 609 | * EEPROM. However, the above description is the default. |
| 610 | */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 611 | if ((etdev->eepromData[1] & 0x4) == 0) { |
| 612 | MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2), |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 613 | &lcr2.value); |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 614 | if ((etdev->eepromData[1] & 0x8) == 0) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 615 | lcr2.bits.led_tx_rx = 0x3; |
| 616 | else |
| 617 | lcr2.bits.led_tx_rx = 0x4; |
| 618 | lcr2.bits.led_link = 0xa; |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 619 | MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2), |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 620 | lcr2.value); |
| 621 | } |
| 622 | |
| 623 | /* Determine if we need to go into a force mode and set it */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 624 | if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) { |
| 625 | if (etdev->RegistryFlowControl == TxOnly || |
| 626 | etdev->RegistryFlowControl == Both) |
| 627 | ET1310_PhyAccessMiBit(etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 628 | TRUEPHY_BIT_SET, 4, 11, NULL); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 629 | else |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 630 | ET1310_PhyAccessMiBit(etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 631 | TRUEPHY_BIT_CLEAR, 4, 11, NULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 632 | |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 633 | if (etdev->RegistryFlowControl == Both) |
| 634 | ET1310_PhyAccessMiBit(etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 635 | TRUEPHY_BIT_SET, 4, 10, NULL); |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 636 | else |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 637 | ET1310_PhyAccessMiBit(etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 638 | TRUEPHY_BIT_CLEAR, 4, 10, NULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 639 | |
| 640 | /* Set the phy to autonegotiation */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 641 | ET1310_PhyAutoNeg(etdev, true); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 642 | |
| 643 | /* NOTE - Do we need this? */ |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 644 | ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL); |
| 645 | return; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 646 | } |
Alan Cox | e1bc584 | 2009-10-06 15:51:17 +0100 | [diff] [blame^] | 647 | |
| 648 | ET1310_PhyAutoNeg(etdev, false); |
| 649 | |
| 650 | /* Set to the correct force mode. */ |
| 651 | if (etdev->AiForceDpx != 1) { |
| 652 | if (etdev->RegistryFlowControl == TxOnly || |
| 653 | etdev->RegistryFlowControl == Both) |
| 654 | ET1310_PhyAccessMiBit(etdev, |
| 655 | TRUEPHY_BIT_SET, 4, 11, NULL); |
| 656 | else |
| 657 | ET1310_PhyAccessMiBit(etdev, |
| 658 | TRUEPHY_BIT_CLEAR, 4, 11, NULL); |
| 659 | |
| 660 | if (etdev->RegistryFlowControl == Both) |
| 661 | ET1310_PhyAccessMiBit(etdev, |
| 662 | TRUEPHY_BIT_SET, 4, 10, NULL); |
| 663 | else |
| 664 | ET1310_PhyAccessMiBit(etdev, |
| 665 | TRUEPHY_BIT_CLEAR, 4, 10, NULL); |
| 666 | } else { |
| 667 | ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL); |
| 668 | ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL); |
| 669 | } |
| 670 | ET1310_PhyPowerDown(etdev, 1); |
| 671 | switch (etdev->AiForceSpeed) { |
| 672 | case 10: |
| 673 | /* First we need to turn off all other advertisement */ |
| 674 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 675 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 676 | if (etdev->AiForceDpx == 1) { |
| 677 | /* Set our advertise values accordingly */ |
| 678 | ET1310_PhyAdvertise10BaseT(etdev, |
| 679 | TRUEPHY_ADV_DUPLEX_HALF); |
| 680 | } else if (etdev->AiForceDpx == 2) { |
| 681 | /* Set our advertise values accordingly */ |
| 682 | ET1310_PhyAdvertise10BaseT(etdev, |
| 683 | TRUEPHY_ADV_DUPLEX_FULL); |
| 684 | } else { |
| 685 | /* Disable autoneg */ |
| 686 | ET1310_PhyAutoNeg(etdev, false); |
| 687 | /* Disable rest of the advertisements */ |
| 688 | ET1310_PhyAdvertise10BaseT(etdev, |
| 689 | TRUEPHY_ADV_DUPLEX_NONE); |
| 690 | /* Force 10 Mbps */ |
| 691 | ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS); |
| 692 | /* Force Full duplex */ |
| 693 | ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL); |
| 694 | } |
| 695 | break; |
| 696 | case 100: |
| 697 | /* first we need to turn off all other advertisement */ |
| 698 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 699 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 700 | if (etdev->AiForceDpx == 1) { |
| 701 | /* Set our advertise values accordingly */ |
| 702 | ET1310_PhyAdvertise100BaseT(etdev, |
| 703 | TRUEPHY_ADV_DUPLEX_HALF); |
| 704 | /* Set speed */ |
| 705 | ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS); |
| 706 | } else if (etdev->AiForceDpx == 2) { |
| 707 | /* Set our advertise values accordingly */ |
| 708 | ET1310_PhyAdvertise100BaseT(etdev, |
| 709 | TRUEPHY_ADV_DUPLEX_FULL); |
| 710 | } else { |
| 711 | /* Disable autoneg */ |
| 712 | ET1310_PhyAutoNeg(etdev, false); |
| 713 | /* Disable other advertisement */ |
| 714 | ET1310_PhyAdvertise100BaseT(etdev, |
| 715 | TRUEPHY_ADV_DUPLEX_NONE); |
| 716 | /* Force 100 Mbps */ |
| 717 | ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS); |
| 718 | /* Force Full duplex */ |
| 719 | ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL); |
| 720 | } |
| 721 | break; |
| 722 | case 1000: |
| 723 | /* first we need to turn off all other advertisement */ |
| 724 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 725 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 726 | /* set our advertise values accordingly */ |
| 727 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL); |
| 728 | break; |
| 729 | } |
| 730 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 731 | } |
| 732 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 733 | void et131x_Mii_check(struct et131x_adapter *etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 734 | MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints) |
| 735 | { |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 736 | u8 link_status; |
| 737 | u32 autoneg_status; |
| 738 | u32 speed; |
| 739 | u32 duplex; |
| 740 | u32 mdi_mdix; |
| 741 | u32 masterslave; |
| 742 | u32 polarity; |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 743 | unsigned long flags; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 744 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 745 | if (bmsr_ints.bits.link_status) { |
| 746 | if (bmsr.bits.link_status) { |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 747 | etdev->PoMgmt.TransPhyComaModeOnBoot = 20; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 748 | |
| 749 | /* Update our state variables and indicate the |
| 750 | * connected state |
| 751 | */ |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 752 | spin_lock_irqsave(&etdev->Lock, flags); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 753 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 754 | etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT; |
Alan Cox | f6b35d6 | 2009-08-27 11:02:05 +0100 | [diff] [blame] | 755 | etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 756 | |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 757 | spin_unlock_irqrestore(&etdev->Lock, flags); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 758 | |
Alan Cox | 5f1377d | 2009-10-06 15:47:55 +0100 | [diff] [blame] | 759 | netif_carrier_on(etdev->netdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 760 | } else { |
Alan Cox | 1570003 | 2009-08-27 11:03:09 +0100 | [diff] [blame] | 761 | dev_warn(&etdev->pdev->dev, |
| 762 | "Link down - cable problem ?\n"); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 763 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 764 | if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 765 | /* NOTE - Is there a way to query this without |
| 766 | * TruePHY? |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 767 | * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 768 | */ |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 769 | u16 Register18; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 770 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 771 | MiRead(etdev, 0x12, &Register18); |
| 772 | MiWrite(etdev, 0x12, Register18 | 0x4); |
| 773 | MiWrite(etdev, 0x10, Register18 | 0x8402); |
| 774 | MiWrite(etdev, 0x11, Register18 | 511); |
| 775 | MiWrite(etdev, 0x12, Register18); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 776 | } |
| 777 | |
| 778 | /* For the first N seconds of life, we are in "link |
| 779 | * detection" When we are in this state, we should |
| 780 | * only report "connected". When the LinkDetection |
| 781 | * Timer expires, we can report disconnected (handled |
| 782 | * in the LinkDetectionDPC). |
| 783 | */ |
Alan Cox | f6b35d6 | 2009-08-27 11:02:05 +0100 | [diff] [blame] | 784 | if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) || |
| 785 | (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) { |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 786 | spin_lock_irqsave(&etdev->Lock, flags); |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 787 | etdev->MediaState = |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 788 | NETIF_STATUS_MEDIA_DISCONNECT; |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 789 | spin_unlock_irqrestore(&etdev->Lock, |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 790 | flags); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 791 | |
Alan Cox | 5f1377d | 2009-10-06 15:47:55 +0100 | [diff] [blame] | 792 | netif_carrier_off(etdev->netdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 793 | } |
| 794 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 795 | etdev->linkspeed = 0; |
Alan Cox | 576b38e | 2009-08-27 11:00:47 +0100 | [diff] [blame] | 796 | etdev->duplex_mode = 0; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 797 | |
| 798 | /* Free the packets being actively sent & stopped */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 799 | et131x_free_busy_send_packets(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 800 | |
| 801 | /* Re-initialize the send structures */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 802 | et131x_init_send(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 803 | |
| 804 | /* Reset the RFD list and re-start RU */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 805 | et131x_reset_recv(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 806 | |
| 807 | /* |
| 808 | * Bring the device back to the state it was during |
| 809 | * init prior to autonegotiation being complete. This |
| 810 | * way, when we get the auto-neg complete interrupt, |
| 811 | * we can complete init by calling ConfigMacREGS2. |
| 812 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 813 | et131x_soft_reset(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 814 | |
| 815 | /* Setup ET1310 as per the documentation */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 816 | et131x_adapter_setup(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 817 | |
| 818 | /* Setup the PHY into coma mode until the cable is |
| 819 | * plugged back in |
| 820 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 821 | if (etdev->RegistryPhyComa == 1) |
| 822 | EnablePhyComa(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 823 | } |
| 824 | } |
| 825 | |
| 826 | if (bmsr_ints.bits.auto_neg_complete || |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 827 | (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) { |
| 828 | if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) { |
| 829 | ET1310_PhyLinkStatus(etdev, |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 830 | &link_status, &autoneg_status, |
| 831 | &speed, &duplex, &mdi_mdix, |
| 832 | &masterslave, &polarity); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 833 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 834 | etdev->linkspeed = speed; |
| 835 | etdev->duplex_mode = duplex; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 836 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 837 | etdev->PoMgmt.TransPhyComaModeOnBoot = 20; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 838 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 839 | if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 840 | /* |
| 841 | * NOTE - Is there a way to query this without |
| 842 | * TruePHY? |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 843 | * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 844 | */ |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 845 | u16 Register18; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 846 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 847 | MiRead(etdev, 0x12, &Register18); |
| 848 | MiWrite(etdev, 0x12, Register18 | 0x4); |
| 849 | MiWrite(etdev, 0x10, Register18 | 0x8402); |
| 850 | MiWrite(etdev, 0x11, Register18 | 511); |
| 851 | MiWrite(etdev, 0x12, Register18); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 852 | } |
| 853 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 854 | ConfigFlowControl(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 855 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 856 | if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS && |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 857 | etdev->RegistryJumboPacket > 2048) |
| 858 | ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff, |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 859 | 0x2000); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 860 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 861 | SetRxDmaTimer(etdev); |
| 862 | ConfigMACRegs2(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 863 | } |
| 864 | } |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 865 | } |
| 866 | |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 867 | /* |
| 868 | * The routines which follow provide low-level access to the PHY, and are used |
| 869 | * primarily by the routines above (although there are a few places elsewhere |
| 870 | * in the driver where this level of access is required). |
| 871 | */ |
| 872 | |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 873 | static const u16 ConfigPhy[25][2] = { |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 874 | /* Reg Value Register */ |
| 875 | /* Addr */ |
| 876 | {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */ |
| 877 | {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */ |
| 878 | {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */ |
| 879 | |
| 880 | {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */ |
| 881 | {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */ |
| 882 | {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */ |
| 883 | |
| 884 | {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */ |
| 885 | {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */ |
| 886 | {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */ |
| 887 | |
| 888 | {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */ |
| 889 | {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */ |
| 890 | {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */ |
| 891 | |
| 892 | {0x300D, 1}, /* DisableNorm */ |
| 893 | |
| 894 | {0x280C, 0x0180}, /* LinkHoldEnd */ |
| 895 | |
| 896 | {0x1C21, 0x0002}, /* AlphaM */ |
| 897 | |
| 898 | {0x3821, 6}, /* FfeLkgTx0 */ |
| 899 | {0x381D, 1}, /* FfeLkg1g4 */ |
| 900 | {0x381E, 1}, /* FfeLkg1g5 */ |
| 901 | {0x381F, 1}, /* FfeLkg1g6 */ |
| 902 | {0x3820, 1}, /* FfeLkg1g7 */ |
| 903 | |
| 904 | {0x8402, 0x01F0}, /* Btinact */ |
| 905 | {0x800E, 20}, /* LftrainTime */ |
| 906 | {0x800F, 24}, /* DvguardTime */ |
| 907 | {0x8010, 46}, /* IdlguardTime */ |
| 908 | |
| 909 | {0, 0} |
| 910 | |
| 911 | }; |
| 912 | |
| 913 | /* condensed version of the phy initialization routine */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 914 | void ET1310_PhyInit(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 915 | { |
Alan Cox | 1210db9 | 2009-10-06 15:51:10 +0100 | [diff] [blame] | 916 | u16 data, index; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 917 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 918 | if (etdev == NULL) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 919 | return; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 920 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 921 | /* get the identity (again ?) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 922 | MiRead(etdev, PHY_ID_1, &data); |
| 923 | MiRead(etdev, PHY_ID_2, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 924 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 925 | /* what does this do/achieve ? */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 926 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 927 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 928 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 929 | /* read modem register 0402, should I do something with the return |
| 930 | data ? */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 931 | MiWrite(etdev, PHY_INDEX_REG, 0x0402); |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 932 | MiRead(etdev, PHY_DATA_REG, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 933 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 934 | /* what does this do/achieve ? */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 935 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 936 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 937 | /* get the identity (again ?) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 938 | MiRead(etdev, PHY_ID_1, &data); |
| 939 | MiRead(etdev, PHY_ID_2, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 940 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 941 | /* what does this achieve ? */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 942 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 943 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 944 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 945 | /* read modem register 0402, should I do something with |
| 946 | the return data? */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 947 | MiWrite(etdev, PHY_INDEX_REG, 0x0402); |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 948 | MiRead(etdev, PHY_DATA_REG, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 949 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 950 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 951 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 952 | /* what does this achieve (should return 0x1040) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 953 | MiRead(etdev, PHY_CONTROL, &data); |
| 954 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 955 | MiWrite(etdev, PHY_CONTROL, 0x1840); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 956 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 957 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 958 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 959 | /* here the writing of the array starts.... */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 960 | index = 0; |
| 961 | while (ConfigPhy[index][0] != 0x0000) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 962 | /* write value */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 963 | MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]); |
| 964 | MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 965 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 966 | /* read it back */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 967 | MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]); |
| 968 | MiRead(etdev, PHY_DATA_REG, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 969 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 970 | /* do a check on the value read back ? */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 971 | index++; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 972 | } |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 973 | /* here the writing of the array ends... */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 974 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 975 | MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */ |
| 976 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 977 | MiWrite(etdev, PHY_CONTROL, 0x1040); |
| 978 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 979 | } |
| 980 | |