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Viresh Kumard3f797d2012-04-20 20:15:34 +05301* Synopsys Designware DMA Controller
2
3Required properties:
4- compatible: "snps,dma-spear1340"
5- reg: Address range of the DMAC registers
Viresh Kumard3f797d2012-04-20 20:15:34 +05306- interrupt: Should contain the DMAC interrupt number
Arnd Bergmannf9c6a652013-02-27 21:36:03 +00007- dma-channels: Number of channels supported by hardware
8- dma-requests: Number of DMA request lines supported, up to 16
9- dma-masters: Number of AHB masters supported by the controller
10- #dma-cells: must be <3>
Viresh Kumara9ddb572012-10-16 09:49:17 +053011- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
12 1: descending
13- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14 increase from chan n->0
15- block_size: Maximum block size supported by the controller
Viresh Kumara9ddb572012-10-16 09:49:17 +053016- data_width: Maximum data width supported by hardware per AHB master
17 (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
Arnd Bergmannf9c6a652013-02-27 21:36:03 +000018
19
20Optional properties:
21- interrupt-parent: Should be the phandle for the interrupt controller
22 that services interrupts for this device
23- is_private: The device channels should be marked as private and not for by the
24 general purpose DMA channel allocator. False if not passed.
Viresh Kumard3f797d2012-04-20 20:15:34 +053025
26Example:
27
Arnd Bergmannf9c6a652013-02-27 21:36:03 +000028 dmahost: dma@fc000000 {
Viresh Kumard3f797d2012-04-20 20:15:34 +053029 compatible = "snps,dma-spear1340";
30 reg = <0xfc000000 0x1000>;
31 interrupt-parent = <&vic1>;
32 interrupts = <12>;
Viresh Kumara9ddb572012-10-16 09:49:17 +053033
Arnd Bergmannf9c6a652013-02-27 21:36:03 +000034 dma-channels = <8>;
35 dma-requests = <16>;
36 dma-masters = <2>;
37 #dma-cells = <3>;
Viresh Kumara9ddb572012-10-16 09:49:17 +053038 chan_allocation_order = <1>;
39 chan_priority = <1>;
40 block_size = <0xfff>;
Viresh Kumara9ddb572012-10-16 09:49:17 +053041 data_width = <3 3 0 0>;
Arnd Bergmannf9c6a652013-02-27 21:36:03 +000042 };
Viresh Kumara9ddb572012-10-16 09:49:17 +053043
Arnd Bergmannf9c6a652013-02-27 21:36:03 +000044DMA clients connected to the Designware DMA controller must use the format
45described in the dma.txt file, using a four-cell specifier for each channel.
46The four cells in order are:
47
481. A phandle pointing to the DMA controller
492. The DMA request line number
503. Source master for transfers on allocated channel
514. Destination master for transfers on allocated channel
52
53Example:
54
55 serial@e0000000 {
56 compatible = "arm,pl011", "arm,primecell";
57 reg = <0xe0000000 0x1000>;
58 interrupts = <0 35 0x4>;
59 status = "disabled";
60 dmas = <&dmahost 12 0 1>,
61 <&dmahost 13 0 1 0>;
62 dma-names = "rx", "rx";
Viresh Kumard3f797d2012-04-20 20:15:34 +053063 };