blob: 4ed89fa9ae46fa05e765fcaaa04854b7c4051fe0 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf648d122008-01-13 16:02:57 -050016 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
Jeff Garzik8148ff42007-10-16 20:56:09 -040042#define FORCEDETH_VERSION "0.61"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#define DRV_NAME "forcedeth"
44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/pci.h>
48#include <linux/interrupt.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/delay.h>
52#include <linux/spinlock.h>
53#include <linux/ethtool.h>
54#include <linux/timer.h>
55#include <linux/skbuff.h>
56#include <linux/mii.h>
57#include <linux/random.h>
58#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020059#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080060#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62#include <asm/irq.h>
63#include <asm/io.h>
64#include <asm/uaccess.h>
65#include <asm/system.h>
66
67#if 0
68#define dprintk printk
69#else
70#define dprintk(x...) do { } while (0)
71#endif
72
Stephen Hemmingerbea33482007-10-03 16:41:36 -070073#define TX_WORK_PER_LOOP 64
74#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/*
77 * Hardware access:
78 */
79
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -050080#define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
81#define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
82#define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
83#define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
84#define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
85#define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
86#define DEV_HAS_MSI 0x00040 /* device supports MSI */
87#define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
88#define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
89#define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
90#define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
91#define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
92#define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
93#define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
94#define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
95#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
Ayaz Abdulla3b446c32008-03-10 14:58:21 -050098#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
Ayaz Abdullaa4336862008-04-18 13:50:43 -070099#define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101enum {
102 NvRegIrqStatus = 0x000,
103#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500104#define NVREG_IRQSTAT_MASK 0x81ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 NvRegIrqMask = 0x004,
106#define NVREG_IRQ_RX_ERROR 0x0001
107#define NVREG_IRQ_RX 0x0002
108#define NVREG_IRQ_RX_NOBUF 0x0004
109#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200110#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111#define NVREG_IRQ_TIMER 0x0020
112#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500113#define NVREG_IRQ_RX_FORCED 0x0080
114#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500115#define NVREG_IRQ_RECOVER_ERROR 0x8000
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500116#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400117#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500118#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
119#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500120#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200121
122#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500123 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500124 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126 NvRegUnknownSetupReg6 = 0x008,
127#define NVREG_UNKSETUP6_VAL 3
128
129/*
130 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
131 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
132 */
133 NvRegPollingInterval = 0x00c,
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -0500134#define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500135#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500136 NvRegMSIMap0 = 0x020,
137 NvRegMSIMap1 = 0x024,
138 NvRegMSIIrqMask = 0x030,
139#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400141#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142#define NVREG_MISC1_HD 0x02
143#define NVREG_MISC1_FORCE 0x3b0f3c
144
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500145 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400146#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 NvRegTransmitterControl = 0x084,
148#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500149#define NVREG_XMITCTL_MGMT_ST 0x40000000
150#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
151#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
152#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
153#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
154#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
155#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
156#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
157#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500158#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 NvRegTransmitterStatus = 0x088,
160#define NVREG_XMITSTAT_BUSY 0x01
161
162 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400163#define NVREG_PFF_PAUSE_RX 0x08
164#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165#define NVREG_PFF_PROMISC 0x80
166#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400167#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168
169 NvRegOffloadConfig = 0x90,
170#define NVREG_OFFLOAD_HOMEPHY 0x601
171#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl = 0x094,
173#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500174#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 NvRegReceiverStatus = 0x98,
176#define NVREG_RCVSTAT_BUSY 0x01
177
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700178 NvRegSlotTime = 0x9c,
179#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182#define NVREG_SLOTTIME_HALF 0x0000ff00
183#define NVREG_SLOTTIME_DEFAULT 0x00007f00
184#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400186 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500187#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400193 NvRegRxDeferral = 0xA4,
194#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 NvRegMacAddrA = 0xA8,
196 NvRegMacAddrB = 0xAC,
197 NvRegMulticastAddrA = 0xB0,
198#define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB = 0xB4,
200 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500201#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500203#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
205 NvRegPhyInterface = 0xC0,
206#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700207 NvRegBackOffControl = 0xC4,
208#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210#define NVREG_BKOFFCTRL_SELECT 24
211#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212
213 NvRegTxRingPhysAddr = 0x100,
214 NvRegRxRingPhysAddr = 0x104,
215 NvRegRingSizes = 0x108,
216#define NVREG_RINGSZ_TXSHIFT 0
217#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400218 NvRegTransmitPoll = 0x10c,
219#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 NvRegLinkSpeed = 0x110,
221#define NVREG_LINKSPEED_FORCE 0x10000
222#define NVREG_LINKSPEED_10 1000
223#define NVREG_LINKSPEED_100 100
224#define NVREG_LINKSPEED_1000 50
225#define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5 = 0x130,
227#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400228 NvRegTxWatermark = 0x13c,
229#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 NvRegTxRxControl = 0x144,
233#define NVREG_TXRXCTL_KICK 0x0001
234#define NVREG_TXRXCTL_BIT1 0x0002
235#define NVREG_TXRXCTL_BIT2 0x0004
236#define NVREG_TXRXCTL_IDLE 0x0008
237#define NVREG_TXRXCTL_RESET 0x0010
238#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400239#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500240#define NVREG_TXRXCTL_DESC_2 0x002100
241#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500242#define NVREG_TXRXCTL_VLANSTRIP 0x00040
243#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500244 NvRegTxRingPhysAddrHigh = 0x148,
245 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400246 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500247#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 NvRegMIIStatus = 0x180,
252#define NVREG_MIISTAT_ERROR 0x0001
253#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500254#define NVREG_MIISTAT_MASK_RW 0x0007
255#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500256 NvRegMIIMask = 0x184,
257#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
259 NvRegAdapterControl = 0x188,
260#define NVREG_ADAPTCTL_START 0x02
261#define NVREG_ADAPTCTL_LINKUP 0x04
262#define NVREG_ADAPTCTL_PHYVALID 0x40000
263#define NVREG_ADAPTCTL_RUNNING 0x100000
264#define NVREG_ADAPTCTL_PHYSHIFT 24
265 NvRegMIISpeed = 0x18c,
266#define NVREG_MIISPEED_BIT8 (1<<8)
267#define NVREG_MIIDELAY 5
268 NvRegMIIControl = 0x190,
269#define NVREG_MIICTL_INUSE 0x08000
270#define NVREG_MIICTL_WRITE 0x00400
271#define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData = 0x194,
273 NvRegWakeUpFlags = 0x200,
274#define NVREG_WAKEUPFLAGS_VAL 0x7770
275#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
276#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
277#define NVREG_WAKEUPFLAGS_D3SHIFT 12
278#define NVREG_WAKEUPFLAGS_D2SHIFT 8
279#define NVREG_WAKEUPFLAGS_D1SHIFT 4
280#define NVREG_WAKEUPFLAGS_D0SHIFT 0
281#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
282#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
283#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
284#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
285
286 NvRegPatternCRC = 0x204,
287 NvRegPatternMask = 0x208,
288 NvRegPowerCap = 0x268,
289#define NVREG_POWERCAP_D3SUPP (1<<30)
290#define NVREG_POWERCAP_D2SUPP (1<<26)
291#define NVREG_POWERCAP_D1SUPP (1<<25)
292 NvRegPowerState = 0x26c,
293#define NVREG_POWERSTATE_POWEREDUP 0x8000
294#define NVREG_POWERSTATE_VALID 0x0100
295#define NVREG_POWERSTATE_MASK 0x0003
296#define NVREG_POWERSTATE_D0 0x0000
297#define NVREG_POWERSTATE_D1 0x0001
298#define NVREG_POWERSTATE_D2 0x0002
299#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400300 NvRegTxCnt = 0x280,
301 NvRegTxZeroReXmt = 0x284,
302 NvRegTxOneReXmt = 0x288,
303 NvRegTxManyReXmt = 0x28c,
304 NvRegTxLateCol = 0x290,
305 NvRegTxUnderflow = 0x294,
306 NvRegTxLossCarrier = 0x298,
307 NvRegTxExcessDef = 0x29c,
308 NvRegTxRetryErr = 0x2a0,
309 NvRegRxFrameErr = 0x2a4,
310 NvRegRxExtraByte = 0x2a8,
311 NvRegRxLateCol = 0x2ac,
312 NvRegRxRunt = 0x2b0,
313 NvRegRxFrameTooLong = 0x2b4,
314 NvRegRxOverflow = 0x2b8,
315 NvRegRxFCSErr = 0x2bc,
316 NvRegRxFrameAlignErr = 0x2c0,
317 NvRegRxLenErr = 0x2c4,
318 NvRegRxUnicast = 0x2c8,
319 NvRegRxMulticast = 0x2cc,
320 NvRegRxBroadcast = 0x2d0,
321 NvRegTxDef = 0x2d4,
322 NvRegTxFrame = 0x2d8,
323 NvRegRxCnt = 0x2dc,
324 NvRegTxPause = 0x2e0,
325 NvRegRxPause = 0x2e4,
326 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500327 NvRegVlanControl = 0x300,
328#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500329 NvRegMSIXMap0 = 0x3e0,
330 NvRegMSIXMap1 = 0x3e4,
331 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400332
333 NvRegPowerState2 = 0x600,
334#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
335#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336};
337
338/* Big endian: should work, but is untested */
339struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700340 __le32 buf;
341 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342};
343
Manfred Spraulee733622005-07-31 18:32:26 +0200344struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700345 __le32 bufhigh;
346 __le32 buflow;
347 __le32 txvlan;
348 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200349};
350
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700351union ring_type {
Manfred Spraulee733622005-07-31 18:32:26 +0200352 struct ring_desc* orig;
353 struct ring_desc_ex* ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700354};
Manfred Spraulee733622005-07-31 18:32:26 +0200355
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356#define FLAG_MASK_V1 0xffff0000
357#define FLAG_MASK_V2 0xffffc000
358#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
359#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
360
361#define NV_TX_LASTPACKET (1<<16)
362#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700363#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200364#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365#define NV_TX_DEFERRED (1<<26)
366#define NV_TX_CARRIERLOST (1<<27)
367#define NV_TX_LATECOLLISION (1<<28)
368#define NV_TX_UNDERFLOW (1<<29)
369#define NV_TX_ERROR (1<<30)
370#define NV_TX_VALID (1<<31)
371
372#define NV_TX2_LASTPACKET (1<<29)
373#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700374#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200375#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376#define NV_TX2_DEFERRED (1<<25)
377#define NV_TX2_CARRIERLOST (1<<26)
378#define NV_TX2_LATECOLLISION (1<<27)
379#define NV_TX2_UNDERFLOW (1<<28)
380/* error and valid are the same for both */
381#define NV_TX2_ERROR (1<<30)
382#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400383#define NV_TX2_TSO (1<<28)
384#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800385#define NV_TX2_TSO_MAX_SHIFT 14
386#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400387#define NV_TX2_CHECKSUM_L3 (1<<27)
388#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500390#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
391
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392#define NV_RX_DESCRIPTORVALID (1<<16)
393#define NV_RX_MISSEDFRAME (1<<17)
394#define NV_RX_SUBSTRACT1 (1<<18)
395#define NV_RX_ERROR1 (1<<23)
396#define NV_RX_ERROR2 (1<<24)
397#define NV_RX_ERROR3 (1<<25)
398#define NV_RX_ERROR4 (1<<26)
399#define NV_RX_CRCERR (1<<27)
400#define NV_RX_OVERFLOW (1<<28)
401#define NV_RX_FRAMINGERR (1<<29)
402#define NV_RX_ERROR (1<<30)
403#define NV_RX_AVAIL (1<<31)
404
405#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500406#define NV_RX2_CHECKSUM_IP (0x10000000)
407#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
408#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409#define NV_RX2_DESCRIPTORVALID (1<<29)
410#define NV_RX2_SUBSTRACT1 (1<<25)
411#define NV_RX2_ERROR1 (1<<18)
412#define NV_RX2_ERROR2 (1<<19)
413#define NV_RX2_ERROR3 (1<<20)
414#define NV_RX2_ERROR4 (1<<21)
415#define NV_RX2_CRCERR (1<<22)
416#define NV_RX2_OVERFLOW (1<<23)
417#define NV_RX2_FRAMINGERR (1<<24)
418/* error and avail are the same for both */
419#define NV_RX2_ERROR (1<<30)
420#define NV_RX2_AVAIL (1<<31)
421
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500422#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
423#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
424
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425/* Miscelaneous hardware related defines: */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400426#define NV_PCI_REGSZ_VER1 0x270
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500427#define NV_PCI_REGSZ_VER2 0x2d4
428#define NV_PCI_REGSZ_VER3 0x604
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200429#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430
431/* various timeout delays: all in usec */
432#define NV_TXRX_RESET_DELAY 4
433#define NV_TXSTOP_DELAY1 10
434#define NV_TXSTOP_DELAY1MAX 500000
435#define NV_TXSTOP_DELAY2 100
436#define NV_RXSTOP_DELAY1 10
437#define NV_RXSTOP_DELAY1MAX 500000
438#define NV_RXSTOP_DELAY2 100
439#define NV_SETUP5_DELAY 5
440#define NV_SETUP5_DELAYMAX 50000
441#define NV_POWERUP_DELAY 5
442#define NV_POWERUP_DELAYMAX 5000
443#define NV_MIIBUSY_DELAY 50
444#define NV_MIIPHY_DELAY 10
445#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400446#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
448#define NV_WAKEUPPATTERNS 5
449#define NV_WAKEUPMASKENTRIES 4
450
451/* General driver defaults */
452#define NV_WATCHDOG_TIMEO (5*HZ)
453
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400454#define RX_RING_DEFAULT 128
455#define TX_RING_DEFAULT 256
456#define RX_RING_MIN 128
457#define TX_RING_MIN 64
458#define RING_MAX_DESC_VER_1 1024
459#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
461/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200462#define NV_RX_HEADERS (64)
463/* even more slack. */
464#define NV_RX_ALLOC_PAD (64)
465
466/* maximum mtu size */
467#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
468#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
470#define OOM_REFILL (1+HZ/20)
471#define POLL_WAIT (1+HZ/100)
472#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400473#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400475/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400477 * The nic supports three different descriptor types:
478 * - DESC_VER_1: Original
479 * - DESC_VER_2: support for jumbo frames.
480 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400482#define DESC_VER_1 1
483#define DESC_VER_2 2
484#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485
486/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400487#define PHY_OUI_MARVELL 0x5043
488#define PHY_OUI_CICADA 0x03f1
489#define PHY_OUI_VITESSE 0x01c1
490#define PHY_OUI_REALTEK 0x0732
491#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492#define PHYID1_OUI_MASK 0x03ff
493#define PHYID1_OUI_SHFT 6
494#define PHYID2_OUI_MASK 0xfc00
495#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400496#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400497#define PHY_MODEL_REALTEK_8211 0x0110
498#define PHY_REV_MASK 0x0001
499#define PHY_REV_REALTEK_8211B 0x0000
500#define PHY_REV_REALTEK_8211C 0x0001
501#define PHY_MODEL_REALTEK_8201 0x0200
502#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400503#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400504#define PHY_CICADA_INIT1 0x0f000
505#define PHY_CICADA_INIT2 0x0e00
506#define PHY_CICADA_INIT3 0x01000
507#define PHY_CICADA_INIT4 0x0200
508#define PHY_CICADA_INIT5 0x0004
509#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400510#define PHY_VITESSE_INIT_REG1 0x1f
511#define PHY_VITESSE_INIT_REG2 0x10
512#define PHY_VITESSE_INIT_REG3 0x11
513#define PHY_VITESSE_INIT_REG4 0x12
514#define PHY_VITESSE_INIT_MSK1 0xc
515#define PHY_VITESSE_INIT_MSK2 0x0180
516#define PHY_VITESSE_INIT1 0x52b5
517#define PHY_VITESSE_INIT2 0xaf8a
518#define PHY_VITESSE_INIT3 0x8
519#define PHY_VITESSE_INIT4 0x8f8a
520#define PHY_VITESSE_INIT5 0xaf86
521#define PHY_VITESSE_INIT6 0x8f86
522#define PHY_VITESSE_INIT7 0xaf82
523#define PHY_VITESSE_INIT8 0x0100
524#define PHY_VITESSE_INIT9 0x8f82
525#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400526#define PHY_REALTEK_INIT_REG1 0x1f
527#define PHY_REALTEK_INIT_REG2 0x19
528#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400529#define PHY_REALTEK_INIT_REG4 0x14
530#define PHY_REALTEK_INIT_REG5 0x18
531#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400532#define PHY_REALTEK_INIT1 0x0000
533#define PHY_REALTEK_INIT2 0x8e00
534#define PHY_REALTEK_INIT3 0x0001
535#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400536#define PHY_REALTEK_INIT5 0xfb54
537#define PHY_REALTEK_INIT6 0xf5c7
538#define PHY_REALTEK_INIT7 0x1000
539#define PHY_REALTEK_INIT8 0x0003
540#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400541
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542#define PHY_GIGABIT 0x0100
543
544#define PHY_TIMEOUT 0x1
545#define PHY_ERROR 0x2
546
547#define PHY_100 0x1
548#define PHY_1000 0x2
549#define PHY_HALF 0x100
550
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400551#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
552#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
553#define NV_PAUSEFRAME_RX_ENABLE 0x0004
554#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400555#define NV_PAUSEFRAME_RX_REQ 0x0010
556#define NV_PAUSEFRAME_TX_REQ 0x0020
557#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500559/* MSI/MSI-X defines */
560#define NV_MSI_X_MAX_VECTORS 8
561#define NV_MSI_X_VECTORS_MASK 0x000f
562#define NV_MSI_CAPABLE 0x0010
563#define NV_MSI_X_CAPABLE 0x0020
564#define NV_MSI_ENABLED 0x0040
565#define NV_MSI_X_ENABLED 0x0080
566
567#define NV_MSI_X_VECTOR_ALL 0x0
568#define NV_MSI_X_VECTOR_RX 0x0
569#define NV_MSI_X_VECTOR_TX 0x1
570#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500572#define NV_RESTART_TX 0x1
573#define NV_RESTART_RX 0x2
574
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500575#define NV_TX_LIMIT_COUNT 16
576
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400577/* statistics */
578struct nv_ethtool_str {
579 char name[ETH_GSTRING_LEN];
580};
581
582static const struct nv_ethtool_str nv_estats_str[] = {
583 { "tx_bytes" },
584 { "tx_zero_rexmt" },
585 { "tx_one_rexmt" },
586 { "tx_many_rexmt" },
587 { "tx_late_collision" },
588 { "tx_fifo_errors" },
589 { "tx_carrier_errors" },
590 { "tx_excess_deferral" },
591 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400592 { "rx_frame_error" },
593 { "rx_extra_byte" },
594 { "rx_late_collision" },
595 { "rx_runt" },
596 { "rx_frame_too_long" },
597 { "rx_over_errors" },
598 { "rx_crc_errors" },
599 { "rx_frame_align_error" },
600 { "rx_length_error" },
601 { "rx_unicast" },
602 { "rx_multicast" },
603 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400604 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500605 { "rx_errors_total" },
606 { "tx_errors_total" },
607
608 /* version 2 stats */
609 { "tx_deferral" },
610 { "tx_packets" },
611 { "rx_bytes" },
612 { "tx_pause" },
613 { "rx_pause" },
614 { "rx_drop_frame" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400615};
616
617struct nv_ethtool_stats {
618 u64 tx_bytes;
619 u64 tx_zero_rexmt;
620 u64 tx_one_rexmt;
621 u64 tx_many_rexmt;
622 u64 tx_late_collision;
623 u64 tx_fifo_errors;
624 u64 tx_carrier_errors;
625 u64 tx_excess_deferral;
626 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400627 u64 rx_frame_error;
628 u64 rx_extra_byte;
629 u64 rx_late_collision;
630 u64 rx_runt;
631 u64 rx_frame_too_long;
632 u64 rx_over_errors;
633 u64 rx_crc_errors;
634 u64 rx_frame_align_error;
635 u64 rx_length_error;
636 u64 rx_unicast;
637 u64 rx_multicast;
638 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400639 u64 rx_packets;
640 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500641 u64 tx_errors_total;
642
643 /* version 2 stats */
644 u64 tx_deferral;
645 u64 tx_packets;
646 u64 rx_bytes;
647 u64 tx_pause;
648 u64 rx_pause;
649 u64 rx_drop_frame;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400650};
651
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500652#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
653#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
654
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400655/* diagnostics */
656#define NV_TEST_COUNT_BASE 3
657#define NV_TEST_COUNT_EXTENDED 4
658
659static const struct nv_ethtool_str nv_etests_str[] = {
660 { "link (online/offline)" },
661 { "register (offline) " },
662 { "interrupt (offline) " },
663 { "loopback (offline) " }
664};
665
666struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000667 __u32 reg;
668 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400669};
670
671static const struct register_test nv_registers_test[] = {
672 { NvRegUnknownSetupReg6, 0x01 },
673 { NvRegMisc1, 0x03c },
674 { NvRegOffloadConfig, 0x03ff },
675 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400676 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400677 { NvRegWakeUpFlags, 0x07777 },
678 { 0,0 }
679};
680
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500681struct nv_skb_map {
682 struct sk_buff *skb;
683 dma_addr_t dma;
684 unsigned int dma_len;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500685 struct ring_desc_ex *first_tx_desc;
686 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500687};
688
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689/*
690 * SMP locking:
691 * All hardware access under dev->priv->lock, except the performance
692 * critical parts:
693 * - rx is (pseudo-) lockless: it relies on the single-threading provided
694 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700695 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 * needs dev->priv->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700697 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 */
699
700/* in dev: base, irq */
701struct fe_priv {
702 spinlock_t lock;
703
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700704 struct net_device *dev;
705 struct napi_struct napi;
706
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 /* General data:
708 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400709 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 int in_shutdown;
711 u32 linkspeed;
712 int duplex;
713 int autoneg;
714 int fixed_mode;
715 int phyaddr;
716 int wolenabled;
717 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400718 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400719 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400721 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500722 int recover_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723
724 /* General data: RO fields */
725 dma_addr_t ring_addr;
726 struct pci_dev *pci_dev;
727 u32 orig_mac[2];
728 u32 irqmask;
729 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400730 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500731 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400732 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400733 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400734 u32 register_size;
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -0400735 int rx_csum;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500736 u32 mac_in_use;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737
738 void __iomem *base;
739
740 /* rx specific fields.
741 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
742 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500743 union ring_type get_rx, put_rx, first_rx, last_rx;
744 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
745 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
746 struct nv_skb_map *rx_skb;
747
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700748 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200750 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 struct timer_list oom_kick;
752 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400753 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500754 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400755 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756
757 /* media detection workaround.
758 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
759 */
760 int need_linktimer;
761 unsigned long link_timeout;
762 /*
763 * tx specific fields.
764 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500765 union ring_type get_tx, put_tx, first_tx, last_tx;
766 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
767 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
768 struct nv_skb_map *tx_skb;
769
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700770 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400772 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500773 int tx_limit;
774 u32 tx_pkts_in_progress;
775 struct nv_skb_map *tx_change_owner;
776 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500777 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500778
779 /* vlan fields */
780 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500781
782 /* msi/msi-x fields */
783 u32 msi_flags;
784 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400785
786 /* flow control */
787 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200788
789 /* power saved state */
790 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791};
792
793/*
794 * Maximum number of loops until we assume that a bit in the irq mask
795 * is stuck. Overridable with module param.
796 */
797static int max_interrupt_work = 5;
798
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500799/*
800 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400801 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500802 * Throughput Mode: Every tx and rx packet will generate an interrupt.
803 * CPU Mode: Interrupts are controlled by a timer.
804 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400805enum {
806 NV_OPTIMIZATION_MODE_THROUGHPUT,
807 NV_OPTIMIZATION_MODE_CPU
808};
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500809static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
810
811/*
812 * Poll interval for timer irq
813 *
814 * This interval determines how frequent an interrupt is generated.
815 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
816 * Min = 0, and Max = 65535
817 */
818static int poll_interval = -1;
819
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500820/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400821 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500822 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400823enum {
824 NV_MSI_INT_DISABLED,
825 NV_MSI_INT_ENABLED
826};
827static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500828
829/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400830 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500831 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400832enum {
833 NV_MSIX_INT_DISABLED,
834 NV_MSIX_INT_ENABLED
835};
Ayaz Abdullacaf96462007-02-20 03:34:40 -0500836static int msix = NV_MSIX_INT_DISABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400837
838/*
839 * DMA 64bit
840 */
841enum {
842 NV_DMA_64BIT_DISABLED,
843 NV_DMA_64BIT_ENABLED
844};
845static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500846
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400847/*
848 * Crossover Detection
849 * Realtek 8201 phy + some OEM boards do not work properly.
850 */
851enum {
852 NV_CROSSOVER_DETECTION_DISABLED,
853 NV_CROSSOVER_DETECTION_ENABLED
854};
855static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
856
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857static inline struct fe_priv *get_nvpriv(struct net_device *dev)
858{
859 return netdev_priv(dev);
860}
861
862static inline u8 __iomem *get_hwbase(struct net_device *dev)
863{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400864 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865}
866
867static inline void pci_push(u8 __iomem *base)
868{
869 /* force out pending posted writes */
870 readl(base);
871}
872
873static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
874{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700875 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
877}
878
Manfred Spraulee733622005-07-31 18:32:26 +0200879static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
880{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700881 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200882}
883
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400884static bool nv_optimized(struct fe_priv *np)
885{
886 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
887 return false;
888 return true;
889}
890
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
892 int delay, int delaymax, const char *msg)
893{
894 u8 __iomem *base = get_hwbase(dev);
895
896 pci_push(base);
897 do {
898 udelay(delay);
899 delaymax -= delay;
900 if (delaymax < 0) {
901 if (msg)
902 printk(msg);
903 return 1;
904 }
905 } while ((readl(base + offset) & mask) != target);
906 return 0;
907}
908
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500909#define NV_SETUP_RX_RING 0x01
910#define NV_SETUP_TX_RING 0x02
911
Al Viro5bb7ea22007-12-09 16:06:41 +0000912static inline u32 dma_low(dma_addr_t addr)
913{
914 return addr;
915}
916
917static inline u32 dma_high(dma_addr_t addr)
918{
919 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
920}
921
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500922static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
923{
924 struct fe_priv *np = get_nvpriv(dev);
925 u8 __iomem *base = get_hwbase(dev);
926
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400927 if (!nv_optimized(np)) {
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500928 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000929 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500930 }
931 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000932 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500933 }
934 } else {
935 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000936 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
937 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500938 }
939 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000940 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
941 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500942 }
943 }
944}
945
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400946static void free_rings(struct net_device *dev)
947{
948 struct fe_priv *np = get_nvpriv(dev);
949
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400950 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700951 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400952 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
953 np->rx_ring.orig, np->ring_addr);
954 } else {
955 if (np->rx_ring.ex)
956 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
957 np->rx_ring.ex, np->ring_addr);
958 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500959 if (np->rx_skb)
960 kfree(np->rx_skb);
961 if (np->tx_skb)
962 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400963}
964
Ayaz Abdulla84b39322006-05-20 14:59:48 -0700965static int using_multi_irqs(struct net_device *dev)
966{
967 struct fe_priv *np = get_nvpriv(dev);
968
969 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
970 ((np->msi_flags & NV_MSI_X_ENABLED) &&
971 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
972 return 0;
973 else
974 return 1;
975}
976
977static void nv_enable_irq(struct net_device *dev)
978{
979 struct fe_priv *np = get_nvpriv(dev);
980
981 if (!using_multi_irqs(dev)) {
982 if (np->msi_flags & NV_MSI_X_ENABLED)
983 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
984 else
Manfred Spraula7475902007-10-17 21:52:33 +0200985 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -0700986 } else {
987 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
988 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
989 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
990 }
991}
992
993static void nv_disable_irq(struct net_device *dev)
994{
995 struct fe_priv *np = get_nvpriv(dev);
996
997 if (!using_multi_irqs(dev)) {
998 if (np->msi_flags & NV_MSI_X_ENABLED)
999 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1000 else
Manfred Spraula7475902007-10-17 21:52:33 +02001001 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001002 } else {
1003 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1004 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1005 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1006 }
1007}
1008
1009/* In MSIX mode, a write to irqmask behaves as XOR */
1010static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1011{
1012 u8 __iomem *base = get_hwbase(dev);
1013
1014 writel(mask, base + NvRegIrqMask);
1015}
1016
1017static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1018{
1019 struct fe_priv *np = get_nvpriv(dev);
1020 u8 __iomem *base = get_hwbase(dev);
1021
1022 if (np->msi_flags & NV_MSI_X_ENABLED) {
1023 writel(mask, base + NvRegIrqMask);
1024 } else {
1025 if (np->msi_flags & NV_MSI_ENABLED)
1026 writel(0, base + NvRegMSIIrqMask);
1027 writel(0, base + NvRegIrqMask);
1028 }
1029}
1030
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031#define MII_READ (-1)
1032/* mii_rw: read/write a register on the PHY.
1033 *
1034 * Caller must guarantee serialization
1035 */
1036static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1037{
1038 u8 __iomem *base = get_hwbase(dev);
1039 u32 reg;
1040 int retval;
1041
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001042 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043
1044 reg = readl(base + NvRegMIIControl);
1045 if (reg & NVREG_MIICTL_INUSE) {
1046 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1047 udelay(NV_MIIBUSY_DELAY);
1048 }
1049
1050 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1051 if (value != MII_READ) {
1052 writel(value, base + NvRegMIIData);
1053 reg |= NVREG_MIICTL_WRITE;
1054 }
1055 writel(reg, base + NvRegMIIControl);
1056
1057 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1058 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1059 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1060 dev->name, miireg, addr);
1061 retval = -1;
1062 } else if (value != MII_READ) {
1063 /* it was a write operation - fewer failures are detectable */
1064 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1065 dev->name, value, miireg, addr);
1066 retval = 0;
1067 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1068 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1069 dev->name, miireg, addr);
1070 retval = -1;
1071 } else {
1072 retval = readl(base + NvRegMIIData);
1073 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1074 dev->name, miireg, addr, retval);
1075 }
1076
1077 return retval;
1078}
1079
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001080static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001082 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 u32 miicontrol;
1084 unsigned int tries = 0;
1085
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001086 miicontrol = BMCR_RESET | bmcr_setup;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1088 return -1;
1089 }
1090
1091 /* wait for 500ms */
1092 msleep(500);
1093
1094 /* must wait till reset is deasserted */
1095 while (miicontrol & BMCR_RESET) {
1096 msleep(10);
1097 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1098 /* FIXME: 100 tries seem excessive */
1099 if (tries++ > 100)
1100 return -1;
1101 }
1102 return 0;
1103}
1104
1105static int phy_init(struct net_device *dev)
1106{
1107 struct fe_priv *np = get_nvpriv(dev);
1108 u8 __iomem *base = get_hwbase(dev);
1109 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1110
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001111 /* phy errata for E3016 phy */
1112 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1113 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1114 reg &= ~PHY_MARVELL_E3016_INITMASK;
1115 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1116 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1117 return PHY_ERROR;
1118 }
1119 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001120 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001121 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1122 np->phy_rev == PHY_REV_REALTEK_8211B) {
1123 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1124 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1125 return PHY_ERROR;
1126 }
1127 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1128 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1129 return PHY_ERROR;
1130 }
1131 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1132 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1133 return PHY_ERROR;
1134 }
1135 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1136 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137 return PHY_ERROR;
1138 }
1139 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1140 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1141 return PHY_ERROR;
1142 }
1143 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1144 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145 return PHY_ERROR;
1146 }
1147 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1148 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149 return PHY_ERROR;
1150 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001151 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001152 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1153 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1154 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1155 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1156 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1157 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1158 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1159 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1160 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1161 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1162 phy_reserved |= PHY_REALTEK_INIT7;
1163 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1164 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165 return PHY_ERROR;
1166 }
1167 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001168 }
1169 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001170
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 /* set advertise register */
1172 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001173 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001174 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1175 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1176 return PHY_ERROR;
1177 }
1178
1179 /* get phy interface type */
1180 phyinterface = readl(base + NvRegPhyInterface);
1181
1182 /* see if gigabit phy */
1183 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1184 if (mii_status & PHY_GIGABIT) {
1185 np->gigabit = PHY_GIGABIT;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001186 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187 mii_control_1000 &= ~ADVERTISE_1000HALF;
1188 if (phyinterface & PHY_RGMII)
1189 mii_control_1000 |= ADVERTISE_1000FULL;
1190 else
1191 mii_control_1000 &= ~ADVERTISE_1000FULL;
1192
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001193 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1195 return PHY_ERROR;
1196 }
1197 }
1198 else
1199 np->gigabit = 0;
1200
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001201 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1202 mii_control |= BMCR_ANENABLE;
1203
1204 /* reset the phy
1205 * (certain phys need bmcr to be setup with reset)
1206 */
1207 if (phy_reset(dev, mii_control)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211
1212 /* phy vendor specific configuration */
1213 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1214 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001215 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1216 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1218 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219 return PHY_ERROR;
1220 }
1221 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001222 phy_reserved |= PHY_CICADA_INIT5;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1224 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225 return PHY_ERROR;
1226 }
1227 }
1228 if (np->phy_oui == PHY_OUI_CICADA) {
1229 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001230 phy_reserved |= PHY_CICADA_INIT6;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1232 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233 return PHY_ERROR;
1234 }
1235 }
Ayaz Abdullad215d8a2007-07-15 06:50:53 -04001236 if (np->phy_oui == PHY_OUI_VITESSE) {
1237 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1238 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239 return PHY_ERROR;
1240 }
1241 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1242 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1243 return PHY_ERROR;
1244 }
1245 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1246 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1247 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1248 return PHY_ERROR;
1249 }
1250 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1251 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1252 phy_reserved |= PHY_VITESSE_INIT3;
1253 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1254 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255 return PHY_ERROR;
1256 }
1257 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1258 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259 return PHY_ERROR;
1260 }
1261 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1262 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1263 return PHY_ERROR;
1264 }
1265 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1266 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1267 phy_reserved |= PHY_VITESSE_INIT3;
1268 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1269 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270 return PHY_ERROR;
1271 }
1272 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1273 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1274 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275 return PHY_ERROR;
1276 }
1277 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1278 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1279 return PHY_ERROR;
1280 }
1281 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1282 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1283 return PHY_ERROR;
1284 }
1285 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1286 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1287 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1288 return PHY_ERROR;
1289 }
1290 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1291 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1292 phy_reserved |= PHY_VITESSE_INIT8;
1293 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1294 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1295 return PHY_ERROR;
1296 }
1297 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1298 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1299 return PHY_ERROR;
1300 }
1301 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1302 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1303 return PHY_ERROR;
1304 }
1305 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001306 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001307 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1308 np->phy_rev == PHY_REV_REALTEK_8211B) {
1309 /* reset could have cleared these out, set them back */
1310 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1311 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1312 return PHY_ERROR;
1313 }
1314 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1315 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1316 return PHY_ERROR;
1317 }
1318 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1319 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1320 return PHY_ERROR;
1321 }
1322 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1323 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324 return PHY_ERROR;
1325 }
1326 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1327 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328 return PHY_ERROR;
1329 }
1330 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1331 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332 return PHY_ERROR;
1333 }
1334 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1335 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336 return PHY_ERROR;
1337 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001338 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001339 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1340 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1341 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1342 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1343 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1344 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1345 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1346 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1347 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1348 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1349 phy_reserved |= PHY_REALTEK_INIT7;
1350 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1351 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1352 return PHY_ERROR;
1353 }
1354 }
1355 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1356 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1357 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1358 return PHY_ERROR;
1359 }
1360 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1361 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1362 phy_reserved |= PHY_REALTEK_INIT3;
1363 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1364 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365 return PHY_ERROR;
1366 }
1367 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1368 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369 return PHY_ERROR;
1370 }
1371 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001372 }
1373 }
1374
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001375 /* some phys clear out pause advertisment on reset, set it back */
1376 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
1378 /* restart auto negotiation */
1379 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1380 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1381 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1382 return PHY_ERROR;
1383 }
1384
1385 return 0;
1386}
1387
1388static void nv_start_rx(struct net_device *dev)
1389{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001390 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001391 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001392 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393
1394 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1395 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001396 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1397 rx_ctrl &= ~NVREG_RCVCTL_START;
1398 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 pci_push(base);
1400 }
1401 writel(np->linkspeed, base + NvRegLinkSpeed);
1402 pci_push(base);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001403 rx_ctrl |= NVREG_RCVCTL_START;
1404 if (np->mac_in_use)
1405 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1406 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1408 dev->name, np->duplex, np->linkspeed);
1409 pci_push(base);
1410}
1411
1412static void nv_stop_rx(struct net_device *dev)
1413{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001414 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001416 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417
1418 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001419 if (!np->mac_in_use)
1420 rx_ctrl &= ~NVREG_RCVCTL_START;
1421 else
1422 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1423 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1425 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1426 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1427
1428 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001429 if (!np->mac_in_use)
1430 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431}
1432
1433static void nv_start_tx(struct net_device *dev)
1434{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001435 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001437 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438
1439 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001440 tx_ctrl |= NVREG_XMITCTL_START;
1441 if (np->mac_in_use)
1442 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1443 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 pci_push(base);
1445}
1446
1447static void nv_stop_tx(struct net_device *dev)
1448{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001449 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001451 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452
1453 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001454 if (!np->mac_in_use)
1455 tx_ctrl &= ~NVREG_XMITCTL_START;
1456 else
1457 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1458 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1460 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1461 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1462
1463 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001464 if (!np->mac_in_use)
1465 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1466 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467}
1468
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001469static void nv_start_rxtx(struct net_device *dev)
1470{
1471 nv_start_rx(dev);
1472 nv_start_tx(dev);
1473}
1474
1475static void nv_stop_rxtx(struct net_device *dev)
1476{
1477 nv_stop_rx(dev);
1478 nv_stop_tx(dev);
1479}
1480
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481static void nv_txrx_reset(struct net_device *dev)
1482{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001483 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484 u8 __iomem *base = get_hwbase(dev);
1485
1486 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001487 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488 pci_push(base);
1489 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001490 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491 pci_push(base);
1492}
1493
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001494static void nv_mac_reset(struct net_device *dev)
1495{
1496 struct fe_priv *np = netdev_priv(dev);
1497 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001498 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001499
1500 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001501
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001502 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1503 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001504
1505 /* save registers since they will be cleared on reset */
1506 temp1 = readl(base + NvRegMacAddrA);
1507 temp2 = readl(base + NvRegMacAddrB);
1508 temp3 = readl(base + NvRegTransmitPoll);
1509
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001510 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1511 pci_push(base);
1512 udelay(NV_MAC_RESET_DELAY);
1513 writel(0, base + NvRegMacReset);
1514 pci_push(base);
1515 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001516
1517 /* restore saved registers */
1518 writel(temp1, base + NvRegMacAddrA);
1519 writel(temp2, base + NvRegMacAddrB);
1520 writel(temp3, base + NvRegTransmitPoll);
1521
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001522 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1523 pci_push(base);
1524}
1525
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001526static void nv_get_hw_stats(struct net_device *dev)
1527{
1528 struct fe_priv *np = netdev_priv(dev);
1529 u8 __iomem *base = get_hwbase(dev);
1530
1531 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1532 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1533 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1534 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1535 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1536 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1537 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1538 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1539 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1540 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1541 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1542 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1543 np->estats.rx_runt += readl(base + NvRegRxRunt);
1544 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1545 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1546 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1547 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1548 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1549 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1550 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1551 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1552 np->estats.rx_packets =
1553 np->estats.rx_unicast +
1554 np->estats.rx_multicast +
1555 np->estats.rx_broadcast;
1556 np->estats.rx_errors_total =
1557 np->estats.rx_crc_errors +
1558 np->estats.rx_over_errors +
1559 np->estats.rx_frame_error +
1560 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1561 np->estats.rx_late_collision +
1562 np->estats.rx_runt +
1563 np->estats.rx_frame_too_long;
1564 np->estats.tx_errors_total =
1565 np->estats.tx_late_collision +
1566 np->estats.tx_fifo_errors +
1567 np->estats.tx_carrier_errors +
1568 np->estats.tx_excess_deferral +
1569 np->estats.tx_retry_error;
1570
1571 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1572 np->estats.tx_deferral += readl(base + NvRegTxDef);
1573 np->estats.tx_packets += readl(base + NvRegTxFrame);
1574 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1575 np->estats.tx_pause += readl(base + NvRegTxPause);
1576 np->estats.rx_pause += readl(base + NvRegRxPause);
1577 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1578 }
1579}
1580
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581/*
1582 * nv_get_stats: dev->get_stats function
1583 * Get latest stats value from the nic.
1584 * Called with read_lock(&dev_base_lock) held for read -
1585 * only synchronized against unregister_netdevice.
1586 */
1587static struct net_device_stats *nv_get_stats(struct net_device *dev)
1588{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001589 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001590
Ayaz Abdulla21828162007-01-23 12:27:21 -05001591 /* If the nic supports hw counters then retrieve latest values */
1592 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1593 nv_get_hw_stats(dev);
1594
1595 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001596 dev->stats.tx_bytes = np->estats.tx_bytes;
1597 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1598 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1599 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1600 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1601 dev->stats.rx_errors = np->estats.rx_errors_total;
1602 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001603 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001604
1605 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606}
1607
1608/*
1609 * nv_alloc_rx: fill rx ring entries.
1610 * Return 1 if the allocations for the skbs failed and the
1611 * rx engine is without Available descriptors
1612 */
1613static int nv_alloc_rx(struct net_device *dev)
1614{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001615 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001616 struct ring_desc* less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001617
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001618 less_rx = np->get_rx.orig;
1619 if (less_rx-- == np->first_rx.orig)
1620 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001621
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001622 while (np->put_rx.orig != less_rx) {
1623 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001624 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001625 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001626 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1627 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001628 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001629 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001630 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001631 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1632 wmb();
1633 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001634 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001635 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001636 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001637 np->put_rx_ctx = np->first_rx_ctx;
1638 } else {
1639 return 1;
1640 }
1641 }
1642 return 0;
1643}
1644
1645static int nv_alloc_rx_optimized(struct net_device *dev)
1646{
1647 struct fe_priv *np = netdev_priv(dev);
1648 struct ring_desc_ex* less_rx;
1649
1650 less_rx = np->get_rx.ex;
1651 if (less_rx-- == np->first_rx.ex)
1652 less_rx = np->last_rx.ex;
1653
1654 while (np->put_rx.ex != less_rx) {
1655 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1656 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001657 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001658 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1659 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001660 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001661 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001662 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001663 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1664 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001665 wmb();
1666 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001667 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001668 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001669 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001670 np->put_rx_ctx = np->first_rx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671 } else {
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001672 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675 return 0;
1676}
1677
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001678/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1679#ifdef CONFIG_FORCEDETH_NAPI
1680static void nv_do_rx_refill(unsigned long data)
1681{
1682 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001683 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001684
1685 /* Just reschedule NAPI rx processing */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001686 netif_rx_schedule(dev, &np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001687}
1688#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689static void nv_do_rx_refill(unsigned long data)
1690{
1691 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001692 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001693 int retcode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001694
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001695 if (!using_multi_irqs(dev)) {
1696 if (np->msi_flags & NV_MSI_X_ENABLED)
1697 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1698 else
Manfred Spraula7475902007-10-17 21:52:33 +02001699 disable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05001700 } else {
1701 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1702 }
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001703 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001704 retcode = nv_alloc_rx(dev);
1705 else
1706 retcode = nv_alloc_rx_optimized(dev);
1707 if (retcode) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001708 spin_lock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709 if (!np->in_shutdown)
1710 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001711 spin_unlock_irq(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001712 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001713 if (!using_multi_irqs(dev)) {
1714 if (np->msi_flags & NV_MSI_X_ENABLED)
1715 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1716 else
Manfred Spraula7475902007-10-17 21:52:33 +02001717 enable_irq(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05001718 } else {
1719 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1720 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001722#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001724static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001725{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001726 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001727 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001728
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001729 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001730
1731 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001732 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1733 else
1734 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1735 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1736 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001737
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001738 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001739 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001740 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001741 np->rx_ring.orig[i].buf = 0;
1742 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001743 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001744 np->rx_ring.ex[i].txvlan = 0;
1745 np->rx_ring.ex[i].bufhigh = 0;
1746 np->rx_ring.ex[i].buflow = 0;
1747 }
1748 np->rx_skb[i].skb = NULL;
1749 np->rx_skb[i].dma = 0;
1750 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001751}
1752
1753static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001754{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001755 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001756 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001757
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001758 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001759
1760 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001761 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1762 else
1763 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1764 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1765 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001766 np->tx_pkts_in_progress = 0;
1767 np->tx_change_owner = NULL;
1768 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001770 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001771 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001772 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001773 np->tx_ring.orig[i].buf = 0;
1774 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001775 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001776 np->tx_ring.ex[i].txvlan = 0;
1777 np->tx_ring.ex[i].bufhigh = 0;
1778 np->tx_ring.ex[i].buflow = 0;
1779 }
1780 np->tx_skb[i].skb = NULL;
1781 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001782 np->tx_skb[i].dma_len = 0;
1783 np->tx_skb[i].first_tx_desc = NULL;
1784 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001785 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001786}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787
Manfred Sprauld81c0982005-07-31 18:20:30 +02001788static int nv_init_ring(struct net_device *dev)
1789{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001790 struct fe_priv *np = netdev_priv(dev);
1791
Manfred Sprauld81c0982005-07-31 18:20:30 +02001792 nv_init_tx(dev);
1793 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001794
1795 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001796 return nv_alloc_rx(dev);
1797 else
1798 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001799}
1800
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001801static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001802{
1803 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08001804
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001805 if (tx_skb->dma) {
1806 pci_unmap_page(np->pci_dev, tx_skb->dma,
1807 tx_skb->dma_len,
Ayaz Abdullafa454592006-01-05 22:45:45 -08001808 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001809 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001810 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001811 if (tx_skb->skb) {
1812 dev_kfree_skb_any(tx_skb->skb);
1813 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001814 return 1;
1815 } else {
1816 return 0;
1817 }
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001818}
1819
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820static void nv_drain_tx(struct net_device *dev)
1821{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001822 struct fe_priv *np = netdev_priv(dev);
1823 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001824
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001825 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001826 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001827 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001828 np->tx_ring.orig[i].buf = 0;
1829 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001830 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001831 np->tx_ring.ex[i].txvlan = 0;
1832 np->tx_ring.ex[i].bufhigh = 0;
1833 np->tx_ring.ex[i].buflow = 0;
1834 }
1835 if (nv_release_txskb(dev, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001836 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001837 np->tx_skb[i].dma = 0;
1838 np->tx_skb[i].dma_len = 0;
1839 np->tx_skb[i].first_tx_desc = NULL;
1840 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001841 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001842 np->tx_pkts_in_progress = 0;
1843 np->tx_change_owner = NULL;
1844 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845}
1846
1847static void nv_drain_rx(struct net_device *dev)
1848{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001849 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001851
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001852 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001853 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001854 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001855 np->rx_ring.orig[i].buf = 0;
1856 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001857 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001858 np->rx_ring.ex[i].txvlan = 0;
1859 np->rx_ring.ex[i].bufhigh = 0;
1860 np->rx_ring.ex[i].buflow = 0;
1861 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001862 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001863 if (np->rx_skb[i].skb) {
1864 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001865 (skb_end_pointer(np->rx_skb[i].skb) -
1866 np->rx_skb[i].skb->data),
1867 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001868 dev_kfree_skb(np->rx_skb[i].skb);
1869 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870 }
1871 }
1872}
1873
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001874static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875{
1876 nv_drain_tx(dev);
1877 nv_drain_rx(dev);
1878}
1879
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001880static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1881{
1882 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1883}
1884
Ayaz Abdullaa4336862008-04-18 13:50:43 -07001885static void nv_legacybackoff_reseed(struct net_device *dev)
1886{
1887 u8 __iomem *base = get_hwbase(dev);
1888 u32 reg;
1889 u32 low;
1890 int tx_status = 0;
1891
1892 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1893 get_random_bytes(&low, sizeof(low));
1894 reg |= low & NVREG_SLOTTIME_MASK;
1895
1896 /* Need to stop tx before change takes effect.
1897 * Caller has already gained np->lock.
1898 */
1899 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1900 if (tx_status)
1901 nv_stop_tx(dev);
1902 nv_stop_rx(dev);
1903 writel(reg, base + NvRegSlotTime);
1904 if (tx_status)
1905 nv_start_tx(dev);
1906 nv_start_rx(dev);
1907}
1908
1909/* Gear Backoff Seeds */
1910#define BACKOFF_SEEDSET_ROWS 8
1911#define BACKOFF_SEEDSET_LFSRS 15
1912
1913/* Known Good seed sets */
1914static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1915 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1916 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1917 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1918 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1919 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1920 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1921 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1922 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1923
1924static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1925 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1926 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1928 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1929 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1930 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1931 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1932 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1933
1934static void nv_gear_backoff_reseed(struct net_device *dev)
1935{
1936 u8 __iomem *base = get_hwbase(dev);
1937 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
1938 u32 temp, seedset, combinedSeed;
1939 int i;
1940
1941 /* Setup seed for free running LFSR */
1942 /* We are going to read the time stamp counter 3 times
1943 and swizzle bits around to increase randomness */
1944 get_random_bytes(&miniseed1, sizeof(miniseed1));
1945 miniseed1 &= 0x0fff;
1946 if (miniseed1 == 0)
1947 miniseed1 = 0xabc;
1948
1949 get_random_bytes(&miniseed2, sizeof(miniseed2));
1950 miniseed2 &= 0x0fff;
1951 if (miniseed2 == 0)
1952 miniseed2 = 0xabc;
1953 miniseed2_reversed =
1954 ((miniseed2 & 0xF00) >> 8) |
1955 (miniseed2 & 0x0F0) |
1956 ((miniseed2 & 0x00F) << 8);
1957
1958 get_random_bytes(&miniseed3, sizeof(miniseed3));
1959 miniseed3 &= 0x0fff;
1960 if (miniseed3 == 0)
1961 miniseed3 = 0xabc;
1962 miniseed3_reversed =
1963 ((miniseed3 & 0xF00) >> 8) |
1964 (miniseed3 & 0x0F0) |
1965 ((miniseed3 & 0x00F) << 8);
1966
1967 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
1968 (miniseed2 ^ miniseed3_reversed);
1969
1970 /* Seeds can not be zero */
1971 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
1972 combinedSeed |= 0x08;
1973 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
1974 combinedSeed |= 0x8000;
1975
1976 /* No need to disable tx here */
1977 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
1978 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
1979 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
1980 writel(temp,base + NvRegBackOffControl);
1981
1982 /* Setup seeds for all gear LFSRs. */
1983 get_random_bytes(&seedset, sizeof(seedset));
1984 seedset = seedset % BACKOFF_SEEDSET_ROWS;
1985 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
1986 {
1987 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
1988 temp |= main_seedset[seedset][i-1] & 0x3ff;
1989 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
1990 writel(temp, base + NvRegBackOffControl);
1991 }
1992}
1993
Linus Torvalds1da177e2005-04-16 15:20:36 -07001994/*
1995 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07001996 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001997 */
1998static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1999{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002000 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002001 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002002 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2003 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002004 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002005 u32 offset = 0;
2006 u32 bcnt;
2007 u32 size = skb->len-skb->data_len;
2008 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002009 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002010 struct ring_desc* put_tx;
2011 struct ring_desc* start_tx;
2012 struct ring_desc* prev_tx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002013 struct nv_skb_map* prev_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002014 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002015
2016 /* add fragments to entries count */
2017 for (i = 0; i < fragments; i++) {
2018 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2019 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2020 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002022 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002023 if (unlikely(empty_slots <= entries)) {
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002024 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002025 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002026 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002027 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002028 return NETDEV_TX_BUSY;
2029 }
2030
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002031 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002032
Ayaz Abdullafa454592006-01-05 22:45:45 -08002033 /* setup the header buffer */
2034 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002035 prev_tx = put_tx;
2036 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002037 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002038 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002039 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002040 np->put_tx_ctx->dma_len = bcnt;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002041 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2042 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002043
Ayaz Abdullafa454592006-01-05 22:45:45 -08002044 tx_flags = np->tx_flags;
2045 offset += bcnt;
2046 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002047 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002048 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002049 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002050 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002051 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002052
2053 /* setup the fragments */
2054 for (i = 0; i < fragments; i++) {
2055 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2056 u32 size = frag->size;
2057 offset = 0;
2058
2059 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002060 prev_tx = put_tx;
2061 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002062 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002063 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2064 PCI_DMA_TODEVICE);
2065 np->put_tx_ctx->dma_len = bcnt;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002066 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2067 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002068
Ayaz Abdullafa454592006-01-05 22:45:45 -08002069 offset += bcnt;
2070 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002071 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002072 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002073 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002074 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002075 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002076 }
2077
Ayaz Abdullafa454592006-01-05 22:45:45 -08002078 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002079 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002080
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002081 /* save skb in this slot's context area */
2082 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002083
Herbert Xu89114af2006-07-08 13:34:32 -07002084 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002085 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002086 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002087 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002088 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002089
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002090 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002091
Ayaz Abdullafa454592006-01-05 22:45:45 -08002092 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002093 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2094 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002095
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002096 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002097
2098 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2099 dev->name, entries, tx_flags_extra);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002100 {
2101 int j;
2102 for (j=0; j<64; j++) {
2103 if ((j%16) == 0)
2104 dprintk("\n%03x:", j);
2105 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2106 }
2107 dprintk("\n");
2108 }
2109
Linus Torvalds1da177e2005-04-16 15:20:36 -07002110 dev->trans_start = jiffies;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002111 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002112 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002113}
2114
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002115static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2116{
2117 struct fe_priv *np = netdev_priv(dev);
2118 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002119 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002120 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2121 unsigned int i;
2122 u32 offset = 0;
2123 u32 bcnt;
2124 u32 size = skb->len-skb->data_len;
2125 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2126 u32 empty_slots;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002127 struct ring_desc_ex* put_tx;
2128 struct ring_desc_ex* start_tx;
2129 struct ring_desc_ex* prev_tx;
2130 struct nv_skb_map* prev_tx_ctx;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002131 struct nv_skb_map* start_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002132 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002133
2134 /* add fragments to entries count */
2135 for (i = 0; i < fragments; i++) {
2136 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2137 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2138 }
2139
2140 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002141 if (unlikely(empty_slots <= entries)) {
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002142 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002143 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002144 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002145 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002146 return NETDEV_TX_BUSY;
2147 }
2148
2149 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002150 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002151
2152 /* setup the header buffer */
2153 do {
2154 prev_tx = put_tx;
2155 prev_tx_ctx = np->put_tx_ctx;
2156 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2157 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2158 PCI_DMA_TODEVICE);
2159 np->put_tx_ctx->dma_len = bcnt;
Al Viro5bb7ea22007-12-09 16:06:41 +00002160 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2161 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002162 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002163
2164 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002165 offset += bcnt;
2166 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002167 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002168 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002169 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002170 np->put_tx_ctx = np->first_tx_ctx;
2171 } while (size);
2172
2173 /* setup the fragments */
2174 for (i = 0; i < fragments; i++) {
2175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2176 u32 size = frag->size;
2177 offset = 0;
2178
2179 do {
2180 prev_tx = put_tx;
2181 prev_tx_ctx = np->put_tx_ctx;
2182 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2183 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2184 PCI_DMA_TODEVICE);
2185 np->put_tx_ctx->dma_len = bcnt;
Al Viro5bb7ea22007-12-09 16:06:41 +00002186 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2187 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002188 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002189
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002190 offset += bcnt;
2191 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002192 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002193 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002194 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002195 np->put_tx_ctx = np->first_tx_ctx;
2196 } while (size);
2197 }
2198
2199 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002200 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002201
2202 /* save skb in this slot's context area */
2203 prev_tx_ctx->skb = skb;
2204
2205 if (skb_is_gso(skb))
2206 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2207 else
2208 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2209 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2210
2211 /* vlan tag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002212 if (likely(!np->vlangrp)) {
2213 start_tx->txvlan = 0;
2214 } else {
2215 if (vlan_tx_tag_present(skb))
2216 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2217 else
2218 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002219 }
2220
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002221 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002222
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002223 if (np->tx_limit) {
2224 /* Limit the number of outstanding tx. Setup all fragments, but
2225 * do not set the VALID bit on the first descriptor. Save a pointer
2226 * to that descriptor and also for next skb_map element.
2227 */
2228
2229 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2230 if (!np->tx_change_owner)
2231 np->tx_change_owner = start_tx_ctx;
2232
2233 /* remove VALID bit */
2234 tx_flags &= ~NV_TX2_VALID;
2235 start_tx_ctx->first_tx_desc = start_tx;
2236 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2237 np->tx_end_flip = np->put_tx_ctx;
2238 } else {
2239 np->tx_pkts_in_progress++;
2240 }
2241 }
2242
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002243 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002244 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2245 np->put_tx.ex = put_tx;
2246
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002247 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002248
2249 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2250 dev->name, entries, tx_flags_extra);
2251 {
2252 int j;
2253 for (j=0; j<64; j++) {
2254 if ((j%16) == 0)
2255 dprintk("\n%03x:", j);
2256 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2257 }
2258 dprintk("\n");
2259 }
2260
2261 dev->trans_start = jiffies;
2262 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002263 return NETDEV_TX_OK;
2264}
2265
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002266static inline void nv_tx_flip_ownership(struct net_device *dev)
2267{
2268 struct fe_priv *np = netdev_priv(dev);
2269
2270 np->tx_pkts_in_progress--;
2271 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002272 np->tx_change_owner->first_tx_desc->flaglen |=
2273 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002274 np->tx_pkts_in_progress++;
2275
2276 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2277 if (np->tx_change_owner == np->tx_end_flip)
2278 np->tx_change_owner = NULL;
2279
2280 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2281 }
2282}
2283
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284/*
2285 * nv_tx_done: check for completed packets, release the skbs.
2286 *
2287 * Caller must own np->lock.
2288 */
2289static void nv_tx_done(struct net_device *dev)
2290{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002291 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002292 u32 flags;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002293 struct ring_desc* orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002294
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002295 while ((np->get_tx.orig != np->put_tx.orig) &&
2296 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002297
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002298 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2299 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002300
2301 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2302 np->get_tx_ctx->dma_len,
2303 PCI_DMA_TODEVICE);
2304 np->get_tx_ctx->dma = 0;
2305
Linus Torvalds1da177e2005-04-16 15:20:36 -07002306 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002307 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002308 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002309 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002310 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002311 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002312 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002313 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2314 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002315 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002316 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002317 dev->stats.tx_packets++;
2318 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002319 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002320 dev_kfree_skb_any(np->get_tx_ctx->skb);
2321 np->get_tx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002322 }
2323 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002324 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002325 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002326 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002327 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002328 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002329 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002330 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2331 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002332 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002333 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002334 dev->stats.tx_packets++;
2335 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002336 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002337 dev_kfree_skb_any(np->get_tx_ctx->skb);
2338 np->get_tx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002339 }
2340 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002341 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002342 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002343 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002344 np->get_tx_ctx = np->first_tx_ctx;
2345 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002346 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002347 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002348 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002349 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002350}
2351
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002352static void nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002353{
2354 struct fe_priv *np = netdev_priv(dev);
2355 u32 flags;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002356 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002357
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002358 while ((np->get_tx.ex != np->put_tx.ex) &&
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002359 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2360 (limit-- > 0)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002361
2362 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2363 dev->name, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002364
2365 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2366 np->get_tx_ctx->dma_len,
2367 PCI_DMA_TODEVICE);
2368 np->get_tx_ctx->dma = 0;
2369
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002370 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002371 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002372 dev->stats.tx_packets++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002373 else {
2374 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2375 if (np->driver_data & DEV_HAS_GEAR_MODE)
2376 nv_gear_backoff_reseed(dev);
2377 else
2378 nv_legacybackoff_reseed(dev);
2379 }
2380 }
2381
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002382 dev_kfree_skb_any(np->get_tx_ctx->skb);
2383 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002384
2385 if (np->tx_limit) {
2386 nv_tx_flip_ownership(dev);
2387 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002388 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002389 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002390 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002391 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002392 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002393 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002394 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002395 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002396 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002397 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002398}
2399
2400/*
2401 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002402 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002403 */
2404static void nv_tx_timeout(struct net_device *dev)
2405{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002406 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002408 u32 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002409
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002410 if (np->msi_flags & NV_MSI_X_ENABLED)
2411 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2412 else
2413 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2414
2415 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416
Manfred Spraulc2dba062005-07-31 18:29:47 +02002417 {
2418 int i;
2419
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002420 printk(KERN_INFO "%s: Ring at %lx\n",
2421 dev->name, (unsigned long)np->ring_addr);
Manfred Spraulc2dba062005-07-31 18:29:47 +02002422 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04002423 for (i=0;i<=np->register_size;i+= 32) {
Manfred Spraulc2dba062005-07-31 18:29:47 +02002424 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2425 i,
2426 readl(base + i + 0), readl(base + i + 4),
2427 readl(base + i + 8), readl(base + i + 12),
2428 readl(base + i + 16), readl(base + i + 20),
2429 readl(base + i + 24), readl(base + i + 28));
2430 }
2431 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002432 for (i=0;i<np->tx_ring_size;i+= 4) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002433 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02002434 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002435 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002436 le32_to_cpu(np->tx_ring.orig[i].buf),
2437 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2438 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2439 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2440 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2441 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2442 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2443 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002444 } else {
2445 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002446 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002447 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2448 le32_to_cpu(np->tx_ring.ex[i].buflow),
2449 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2450 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2451 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2452 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2453 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2454 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2455 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2456 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2457 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2458 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002459 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002460 }
2461 }
2462
Linus Torvalds1da177e2005-04-16 15:20:36 -07002463 spin_lock_irq(&np->lock);
2464
2465 /* 1) stop tx engine */
2466 nv_stop_tx(dev);
2467
2468 /* 2) check that the packets were not sent already: */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002469 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002470 nv_tx_done(dev);
2471 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002472 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473
2474 /* 3) if there are dead entries: clear everything */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002475 if (np->get_tx_ctx != np->put_tx_ctx) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002476 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2477 nv_drain_tx(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002478 nv_init_tx(dev);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002479 setup_hw_rings(dev, NV_SETUP_TX_RING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002480 }
2481
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002482 netif_wake_queue(dev);
2483
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484 /* 4) restart tx engine */
2485 nv_start_tx(dev);
2486 spin_unlock_irq(&np->lock);
2487}
2488
Manfred Spraul22c6d142005-04-19 21:17:09 +02002489/*
2490 * Called when the nic notices a mismatch between the actual data len on the
2491 * wire and the len indicated in the 802 header
2492 */
2493static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2494{
2495 int hdrlen; /* length of the 802 header */
2496 int protolen; /* length as stored in the proto field */
2497
2498 /* 1) calculate len according to header */
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002499 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
Manfred Spraul22c6d142005-04-19 21:17:09 +02002500 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2501 hdrlen = VLAN_HLEN;
2502 } else {
2503 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2504 hdrlen = ETH_HLEN;
2505 }
2506 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2507 dev->name, datalen, protolen, hdrlen);
2508 if (protolen > ETH_DATA_LEN)
2509 return datalen; /* Value in proto field not a len, no checks possible */
2510
2511 protolen += hdrlen;
2512 /* consistency checks: */
2513 if (datalen > ETH_ZLEN) {
2514 if (datalen >= protolen) {
2515 /* more data on wire than in 802 header, trim of
2516 * additional data.
2517 */
2518 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2519 dev->name, protolen);
2520 return protolen;
2521 } else {
2522 /* less data on wire than mentioned in header.
2523 * Discard the packet.
2524 */
2525 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2526 dev->name);
2527 return -1;
2528 }
2529 } else {
2530 /* short packet. Accept only if 802 values are also short */
2531 if (protolen > ETH_ZLEN) {
2532 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2533 dev->name);
2534 return -1;
2535 }
2536 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2537 dev->name, datalen);
2538 return datalen;
2539 }
2540}
2541
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002542static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002543{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002544 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002545 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002546 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002547 struct sk_buff *skb;
2548 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002549
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002550 while((np->get_rx.orig != np->put_rx.orig) &&
2551 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002552 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002553
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002554 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2555 dev->name, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002556
Linus Torvalds1da177e2005-04-16 15:20:36 -07002557 /*
2558 * the packet is for us - immediately tear down the pci mapping.
2559 * TODO: check if a prefetch of the first cacheline improves
2560 * the performance.
2561 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002562 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2563 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002564 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002565 skb = np->get_rx_ctx->skb;
2566 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002567
2568 {
2569 int j;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002570 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571 for (j=0; j<64; j++) {
2572 if ((j%16) == 0)
2573 dprintk("\n%03x:", j);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002574 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002575 }
2576 dprintk("\n");
2577 }
2578 /* look at what we actually got: */
2579 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002580 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2581 len = flags & LEN_MASK_V1;
2582 if (unlikely(flags & NV_RX_ERROR)) {
2583 if (flags & NV_RX_ERROR4) {
2584 len = nv_getlen(dev, skb->data, len);
2585 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002586 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002587 dev_kfree_skb(skb);
2588 goto next_pkt;
2589 }
2590 }
2591 /* framing errors are soft errors */
2592 else if (flags & NV_RX_FRAMINGERR) {
2593 if (flags & NV_RX_SUBSTRACT1) {
2594 len--;
2595 }
2596 }
2597 /* the rest are hard errors */
2598 else {
2599 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002600 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002601 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002602 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002603 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002604 dev->stats.rx_over_errors++;
2605 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002606 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002607 goto next_pkt;
2608 }
2609 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002610 } else {
2611 dev_kfree_skb(skb);
2612 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002613 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002614 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002615 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2616 len = flags & LEN_MASK_V2;
2617 if (unlikely(flags & NV_RX2_ERROR)) {
2618 if (flags & NV_RX2_ERROR4) {
2619 len = nv_getlen(dev, skb->data, len);
2620 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002621 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002622 dev_kfree_skb(skb);
2623 goto next_pkt;
2624 }
2625 }
2626 /* framing errors are soft errors */
2627 else if (flags & NV_RX2_FRAMINGERR) {
2628 if (flags & NV_RX2_SUBSTRACT1) {
2629 len--;
2630 }
2631 }
2632 /* the rest are hard errors */
2633 else {
2634 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002635 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002636 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002637 dev->stats.rx_over_errors++;
2638 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002639 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002640 goto next_pkt;
2641 }
2642 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002643 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2644 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002645 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002646 } else {
2647 dev_kfree_skb(skb);
2648 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002649 }
2650 }
2651 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652 skb_put(skb, len);
2653 skb->protocol = eth_type_trans(skb, dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002654 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2655 dev->name, len, skb->protocol);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002656#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002657 netif_receive_skb(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002658#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002659 netif_rx(skb);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002660#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002661 dev->last_rx = jiffies;
Jeff Garzik8148ff42007-10-16 20:56:09 -04002662 dev->stats.rx_packets++;
2663 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002664next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002665 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002666 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002667 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002668 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002669
2670 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002671 }
2672
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002673 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002674}
2675
2676static int nv_rx_process_optimized(struct net_device *dev, int limit)
2677{
2678 struct fe_priv *np = netdev_priv(dev);
2679 u32 flags;
2680 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002681 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002682 struct sk_buff *skb;
2683 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002684
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002685 while((np->get_rx.ex != np->put_rx.ex) &&
2686 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002687 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002688
2689 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2690 dev->name, flags);
2691
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002692 /*
2693 * the packet is for us - immediately tear down the pci mapping.
2694 * TODO: check if a prefetch of the first cacheline improves
2695 * the performance.
2696 */
2697 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2698 np->get_rx_ctx->dma_len,
2699 PCI_DMA_FROMDEVICE);
2700 skb = np->get_rx_ctx->skb;
2701 np->get_rx_ctx->skb = NULL;
2702
2703 {
2704 int j;
2705 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2706 for (j=0; j<64; j++) {
2707 if ((j%16) == 0)
2708 dprintk("\n%03x:", j);
2709 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2710 }
2711 dprintk("\n");
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002712 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002713 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002714 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2715 len = flags & LEN_MASK_V2;
2716 if (unlikely(flags & NV_RX2_ERROR)) {
2717 if (flags & NV_RX2_ERROR4) {
2718 len = nv_getlen(dev, skb->data, len);
2719 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002720 dev_kfree_skb(skb);
2721 goto next_pkt;
2722 }
2723 }
2724 /* framing errors are soft errors */
2725 else if (flags & NV_RX2_FRAMINGERR) {
2726 if (flags & NV_RX2_SUBSTRACT1) {
2727 len--;
2728 }
2729 }
2730 /* the rest are hard errors */
2731 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002732 dev_kfree_skb(skb);
2733 goto next_pkt;
2734 }
2735 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002736
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002737 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2738 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002739 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002740
2741 /* got a valid packet - forward it to the network core */
2742 skb_put(skb, len);
2743 skb->protocol = eth_type_trans(skb, dev);
2744 prefetch(skb->data);
2745
2746 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2747 dev->name, len, skb->protocol);
2748
2749 if (likely(!np->vlangrp)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002750#ifdef CONFIG_FORCEDETH_NAPI
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002751 netif_receive_skb(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002752#else
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002753 netif_rx(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002754#endif
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002755 } else {
2756 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2757 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2758#ifdef CONFIG_FORCEDETH_NAPI
2759 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2760 vlanflags & NV_RX3_VLAN_TAG_MASK);
2761#else
2762 vlan_hwaccel_rx(skb, np->vlangrp,
2763 vlanflags & NV_RX3_VLAN_TAG_MASK);
2764#endif
2765 } else {
2766#ifdef CONFIG_FORCEDETH_NAPI
2767 netif_receive_skb(skb);
2768#else
2769 netif_rx(skb);
2770#endif
2771 }
2772 }
2773
2774 dev->last_rx = jiffies;
Jeff Garzik8148ff42007-10-16 20:56:09 -04002775 dev->stats.rx_packets++;
2776 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002777 } else {
2778 dev_kfree_skb(skb);
2779 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002780next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002781 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002782 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002783 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002784 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002785
2786 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002787 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002788
Ingo Molnarc1b71512007-10-17 12:18:23 +02002789 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002790}
2791
Manfred Sprauld81c0982005-07-31 18:20:30 +02002792static void set_bufsize(struct net_device *dev)
2793{
2794 struct fe_priv *np = netdev_priv(dev);
2795
2796 if (dev->mtu <= ETH_DATA_LEN)
2797 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2798 else
2799 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2800}
2801
Linus Torvalds1da177e2005-04-16 15:20:36 -07002802/*
2803 * nv_change_mtu: dev->change_mtu function
2804 * Called with dev_base_lock held for read.
2805 */
2806static int nv_change_mtu(struct net_device *dev, int new_mtu)
2807{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002808 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002809 int old_mtu;
2810
2811 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002812 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002813
2814 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002815 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002816
2817 /* return early if the buffer sizes will not change */
2818 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2819 return 0;
2820 if (old_mtu == new_mtu)
2821 return 0;
2822
2823 /* synchronized against open : rtnl_lock() held by caller */
2824 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002825 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002826 /*
2827 * It seems that the nic preloads valid ring entries into an
2828 * internal buffer. The procedure for flushing everything is
2829 * guessed, there is probably a simpler approach.
2830 * Changing the MTU is a rare event, it shouldn't matter.
2831 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002832 nv_disable_irq(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002833 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002834 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002835 spin_lock(&np->lock);
2836 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002837 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002838 nv_txrx_reset(dev);
2839 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002840 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002841 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002842 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002843 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02002844 if (!np->in_shutdown)
2845 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2846 }
2847 /* reinit nic view of the rx queue */
2848 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002849 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002850 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02002851 base + NvRegRingSizes);
2852 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002853 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002854 pci_push(base);
2855
2856 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002857 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002858 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002859 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002860 netif_tx_unlock_bh(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002861 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002862 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002863 return 0;
2864}
2865
Manfred Spraul72b31782005-07-31 18:33:34 +02002866static void nv_copy_mac_to_hw(struct net_device *dev)
2867{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002868 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002869 u32 mac[2];
2870
2871 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2872 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2873 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2874
2875 writel(mac[0], base + NvRegMacAddrA);
2876 writel(mac[1], base + NvRegMacAddrB);
2877}
2878
2879/*
2880 * nv_set_mac_address: dev->set_mac_address function
2881 * Called with rtnl_lock() held.
2882 */
2883static int nv_set_mac_address(struct net_device *dev, void *addr)
2884{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002885 struct fe_priv *np = netdev_priv(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002886 struct sockaddr *macaddr = (struct sockaddr*)addr;
2887
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002888 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02002889 return -EADDRNOTAVAIL;
2890
2891 /* synchronized against open : rtnl_lock() held by caller */
2892 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2893
2894 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07002895 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002896 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002897 spin_lock_irq(&np->lock);
2898
2899 /* stop rx engine */
2900 nv_stop_rx(dev);
2901
2902 /* set mac address */
2903 nv_copy_mac_to_hw(dev);
2904
2905 /* restart rx engine */
2906 nv_start_rx(dev);
2907 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002908 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002909 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002910 } else {
2911 nv_copy_mac_to_hw(dev);
2912 }
2913 return 0;
2914}
2915
Linus Torvalds1da177e2005-04-16 15:20:36 -07002916/*
2917 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07002918 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002919 */
2920static void nv_set_multicast(struct net_device *dev)
2921{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002922 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002923 u8 __iomem *base = get_hwbase(dev);
2924 u32 addr[2];
2925 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002926 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002927
2928 memset(addr, 0, sizeof(addr));
2929 memset(mask, 0, sizeof(mask));
2930
2931 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002932 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002933 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002934 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002935
2936 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2937 u32 alwaysOff[2];
2938 u32 alwaysOn[2];
2939
2940 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2941 if (dev->flags & IFF_ALLMULTI) {
2942 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2943 } else {
2944 struct dev_mc_list *walk;
2945
2946 walk = dev->mc_list;
2947 while (walk != NULL) {
2948 u32 a, b;
Al Viro5bb7ea22007-12-09 16:06:41 +00002949 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2950 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002951 alwaysOn[0] &= a;
2952 alwaysOff[0] &= ~a;
2953 alwaysOn[1] &= b;
2954 alwaysOff[1] &= ~b;
2955 walk = walk->next;
2956 }
2957 }
2958 addr[0] = alwaysOn[0];
2959 addr[1] = alwaysOn[1];
2960 mask[0] = alwaysOn[0] | alwaysOff[0];
2961 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05002962 } else {
2963 mask[0] = NVREG_MCASTMASKA_NONE;
2964 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002965 }
2966 }
2967 addr[0] |= NVREG_MCASTADDRA_FORCE;
2968 pff |= NVREG_PFF_ALWAYS;
2969 spin_lock_irq(&np->lock);
2970 nv_stop_rx(dev);
2971 writel(addr[0], base + NvRegMulticastAddrA);
2972 writel(addr[1], base + NvRegMulticastAddrB);
2973 writel(mask[0], base + NvRegMulticastMaskA);
2974 writel(mask[1], base + NvRegMulticastMaskB);
2975 writel(pff, base + NvRegPacketFilterFlags);
2976 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2977 dev->name);
2978 nv_start_rx(dev);
2979 spin_unlock_irq(&np->lock);
2980}
2981
Adrian Bunkc7985052006-06-22 12:03:29 +02002982static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002983{
2984 struct fe_priv *np = netdev_priv(dev);
2985 u8 __iomem *base = get_hwbase(dev);
2986
2987 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2988
2989 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2990 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2991 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2992 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2993 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2994 } else {
2995 writel(pff, base + NvRegPacketFilterFlags);
2996 }
2997 }
2998 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2999 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3000 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003001 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3002 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3003 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3004 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
3005 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3006 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003007 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3008 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3009 } else {
3010 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3011 writel(regmisc, base + NvRegMisc1);
3012 }
3013 }
3014}
3015
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003016/**
3017 * nv_update_linkspeed: Setup the MAC according to the link partner
3018 * @dev: Network device to be configured
3019 *
3020 * The function queries the PHY and checks if there is a link partner.
3021 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3022 * set to 10 MBit HD.
3023 *
3024 * The function returns 0 if there is no link partner and 1 if there is
3025 * a good link partner.
3026 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003027static int nv_update_linkspeed(struct net_device *dev)
3028{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003029 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003030 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003031 int adv = 0;
3032 int lpa = 0;
3033 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003034 int newls = np->linkspeed;
3035 int newdup = np->duplex;
3036 int mii_status;
3037 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003038 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003039 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003040 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003041
3042 /* BMSR_LSTATUS is latched, read it twice:
3043 * we want the current value.
3044 */
3045 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3046 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3047
3048 if (!(mii_status & BMSR_LSTATUS)) {
3049 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3050 dev->name);
3051 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3052 newdup = 0;
3053 retval = 0;
3054 goto set_speed;
3055 }
3056
3057 if (np->autoneg == 0) {
3058 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3059 dev->name, np->fixed_mode);
3060 if (np->fixed_mode & LPA_100FULL) {
3061 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3062 newdup = 1;
3063 } else if (np->fixed_mode & LPA_100HALF) {
3064 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3065 newdup = 0;
3066 } else if (np->fixed_mode & LPA_10FULL) {
3067 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3068 newdup = 1;
3069 } else {
3070 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3071 newdup = 0;
3072 }
3073 retval = 1;
3074 goto set_speed;
3075 }
3076 /* check auto negotiation is complete */
3077 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3078 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3079 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3080 newdup = 0;
3081 retval = 0;
3082 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3083 goto set_speed;
3084 }
3085
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003086 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3087 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3088 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3089 dev->name, adv, lpa);
3090
Linus Torvalds1da177e2005-04-16 15:20:36 -07003091 retval = 1;
3092 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003093 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3094 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003095
3096 if ((control_1000 & ADVERTISE_1000FULL) &&
3097 (status_1000 & LPA_1000FULL)) {
3098 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3099 dev->name);
3100 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3101 newdup = 1;
3102 goto set_speed;
3103 }
3104 }
3105
Linus Torvalds1da177e2005-04-16 15:20:36 -07003106 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003107 adv_lpa = lpa & adv;
3108 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003109 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3110 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003111 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003112 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3113 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003114 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003115 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3116 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003117 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003118 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3119 newdup = 0;
3120 } else {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003121 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003122 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3123 newdup = 0;
3124 }
3125
3126set_speed:
3127 if (np->duplex == newdup && np->linkspeed == newls)
3128 return retval;
3129
3130 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3131 dev->name, np->linkspeed, np->duplex, newls, newdup);
3132
3133 np->duplex = newdup;
3134 np->linkspeed = newls;
3135
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003136 /* The transmitter and receiver must be restarted for safe update */
3137 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3138 txrxFlags |= NV_RESTART_TX;
3139 nv_stop_tx(dev);
3140 }
3141 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3142 txrxFlags |= NV_RESTART_RX;
3143 nv_stop_rx(dev);
3144 }
3145
Linus Torvalds1da177e2005-04-16 15:20:36 -07003146 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003147 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003148 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003149 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3150 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3151 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003152 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003153 phyreg |= NVREG_SLOTTIME_1000_FULL;
3154 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003155 }
3156
3157 phyreg = readl(base + NvRegPhyInterface);
3158 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3159 if (np->duplex == 0)
3160 phyreg |= PHY_HALF;
3161 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3162 phyreg |= PHY_100;
3163 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3164 phyreg |= PHY_1000;
3165 writel(phyreg, base + NvRegPhyInterface);
3166
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003167 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003168 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003169 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003170 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003171 } else {
3172 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3173 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3174 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3175 else
3176 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3177 } else {
3178 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3179 }
3180 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003181 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003182 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3183 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3184 else
3185 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003186 }
3187 writel(txreg, base + NvRegTxDeferral);
3188
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003189 if (np->desc_ver == DESC_VER_1) {
3190 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3191 } else {
3192 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3193 txreg = NVREG_TX_WM_DESC2_3_1000;
3194 else
3195 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3196 }
3197 writel(txreg, base + NvRegTxWatermark);
3198
Linus Torvalds1da177e2005-04-16 15:20:36 -07003199 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3200 base + NvRegMisc1);
3201 pci_push(base);
3202 writel(np->linkspeed, base + NvRegLinkSpeed);
3203 pci_push(base);
3204
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003205 pause_flags = 0;
3206 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003207 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003208 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3209 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3210 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003211
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003212 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003213 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003214 if (lpa_pause & LPA_PAUSE_CAP) {
3215 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3216 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3217 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3218 }
3219 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003220 case ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003221 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3222 {
3223 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3224 }
3225 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003226 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003227 if (lpa_pause & LPA_PAUSE_CAP)
3228 {
3229 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3230 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3231 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3232 }
3233 if (lpa_pause == LPA_PAUSE_ASYM)
3234 {
3235 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3236 }
3237 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003238 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003239 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003240 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003241 }
3242 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003243 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003244
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003245 if (txrxFlags & NV_RESTART_TX)
3246 nv_start_tx(dev);
3247 if (txrxFlags & NV_RESTART_RX)
3248 nv_start_rx(dev);
3249
Linus Torvalds1da177e2005-04-16 15:20:36 -07003250 return retval;
3251}
3252
3253static void nv_linkchange(struct net_device *dev)
3254{
3255 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003256 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003257 netif_carrier_on(dev);
3258 printk(KERN_INFO "%s: link up.\n", dev->name);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003259 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003260 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003261 } else {
3262 if (netif_carrier_ok(dev)) {
3263 netif_carrier_off(dev);
3264 printk(KERN_INFO "%s: link down.\n", dev->name);
3265 nv_stop_rx(dev);
3266 }
3267 }
3268}
3269
3270static void nv_link_irq(struct net_device *dev)
3271{
3272 u8 __iomem *base = get_hwbase(dev);
3273 u32 miistat;
3274
3275 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003276 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003277 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3278
3279 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3280 nv_linkchange(dev);
3281 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3282}
3283
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003284static void nv_msi_workaround(struct fe_priv *np)
3285{
3286
3287 /* Need to toggle the msi irq mask within the ethernet device,
3288 * otherwise, future interrupts will not be detected.
3289 */
3290 if (np->msi_flags & NV_MSI_ENABLED) {
3291 u8 __iomem *base = np->base;
3292
3293 writel(0, base + NvRegMSIIrqMask);
3294 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3295 }
3296}
3297
David Howells7d12e782006-10-05 14:55:46 +01003298static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003299{
3300 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003301 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003302 u8 __iomem *base = get_hwbase(dev);
3303 u32 events;
3304 int i;
3305
3306 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3307
3308 for (i=0; ; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003309 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3310 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3311 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3312 } else {
3313 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3314 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3315 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003316 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3317 if (!(events & np->irqmask))
3318 break;
3319
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003320 nv_msi_workaround(np);
3321
Ayaz Abdullaa971c322005-11-11 08:30:38 -05003322 spin_lock(&np->lock);
3323 nv_tx_done(dev);
3324 spin_unlock(&np->lock);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003325
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003326#ifdef CONFIG_FORCEDETH_NAPI
3327 if (events & NVREG_IRQ_RX_ALL) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003328 netif_rx_schedule(dev, &np->napi);
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003329
3330 /* Disable furthur receive irq's */
3331 spin_lock(&np->lock);
3332 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3333
3334 if (np->msi_flags & NV_MSI_X_ENABLED)
3335 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3336 else
3337 writel(np->irqmask, base + NvRegIrqMask);
3338 spin_unlock(&np->lock);
3339 }
3340#else
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003341 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003342 if (unlikely(nv_alloc_rx(dev))) {
3343 spin_lock(&np->lock);
3344 if (!np->in_shutdown)
3345 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3346 spin_unlock(&np->lock);
3347 }
3348 }
3349#endif
3350 if (unlikely(events & NVREG_IRQ_LINK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003351 spin_lock(&np->lock);
3352 nv_link_irq(dev);
3353 spin_unlock(&np->lock);
3354 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003355 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003356 spin_lock(&np->lock);
3357 nv_linkchange(dev);
3358 spin_unlock(&np->lock);
3359 np->link_timeout = jiffies + LINK_TIMEOUT;
3360 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003361 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003362 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3363 dev->name, events);
3364 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003365 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003366 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3367 dev->name, events);
3368 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003369 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3370 spin_lock(&np->lock);
3371 /* disable interrupts on the nic */
3372 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3373 writel(0, base + NvRegIrqMask);
3374 else
3375 writel(np->irqmask, base + NvRegIrqMask);
3376 pci_push(base);
3377
3378 if (!np->in_shutdown) {
3379 np->nic_poll_irq = np->irqmask;
3380 np->recover_error = 1;
3381 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3382 }
3383 spin_unlock(&np->lock);
3384 break;
3385 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003386 if (unlikely(i > max_interrupt_work)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003387 spin_lock(&np->lock);
3388 /* disable interrupts on the nic */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003389 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3390 writel(0, base + NvRegIrqMask);
3391 else
3392 writel(np->irqmask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003393 pci_push(base);
3394
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003395 if (!np->in_shutdown) {
3396 np->nic_poll_irq = np->irqmask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003397 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003398 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003399 spin_unlock(&np->lock);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003400 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003401 break;
3402 }
3403
3404 }
3405 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3406
3407 return IRQ_RETVAL(i);
3408}
3409
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003410/**
3411 * All _optimized functions are used to help increase performance
3412 * (reduce CPU and increase throughput). They use descripter version 3,
3413 * compiler directives, and reduce memory accesses.
3414 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003415static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3416{
3417 struct net_device *dev = (struct net_device *) data;
3418 struct fe_priv *np = netdev_priv(dev);
3419 u8 __iomem *base = get_hwbase(dev);
3420 u32 events;
3421 int i;
3422
3423 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3424
3425 for (i=0; ; i++) {
3426 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3427 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3428 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3429 } else {
3430 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3431 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3432 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003433 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3434 if (!(events & np->irqmask))
3435 break;
3436
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003437 nv_msi_workaround(np);
3438
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003439 spin_lock(&np->lock);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003440 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003441 spin_unlock(&np->lock);
3442
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003443#ifdef CONFIG_FORCEDETH_NAPI
3444 if (events & NVREG_IRQ_RX_ALL) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003445 netif_rx_schedule(dev, &np->napi);
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003446
3447 /* Disable furthur receive irq's */
3448 spin_lock(&np->lock);
3449 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3450
3451 if (np->msi_flags & NV_MSI_X_ENABLED)
3452 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3453 else
3454 writel(np->irqmask, base + NvRegIrqMask);
3455 spin_unlock(&np->lock);
3456 }
3457#else
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003458 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003459 if (unlikely(nv_alloc_rx_optimized(dev))) {
3460 spin_lock(&np->lock);
3461 if (!np->in_shutdown)
3462 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3463 spin_unlock(&np->lock);
3464 }
3465 }
3466#endif
3467 if (unlikely(events & NVREG_IRQ_LINK)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003468 spin_lock(&np->lock);
3469 nv_link_irq(dev);
3470 spin_unlock(&np->lock);
3471 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003472 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003473 spin_lock(&np->lock);
3474 nv_linkchange(dev);
3475 spin_unlock(&np->lock);
3476 np->link_timeout = jiffies + LINK_TIMEOUT;
3477 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003478 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003479 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3480 dev->name, events);
3481 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003482 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003483 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3484 dev->name, events);
3485 }
3486 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3487 spin_lock(&np->lock);
3488 /* disable interrupts on the nic */
3489 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3490 writel(0, base + NvRegIrqMask);
3491 else
3492 writel(np->irqmask, base + NvRegIrqMask);
3493 pci_push(base);
3494
3495 if (!np->in_shutdown) {
3496 np->nic_poll_irq = np->irqmask;
3497 np->recover_error = 1;
3498 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3499 }
3500 spin_unlock(&np->lock);
3501 break;
3502 }
3503
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003504 if (unlikely(i > max_interrupt_work)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003505 spin_lock(&np->lock);
3506 /* disable interrupts on the nic */
3507 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3508 writel(0, base + NvRegIrqMask);
3509 else
3510 writel(np->irqmask, base + NvRegIrqMask);
3511 pci_push(base);
3512
3513 if (!np->in_shutdown) {
3514 np->nic_poll_irq = np->irqmask;
3515 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3516 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003517 spin_unlock(&np->lock);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003518 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003519 break;
3520 }
3521
3522 }
3523 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3524
3525 return IRQ_RETVAL(i);
3526}
3527
David Howells7d12e782006-10-05 14:55:46 +01003528static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003529{
3530 struct net_device *dev = (struct net_device *) data;
3531 struct fe_priv *np = netdev_priv(dev);
3532 u8 __iomem *base = get_hwbase(dev);
3533 u32 events;
3534 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003535 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003536
3537 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3538
3539 for (i=0; ; i++) {
3540 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3541 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003542 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3543 if (!(events & np->irqmask))
3544 break;
3545
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003546 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003547 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003548 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003549
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003550 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003551 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3552 dev->name, events);
3553 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003554 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003555 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003556 /* disable interrupts on the nic */
3557 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3558 pci_push(base);
3559
3560 if (!np->in_shutdown) {
3561 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3562 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3563 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003564 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003565 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003566 break;
3567 }
3568
3569 }
3570 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3571
3572 return IRQ_RETVAL(i);
3573}
3574
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003575#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003576static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003577{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003578 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3579 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003580 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003581 unsigned long flags;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003582 int pkts, retcode;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003583
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003584 if (!nv_optimized(np)) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003585 pkts = nv_rx_process(dev, budget);
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003586 retcode = nv_alloc_rx(dev);
3587 } else {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003588 pkts = nv_rx_process_optimized(dev, budget);
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003589 retcode = nv_alloc_rx_optimized(dev);
3590 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003591
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003592 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003593 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003594 if (!np->in_shutdown)
3595 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003596 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003597 }
3598
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003599 if (pkts < budget) {
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003600 /* re-enable receive interrupts */
Francois Romieud15e9c42006-12-17 23:03:15 +01003601 spin_lock_irqsave(&np->lock, flags);
3602
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003603 __netif_rx_complete(dev, napi);
3604
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003605 np->irqmask |= NVREG_IRQ_RX_ALL;
3606 if (np->msi_flags & NV_MSI_X_ENABLED)
3607 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3608 else
3609 writel(np->irqmask, base + NvRegIrqMask);
Francois Romieud15e9c42006-12-17 23:03:15 +01003610
3611 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003612 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003613 return pkts;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003614}
3615#endif
3616
3617#ifdef CONFIG_FORCEDETH_NAPI
David Howells7d12e782006-10-05 14:55:46 +01003618static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003619{
3620 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003621 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003622 u8 __iomem *base = get_hwbase(dev);
3623 u32 events;
3624
3625 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3626 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3627
3628 if (events) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003629 netif_rx_schedule(dev, &np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003630 /* disable receive interrupts on the nic */
3631 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3632 pci_push(base);
3633 }
3634 return IRQ_HANDLED;
3635}
3636#else
David Howells7d12e782006-10-05 14:55:46 +01003637static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003638{
3639 struct net_device *dev = (struct net_device *) data;
3640 struct fe_priv *np = netdev_priv(dev);
3641 u8 __iomem *base = get_hwbase(dev);
3642 u32 events;
3643 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003644 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003645
3646 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3647
3648 for (i=0; ; i++) {
3649 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3650 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003651 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3652 if (!(events & np->irqmask))
3653 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003654
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003655 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003656 if (unlikely(nv_alloc_rx_optimized(dev))) {
3657 spin_lock_irqsave(&np->lock, flags);
3658 if (!np->in_shutdown)
3659 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3660 spin_unlock_irqrestore(&np->lock, flags);
3661 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003662 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003663
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003664 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003665 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003666 /* disable interrupts on the nic */
3667 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3668 pci_push(base);
3669
3670 if (!np->in_shutdown) {
3671 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3672 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3673 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003674 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003675 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003676 break;
3677 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003678 }
3679 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3680
3681 return IRQ_RETVAL(i);
3682}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003683#endif
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003684
David Howells7d12e782006-10-05 14:55:46 +01003685static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003686{
3687 struct net_device *dev = (struct net_device *) data;
3688 struct fe_priv *np = netdev_priv(dev);
3689 u8 __iomem *base = get_hwbase(dev);
3690 u32 events;
3691 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003692 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003693
3694 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3695
3696 for (i=0; ; i++) {
3697 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3698 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003699 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3700 if (!(events & np->irqmask))
3701 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003702
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003703 /* check tx in case we reached max loop limit in tx isr */
3704 spin_lock_irqsave(&np->lock, flags);
3705 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3706 spin_unlock_irqrestore(&np->lock, flags);
3707
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003708 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003709 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003710 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003711 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003712 }
3713 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003714 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003715 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003716 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003717 np->link_timeout = jiffies + LINK_TIMEOUT;
3718 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003719 if (events & NVREG_IRQ_RECOVER_ERROR) {
3720 spin_lock_irq(&np->lock);
3721 /* disable interrupts on the nic */
3722 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3723 pci_push(base);
3724
3725 if (!np->in_shutdown) {
3726 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3727 np->recover_error = 1;
3728 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3729 }
3730 spin_unlock_irq(&np->lock);
3731 break;
3732 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003733 if (events & (NVREG_IRQ_UNKNOWN)) {
3734 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3735 dev->name, events);
3736 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003737 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003738 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003739 /* disable interrupts on the nic */
3740 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3741 pci_push(base);
3742
3743 if (!np->in_shutdown) {
3744 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3745 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3746 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003747 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003748 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003749 break;
3750 }
3751
3752 }
3753 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3754
3755 return IRQ_RETVAL(i);
3756}
3757
David Howells7d12e782006-10-05 14:55:46 +01003758static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003759{
3760 struct net_device *dev = (struct net_device *) data;
3761 struct fe_priv *np = netdev_priv(dev);
3762 u8 __iomem *base = get_hwbase(dev);
3763 u32 events;
3764
3765 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3766
3767 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3768 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3769 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3770 } else {
3771 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3772 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3773 }
3774 pci_push(base);
3775 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3776 if (!(events & NVREG_IRQ_TIMER))
3777 return IRQ_RETVAL(0);
3778
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003779 nv_msi_workaround(np);
3780
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003781 spin_lock(&np->lock);
3782 np->intr_test = 1;
3783 spin_unlock(&np->lock);
3784
3785 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3786
3787 return IRQ_RETVAL(1);
3788}
3789
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003790static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3791{
3792 u8 __iomem *base = get_hwbase(dev);
3793 int i;
3794 u32 msixmap = 0;
3795
3796 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3797 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3798 * the remaining 8 interrupts.
3799 */
3800 for (i = 0; i < 8; i++) {
3801 if ((irqmask >> i) & 0x1) {
3802 msixmap |= vector << (i << 2);
3803 }
3804 }
3805 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3806
3807 msixmap = 0;
3808 for (i = 0; i < 8; i++) {
3809 if ((irqmask >> (i + 8)) & 0x1) {
3810 msixmap |= vector << (i << 2);
3811 }
3812 }
3813 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3814}
3815
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003816static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003817{
3818 struct fe_priv *np = get_nvpriv(dev);
3819 u8 __iomem *base = get_hwbase(dev);
3820 int ret = 1;
3821 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003822 irqreturn_t (*handler)(int foo, void *data);
3823
3824 if (intr_test) {
3825 handler = nv_nic_irq_test;
3826 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003827 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003828 handler = nv_nic_irq_optimized;
3829 else
3830 handler = nv_nic_irq;
3831 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003832
3833 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3834 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3835 np->msi_x_entry[i].entry = i;
3836 }
3837 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3838 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003839 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003840 /* Request irq for rx handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003841 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003842 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3843 pci_disable_msix(np->pci_dev);
3844 np->msi_flags &= ~NV_MSI_X_ENABLED;
3845 goto out_err;
3846 }
3847 /* Request irq for tx handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003848 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003849 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3850 pci_disable_msix(np->pci_dev);
3851 np->msi_flags &= ~NV_MSI_X_ENABLED;
3852 goto out_free_rx;
3853 }
3854 /* Request irq for link and timer handling */
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07003855 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003856 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3857 pci_disable_msix(np->pci_dev);
3858 np->msi_flags &= ~NV_MSI_X_ENABLED;
3859 goto out_free_tx;
3860 }
3861 /* map interrupts to their respective vector */
3862 writel(0, base + NvRegMSIXMap0);
3863 writel(0, base + NvRegMSIXMap1);
3864 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3865 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3866 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3867 } else {
3868 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003869 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003870 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3871 pci_disable_msix(np->pci_dev);
3872 np->msi_flags &= ~NV_MSI_X_ENABLED;
3873 goto out_err;
3874 }
3875
3876 /* map interrupts to vector 0 */
3877 writel(0, base + NvRegMSIXMap0);
3878 writel(0, base + NvRegMSIXMap1);
3879 }
3880 }
3881 }
3882 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3883 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3884 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003885 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003886 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003887 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3888 pci_disable_msi(np->pci_dev);
3889 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003890 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003891 goto out_err;
3892 }
3893
3894 /* map interrupts to vector 0 */
3895 writel(0, base + NvRegMSIMap0);
3896 writel(0, base + NvRegMSIMap1);
3897 /* enable msi vector 0 */
3898 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3899 }
3900 }
3901 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003902 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003903 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003904
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003905 }
3906
3907 return 0;
3908out_free_tx:
3909 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3910out_free_rx:
3911 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3912out_err:
3913 return 1;
3914}
3915
3916static void nv_free_irq(struct net_device *dev)
3917{
3918 struct fe_priv *np = get_nvpriv(dev);
3919 int i;
3920
3921 if (np->msi_flags & NV_MSI_X_ENABLED) {
3922 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3923 free_irq(np->msi_x_entry[i].vector, dev);
3924 }
3925 pci_disable_msix(np->pci_dev);
3926 np->msi_flags &= ~NV_MSI_X_ENABLED;
3927 } else {
3928 free_irq(np->pci_dev->irq, dev);
3929 if (np->msi_flags & NV_MSI_ENABLED) {
3930 pci_disable_msi(np->pci_dev);
3931 np->msi_flags &= ~NV_MSI_ENABLED;
3932 }
3933 }
3934}
3935
Linus Torvalds1da177e2005-04-16 15:20:36 -07003936static void nv_do_nic_poll(unsigned long data)
3937{
3938 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003939 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003940 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003941 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003942
Linus Torvalds1da177e2005-04-16 15:20:36 -07003943 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003944 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07003945 * reenable interrupts on the nic, we have to do this before calling
3946 * nv_nic_irq because that may decide to do otherwise
3947 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003948
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003949 if (!using_multi_irqs(dev)) {
3950 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003951 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003952 else
Manfred Spraula7475902007-10-17 21:52:33 +02003953 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003954 mask = np->irqmask;
3955 } else {
3956 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003957 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003958 mask |= NVREG_IRQ_RX_ALL;
3959 }
3960 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003961 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003962 mask |= NVREG_IRQ_TX_ALL;
3963 }
3964 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003965 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003966 mask |= NVREG_IRQ_OTHER;
3967 }
3968 }
3969 np->nic_poll_irq = 0;
3970
Manfred Spraula7475902007-10-17 21:52:33 +02003971 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3972
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003973 if (np->recover_error) {
3974 np->recover_error = 0;
3975 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3976 if (netif_running(dev)) {
3977 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003978 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003979 spin_lock(&np->lock);
3980 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003981 nv_stop_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003982 nv_txrx_reset(dev);
3983 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003984 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003985 /* reinit driver view of the rx queue */
3986 set_bufsize(dev);
3987 if (nv_init_ring(dev)) {
3988 if (!np->in_shutdown)
3989 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3990 }
3991 /* reinit nic view of the rx queue */
3992 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3993 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3994 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3995 base + NvRegRingSizes);
3996 pci_push(base);
3997 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3998 pci_push(base);
3999
4000 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004001 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004002 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004003 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05004004 netif_tx_unlock_bh(dev);
4005 }
4006 }
4007
Jeff Garzikf3b197a2006-05-26 21:39:03 -04004008
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004009 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004010 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004011
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004012 if (!using_multi_irqs(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004013 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05004014 nv_nic_irq_optimized(0, dev);
4015 else
4016 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004017 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004018 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07004019 else
Manfred Spraula7475902007-10-17 21:52:33 +02004020 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004021 } else {
4022 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
David Howells7d12e782006-10-05 14:55:46 +01004023 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004024 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004025 }
4026 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
David Howells7d12e782006-10-05 14:55:46 +01004027 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004028 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004029 }
4030 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
David Howells7d12e782006-10-05 14:55:46 +01004031 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07004032 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05004033 }
4034 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004035}
4036
Michal Schmidt2918c352005-05-12 19:42:06 -04004037#ifdef CONFIG_NET_POLL_CONTROLLER
4038static void nv_poll_controller(struct net_device *dev)
4039{
4040 nv_do_nic_poll((unsigned long) dev);
4041}
4042#endif
4043
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004044static void nv_do_stats_poll(unsigned long data)
4045{
4046 struct net_device *dev = (struct net_device *) data;
4047 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004048
Ayaz Abdulla57fff692007-01-23 12:27:00 -05004049 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004050
4051 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00004052 mod_timer(&np->stats_poll,
4053 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004054}
4055
Linus Torvalds1da177e2005-04-16 15:20:36 -07004056static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4057{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004058 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04004059 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004060 strcpy(info->version, FORCEDETH_VERSION);
4061 strcpy(info->bus_info, pci_name(np->pci_dev));
4062}
4063
4064static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4065{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004066 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004067 wolinfo->supported = WAKE_MAGIC;
4068
4069 spin_lock_irq(&np->lock);
4070 if (np->wolenabled)
4071 wolinfo->wolopts = WAKE_MAGIC;
4072 spin_unlock_irq(&np->lock);
4073}
4074
4075static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4076{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004077 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004078 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004079 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004080
Linus Torvalds1da177e2005-04-16 15:20:36 -07004081 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004082 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004083 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004084 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004085 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004086 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004087 if (netif_running(dev)) {
4088 spin_lock_irq(&np->lock);
4089 writel(flags, base + NvRegWakeUpFlags);
4090 spin_unlock_irq(&np->lock);
4091 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004092 return 0;
4093}
4094
4095static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4096{
4097 struct fe_priv *np = netdev_priv(dev);
4098 int adv;
4099
4100 spin_lock_irq(&np->lock);
4101 ecmd->port = PORT_MII;
4102 if (!netif_running(dev)) {
4103 /* We do not track link speed / duplex setting if the
4104 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004105 if (nv_update_linkspeed(dev)) {
4106 if (!netif_carrier_ok(dev))
4107 netif_carrier_on(dev);
4108 } else {
4109 if (netif_carrier_ok(dev))
4110 netif_carrier_off(dev);
4111 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004112 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004113
4114 if (netif_carrier_ok(dev)) {
4115 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004116 case NVREG_LINKSPEED_10:
4117 ecmd->speed = SPEED_10;
4118 break;
4119 case NVREG_LINKSPEED_100:
4120 ecmd->speed = SPEED_100;
4121 break;
4122 case NVREG_LINKSPEED_1000:
4123 ecmd->speed = SPEED_1000;
4124 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004125 }
4126 ecmd->duplex = DUPLEX_HALF;
4127 if (np->duplex)
4128 ecmd->duplex = DUPLEX_FULL;
4129 } else {
4130 ecmd->speed = -1;
4131 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004132 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004133
4134 ecmd->autoneg = np->autoneg;
4135
4136 ecmd->advertising = ADVERTISED_MII;
4137 if (np->autoneg) {
4138 ecmd->advertising |= ADVERTISED_Autoneg;
4139 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004140 if (adv & ADVERTISE_10HALF)
4141 ecmd->advertising |= ADVERTISED_10baseT_Half;
4142 if (adv & ADVERTISE_10FULL)
4143 ecmd->advertising |= ADVERTISED_10baseT_Full;
4144 if (adv & ADVERTISE_100HALF)
4145 ecmd->advertising |= ADVERTISED_100baseT_Half;
4146 if (adv & ADVERTISE_100FULL)
4147 ecmd->advertising |= ADVERTISED_100baseT_Full;
4148 if (np->gigabit == PHY_GIGABIT) {
4149 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4150 if (adv & ADVERTISE_1000FULL)
4151 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4152 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004153 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004154 ecmd->supported = (SUPPORTED_Autoneg |
4155 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4156 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4157 SUPPORTED_MII);
4158 if (np->gigabit == PHY_GIGABIT)
4159 ecmd->supported |= SUPPORTED_1000baseT_Full;
4160
4161 ecmd->phy_address = np->phyaddr;
4162 ecmd->transceiver = XCVR_EXTERNAL;
4163
4164 /* ignore maxtxpkt, maxrxpkt for now */
4165 spin_unlock_irq(&np->lock);
4166 return 0;
4167}
4168
4169static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4170{
4171 struct fe_priv *np = netdev_priv(dev);
4172
4173 if (ecmd->port != PORT_MII)
4174 return -EINVAL;
4175 if (ecmd->transceiver != XCVR_EXTERNAL)
4176 return -EINVAL;
4177 if (ecmd->phy_address != np->phyaddr) {
4178 /* TODO: support switching between multiple phys. Should be
4179 * trivial, but not enabled due to lack of test hardware. */
4180 return -EINVAL;
4181 }
4182 if (ecmd->autoneg == AUTONEG_ENABLE) {
4183 u32 mask;
4184
4185 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4186 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4187 if (np->gigabit == PHY_GIGABIT)
4188 mask |= ADVERTISED_1000baseT_Full;
4189
4190 if ((ecmd->advertising & mask) == 0)
4191 return -EINVAL;
4192
4193 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4194 /* Note: autonegotiation disable, speed 1000 intentionally
4195 * forbidden - noone should need that. */
4196
4197 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4198 return -EINVAL;
4199 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4200 return -EINVAL;
4201 } else {
4202 return -EINVAL;
4203 }
4204
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004205 netif_carrier_off(dev);
4206 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004207 unsigned long flags;
4208
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004209 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004210 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004211 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004212 /* with plain spinlock lockdep complains */
4213 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004214 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004215 /* FIXME:
4216 * this can take some time, and interrupts are disabled
4217 * due to spin_lock_irqsave, but let's hope no daemon
4218 * is going to change the settings very often...
4219 * Worst case:
4220 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4221 * + some minor delays, which is up to a second approximately
4222 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004223 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004224 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004225 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004226 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004227 }
4228
Linus Torvalds1da177e2005-04-16 15:20:36 -07004229 if (ecmd->autoneg == AUTONEG_ENABLE) {
4230 int adv, bmcr;
4231
4232 np->autoneg = 1;
4233
4234 /* advertise only what has been requested */
4235 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004236 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004237 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4238 adv |= ADVERTISE_10HALF;
4239 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004240 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004241 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4242 adv |= ADVERTISE_100HALF;
4243 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004244 adv |= ADVERTISE_100FULL;
4245 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4246 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4247 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4248 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004249 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4250
4251 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004252 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004253 adv &= ~ADVERTISE_1000FULL;
4254 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4255 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004256 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004257 }
4258
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004259 if (netif_running(dev))
4260 printk(KERN_INFO "%s: link down.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004261 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004262 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4263 bmcr |= BMCR_ANENABLE;
4264 /* reset the phy in order for settings to stick,
4265 * and cause autoneg to start */
4266 if (phy_reset(dev, bmcr)) {
4267 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4268 return -EINVAL;
4269 }
4270 } else {
4271 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4272 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4273 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004274 } else {
4275 int adv, bmcr;
4276
4277 np->autoneg = 0;
4278
4279 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004280 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004281 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4282 adv |= ADVERTISE_10HALF;
4283 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004284 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004285 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4286 adv |= ADVERTISE_100HALF;
4287 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004288 adv |= ADVERTISE_100FULL;
4289 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4290 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4291 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4292 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4293 }
4294 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4295 adv |= ADVERTISE_PAUSE_ASYM;
4296 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4297 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004298 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4299 np->fixed_mode = adv;
4300
4301 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004302 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004303 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004304 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004305 }
4306
4307 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004308 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4309 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004310 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004311 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004312 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004313 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004314 /* reset the phy in order for forced mode settings to stick */
4315 if (phy_reset(dev, bmcr)) {
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004316 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4317 return -EINVAL;
4318 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004319 } else {
4320 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4321 if (netif_running(dev)) {
4322 /* Wait a bit and then reconfigure the nic. */
4323 udelay(10);
4324 nv_linkchange(dev);
4325 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004326 }
4327 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004328
4329 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004330 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004331 nv_enable_irq(dev);
4332 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004333
4334 return 0;
4335}
4336
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004337#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004338
4339static int nv_get_regs_len(struct net_device *dev)
4340{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004341 struct fe_priv *np = netdev_priv(dev);
4342 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004343}
4344
4345static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4346{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004347 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004348 u8 __iomem *base = get_hwbase(dev);
4349 u32 *rbuf = buf;
4350 int i;
4351
4352 regs->version = FORCEDETH_REGS_VER;
4353 spin_lock_irq(&np->lock);
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004354 for (i = 0;i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004355 rbuf[i] = readl(base + i*sizeof(u32));
4356 spin_unlock_irq(&np->lock);
4357}
4358
4359static int nv_nway_reset(struct net_device *dev)
4360{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004361 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004362 int ret;
4363
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004364 if (np->autoneg) {
4365 int bmcr;
4366
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004367 netif_carrier_off(dev);
4368 if (netif_running(dev)) {
4369 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004370 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004371 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004372 spin_lock(&np->lock);
4373 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004374 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004375 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004376 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004377 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004378 printk(KERN_INFO "%s: link down.\n", dev->name);
4379 }
4380
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004381 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004382 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4383 bmcr |= BMCR_ANENABLE;
4384 /* reset the phy in order for settings to stick*/
4385 if (phy_reset(dev, bmcr)) {
4386 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4387 return -EINVAL;
4388 }
4389 } else {
4390 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4391 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4392 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004393
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004394 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004395 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004396 nv_enable_irq(dev);
4397 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004398 ret = 0;
4399 } else {
4400 ret = -EINVAL;
4401 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004402
4403 return ret;
4404}
4405
Zachary Amsden0674d592006-06-04 02:51:38 -07004406static int nv_set_tso(struct net_device *dev, u32 value)
4407{
4408 struct fe_priv *np = netdev_priv(dev);
4409
4410 if ((np->driver_data & DEV_HAS_CHECKSUM))
4411 return ethtool_op_set_tso(dev, value);
4412 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004413 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004414}
Zachary Amsden0674d592006-06-04 02:51:38 -07004415
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004416static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4417{
4418 struct fe_priv *np = netdev_priv(dev);
4419
4420 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4421 ring->rx_mini_max_pending = 0;
4422 ring->rx_jumbo_max_pending = 0;
4423 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4424
4425 ring->rx_pending = np->rx_ring_size;
4426 ring->rx_mini_pending = 0;
4427 ring->rx_jumbo_pending = 0;
4428 ring->tx_pending = np->tx_ring_size;
4429}
4430
4431static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4432{
4433 struct fe_priv *np = netdev_priv(dev);
4434 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004435 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004436 dma_addr_t ring_addr;
4437
4438 if (ring->rx_pending < RX_RING_MIN ||
4439 ring->tx_pending < TX_RING_MIN ||
4440 ring->rx_mini_pending != 0 ||
4441 ring->rx_jumbo_pending != 0 ||
4442 (np->desc_ver == DESC_VER_1 &&
4443 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4444 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4445 (np->desc_ver != DESC_VER_1 &&
4446 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4447 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4448 return -EINVAL;
4449 }
4450
4451 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004452 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004453 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4454 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4455 &ring_addr);
4456 } else {
4457 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4458 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4459 &ring_addr);
4460 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004461 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4462 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4463 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004464 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004465 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004466 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004467 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4468 rxtx_ring, ring_addr);
4469 } else {
4470 if (rxtx_ring)
4471 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4472 rxtx_ring, ring_addr);
4473 }
4474 if (rx_skbuff)
4475 kfree(rx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004476 if (tx_skbuff)
4477 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004478 goto exit;
4479 }
4480
4481 if (netif_running(dev)) {
4482 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004483 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004484 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004485 spin_lock(&np->lock);
4486 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004487 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004488 nv_txrx_reset(dev);
4489 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004490 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004491 /* delete queues */
4492 free_rings(dev);
4493 }
4494
4495 /* set new values */
4496 np->rx_ring_size = ring->rx_pending;
4497 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004498
4499 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004500 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4501 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4502 } else {
4503 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4504 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4505 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004506 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4507 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004508 np->ring_addr = ring_addr;
4509
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004510 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4511 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004512
4513 if (netif_running(dev)) {
4514 /* reinit driver view of the queues */
4515 set_bufsize(dev);
4516 if (nv_init_ring(dev)) {
4517 if (!np->in_shutdown)
4518 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4519 }
4520
4521 /* reinit nic view of the queues */
4522 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4523 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4524 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4525 base + NvRegRingSizes);
4526 pci_push(base);
4527 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4528 pci_push(base);
4529
4530 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004531 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004532 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004533 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004534 netif_tx_unlock_bh(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004535 nv_enable_irq(dev);
4536 }
4537 return 0;
4538exit:
4539 return -ENOMEM;
4540}
4541
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004542static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4543{
4544 struct fe_priv *np = netdev_priv(dev);
4545
4546 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4547 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4548 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4549}
4550
4551static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4552{
4553 struct fe_priv *np = netdev_priv(dev);
4554 int adv, bmcr;
4555
4556 if ((!np->autoneg && np->duplex == 0) ||
4557 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4558 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4559 dev->name);
4560 return -EINVAL;
4561 }
4562 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4563 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4564 return -EINVAL;
4565 }
4566
4567 netif_carrier_off(dev);
4568 if (netif_running(dev)) {
4569 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004570 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004571 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004572 spin_lock(&np->lock);
4573 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004574 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004575 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004576 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004577 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004578 }
4579
4580 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4581 if (pause->rx_pause)
4582 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4583 if (pause->tx_pause)
4584 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4585
4586 if (np->autoneg && pause->autoneg) {
4587 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4588
4589 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4590 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4591 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4592 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4593 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4594 adv |= ADVERTISE_PAUSE_ASYM;
4595 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4596
4597 if (netif_running(dev))
4598 printk(KERN_INFO "%s: link down.\n", dev->name);
4599 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4600 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4601 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4602 } else {
4603 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4604 if (pause->rx_pause)
4605 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4606 if (pause->tx_pause)
4607 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4608
4609 if (!netif_running(dev))
4610 nv_update_linkspeed(dev);
4611 else
4612 nv_update_pause(dev, np->pause_flags);
4613 }
4614
4615 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004616 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004617 nv_enable_irq(dev);
4618 }
4619 return 0;
4620}
4621
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004622static u32 nv_get_rx_csum(struct net_device *dev)
4623{
4624 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004625 return (np->rx_csum) != 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004626}
4627
4628static int nv_set_rx_csum(struct net_device *dev, u32 data)
4629{
4630 struct fe_priv *np = netdev_priv(dev);
4631 u8 __iomem *base = get_hwbase(dev);
4632 int retcode = 0;
4633
4634 if (np->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004635 if (data) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004636 np->rx_csum = 1;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004637 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004638 } else {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004639 np->rx_csum = 0;
4640 /* vlan is dependent on rx checksum offload */
4641 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4642 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004643 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004644 if (netif_running(dev)) {
4645 spin_lock_irq(&np->lock);
4646 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4647 spin_unlock_irq(&np->lock);
4648 }
4649 } else {
4650 return -EINVAL;
4651 }
4652
4653 return retcode;
4654}
4655
4656static int nv_set_tx_csum(struct net_device *dev, u32 data)
4657{
4658 struct fe_priv *np = netdev_priv(dev);
4659
4660 if (np->driver_data & DEV_HAS_CHECKSUM)
4661 return ethtool_op_set_tx_hw_csum(dev, data);
4662 else
4663 return -EOPNOTSUPP;
4664}
4665
4666static int nv_set_sg(struct net_device *dev, u32 data)
4667{
4668 struct fe_priv *np = netdev_priv(dev);
4669
4670 if (np->driver_data & DEV_HAS_CHECKSUM)
4671 return ethtool_op_set_sg(dev, data);
4672 else
4673 return -EOPNOTSUPP;
4674}
4675
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004676static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004677{
4678 struct fe_priv *np = netdev_priv(dev);
4679
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004680 switch (sset) {
4681 case ETH_SS_TEST:
4682 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4683 return NV_TEST_COUNT_EXTENDED;
4684 else
4685 return NV_TEST_COUNT_BASE;
4686 case ETH_SS_STATS:
4687 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4688 return NV_DEV_STATISTICS_V1_COUNT;
4689 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4690 return NV_DEV_STATISTICS_V2_COUNT;
4691 else
4692 return 0;
4693 default:
4694 return -EOPNOTSUPP;
4695 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004696}
4697
4698static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4699{
4700 struct fe_priv *np = netdev_priv(dev);
4701
4702 /* update stats */
4703 nv_do_stats_poll((unsigned long)dev);
4704
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004705 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004706}
4707
4708static int nv_link_test(struct net_device *dev)
4709{
4710 struct fe_priv *np = netdev_priv(dev);
4711 int mii_status;
4712
4713 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4714 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4715
4716 /* check phy link status */
4717 if (!(mii_status & BMSR_LSTATUS))
4718 return 0;
4719 else
4720 return 1;
4721}
4722
4723static int nv_register_test(struct net_device *dev)
4724{
4725 u8 __iomem *base = get_hwbase(dev);
4726 int i = 0;
4727 u32 orig_read, new_read;
4728
4729 do {
4730 orig_read = readl(base + nv_registers_test[i].reg);
4731
4732 /* xor with mask to toggle bits */
4733 orig_read ^= nv_registers_test[i].mask;
4734
4735 writel(orig_read, base + nv_registers_test[i].reg);
4736
4737 new_read = readl(base + nv_registers_test[i].reg);
4738
4739 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4740 return 0;
4741
4742 /* restore original value */
4743 orig_read ^= nv_registers_test[i].mask;
4744 writel(orig_read, base + nv_registers_test[i].reg);
4745
4746 } while (nv_registers_test[++i].reg != 0);
4747
4748 return 1;
4749}
4750
4751static int nv_interrupt_test(struct net_device *dev)
4752{
4753 struct fe_priv *np = netdev_priv(dev);
4754 u8 __iomem *base = get_hwbase(dev);
4755 int ret = 1;
4756 int testcnt;
4757 u32 save_msi_flags, save_poll_interval = 0;
4758
4759 if (netif_running(dev)) {
4760 /* free current irq */
4761 nv_free_irq(dev);
4762 save_poll_interval = readl(base+NvRegPollingInterval);
4763 }
4764
4765 /* flag to test interrupt handler */
4766 np->intr_test = 0;
4767
4768 /* setup test irq */
4769 save_msi_flags = np->msi_flags;
4770 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4771 np->msi_flags |= 0x001; /* setup 1 vector */
4772 if (nv_request_irq(dev, 1))
4773 return 0;
4774
4775 /* setup timer interrupt */
4776 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4777 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4778
4779 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4780
4781 /* wait for at least one interrupt */
4782 msleep(100);
4783
4784 spin_lock_irq(&np->lock);
4785
4786 /* flag should be set within ISR */
4787 testcnt = np->intr_test;
4788 if (!testcnt)
4789 ret = 2;
4790
4791 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4792 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4793 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4794 else
4795 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4796
4797 spin_unlock_irq(&np->lock);
4798
4799 nv_free_irq(dev);
4800
4801 np->msi_flags = save_msi_flags;
4802
4803 if (netif_running(dev)) {
4804 writel(save_poll_interval, base + NvRegPollingInterval);
4805 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4806 /* restore original irq */
4807 if (nv_request_irq(dev, 0))
4808 return 0;
4809 }
4810
4811 return ret;
4812}
4813
4814static int nv_loopback_test(struct net_device *dev)
4815{
4816 struct fe_priv *np = netdev_priv(dev);
4817 u8 __iomem *base = get_hwbase(dev);
4818 struct sk_buff *tx_skb, *rx_skb;
4819 dma_addr_t test_dma_addr;
4820 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004821 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004822 int len, i, pkt_len;
4823 u8 *pkt_data;
4824 u32 filter_flags = 0;
4825 u32 misc1_flags = 0;
4826 int ret = 1;
4827
4828 if (netif_running(dev)) {
4829 nv_disable_irq(dev);
4830 filter_flags = readl(base + NvRegPacketFilterFlags);
4831 misc1_flags = readl(base + NvRegMisc1);
4832 } else {
4833 nv_txrx_reset(dev);
4834 }
4835
4836 /* reinit driver view of the rx queue */
4837 set_bufsize(dev);
4838 nv_init_ring(dev);
4839
4840 /* setup hardware for loopback */
4841 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4842 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4843
4844 /* reinit nic view of the rx queue */
4845 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4846 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4847 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4848 base + NvRegRingSizes);
4849 pci_push(base);
4850
4851 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004852 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004853
4854 /* setup packet for tx */
4855 pkt_len = ETH_DATA_LEN;
4856 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07004857 if (!tx_skb) {
4858 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4859 " of %s\n", dev->name);
4860 ret = 0;
4861 goto out;
4862 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03004863 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4864 skb_tailroom(tx_skb),
4865 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004866 pkt_data = skb_put(tx_skb, pkt_len);
4867 for (i = 0; i < pkt_len; i++)
4868 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004869
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004870 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004871 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4872 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004873 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00004874 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4875 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004876 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004877 }
4878 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4879 pci_push(get_hwbase(dev));
4880
4881 msleep(500);
4882
4883 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004884 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004885 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004886 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4887
4888 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004889 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004890 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4891 }
4892
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004893 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004894 ret = 0;
4895 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004896 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004897 ret = 0;
4898 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004899 if (flags & NV_RX2_ERROR) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004900 ret = 0;
4901 }
4902 }
4903
4904 if (ret) {
4905 if (len != pkt_len) {
4906 ret = 0;
4907 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4908 dev->name, len, pkt_len);
4909 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004910 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004911 for (i = 0; i < pkt_len; i++) {
4912 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4913 ret = 0;
4914 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4915 dev->name, i);
4916 break;
4917 }
4918 }
4919 }
4920 } else {
4921 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4922 }
4923
4924 pci_unmap_page(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07004925 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004926 PCI_DMA_TODEVICE);
4927 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07004928 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004929 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004930 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004931 nv_txrx_reset(dev);
4932 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004933 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004934
4935 if (netif_running(dev)) {
4936 writel(misc1_flags, base + NvRegMisc1);
4937 writel(filter_flags, base + NvRegPacketFilterFlags);
4938 nv_enable_irq(dev);
4939 }
4940
4941 return ret;
4942}
4943
4944static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4945{
4946 struct fe_priv *np = netdev_priv(dev);
4947 u8 __iomem *base = get_hwbase(dev);
4948 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004949 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004950
4951 if (!nv_link_test(dev)) {
4952 test->flags |= ETH_TEST_FL_FAILED;
4953 buffer[0] = 1;
4954 }
4955
4956 if (test->flags & ETH_TEST_FL_OFFLINE) {
4957 if (netif_running(dev)) {
4958 netif_stop_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004959#ifdef CONFIG_FORCEDETH_NAPI
4960 napi_disable(&np->napi);
4961#endif
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004962 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004963 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004964 spin_lock_irq(&np->lock);
4965 nv_disable_hw_interrupts(dev, np->irqmask);
4966 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4967 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4968 } else {
4969 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4970 }
4971 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004972 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004973 nv_txrx_reset(dev);
4974 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004975 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004976 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004977 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004978 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004979 }
4980
4981 if (!nv_register_test(dev)) {
4982 test->flags |= ETH_TEST_FL_FAILED;
4983 buffer[1] = 1;
4984 }
4985
4986 result = nv_interrupt_test(dev);
4987 if (result != 1) {
4988 test->flags |= ETH_TEST_FL_FAILED;
4989 buffer[2] = 1;
4990 }
4991 if (result == 0) {
4992 /* bail out */
4993 return;
4994 }
4995
4996 if (!nv_loopback_test(dev)) {
4997 test->flags |= ETH_TEST_FL_FAILED;
4998 buffer[3] = 1;
4999 }
5000
5001 if (netif_running(dev)) {
5002 /* reinit driver view of the rx queue */
5003 set_bufsize(dev);
5004 if (nv_init_ring(dev)) {
5005 if (!np->in_shutdown)
5006 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5007 }
5008 /* reinit nic view of the rx queue */
5009 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5010 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5011 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5012 base + NvRegRingSizes);
5013 pci_push(base);
5014 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5015 pci_push(base);
5016 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005017 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005018 netif_start_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005019#ifdef CONFIG_FORCEDETH_NAPI
5020 napi_enable(&np->napi);
5021#endif
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005022 nv_enable_hw_interrupts(dev, np->irqmask);
5023 }
5024 }
5025}
5026
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005027static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5028{
5029 switch (stringset) {
5030 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005031 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005032 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005033 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005034 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005035 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005036 }
5037}
5038
Jeff Garzik7282d492006-09-13 14:30:00 -04005039static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005040 .get_drvinfo = nv_get_drvinfo,
5041 .get_link = ethtool_op_get_link,
5042 .get_wol = nv_get_wol,
5043 .set_wol = nv_set_wol,
5044 .get_settings = nv_get_settings,
5045 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005046 .get_regs_len = nv_get_regs_len,
5047 .get_regs = nv_get_regs,
5048 .nway_reset = nv_nway_reset,
Ayaz Abdulla6a788142006-06-10 22:47:26 -04005049 .set_tso = nv_set_tso,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005050 .get_ringparam = nv_get_ringparam,
5051 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005052 .get_pauseparam = nv_get_pauseparam,
5053 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005054 .get_rx_csum = nv_get_rx_csum,
5055 .set_rx_csum = nv_set_rx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005056 .set_tx_csum = nv_set_tx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005057 .set_sg = nv_set_sg,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005058 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005059 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005060 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005061 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005062};
5063
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005064static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5065{
5066 struct fe_priv *np = get_nvpriv(dev);
5067
5068 spin_lock_irq(&np->lock);
5069
5070 /* save vlan group */
5071 np->vlangrp = grp;
5072
5073 if (grp) {
5074 /* enable vlan on MAC */
5075 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5076 } else {
5077 /* disable vlan on MAC */
5078 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5079 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5080 }
5081
5082 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5083
5084 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07005085}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005086
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005087/* The mgmt unit and driver use a semaphore to access the phy during init */
5088static int nv_mgmt_acquire_sema(struct net_device *dev)
5089{
5090 u8 __iomem *base = get_hwbase(dev);
5091 int i;
5092 u32 tx_ctrl, mgmt_sema;
5093
5094 for (i = 0; i < 10; i++) {
5095 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5096 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5097 break;
5098 msleep(500);
5099 }
5100
5101 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5102 return 0;
5103
5104 for (i = 0; i < 2; i++) {
5105 tx_ctrl = readl(base + NvRegTransmitterControl);
5106 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5107 writel(tx_ctrl, base + NvRegTransmitterControl);
5108
5109 /* verify that semaphore was acquired */
5110 tx_ctrl = readl(base + NvRegTransmitterControl);
5111 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5112 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5113 return 1;
5114 else
5115 udelay(50);
5116 }
5117
5118 return 0;
5119}
5120
Linus Torvalds1da177e2005-04-16 15:20:36 -07005121static int nv_open(struct net_device *dev)
5122{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005123 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005124 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005125 int ret = 1;
5126 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005127 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005128
5129 dprintk(KERN_DEBUG "nv_open: begin\n");
5130
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005131 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005132 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5133 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005134 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5135 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005136 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5137 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005138 writel(0, base + NvRegPacketFilterFlags);
5139
5140 writel(0, base + NvRegTransmitterControl);
5141 writel(0, base + NvRegReceiverControl);
5142
5143 writel(0, base + NvRegAdapterControl);
5144
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005145 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5146 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5147
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005148 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005149 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005150 oom = nv_init_ring(dev);
5151
5152 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005153 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005154 nv_txrx_reset(dev);
5155 writel(0, base + NvRegUnknownSetupReg6);
5156
5157 np->in_shutdown = 0;
5158
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005159 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005160 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005161 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005162 base + NvRegRingSizes);
5163
Linus Torvalds1da177e2005-04-16 15:20:36 -07005164 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005165 if (np->desc_ver == DESC_VER_1)
5166 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5167 else
5168 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005169 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005170 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005171 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005172 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005173 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5174 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5175 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5176
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005177 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005178 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005179 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005180
Linus Torvalds1da177e2005-04-16 15:20:36 -07005181 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5182 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5183 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005184 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005185
5186 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005187
5188 get_random_bytes(&low, sizeof(low));
5189 low &= NVREG_SLOTTIME_MASK;
5190 if (np->desc_ver == DESC_VER_1) {
5191 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5192 } else {
5193 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5194 /* setup legacy backoff */
5195 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5196 } else {
5197 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5198 nv_gear_backoff_reseed(dev);
5199 }
5200 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005201 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5202 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005203 if (poll_interval == -1) {
5204 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5205 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5206 else
5207 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5208 }
5209 else
5210 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005211 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5212 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5213 base + NvRegAdapterControl);
5214 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005215 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005216 if (np->wolenabled)
5217 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005218
5219 i = readl(base + NvRegPowerState);
5220 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5221 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5222
5223 pci_push(base);
5224 udelay(10);
5225 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5226
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005227 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005228 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005229 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005230 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5231 pci_push(base);
5232
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005233 if (nv_request_irq(dev, 0)) {
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005234 goto out_drain;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005235 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005236
5237 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005238 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005239
5240 spin_lock_irq(&np->lock);
5241 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5242 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005243 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5244 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005245 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5246 /* One manual link speed update: Interrupts are enabled, future link
5247 * speed changes cause interrupts and are handled by nv_link_irq().
5248 */
5249 {
5250 u32 miistat;
5251 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005252 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005253 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5254 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005255 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5256 * to init hw */
5257 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005258 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005259 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005260 netif_start_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005261#ifdef CONFIG_FORCEDETH_NAPI
5262 napi_enable(&np->napi);
5263#endif
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005264
Linus Torvalds1da177e2005-04-16 15:20:36 -07005265 if (ret) {
5266 netif_carrier_on(dev);
5267 } else {
Ed Swierkf7ab6972007-09-28 22:42:13 -07005268 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005269 netif_carrier_off(dev);
5270 }
5271 if (oom)
5272 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005273
5274 /* start statistics timer */
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005275 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005276 mod_timer(&np->stats_poll,
5277 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005278
Linus Torvalds1da177e2005-04-16 15:20:36 -07005279 spin_unlock_irq(&np->lock);
5280
5281 return 0;
5282out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005283 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005284 return ret;
5285}
5286
5287static int nv_close(struct net_device *dev)
5288{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005289 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005290 u8 __iomem *base;
5291
5292 spin_lock_irq(&np->lock);
5293 np->in_shutdown = 1;
5294 spin_unlock_irq(&np->lock);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005295#ifdef CONFIG_FORCEDETH_NAPI
5296 napi_disable(&np->napi);
5297#endif
Manfred Spraula7475902007-10-17 21:52:33 +02005298 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005299
5300 del_timer_sync(&np->oom_kick);
5301 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005302 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005303
5304 netif_stop_queue(dev);
5305 spin_lock_irq(&np->lock);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005306 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005307 nv_txrx_reset(dev);
5308
5309 /* disable interrupts on the nic or we will lock up */
5310 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005311 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005312 pci_push(base);
5313 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5314
5315 spin_unlock_irq(&np->lock);
5316
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005317 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005318
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005319 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005320
Tim Mann2cc49a52007-06-14 13:16:38 -07005321 if (np->wolenabled) {
5322 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005323 nv_start_rx(dev);
Tim Mann2cc49a52007-06-14 13:16:38 -07005324 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005325
5326 /* FIXME: power down nic */
5327
5328 return 0;
5329}
5330
5331static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5332{
5333 struct net_device *dev;
5334 struct fe_priv *np;
5335 unsigned long addr;
5336 u8 __iomem *base;
5337 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005338 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005339 u32 phystate_orig = 0, phystate;
5340 int phyinitialized = 0;
Joe Perches0795af52007-10-03 17:59:30 -07005341 DECLARE_MAC_BUF(mac);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005342 static int printed_version;
5343
5344 if (!printed_version++)
5345 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5346 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005347
5348 dev = alloc_etherdev(sizeof(struct fe_priv));
5349 err = -ENOMEM;
5350 if (!dev)
5351 goto out;
5352
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005353 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005354 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005355 np->pci_dev = pci_dev;
5356 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005357 SET_NETDEV_DEV(dev, &pci_dev->dev);
5358
5359 init_timer(&np->oom_kick);
5360 np->oom_kick.data = (unsigned long) dev;
5361 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5362 init_timer(&np->nic_poll);
5363 np->nic_poll.data = (unsigned long) dev;
5364 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005365 init_timer(&np->stats_poll);
5366 np->stats_poll.data = (unsigned long) dev;
5367 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005368
5369 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005370 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005371 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005372
5373 pci_set_master(pci_dev);
5374
5375 err = pci_request_regions(pci_dev, DRV_NAME);
5376 if (err < 0)
5377 goto out_disable;
5378
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005379 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5380 np->register_size = NV_PCI_REGSZ_VER3;
5381 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005382 np->register_size = NV_PCI_REGSZ_VER2;
5383 else
5384 np->register_size = NV_PCI_REGSZ_VER1;
5385
Linus Torvalds1da177e2005-04-16 15:20:36 -07005386 err = -EINVAL;
5387 addr = 0;
5388 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5389 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5390 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5391 pci_resource_len(pci_dev, i),
5392 pci_resource_flags(pci_dev, i));
5393 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005394 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005395 addr = pci_resource_start(pci_dev, i);
5396 break;
5397 }
5398 }
5399 if (i == DEVICE_COUNT_RESOURCE) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005400 dev_printk(KERN_INFO, &pci_dev->dev,
5401 "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005402 goto out_relreg;
5403 }
5404
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005405 /* copy of driver data */
5406 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005407 /* copy of device id */
5408 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005409
Linus Torvalds1da177e2005-04-16 15:20:36 -07005410 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005411 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5412 /* packet format 3: supports 40-bit addressing */
5413 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005414 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005415 if (dma_64bit) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005416 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5417 dev_printk(KERN_INFO, &pci_dev->dev,
5418 "64-bit DMA failed, using 32-bit addressing\n");
5419 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005420 dev->features |= NETIF_F_HIGHDMA;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005421 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005422 dev_printk(KERN_INFO, &pci_dev->dev,
5423 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005424 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005425 }
Manfred Spraulee733622005-07-31 18:32:26 +02005426 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5427 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005428 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005429 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005430 } else {
5431 /* original packet format */
5432 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005433 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005434 }
Manfred Spraulee733622005-07-31 18:32:26 +02005435
5436 np->pkt_limit = NV_PKTLIMIT_1;
5437 if (id->driver_data & DEV_HAS_LARGEDESC)
5438 np->pkt_limit = NV_PKTLIMIT_2;
5439
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005440 if (id->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04005441 np->rx_csum = 1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005442 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005443 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
Ayaz Abdullafa454592006-01-05 22:45:45 -08005444 dev->features |= NETIF_F_TSO;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005445 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005446
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005447 np->vlanctl_bits = 0;
5448 if (id->driver_data & DEV_HAS_VLAN) {
5449 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5450 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5451 dev->vlan_rx_register = nv_vlan_rx_register;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005452 }
5453
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005454 np->msi_flags = 0;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005455 if ((id->driver_data & DEV_HAS_MSI) && msi) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005456 np->msi_flags |= NV_MSI_CAPABLE;
5457 }
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005458 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005459 np->msi_flags |= NV_MSI_X_CAPABLE;
5460 }
5461
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005462 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005463 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5464 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5465 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005466 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005467 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005468
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005469
Linus Torvalds1da177e2005-04-16 15:20:36 -07005470 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005471 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005472 if (!np->base)
5473 goto out_relreg;
5474 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005475
Linus Torvalds1da177e2005-04-16 15:20:36 -07005476 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005477
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005478 np->rx_ring_size = RX_RING_DEFAULT;
5479 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005480
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005481 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005482 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005483 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005484 &np->ring_addr);
5485 if (!np->rx_ring.orig)
5486 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005487 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005488 } else {
5489 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005490 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005491 &np->ring_addr);
5492 if (!np->rx_ring.ex)
5493 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005494 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005495 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005496 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5497 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005498 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005499 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005500
5501 dev->open = nv_open;
5502 dev->stop = nv_close;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005503
5504 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005505 dev->hard_start_xmit = nv_start_xmit;
5506 else
5507 dev->hard_start_xmit = nv_start_xmit_optimized;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005508 dev->get_stats = nv_get_stats;
5509 dev->change_mtu = nv_change_mtu;
Manfred Spraul72b31782005-07-31 18:33:34 +02005510 dev->set_mac_address = nv_set_mac_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005511 dev->set_multicast_list = nv_set_multicast;
Michal Schmidt2918c352005-05-12 19:42:06 -04005512#ifdef CONFIG_NET_POLL_CONTROLLER
5513 dev->poll_controller = nv_poll_controller;
5514#endif
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005515#ifdef CONFIG_FORCEDETH_NAPI
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005516 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005517#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07005518 SET_ETHTOOL_OPS(dev, &ops);
5519 dev->tx_timeout = nv_tx_timeout;
5520 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5521
5522 pci_set_drvdata(pci_dev, dev);
5523
5524 /* read the mac address */
5525 base = get_hwbase(dev);
5526 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5527 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5528
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005529 /* check the workaround bit for correct mac address order */
5530 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005531 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005532 /* mac address is already in correct order */
5533 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5534 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5535 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5536 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5537 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5538 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005539 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5540 /* mac address is already in correct order */
5541 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5542 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5543 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5544 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5545 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5546 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5547 /*
5548 * Set orig mac address back to the reversed version.
5549 * This flag will be cleared during low power transition.
5550 * Therefore, we should always put back the reversed address.
5551 */
5552 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5553 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5554 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005555 } else {
5556 /* need to reverse mac address to correct order */
5557 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5558 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5559 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5560 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5561 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5562 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005563 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5564 }
John W. Linvillec704b852005-09-12 10:48:56 -04005565 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005566
John W. Linvillec704b852005-09-12 10:48:56 -04005567 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005568 /*
5569 * Bad mac address. At least one bios sets the mac address
5570 * to 01:23:45:67:89:ab
5571 */
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005572 dev_printk(KERN_ERR, &pci_dev->dev,
5573 "Invalid Mac address detected: %s\n",
5574 print_mac(mac, dev->dev_addr));
5575 dev_printk(KERN_ERR, &pci_dev->dev,
5576 "Please complain to your hardware vendor. Switching to a random MAC.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005577 dev->dev_addr[0] = 0x00;
5578 dev->dev_addr[1] = 0x00;
5579 dev->dev_addr[2] = 0x6c;
5580 get_random_bytes(&dev->dev_addr[3], 3);
5581 }
5582
Joe Perches0795af52007-10-03 17:59:30 -07005583 dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5584 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005585
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005586 /* set mac address */
5587 nv_copy_mac_to_hw(dev);
5588
Tobias Diedrich9a60a822008-06-01 00:54:42 +02005589 /* Workaround current PCI init glitch: wakeup bits aren't
5590 * being set from PCI PM capability.
5591 */
5592 device_init_wakeup(&pci_dev->dev, 1);
5593
Linus Torvalds1da177e2005-04-16 15:20:36 -07005594 /* disable WOL */
5595 writel(0, base + NvRegWakeUpFlags);
5596 np->wolenabled = 0;
5597
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005598 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005599
5600 /* take phy and nic out of low power mode */
5601 powerstate = readl(base + NvRegPowerState2);
5602 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5603 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5604 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
Auke Kok44c10132007-06-08 15:46:36 -07005605 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005606 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5607 writel(powerstate, base + NvRegPowerState2);
5608 }
5609
Linus Torvalds1da177e2005-04-16 15:20:36 -07005610 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005611 np->tx_flags = NV_TX_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005612 } else {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005613 np->tx_flags = NV_TX2_VALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005614 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005615 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005616 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005617 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5618 np->msi_flags |= 0x0003;
5619 } else {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005620 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005621 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5622 np->msi_flags |= 0x0001;
5623 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005624
Linus Torvalds1da177e2005-04-16 15:20:36 -07005625 if (id->driver_data & DEV_NEED_TIMERIRQ)
5626 np->irqmask |= NVREG_IRQ_TIMER;
5627 if (id->driver_data & DEV_NEED_LINKTIMER) {
5628 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5629 np->need_linktimer = 1;
5630 np->link_timeout = jiffies + LINK_TIMEOUT;
5631 } else {
5632 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5633 np->need_linktimer = 0;
5634 }
5635
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005636 /* Limit the number of tx's outstanding for hw bug */
5637 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5638 np->tx_limit = 1;
5639 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5640 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5641 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5642 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5643 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5644 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5645 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5646 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5647 pci_dev->revision >= 0xA2)
5648 np->tx_limit = 0;
5649 }
5650
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005651 /* clear phy state and temporarily halt phy interrupts */
5652 writel(0, base + NvRegMIIMask);
5653 phystate = readl(base + NvRegAdapterControl);
5654 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5655 phystate_orig = 1;
5656 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5657 writel(phystate, base + NvRegAdapterControl);
5658 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005659 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005660
5661 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005662 /* management unit running on the mac? */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005663 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5664 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5665 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
Ayaz Abdulla9e555932007-11-21 15:02:58 -08005666 if (nv_mgmt_acquire_sema(dev)) {
5667 /* management unit setup the phy already? */
5668 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5669 NVREG_XMITCTL_SYNC_PHY_INIT) {
5670 /* phy is inited by mgmt unit */
5671 phyinitialized = 1;
5672 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5673 } else {
5674 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005675 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005676 }
5677 }
5678 }
5679
Linus Torvalds1da177e2005-04-16 15:20:36 -07005680 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005681 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005682 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005683 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005684
5685 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005686 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005687 spin_unlock_irq(&np->lock);
5688 if (id1 < 0 || id1 == 0xffff)
5689 continue;
5690 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005691 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005692 spin_unlock_irq(&np->lock);
5693 if (id2 < 0 || id2 == 0xffff)
5694 continue;
5695
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005696 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005697 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5698 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5699 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005700 pci_name(pci_dev), id1, id2, phyaddr);
5701 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005702 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005703
5704 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5705 if (np->phy_oui == PHY_OUI_REALTEK2)
5706 np->phy_oui = PHY_OUI_REALTEK;
5707 /* Setup phy revision for Realtek */
5708 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5709 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5710
Linus Torvalds1da177e2005-04-16 15:20:36 -07005711 break;
5712 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005713 if (i == 33) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005714 dev_printk(KERN_INFO, &pci_dev->dev,
5715 "open: Could not find a valid PHY.\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005716 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005717 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005718
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005719 if (!phyinitialized) {
5720 /* reset it */
5721 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005722 } else {
5723 /* see if it is a gigabit phy */
5724 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5725 if (mii_status & PHY_GIGABIT) {
5726 np->gigabit = PHY_GIGABIT;
5727 }
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005728 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005729
5730 /* set default link speed settings */
5731 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5732 np->duplex = 0;
5733 np->autoneg = 1;
5734
5735 err = register_netdev(dev);
5736 if (err) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005737 dev_printk(KERN_INFO, &pci_dev->dev,
5738 "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005739 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005740 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005741
5742 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5743 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5744 dev->name,
5745 np->phy_oui,
5746 np->phyaddr,
5747 dev->dev_addr[0],
5748 dev->dev_addr[1],
5749 dev->dev_addr[2],
5750 dev->dev_addr[3],
5751 dev->dev_addr[4],
5752 dev->dev_addr[5]);
5753
5754 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5755 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5756 dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5757 "csum " : "",
5758 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5759 "vlan " : "",
5760 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5761 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5762 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5763 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5764 np->need_linktimer ? "lnktim " : "",
5765 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5766 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5767 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005768
5769 return 0;
5770
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005771out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005772 if (phystate_orig)
5773 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005774 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005775out_freering:
5776 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005777out_unmap:
5778 iounmap(get_hwbase(dev));
5779out_relreg:
5780 pci_release_regions(pci_dev);
5781out_disable:
5782 pci_disable_device(pci_dev);
5783out_free:
5784 free_netdev(dev);
5785out:
5786 return err;
5787}
5788
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005789static void nv_restore_phy(struct net_device *dev)
5790{
5791 struct fe_priv *np = netdev_priv(dev);
5792 u16 phy_reserved, mii_control;
5793
5794 if (np->phy_oui == PHY_OUI_REALTEK &&
5795 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5796 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5797 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5798 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5799 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5800 phy_reserved |= PHY_REALTEK_INIT8;
5801 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5802 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5803
5804 /* restart auto negotiation */
5805 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5806 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5807 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5808 }
5809}
5810
Linus Torvalds1da177e2005-04-16 15:20:36 -07005811static void __devexit nv_remove(struct pci_dev *pci_dev)
5812{
5813 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005814 struct fe_priv *np = netdev_priv(dev);
5815 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005816
5817 unregister_netdev(dev);
5818
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005819 /* special op: write back the misordered MAC address - otherwise
5820 * the next nv_probe would see a wrong address.
5821 */
5822 writel(np->orig_mac[0], base + NvRegMacAddrA);
5823 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08005824 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5825 base + NvRegTransmitPoll);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005826
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005827 /* restore any phy related changes */
5828 nv_restore_phy(dev);
5829
Linus Torvalds1da177e2005-04-16 15:20:36 -07005830 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005831 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005832 iounmap(get_hwbase(dev));
5833 pci_release_regions(pci_dev);
5834 pci_disable_device(pci_dev);
5835 free_netdev(dev);
5836 pci_set_drvdata(pci_dev, NULL);
5837}
5838
Francois Romieua1893172006-10-10 14:33:27 -07005839#ifdef CONFIG_PM
5840static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5841{
5842 struct net_device *dev = pci_get_drvdata(pdev);
5843 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005844 u8 __iomem *base = get_hwbase(dev);
5845 int i;
Francois Romieua1893172006-10-10 14:33:27 -07005846
Tobias Diedrich25d90812008-05-18 15:04:29 +02005847 if (netif_running(dev)) {
5848 // Gross.
5849 nv_close(dev);
5850 }
Francois Romieua1893172006-10-10 14:33:27 -07005851 netif_device_detach(dev);
5852
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005853 /* save non-pci configuration space */
5854 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5855 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5856
Francois Romieua1893172006-10-10 14:33:27 -07005857 pci_save_state(pdev);
5858 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005859 pci_disable_device(pdev);
Francois Romieua1893172006-10-10 14:33:27 -07005860 pci_set_power_state(pdev, pci_choose_state(pdev, state));
Francois Romieua1893172006-10-10 14:33:27 -07005861 return 0;
5862}
5863
5864static int nv_resume(struct pci_dev *pdev)
5865{
5866 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005867 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005868 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005869 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07005870
Francois Romieua1893172006-10-10 14:33:27 -07005871 pci_set_power_state(pdev, PCI_D0);
5872 pci_restore_state(pdev);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005873 /* ack any pending wake events, disable PME */
Francois Romieua1893172006-10-10 14:33:27 -07005874 pci_enable_wake(pdev, PCI_D0, 0);
5875
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005876 /* restore non-pci configuration space */
5877 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5878 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005879
Tobias Diedrich25d90812008-05-18 15:04:29 +02005880 netif_device_attach(dev);
5881 if (netif_running(dev)) {
5882 rc = nv_open(dev);
5883 nv_set_multicast(dev);
5884 }
Francois Romieua1893172006-10-10 14:33:27 -07005885 return rc;
5886}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005887
5888static void nv_shutdown(struct pci_dev *pdev)
5889{
5890 struct net_device *dev = pci_get_drvdata(pdev);
5891 struct fe_priv *np = netdev_priv(dev);
5892
5893 if (netif_running(dev))
5894 nv_close(dev);
5895
5896 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5897 pci_enable_wake(pdev, PCI_D3cold, np->wolenabled);
5898 pci_disable_device(pdev);
5899 pci_set_power_state(pdev, PCI_D3hot);
5900}
Francois Romieua1893172006-10-10 14:33:27 -07005901#else
5902#define nv_suspend NULL
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005903#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07005904#define nv_resume NULL
5905#endif /* CONFIG_PM */
5906
Linus Torvalds1da177e2005-04-16 15:20:36 -07005907static struct pci_device_id pci_tbl[] = {
5908 { /* nForce Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005909 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005910 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005911 },
5912 { /* nForce2 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005913 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005914 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005915 },
5916 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005917 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005918 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005919 },
5920 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005921 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005922 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005923 },
5924 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005925 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005926 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005927 },
5928 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005929 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005930 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005931 },
5932 { /* nForce3 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005933 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005934 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005935 },
5936 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005937 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005938 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005939 },
5940 { /* CK804 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005941 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005942 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005943 },
5944 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005945 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005946 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005947 },
5948 { /* MCP04 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005949 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005950 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005951 },
5952 { /* MCP51 Ethernet Controller */
5953 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005954 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005955 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02005956 { /* MCP51 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005957 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005958 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02005959 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005960 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005961 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005962 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005963 },
5964 { /* MCP55 Ethernet Controller */
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005965 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005966 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02005967 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005968 { /* MCP61 Ethernet Controller */
5969 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005970 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005971 },
5972 { /* MCP61 Ethernet Controller */
5973 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005974 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005975 },
5976 { /* MCP61 Ethernet Controller */
5977 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005978 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005979 },
5980 { /* MCP61 Ethernet Controller */
5981 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005982 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005983 },
5984 { /* MCP65 Ethernet Controller */
5985 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005986 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005987 },
5988 { /* MCP65 Ethernet Controller */
5989 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005990 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005991 },
5992 { /* MCP65 Ethernet Controller */
5993 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005994 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005995 },
5996 { /* MCP65 Ethernet Controller */
5997 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005998 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04005999 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006000 { /* MCP67 Ethernet Controller */
6001 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006002 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006003 },
6004 { /* MCP67 Ethernet Controller */
6005 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006006 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006007 },
6008 { /* MCP67 Ethernet Controller */
6009 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006010 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006011 },
6012 { /* MCP67 Ethernet Controller */
6013 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006014 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006015 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04006016 { /* MCP73 Ethernet Controller */
6017 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006018 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006019 },
6020 { /* MCP73 Ethernet Controller */
6021 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006022 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006023 },
6024 { /* MCP73 Ethernet Controller */
6025 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006026 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006027 },
6028 { /* MCP73 Ethernet Controller */
6029 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006030 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006031 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006032 { /* MCP77 Ethernet Controller */
6033 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006034 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006035 },
6036 { /* MCP77 Ethernet Controller */
6037 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006038 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006039 },
6040 { /* MCP77 Ethernet Controller */
6041 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006042 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006043 },
6044 { /* MCP77 Ethernet Controller */
6045 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006046 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006047 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006048 { /* MCP79 Ethernet Controller */
6049 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006050 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006051 },
6052 { /* MCP79 Ethernet Controller */
6053 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006054 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006055 },
6056 { /* MCP79 Ethernet Controller */
6057 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006058 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006059 },
6060 { /* MCP79 Ethernet Controller */
6061 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
Ayaz Abdullaa4336862008-04-18 13:50:43 -07006062 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006063 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07006064 {0,},
6065};
6066
6067static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006068 .name = DRV_NAME,
6069 .id_table = pci_tbl,
6070 .probe = nv_probe,
6071 .remove = __devexit_p(nv_remove),
6072 .suspend = nv_suspend,
6073 .resume = nv_resume,
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006074 .shutdown = nv_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006075};
6076
Linus Torvalds1da177e2005-04-16 15:20:36 -07006077static int __init init_nic(void)
6078{
Jeff Garzik29917622006-08-19 17:48:59 -04006079 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006080}
6081
6082static void __exit exit_nic(void)
6083{
6084 pci_unregister_driver(&driver);
6085}
6086
6087module_param(max_interrupt_work, int, 0);
6088MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006089module_param(optimization_mode, int, 0);
6090MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6091module_param(poll_interval, int, 0);
6092MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04006093module_param(msi, int, 0);
6094MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6095module_param(msix, int, 0);
6096MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6097module_param(dma_64bit, int, 0);
6098MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006099module_param(phy_cross, int, 0);
6100MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006101
6102MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6103MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6104MODULE_LICENSE("GPL");
6105
6106MODULE_DEVICE_TABLE(pci, pci_tbl);
6107
6108module_init(init_nic);
6109module_exit(exit_nic);