blob: bfbe52691f2c8feb474be5af3d9eccaea1e4e287 [file] [log] [blame]
David Howells0bc42d72010-10-27 17:28:41 +01001#
2# MN10300 CPU cache options
3#
4
5choice
6 prompt "CPU Caching mode"
7 default MN10300_CACHE_WBACK
8 help
9 This option determines the caching mode for the kernel.
10
11 Write-Back caching mode involves the all reads and writes causing
12 the affected cacheline to be read into the cache first before being
13 operated upon. Memory is not then updated by a write until the cache
14 is filled and a cacheline needs to be displaced from the cache to
15 make room. Only at that point is it written back.
16
17 Write-Through caching only fetches cachelines from memory on a
18 read. Writes always get written directly to memory. If the affected
19 cacheline is also in cache, it will be updated too.
20
21 The final option is to turn of caching entirely.
22
23config MN10300_CACHE_WBACK
24 bool "Write-Back"
David Howellsb4784912010-10-27 17:28:46 +010025 help
26 The dcache operates in delayed write-back mode. It must be manually
27 flushed if writes are made that subsequently need to be executed or
28 to be DMA'd by a device.
David Howells0bc42d72010-10-27 17:28:41 +010029
30config MN10300_CACHE_WTHRU
31 bool "Write-Through"
David Howellsb4784912010-10-27 17:28:46 +010032 help
33 The dcache operates in immediate write-through mode. Writes are
34 committed to RAM immediately in addition to being stored in the
35 cache. This means that the written data is immediately available for
36 execution or DMA.
37
38 This is not available for use with an SMP kernel if cache flushing
39 and invalidation by automatic purge register is not selected.
David Howells0bc42d72010-10-27 17:28:41 +010040
41config MN10300_CACHE_DISABLED
42 bool "Disabled"
David Howellsb4784912010-10-27 17:28:46 +010043 help
44 The icache and dcache are disabled.
David Howells0bc42d72010-10-27 17:28:41 +010045
46endchoice
David Howells344af922010-10-27 17:28:42 +010047
48config MN10300_CACHE_ENABLED
49 def_bool y if !MN10300_CACHE_DISABLED
David Howells518d4bb2010-10-27 17:28:43 +010050
51
52choice
53 prompt "CPU cache flush/invalidate method"
Akira Takeuchi9731d232010-10-27 17:28:45 +010054 default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2
55 default MN10300_CACHE_MANAGE_BY_REG if AM34_2
David Howells518d4bb2010-10-27 17:28:43 +010056 depends on MN10300_CACHE_ENABLED
57 help
58 This determines the method by which CPU cache flushing and
59 invalidation is performed.
60
61config MN10300_CACHE_MANAGE_BY_TAG
62 bool "Use the cache tag registers directly"
Akira Takeuchi8be06282010-10-27 17:28:47 +010063 depends on !(SMP && MN10300_CACHE_WTHRU)
David Howells518d4bb2010-10-27 17:28:43 +010064
Akira Takeuchi9731d232010-10-27 17:28:45 +010065config MN10300_CACHE_MANAGE_BY_REG
66 bool "Flush areas by way of automatic purge registers (AM34 only)"
67 depends on AM34_2
68
David Howells518d4bb2010-10-27 17:28:43 +010069endchoice
70
71config MN10300_CACHE_INV_BY_TAG
72 def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED
73
Akira Takeuchi9731d232010-10-27 17:28:45 +010074config MN10300_CACHE_INV_BY_REG
75 def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED
76
David Howells518d4bb2010-10-27 17:28:43 +010077config MN10300_CACHE_FLUSH_BY_TAG
78 def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK
Akira Takeuchi9731d232010-10-27 17:28:45 +010079
80config MN10300_CACHE_FLUSH_BY_REG
81 def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK
David Howellsb4784912010-10-27 17:28:46 +010082
83
84config MN10300_HAS_CACHE_SNOOP
85 def_bool n
86
87config MN10300_CACHE_SNOOP
88 bool "Use CPU Cache Snooping"
89 depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP
90 default y
91
92config MN10300_CACHE_FLUSH_ICACHE
93 def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP
94 help
95 Set if we need the dcache flushing before the icache is invalidated.
96
97config MN10300_CACHE_INV_ICACHE
98 def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP
99 help
100 Set if we need the icache to be invalidated, even if the dcache is in
101 write-through mode and doesn't need flushing.
David Howells7f386ac2011-03-18 16:54:30 +0000102
103#
104# The kernel debugger gets its own separate cache flushing functions
105#
106config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG
107 def_bool y if KERNEL_DEBUGGER && \
108 MN10300_CACHE_WBACK && \
109 !MN10300_CACHE_SNOOP && \
110 MN10300_CACHE_MANAGE_BY_TAG
111 help
112 Set if the debugger needs to flush the dcache and invalidate the
113 icache using the cache tag registers to make breakpoints work.
114
115config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG
116 def_bool y if KERNEL_DEBUGGER && \
117 MN10300_CACHE_WBACK && \
118 !MN10300_CACHE_SNOOP && \
119 MN10300_CACHE_MANAGE_BY_REG
120 help
121 Set if the debugger needs to flush the dcache and invalidate the
122 icache using automatic purge registers to make breakpoints work.
123
124config MN10300_DEBUGGER_CACHE_INV_BY_TAG
125 def_bool y if KERNEL_DEBUGGER && \
126 MN10300_CACHE_WTHRU && \
127 !MN10300_CACHE_SNOOP && \
128 MN10300_CACHE_MANAGE_BY_TAG
129 help
130 Set if the debugger needs to invalidate the icache using the cache
131 tag registers to make breakpoints work.
132
133config MN10300_DEBUGGER_CACHE_INV_BY_REG
134 def_bool y if KERNEL_DEBUGGER && \
135 MN10300_CACHE_WTHRU && \
136 !MN10300_CACHE_SNOOP && \
137 MN10300_CACHE_MANAGE_BY_REG
138 help
139 Set if the debugger needs to invalidate the icache using automatic
140 purge registers to make breakpoints work.
141
142config MN10300_DEBUGGER_CACHE_NO_FLUSH
143 def_bool y if KERNEL_DEBUGGER && \
144 (MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP)
145 help
146 Set if the debugger does not need to flush the dcache and/or
147 invalidate the icache to make breakpoints work.