David Howells | 0bc42d7 | 2010-10-27 17:28:41 +0100 | [diff] [blame] | 1 | # |
| 2 | # MN10300 CPU cache options |
| 3 | # |
| 4 | |
| 5 | choice |
| 6 | prompt "CPU Caching mode" |
| 7 | default MN10300_CACHE_WBACK |
| 8 | help |
| 9 | This option determines the caching mode for the kernel. |
| 10 | |
| 11 | Write-Back caching mode involves the all reads and writes causing |
| 12 | the affected cacheline to be read into the cache first before being |
| 13 | operated upon. Memory is not then updated by a write until the cache |
| 14 | is filled and a cacheline needs to be displaced from the cache to |
| 15 | make room. Only at that point is it written back. |
| 16 | |
| 17 | Write-Through caching only fetches cachelines from memory on a |
| 18 | read. Writes always get written directly to memory. If the affected |
| 19 | cacheline is also in cache, it will be updated too. |
| 20 | |
| 21 | The final option is to turn of caching entirely. |
| 22 | |
| 23 | config MN10300_CACHE_WBACK |
| 24 | bool "Write-Back" |
David Howells | b478491 | 2010-10-27 17:28:46 +0100 | [diff] [blame] | 25 | help |
| 26 | The dcache operates in delayed write-back mode. It must be manually |
| 27 | flushed if writes are made that subsequently need to be executed or |
| 28 | to be DMA'd by a device. |
David Howells | 0bc42d7 | 2010-10-27 17:28:41 +0100 | [diff] [blame] | 29 | |
| 30 | config MN10300_CACHE_WTHRU |
| 31 | bool "Write-Through" |
David Howells | b478491 | 2010-10-27 17:28:46 +0100 | [diff] [blame] | 32 | help |
| 33 | The dcache operates in immediate write-through mode. Writes are |
| 34 | committed to RAM immediately in addition to being stored in the |
| 35 | cache. This means that the written data is immediately available for |
| 36 | execution or DMA. |
| 37 | |
| 38 | This is not available for use with an SMP kernel if cache flushing |
| 39 | and invalidation by automatic purge register is not selected. |
David Howells | 0bc42d7 | 2010-10-27 17:28:41 +0100 | [diff] [blame] | 40 | |
| 41 | config MN10300_CACHE_DISABLED |
| 42 | bool "Disabled" |
David Howells | b478491 | 2010-10-27 17:28:46 +0100 | [diff] [blame] | 43 | help |
| 44 | The icache and dcache are disabled. |
David Howells | 0bc42d7 | 2010-10-27 17:28:41 +0100 | [diff] [blame] | 45 | |
| 46 | endchoice |
David Howells | 344af92 | 2010-10-27 17:28:42 +0100 | [diff] [blame] | 47 | |
| 48 | config MN10300_CACHE_ENABLED |
| 49 | def_bool y if !MN10300_CACHE_DISABLED |
David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 50 | |
| 51 | |
| 52 | choice |
| 53 | prompt "CPU cache flush/invalidate method" |
Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 54 | default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2 |
| 55 | default MN10300_CACHE_MANAGE_BY_REG if AM34_2 |
David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 56 | depends on MN10300_CACHE_ENABLED |
| 57 | help |
| 58 | This determines the method by which CPU cache flushing and |
| 59 | invalidation is performed. |
| 60 | |
| 61 | config MN10300_CACHE_MANAGE_BY_TAG |
| 62 | bool "Use the cache tag registers directly" |
Akira Takeuchi | 8be0628 | 2010-10-27 17:28:47 +0100 | [diff] [blame] | 63 | depends on !(SMP && MN10300_CACHE_WTHRU) |
David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 64 | |
Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 65 | config MN10300_CACHE_MANAGE_BY_REG |
| 66 | bool "Flush areas by way of automatic purge registers (AM34 only)" |
| 67 | depends on AM34_2 |
| 68 | |
David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 69 | endchoice |
| 70 | |
| 71 | config MN10300_CACHE_INV_BY_TAG |
| 72 | def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED |
| 73 | |
Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 74 | config MN10300_CACHE_INV_BY_REG |
| 75 | def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED |
| 76 | |
David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 77 | config MN10300_CACHE_FLUSH_BY_TAG |
| 78 | def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK |
Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame] | 79 | |
| 80 | config MN10300_CACHE_FLUSH_BY_REG |
| 81 | def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK |
David Howells | b478491 | 2010-10-27 17:28:46 +0100 | [diff] [blame] | 82 | |
| 83 | |
| 84 | config MN10300_HAS_CACHE_SNOOP |
| 85 | def_bool n |
| 86 | |
| 87 | config MN10300_CACHE_SNOOP |
| 88 | bool "Use CPU Cache Snooping" |
| 89 | depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP |
| 90 | default y |
| 91 | |
| 92 | config MN10300_CACHE_FLUSH_ICACHE |
| 93 | def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP |
| 94 | help |
| 95 | Set if we need the dcache flushing before the icache is invalidated. |
| 96 | |
| 97 | config MN10300_CACHE_INV_ICACHE |
| 98 | def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP |
| 99 | help |
| 100 | Set if we need the icache to be invalidated, even if the dcache is in |
| 101 | write-through mode and doesn't need flushing. |
David Howells | 7f386ac | 2011-03-18 16:54:30 +0000 | [diff] [blame] | 102 | |
| 103 | # |
| 104 | # The kernel debugger gets its own separate cache flushing functions |
| 105 | # |
| 106 | config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG |
| 107 | def_bool y if KERNEL_DEBUGGER && \ |
| 108 | MN10300_CACHE_WBACK && \ |
| 109 | !MN10300_CACHE_SNOOP && \ |
| 110 | MN10300_CACHE_MANAGE_BY_TAG |
| 111 | help |
| 112 | Set if the debugger needs to flush the dcache and invalidate the |
| 113 | icache using the cache tag registers to make breakpoints work. |
| 114 | |
| 115 | config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG |
| 116 | def_bool y if KERNEL_DEBUGGER && \ |
| 117 | MN10300_CACHE_WBACK && \ |
| 118 | !MN10300_CACHE_SNOOP && \ |
| 119 | MN10300_CACHE_MANAGE_BY_REG |
| 120 | help |
| 121 | Set if the debugger needs to flush the dcache and invalidate the |
| 122 | icache using automatic purge registers to make breakpoints work. |
| 123 | |
| 124 | config MN10300_DEBUGGER_CACHE_INV_BY_TAG |
| 125 | def_bool y if KERNEL_DEBUGGER && \ |
| 126 | MN10300_CACHE_WTHRU && \ |
| 127 | !MN10300_CACHE_SNOOP && \ |
| 128 | MN10300_CACHE_MANAGE_BY_TAG |
| 129 | help |
| 130 | Set if the debugger needs to invalidate the icache using the cache |
| 131 | tag registers to make breakpoints work. |
| 132 | |
| 133 | config MN10300_DEBUGGER_CACHE_INV_BY_REG |
| 134 | def_bool y if KERNEL_DEBUGGER && \ |
| 135 | MN10300_CACHE_WTHRU && \ |
| 136 | !MN10300_CACHE_SNOOP && \ |
| 137 | MN10300_CACHE_MANAGE_BY_REG |
| 138 | help |
| 139 | Set if the debugger needs to invalidate the icache using automatic |
| 140 | purge registers to make breakpoints work. |
| 141 | |
| 142 | config MN10300_DEBUGGER_CACHE_NO_FLUSH |
| 143 | def_bool y if KERNEL_DEBUGGER && \ |
| 144 | (MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP) |
| 145 | help |
| 146 | Set if the debugger does not need to flush the dcache and/or |
| 147 | invalidate the icache to make breakpoints work. |