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Bryan Wu1394f032007-05-06 14:50:22 -07001#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
Mike Frysinger53f8a252007-11-15 15:48:01 +08006mainmenu "Blackfin Kernel Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07007
8config MMU
9 bool
10 default n
11
12config FPU
13 bool
14 default n
15
16config RWSEM_GENERIC_SPINLOCK
17 bool
18 default y
19
20config RWSEM_XCHGADD_ALGORITHM
21 bool
22 default n
23
24config BLACKFIN
25 bool
26 default y
27
Aubrey Lie3defff2007-05-21 18:09:11 +080028config ZONE_DMA
29 bool
30 default y
31
Bryan Wu1394f032007-05-06 14:50:22 -070032config SEMAPHORE_SLEEPERS
33 bool
34 default y
35
36config GENERIC_FIND_NEXT_BIT
37 bool
38 default y
39
40config GENERIC_HWEIGHT
41 bool
42 default y
43
44config GENERIC_HARDIRQS
45 bool
46 default y
47
48config GENERIC_IRQ_PROBE
Mike Frysingere4e9a7a2007-11-15 20:39:34 +080049 bool
Bryan Wu1394f032007-05-06 14:50:22 -070050 default y
51
52config GENERIC_TIME
53 bool
54 default n
55
Michael Hennerichb2d15832007-07-24 15:46:36 +080056config GENERIC_GPIO
Bryan Wu1394f032007-05-06 14:50:22 -070057 bool
58 default y
59
60config FORCE_MAX_ZONEORDER
61 int
62 default "14"
63
64config GENERIC_CALIBRATE_DELAY
65 bool
66 default y
67
Bryan Wu1394f032007-05-06 14:50:22 -070068source "init/Kconfig"
69source "kernel/Kconfig.preempt"
70
71menu "Blackfin Processor Options"
72
73comment "Processor and Board Settings"
74
75choice
76 prompt "CPU"
77 default BF533
78
Michael Hennerich59003142007-10-21 16:54:27 +080079config BF522
80 bool "BF522"
81 help
82 BF522 Processor Support.
83
84config BF525
85 bool "BF525"
86 help
87 BF525 Processor Support.
88
89config BF527
90 bool "BF527"
91 help
92 BF527 Processor Support.
93
Bryan Wu1394f032007-05-06 14:50:22 -070094config BF531
95 bool "BF531"
96 help
97 BF531 Processor Support.
98
99config BF532
100 bool "BF532"
101 help
102 BF532 Processor Support.
103
104config BF533
105 bool "BF533"
106 help
107 BF533 Processor Support.
108
109config BF534
110 bool "BF534"
111 help
112 BF534 Processor Support.
113
114config BF536
115 bool "BF536"
116 help
117 BF536 Processor Support.
118
119config BF537
120 bool "BF537"
121 help
122 BF537 Processor Support.
123
Roy Huang24a07a12007-07-12 22:41:45 +0800124config BF542
125 bool "BF542"
126 help
127 BF542 Processor Support.
128
129config BF544
130 bool "BF544"
131 help
132 BF544 Processor Support.
133
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800134config BF547
135 bool "BF547"
136 help
137 BF547 Processor Support.
138
Roy Huang24a07a12007-07-12 22:41:45 +0800139config BF548
140 bool "BF548"
141 help
142 BF548 Processor Support.
143
144config BF549
145 bool "BF549"
146 help
147 BF549 Processor Support.
148
Bryan Wu1394f032007-05-06 14:50:22 -0700149config BF561
150 bool "BF561"
151 help
152 Not Supported Yet - Work in progress - BF561 Processor Support.
153
154endchoice
155
156choice
157 prompt "Silicon Rev"
Michael Hennerich59003142007-10-21 16:54:27 +0800158 default BF_REV_0_1 if BF527
Bryan Wu1394f032007-05-06 14:50:22 -0700159 default BF_REV_0_2 if BF537
160 default BF_REV_0_3 if BF533
Roy Huang24a07a12007-07-12 22:41:45 +0800161 default BF_REV_0_0 if BF549
162
163config BF_REV_0_0
164 bool "0.0"
Mike Frysingerd07f4382007-11-15 15:49:17 +0800165 depends on (BF52x || BF54x)
Michael Hennerich59003142007-10-21 16:54:27 +0800166
167config BF_REV_0_1
Mike Frysingerd07f4382007-11-15 15:49:17 +0800168 bool "0.1"
169 depends on (BF52x || BF54x)
Bryan Wu1394f032007-05-06 14:50:22 -0700170
171config BF_REV_0_2
172 bool "0.2"
173 depends on (BF537 || BF536 || BF534)
174
175config BF_REV_0_3
176 bool "0.3"
177 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
178
179config BF_REV_0_4
180 bool "0.4"
181 depends on (BF561 || BF533 || BF532 || BF531)
182
183config BF_REV_0_5
184 bool "0.5"
185 depends on (BF561 || BF533 || BF532 || BF531)
186
Jie Zhangde3025f2007-06-25 18:04:12 +0800187config BF_REV_ANY
188 bool "any"
189
190config BF_REV_NONE
191 bool "none"
192
Bryan Wu1394f032007-05-06 14:50:22 -0700193endchoice
194
Michael Hennerich59003142007-10-21 16:54:27 +0800195config BF52x
196 bool
197 depends on (BF522 || BF525 || BF527)
198 default y
199
Roy Huang24a07a12007-07-12 22:41:45 +0800200config BF53x
201 bool
202 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
203 default y
204
205config BF54x
206 bool
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800207 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
Roy Huang24a07a12007-07-12 22:41:45 +0800208 default y
209
Bryan Wu1394f032007-05-06 14:50:22 -0700210config BFIN_DUAL_CORE
211 bool
212 depends on (BF561)
213 default y
214
215config BFIN_SINGLE_CORE
216 bool
217 depends on !BFIN_DUAL_CORE
218 default y
219
Bryan Wu1394f032007-05-06 14:50:22 -0700220config MEM_GENERIC_BOARD
221 bool
222 depends on GENERIC_BOARD
223 default y
224
225config MEM_MT48LC64M4A2FB_7E
226 bool
227 depends on (BFIN533_STAMP)
228 default y
229
230config MEM_MT48LC16M16A2TG_75
231 bool
232 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
Javier Herreroab472a02007-10-29 16:14:44 +0800233 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
234 || H8606_HVSISTEMAS)
Bryan Wu1394f032007-05-06 14:50:22 -0700235 default y
236
237config MEM_MT48LC32M8A2_75
238 bool
239 depends on (BFIN537_STAMP || PNAV10)
240 default y
241
242config MEM_MT48LC8M32B2B5_7
243 bool
244 depends on (BFIN561_BLUETECHNIX_CM)
245 default y
246
Michael Hennerich59003142007-10-21 16:54:27 +0800247config MEM_MT48LC32M16A2TG_75
248 bool
249 depends on (BFIN527_EZKIT)
250 default y
251
Bryan Wu1394f032007-05-06 14:50:22 -0700252config BFIN_SHARED_FLASH_ENET
253 bool
254 depends on (BFIN533_STAMP)
255 default y
256
Michael Hennerich59003142007-10-21 16:54:27 +0800257source "arch/blackfin/mach-bf527/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700258source "arch/blackfin/mach-bf533/Kconfig"
259source "arch/blackfin/mach-bf561/Kconfig"
260source "arch/blackfin/mach-bf537/Kconfig"
Roy Huang24a07a12007-07-12 22:41:45 +0800261source "arch/blackfin/mach-bf548/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700262
263menu "Board customizations"
264
265config CMDLINE_BOOL
266 bool "Default bootloader kernel arguments"
267
268config CMDLINE
269 string "Initial kernel command string"
270 depends on CMDLINE_BOOL
271 default "console=ttyBF0,57600"
272 help
273 If you don't have a boot loader capable of passing a command line string
274 to the kernel, you may specify one here. As a minimum, you should specify
275 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
276
Robin Getzf16295e2007-08-03 18:07:17 +0800277comment "Clock/PLL Setup"
Bryan Wu1394f032007-05-06 14:50:22 -0700278
279config CLKIN_HZ
280 int "Crystal Frequency in Hz"
281 default "11059200" if BFIN533_STAMP
282 default "27000000" if BFIN533_EZKIT
Javier Herreroab472a02007-10-29 16:14:44 +0800283 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
Bryan Wu1394f032007-05-06 14:50:22 -0700284 default "30000000" if BFIN561_EZKIT
285 default "24576000" if PNAV10
286 help
287 The frequency of CLKIN crystal oscillator on the board in Hz.
288
Robin Getzf16295e2007-08-03 18:07:17 +0800289config BFIN_KERNEL_CLOCK
290 bool "Re-program Clocks while Kernel boots?"
291 default n
292 help
293 This option decides if kernel clocks are re-programed from the
294 bootloader settings. If the clocks are not set, the SDRAM settings
295 are also not changed, and the Bootloader does 100% of the hardware
296 configuration.
297
298config PLL_BYPASS
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800299 bool "Bypass PLL"
300 depends on BFIN_KERNEL_CLOCK
301 default n
Robin Getzf16295e2007-08-03 18:07:17 +0800302
303config CLKIN_HALF
304 bool "Half Clock In"
305 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
306 default n
307 help
308 If this is set the clock will be divided by 2, before it goes to the PLL.
309
310config VCO_MULT
311 int "VCO Multiplier"
312 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
313 range 1 64
314 default "22" if BFIN533_EZKIT
315 default "45" if BFIN533_STAMP
Michael Hennerich59003142007-10-21 16:54:27 +0800316 default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800317 default "22" if BFIN533_BLUETECHNIX_CM
318 default "20" if BFIN537_BLUETECHNIX_CM
319 default "20" if BFIN561_BLUETECHNIX_CM
320 default "20" if BFIN561_EZKIT
Javier Herreroab472a02007-10-29 16:14:44 +0800321 default "16" if H8606_HVSISTEMAS
Robin Getzf16295e2007-08-03 18:07:17 +0800322 help
323 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
324 PLL Frequency = (Crystal Frequency) * (this setting)
325
326choice
327 prompt "Core Clock Divider"
328 depends on BFIN_KERNEL_CLOCK
329 default CCLK_DIV_1
330 help
331 This sets the frequency of the core. It can be 1, 2, 4 or 8
332 Core Frequency = (PLL frequency) / (this setting)
333
334config CCLK_DIV_1
335 bool "1"
336
337config CCLK_DIV_2
338 bool "2"
339
340config CCLK_DIV_4
341 bool "4"
342
343config CCLK_DIV_8
344 bool "8"
345endchoice
346
347config SCLK_DIV
348 int "System Clock Divider"
349 depends on BFIN_KERNEL_CLOCK
350 range 1 15
351 default 5 if BFIN533_EZKIT
352 default 5 if BFIN533_STAMP
Michael Hennerich59003142007-10-21 16:54:27 +0800353 default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800354 default 5 if BFIN533_BLUETECHNIX_CM
355 default 4 if BFIN537_BLUETECHNIX_CM
356 default 4 if BFIN561_BLUETECHNIX_CM
357 default 5 if BFIN561_EZKIT
Javier Herreroab472a02007-10-29 16:14:44 +0800358 default 3 if H8606_HVSISTEMAS
Robin Getzf16295e2007-08-03 18:07:17 +0800359 help
360 This sets the frequency of the system clock (including SDRAM or DDR).
361 This can be between 1 and 15
362 System Clock = (PLL frequency) / (this setting)
363
364#
365# Max & Min Speeds for various Chips
366#
367config MAX_VCO_HZ
368 int
369 default 600000000 if BF522
370 default 600000000 if BF525
371 default 600000000 if BF527
372 default 400000000 if BF531
373 default 400000000 if BF532
374 default 750000000 if BF533
375 default 500000000 if BF534
376 default 400000000 if BF536
377 default 600000000 if BF537
378 default 533000000 if BF538
379 default 533000000 if BF539
380 default 600000000 if BF542
381 default 533000000 if BF544
382 default 533000000 if BF549
383 default 600000000 if BF561
384
385config MIN_VCO_HZ
386 int
387 default 50000000
388
389config MAX_SCLK_HZ
390 int
391 default 133000000
392
393config MIN_SCLK_HZ
394 int
395 default 27000000
396
397comment "Kernel Timer/Scheduler"
398
399source kernel/Kconfig.hz
400
401comment "Memory Setup"
402
Bryan Wu1394f032007-05-06 14:50:22 -0700403config MEM_SIZE
404 int "SDRAM Memory Size in MBytes"
405 default 32 if BFIN533_EZKIT
Michael Hennerich59003142007-10-21 16:54:27 +0800406 default 64 if BFIN527_EZKIT
Bryan Wu1394f032007-05-06 14:50:22 -0700407 default 64 if BFIN537_STAMP
408 default 64 if BFIN561_EZKIT
409 default 128 if BFIN533_STAMP
410 default 64 if PNAV10
Javier Herreroab472a02007-10-29 16:14:44 +0800411 default 32 if H8606_HVSISTEMAS
Bryan Wu1394f032007-05-06 14:50:22 -0700412
413config MEM_ADD_WIDTH
414 int "SDRAM Memory Address Width"
415 default 9 if BFIN533_EZKIT
416 default 9 if BFIN561_EZKIT
Javier Herreroab472a02007-10-29 16:14:44 +0800417 default 9 if H8606_HVSISTEMAS
Michael Hennerich59003142007-10-21 16:54:27 +0800418 default 10 if BFIN527_EZKIT
Bryan Wu1394f032007-05-06 14:50:22 -0700419 default 10 if BFIN537_STAMP
420 default 11 if BFIN533_STAMP
421 default 10 if PNAV10
422
423config ENET_FLASH_PIN
424 int "PF port/pin used for flash and ethernet sharing"
425 depends on (BFIN533_STAMP)
426 default 0
427 help
428 PF port/pin used for flash and ethernet sharing to allow other PF
429 pins to be used on other platforms without having to touch common
430 code.
431 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
432
433config BOOT_LOAD
434 hex "Kernel load address for booting"
435 default "0x1000"
Mike Frysinger2d8f1612007-08-05 14:06:16 +0800436 range 0x1000 0x20000000
Bryan Wu1394f032007-05-06 14:50:22 -0700437 help
438 This option allows you to set the load address of the kernel.
439 This can be useful if you are on a board which has a small amount
440 of memory or you wish to reserve some memory at the beginning of
441 the address space.
442
Mike Frysinger2d8f1612007-08-05 14:06:16 +0800443 Note that you need to keep this value above 4k (0x1000) as this
444 memory region is used to capture NULL pointer references as well
445 as some core kernel functions.
Bryan Wu1394f032007-05-06 14:50:22 -0700446
447comment "LED Status Indicators"
448 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
449
450config BFIN_ALIVE_LED
451 bool "Enable Board Alive"
452 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
453 default n
454 help
455 Blink the LEDs you select when the kernel is running. Helps detect
456 a hung kernel.
457
458config BFIN_ALIVE_LED_NUM
459 int "LED"
460 depends on BFIN_ALIVE_LED
461 range 1 3 if BFIN533_STAMP
462 default "3" if BFIN533_STAMP
463 help
464 Select the LED (marked on the board) for you to blink.
465
466config BFIN_IDLE_LED
467 bool "Enable System Load/Idle LED"
468 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
469 default n
470 help
471 Blinks the LED you select when to determine kernel load.
472
473config BFIN_IDLE_LED_NUM
474 int "LED"
475 depends on BFIN_IDLE_LED
476 range 1 3 if BFIN533_STAMP
477 default "2" if BFIN533_STAMP
478 help
479 Select the LED (marked on the board) for you to blink.
480
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800481choice
482 prompt "Blackfin Exception Scratch Register"
483 default BFIN_SCRATCH_REG_RETN
484 help
485 Select the resource to reserve for the Exception handler:
486 - RETN: Non-Maskable Interrupt (NMI)
487 - RETE: Exception Return (JTAG/ICE)
488 - CYCLES: Performance counter
489
490 If you are unsure, please select "RETN".
491
492config BFIN_SCRATCH_REG_RETN
493 bool "RETN"
494 help
495 Use the RETN register in the Blackfin exception handler
496 as a stack scratch register. This means you cannot
497 safely use NMI on the Blackfin while running Linux, but
498 you can debug the system with a JTAG ICE and use the
499 CYCLES performance registers.
500
501 If you are unsure, please select "RETN".
502
503config BFIN_SCRATCH_REG_RETE
504 bool "RETE"
505 help
506 Use the RETE register in the Blackfin exception handler
507 as a stack scratch register. This means you cannot
508 safely use a JTAG ICE while debugging a Blackfin board,
509 but you can safely use the CYCLES performance registers
510 and the NMI.
511
512 If you are unsure, please select "RETN".
513
514config BFIN_SCRATCH_REG_CYCLES
515 bool "CYCLES"
516 help
517 Use the CYCLES register in the Blackfin exception handler
518 as a stack scratch register. This means you cannot
519 safely use the CYCLES performance registers on a Blackfin
520 board at anytime, but you can debug the system with a JTAG
521 ICE and use the NMI.
522
523 If you are unsure, please select "RETN".
524
525endchoice
526
Bryan Wu1394f032007-05-06 14:50:22 -0700527#
528# Sorry - but you need to put the hex address here -
529#
530
531# Flag Data register
532config BFIN_ALIVE_LED_PORT
533 hex
534 default 0xFFC00700 if (BFIN533_STAMP)
535
536# Peripheral Flag Direction Register
537config BFIN_ALIVE_LED_DPORT
538 hex
539 default 0xFFC00730 if (BFIN533_STAMP)
540
541config BFIN_ALIVE_LED_PIN
542 hex
543 default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
544 default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
545 default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
546
547config BFIN_IDLE_LED_PORT
548 hex
549 default 0xFFC00700 if (BFIN533_STAMP)
550
551# Peripheral Flag Direction Register
552config BFIN_IDLE_LED_DPORT
553 hex
554 default 0xFFC00730 if (BFIN533_STAMP)
555
556config BFIN_IDLE_LED_PIN
557 hex
558 default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
559 default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
560 default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
561
Bryan Wu1394f032007-05-06 14:50:22 -0700562endmenu
563
564
565menu "Blackfin Kernel Optimizations"
566
Bryan Wu1394f032007-05-06 14:50:22 -0700567comment "Memory Optimizations"
568
569config I_ENTRY_L1
570 bool "Locate interrupt entry code in L1 Memory"
571 default y
572 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200573 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
574 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700575
576config EXCPT_IRQ_SYSC_L1
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200577 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
Bryan Wu1394f032007-05-06 14:50:22 -0700578 default y
579 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200580 If enabled, the entire ASM lowlevel exception and interrupt entry code
581 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
582 (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700583
584config DO_IRQ_L1
585 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
586 default y
587 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200588 If enabled, the frequently called do_irq dispatcher function is linked
589 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700590
591config CORE_TIMER_IRQ_L1
592 bool "Locate frequently called timer_interrupt() function in L1 Memory"
593 default y
594 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200595 If enabled, the frequently called timer_interrupt() function is linked
596 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700597
598config IDLE_L1
599 bool "Locate frequently idle function in L1 Memory"
600 default y
601 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200602 If enabled, the frequently called idle function is linked
603 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700604
605config SCHEDULE_L1
606 bool "Locate kernel schedule function in L1 Memory"
607 default y
608 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200609 If enabled, the frequently called kernel schedule is linked
610 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700611
612config ARITHMETIC_OPS_L1
613 bool "Locate kernel owned arithmetic functions in L1 Memory"
614 default y
615 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200616 If enabled, arithmetic functions are linked
617 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700618
619config ACCESS_OK_L1
620 bool "Locate access_ok function in L1 Memory"
621 default y
622 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200623 If enabled, the access_ok function is linked
624 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700625
626config MEMSET_L1
627 bool "Locate memset function in L1 Memory"
628 default y
629 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200630 If enabled, the memset function is linked
631 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700632
633config MEMCPY_L1
634 bool "Locate memcpy function in L1 Memory"
635 default y
636 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200637 If enabled, the memcpy function is linked
638 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700639
640config SYS_BFIN_SPINLOCK_L1
641 bool "Locate sys_bfin_spinlock function in L1 Memory"
642 default y
643 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200644 If enabled, sys_bfin_spinlock function is linked
645 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700646
647config IP_CHECKSUM_L1
648 bool "Locate IP Checksum function in L1 Memory"
649 default n
650 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200651 If enabled, the IP Checksum function is linked
652 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700653
654config CACHELINE_ALIGNED_L1
655 bool "Locate cacheline_aligned data to L1 Data Memory"
Michael Hennerich157cc5a2007-07-12 16:20:21 +0800656 default y if !BF54x
657 default n if BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700658 depends on !BF531
659 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200660 If enabled, cacheline_anligned data is linked
661 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700662
663config SYSCALL_TAB_L1
664 bool "Locate Syscall Table L1 Data Memory"
665 default n
666 depends on !BF531
667 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200668 If enabled, the Syscall LUT is linked
669 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700670
671config CPLB_SWITCH_TAB_L1
672 bool "Locate CPLB Switch Tables L1 Data Memory"
673 default n
674 depends on !BF531
675 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200676 If enabled, the CPLB Switch Tables are linked
677 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700678
679endmenu
680
681
682choice
683 prompt "Kernel executes from"
684 help
685 Choose the memory type that the kernel will be running in.
686
687config RAMKERNEL
688 bool "RAM"
689 help
690 The kernel will be resident in RAM when running.
691
692config ROMKERNEL
693 bool "ROM"
694 help
695 The kernel will be resident in FLASH/ROM when running.
696
697endchoice
698
699source "mm/Kconfig"
700
Bryan Wudb0fa202007-07-12 14:55:05 +0800701config LARGE_ALLOCS
702 bool "Allow allocating large blocks (> 1MB) of memory"
703 help
704 Allow the slab memory allocator to keep chains for very large
705 memory sizes - upto 32MB. You may need this if your system has
706 a lot of RAM, and you need to able to allocate very large
707 contiguous chunks. If unsure, say N.
708
Mike Frysinger780431e2007-10-21 23:37:54 +0800709config BFIN_GPTIMERS
710 tristate "Enable Blackfin General Purpose Timers API"
711 default n
712 help
713 Enable support for the General Purpose Timers API. If you
714 are unsure, say N.
715
716 To compile this driver as a module, choose M here: the module
717 will be called gptimers.ko.
718
Bryan Wu1394f032007-05-06 14:50:22 -0700719config BFIN_DMA_5XX
720 bool "Enable DMA Support"
Michael Hennerich59003142007-10-21 16:54:27 +0800721 depends on (BF52x || BF53x || BF561 || BF54x)
Bryan Wu1394f032007-05-06 14:50:22 -0700722 default y
723 help
724 DMA driver for BF5xx.
725
726choice
727 prompt "Uncached SDRAM region"
728 default DMA_UNCACHED_1M
Adrian Bunk247537b2007-09-26 20:02:52 +0200729 depends on BFIN_DMA_5XX
Bryan Wu1394f032007-05-06 14:50:22 -0700730config DMA_UNCACHED_2M
731 bool "Enable 2M DMA region"
732config DMA_UNCACHED_1M
733 bool "Enable 1M DMA region"
734config DMA_UNCACHED_NONE
735 bool "Disable DMA region"
736endchoice
737
738
739comment "Cache Support"
Robin Getz3bebca22007-10-10 23:55:26 +0800740config BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700741 bool "Enable ICACHE"
Robin Getz3bebca22007-10-10 23:55:26 +0800742config BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700743 bool "Enable DCACHE"
Robin Getz3bebca22007-10-10 23:55:26 +0800744config BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700745 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
Robin Getz3bebca22007-10-10 23:55:26 +0800746 depends on BFIN_DCACHE && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700747 default n
Robin Getz3bebca22007-10-10 23:55:26 +0800748config BFIN_ICACHE_LOCK
749 bool "Enable Instruction Cache Locking"
Bryan Wu1394f032007-05-06 14:50:22 -0700750
751choice
752 prompt "Policy"
Robin Getz3bebca22007-10-10 23:55:26 +0800753 depends on BFIN_DCACHE
754 default BFIN_WB
755config BFIN_WB
Bryan Wu1394f032007-05-06 14:50:22 -0700756 bool "Write back"
757 help
758 Write Back Policy:
759 Cached data will be written back to SDRAM only when needed.
760 This can give a nice increase in performance, but beware of
761 broken drivers that do not properly invalidate/flush their
762 cache.
763
764 Write Through Policy:
765 Cached data will always be written back to SDRAM when the
766 cache is updated. This is a completely safe setting, but
767 performance is worse than Write Back.
768
769 If you are unsure of the options and you want to be safe,
770 then go with Write Through.
771
Robin Getz3bebca22007-10-10 23:55:26 +0800772config BFIN_WT
Bryan Wu1394f032007-05-06 14:50:22 -0700773 bool "Write through"
774 help
775 Write Back Policy:
776 Cached data will be written back to SDRAM only when needed.
777 This can give a nice increase in performance, but beware of
778 broken drivers that do not properly invalidate/flush their
779 cache.
780
781 Write Through Policy:
782 Cached data will always be written back to SDRAM when the
783 cache is updated. This is a completely safe setting, but
784 performance is worse than Write Back.
785
786 If you are unsure of the options and you want to be safe,
787 then go with Write Through.
788
789endchoice
790
791config L1_MAX_PIECE
792 int "Set the max L1 SRAM pieces"
793 default 16
794 help
795 Set the max memory pieces for the L1 SRAM allocation algorithm.
796 Min value is 16. Max value is 1024.
797
Bryan Wu1394f032007-05-06 14:50:22 -0700798comment "Asynchonous Memory Configuration"
799
Mike Frysingerddf416b2007-10-10 18:06:47 +0800800menu "EBIU_AMGCTL Global Control"
Bryan Wu1394f032007-05-06 14:50:22 -0700801config C_AMCKEN
802 bool "Enable CLKOUT"
803 default y
804
805config C_CDPRIO
806 bool "DMA has priority over core for ext. accesses"
Michael Hennerich9be343c2007-07-12 11:58:44 +0800807 depends on !BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700808 default n
809
810config C_B0PEN
811 depends on BF561
812 bool "Bank 0 16 bit packing enable"
813 default y
814
815config C_B1PEN
816 depends on BF561
817 bool "Bank 1 16 bit packing enable"
818 default y
819
820config C_B2PEN
821 depends on BF561
822 bool "Bank 2 16 bit packing enable"
823 default y
824
825config C_B3PEN
826 depends on BF561
827 bool "Bank 3 16 bit packing enable"
828 default n
829
830choice
831 prompt"Enable Asynchonous Memory Banks"
832 default C_AMBEN_ALL
833
834config C_AMBEN
835 bool "Disable All Banks"
836
837config C_AMBEN_B0
838 bool "Enable Bank 0"
839
840config C_AMBEN_B0_B1
841 bool "Enable Bank 0 & 1"
842
843config C_AMBEN_B0_B1_B2
844 bool "Enable Bank 0 & 1 & 2"
845
846config C_AMBEN_ALL
847 bool "Enable All Banks"
848endchoice
849endmenu
850
851menu "EBIU_AMBCTL Control"
852config BANK_0
853 hex "Bank 0"
854 default 0x7BB0
855
856config BANK_1
857 hex "Bank 1"
858 default 0x7BB0
859
860config BANK_2
861 hex "Bank 2"
862 default 0x7BB0
863
864config BANK_3
865 hex "Bank 3"
866 default 0x99B3
867endmenu
868
Sonic Zhange40540b2007-11-21 23:49:52 +0800869config EBIU_MBSCTLVAL
870 hex "EBIU Bank Select Control Register"
871 depends on BF54x
872 default 0
873
874config EBIU_MODEVAL
875 hex "Flash Memory Mode Control Register"
876 depends on BF54x
877 default 1
878
879config EBIU_FCTLVAL
880 hex "Flash Memory Bank Control Register"
881 depends on BF54x
882 default 6
Bryan Wu1394f032007-05-06 14:50:22 -0700883endmenu
884
885#############################################################################
886menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
887
888config PCI
889 bool "PCI support"
890 help
891 Support for PCI bus.
892
893source "drivers/pci/Kconfig"
894
895config HOTPLUG
896 bool "Support for hot-pluggable device"
897 help
898 Say Y here if you want to plug devices into your computer while
899 the system is running, and be able to use them quickly. In many
900 cases, the devices can likewise be unplugged at any time too.
901
902 One well known example of this is PCMCIA- or PC-cards, credit-card
903 size devices such as network cards, modems or hard drives which are
904 plugged into slots found on all modern laptop computers. Another
905 example, used on modern desktops as well as laptops, is USB.
906
907 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
908 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
909 Then your kernel will automatically call out to a user mode "policy
910 agent" (/sbin/hotplug) to load modules and set up software needed
911 to use devices as you hotplug them.
912
913source "drivers/pcmcia/Kconfig"
914
915source "drivers/pci/hotplug/Kconfig"
916
917endmenu
918
919menu "Executable file formats"
920
921source "fs/Kconfig.binfmt"
922
923endmenu
924
925menu "Power management options"
926source "kernel/power/Kconfig"
927
928choice
929 prompt "Select PM Wakeup Event Source"
930 default PM_WAKEUP_GPIO_BY_SIC_IWR
931 depends on PM
932 help
933 If you have a GPIO already configured as input with the corresponding PORTx_MASK
934 bit set - "Specify Wakeup Event by SIC_IWR value"
935
936config PM_WAKEUP_GPIO_BY_SIC_IWR
937 bool "Specify Wakeup Event by SIC_IWR value"
938config PM_WAKEUP_BY_GPIO
939 bool "Cause Wakeup Event by GPIO"
940config PM_WAKEUP_GPIO_API
941 bool "Configure Wakeup Event by PM GPIO API"
942
943endchoice
944
945config PM_WAKEUP_SIC_IWR
946 hex "Wakeup Events (SIC_IWR)"
947 depends on PM_WAKEUP_GPIO_BY_SIC_IWR
948 default 0x80000000 if (BF537 || BF536 || BF534)
949 default 0x100000 if (BF533 || BF532 || BF531)
950
951config PM_WAKEUP_GPIO_NUMBER
952 int "Wakeup GPIO number"
953 range 0 47
954 depends on PM_WAKEUP_BY_GPIO
955 default 2 if BFIN537_STAMP
956
957choice
958 prompt "GPIO Polarity"
959 depends on PM_WAKEUP_BY_GPIO
960 default PM_WAKEUP_GPIO_POLAR_H
961config PM_WAKEUP_GPIO_POLAR_H
962 bool "Active High"
963config PM_WAKEUP_GPIO_POLAR_L
964 bool "Active Low"
965config PM_WAKEUP_GPIO_POLAR_EDGE_F
966 bool "Falling EDGE"
967config PM_WAKEUP_GPIO_POLAR_EDGE_R
968 bool "Rising EDGE"
969config PM_WAKEUP_GPIO_POLAR_EDGE_B
970 bool "Both EDGE"
971endchoice
972
973endmenu
974
Roy Huang24a07a12007-07-12 22:41:45 +0800975if (BF537 || BF533 || BF54x)
Bryan Wu1394f032007-05-06 14:50:22 -0700976
977menu "CPU Frequency scaling"
978
979source "drivers/cpufreq/Kconfig"
980
981config CPU_FREQ
982 bool
983 default n
984 help
985 If you want to enable this option, you should select the
986 DPMC driver from Character Devices.
987endmenu
988
989endif
990
991source "net/Kconfig"
992
993source "drivers/Kconfig"
994
995source "fs/Kconfig"
996
Mathieu Desnoyers09caded2007-10-18 23:41:05 -0700997source "kernel/Kconfig.instrumentation"
Bryan Wu1394f032007-05-06 14:50:22 -0700998
Mike Frysinger74ce8322007-11-21 23:50:49 +0800999source "arch/blackfin/Kconfig.debug"
Bryan Wu1394f032007-05-06 14:50:22 -07001000
1001source "security/Kconfig"
1002
1003source "crypto/Kconfig"
1004
1005source "lib/Kconfig"