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Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Banajit Goswamib016de92017-02-15 21:02:30 -080022
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070023 ufs_dev_reset_assert: ufs_dev_reset_assert {
24 config {
25 pins = "ufs_reset";
26 bias-pull-down; /* default: pull down */
27 /*
28 * UFS_RESET driver strengths are having
29 * different values/steps compared to typical
30 * GPIO drive strengths.
31 *
32 * Following table clarifies:
33 *
34 * HDRV value | UFS_RESET | Typical GPIO
35 * (dec) | (mA) | (mA)
36 * 0 | 0.8 | 2
37 * 1 | 1.55 | 4
38 * 2 | 2.35 | 6
39 * 3 | 3.1 | 8
40 * 4 | 3.9 | 10
41 * 5 | 4.65 | 12
42 * 6 | 5.4 | 14
43 * 7 | 6.15 | 16
44 *
45 * POR value for UFS_RESET HDRV is 3 which means
46 * 3.1mA and we want to use that. Hence just
47 * specify 8mA to "drive-strength" binding and
48 * that should result into writing 3 to HDRV
49 * field.
50 */
51 drive-strength = <8>; /* default: 3.1 mA */
52 output-low; /* active low reset */
53 };
54 };
55
56 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
57 config {
58 pins = "ufs_reset";
59 bias-pull-down; /* default: pull down */
60 /*
61 * default: 3.1 mA
62 * check comments under ufs_dev_reset_assert
63 */
64 drive-strength = <8>;
65 output-high; /* active low reset */
66 };
67 };
68
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070069 flash_led3_front {
70 flash_led3_front_en: flash_led3_front_en {
71 mux {
72 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070073 function = "gpio";
74 };
75
76 config {
77 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070078 drive_strength = <2>;
79 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070080 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070081 };
82 };
83
84 flash_led3_front_dis: flash_led3_front_dis {
85 mux {
86 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070087 function = "gpio";
88 };
89
90 config {
91 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070092 drive_strength = <2>;
93 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070094 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070095 };
96 };
97 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070098
Banajit Goswamib016de92017-02-15 21:02:30 -080099 wcd9xxx_intr {
100 wcd_intr_default: wcd_intr_default{
101 mux {
102 pins = "gpio54";
103 function = "gpio";
104 };
105
106 config {
107 pins = "gpio54";
108 drive-strength = <2>; /* 2 mA */
109 bias-pull-down; /* pull down */
110 input-enable;
111 };
112 };
113 };
114
Xiaonian Wang898e0902017-04-08 06:46:29 +0800115 sdc2_clk_on: sdc2_clk_on {
116 config {
117 pins = "sdc2_clk";
118 bias-disable; /* NO pull */
119 drive-strength = <16>; /* 16 MA */
120 };
121 };
122
123 sdc2_clk_off: sdc2_clk_off {
124 config {
125 pins = "sdc2_clk";
126 bias-disable; /* NO pull */
127 drive-strength = <2>; /* 2 MA */
128 };
129 };
130
131 sdc2_cmd_on: sdc2_cmd_on {
132 config {
133 pins = "sdc2_cmd";
134 bias-pull-up; /* pull up */
135 drive-strength = <10>; /* 10 MA */
136 };
137 };
138
139 sdc2_cmd_off: sdc2_cmd_off {
140 config {
141 pins = "sdc2_cmd";
142 bias-pull-up; /* pull up */
143 drive-strength = <2>; /* 2 MA */
144 };
145 };
146
147 sdc2_data_on: sdc2_data_on {
148 config {
149 pins = "sdc2_data";
150 bias-pull-up; /* pull up */
151 drive-strength = <10>; /* 10 MA */
152 };
153 };
154
155 sdc2_data_off: sdc2_data_off {
156 config {
157 pins = "sdc2_data";
158 bias-pull-up; /* pull up */
159 drive-strength = <2>; /* 2 MA */
160 };
161 };
162
Banajit Goswamib016de92017-02-15 21:02:30 -0800163 cdc_reset_ctrl {
164 cdc_reset_sleep: cdc_reset_sleep {
165 mux {
166 pins = "gpio64";
167 function = "gpio";
168 };
169 config {
170 pins = "gpio64";
171 drive-strength = <2>;
172 bias-disable;
173 output-low;
174 };
175 };
176
177 cdc_reset_active:cdc_reset_active {
178 mux {
179 pins = "gpio64";
180 function = "gpio";
181 };
182 config {
183 pins = "gpio64";
184 drive-strength = <8>;
185 bias-pull-down;
186 output-high;
187 };
188 };
189 };
190
191 spkr_i2s_clk_pin {
192 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
193 mux {
194 pins = "gpio69";
195 function = "spkr_i2s";
196 };
197
198 config {
199 pins = "gpio69";
200 drive-strength = <2>; /* 2 mA */
201 bias-pull-down; /* PULL DOWN */
202 };
203 };
204
205 spkr_i2s_clk_active: spkr_i2s_clk_active {
206 mux {
207 pins = "gpio69";
208 function = "spkr_i2s";
209 };
210
211 config {
212 pins = "gpio69";
213 drive-strength = <8>; /* 8 mA */
214 bias-disable; /* NO PULL */
215 };
216 };
217 };
218
219 wcd_gnd_mic_swap {
220 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
221 mux {
222 pins = "gpio51";
223 function = "gpio";
224 };
225 config {
226 pins = "gpio51";
227 drive-strength = <2>;
228 bias-pull-down;
229 output-low;
230 };
231 };
232
233 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
234 mux {
235 pins = "gpio51";
236 function = "gpio";
237 };
238 config {
239 pins = "gpio51";
240 drive-strength = <2>;
241 bias-disable;
242 output-high;
243 };
244 };
245 };
246
247 pri_aux_pcm_clk {
248 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
249 mux {
250 pins = "gpio65";
251 function = "gpio";
252 };
253
254 config {
255 pins = "gpio65";
256 drive-strength = <2>; /* 2 mA */
257 bias-pull-down; /* PULL DOWN */
258 input-enable;
259 };
260 };
261
262 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
263 mux {
264 pins = "gpio65";
265 function = "pri_mi2s";
266 };
267
268 config {
269 pins = "gpio65";
270 drive-strength = <8>; /* 8 mA */
271 bias-disable; /* NO PULL */
272 output-high;
273 };
274 };
275 };
276
277 pri_aux_pcm_sync {
278 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
279 mux {
280 pins = "gpio66";
281 function = "gpio";
282 };
283
284 config {
285 pins = "gpio66";
286 drive-strength = <2>; /* 2 mA */
287 bias-pull-down; /* PULL DOWN */
288 input-enable;
289 };
290 };
291
292 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
293 mux {
294 pins = "gpio66";
295 function = "pri_mi2s_ws";
296 };
297
298 config {
299 pins = "gpio66";
300 drive-strength = <8>; /* 8 mA */
301 bias-disable; /* NO PULL */
302 output-high;
303 };
304 };
305 };
306
307 pri_aux_pcm_din {
308 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
309 mux {
310 pins = "gpio67";
311 function = "gpio";
312 };
313
314 config {
315 pins = "gpio67";
316 drive-strength = <2>; /* 2 mA */
317 bias-pull-down; /* PULL DOWN */
318 input-enable;
319 };
320 };
321
322 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
323 mux {
324 pins = "gpio67";
325 function = "pri_mi2s";
326 };
327
328 config {
329 pins = "gpio67";
330 drive-strength = <8>; /* 8 mA */
331 bias-disable; /* NO PULL */
332 };
333 };
334 };
335
336 pri_aux_pcm_dout {
337 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
338 mux {
339 pins = "gpio68";
340 function = "gpio";
341 };
342
343 config {
344 pins = "gpio68";
345 drive-strength = <2>; /* 2 mA */
346 bias-pull-down; /* PULL DOWN */
347 input-enable;
348 };
349 };
350
351 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
352 mux {
353 pins = "gpio68";
354 function = "pri_mi2s";
355 };
356
357 config {
358 pins = "gpio68";
359 drive-strength = <8>; /* 8 mA */
360 bias-disable; /* NO PULL */
361 };
362 };
363 };
364
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700365 pmx_sde: pmx_sde {
366 sde_dsi_active: sde_dsi_active {
367 mux {
368 pins = "gpio6", "gpio52";
369 function = "gpio";
370 };
371
372 config {
373 pins = "gpio6", "gpio52";
374 drive-strength = <8>; /* 8 mA */
375 bias-disable = <0>; /* no pull */
376 };
377 };
378 sde_dsi_suspend: sde_dsi_suspend {
379 mux {
380 pins = "gpio6", "gpio52";
381 function = "gpio";
382 };
383
384 config {
385 pins = "gpio6", "gpio52";
386 drive-strength = <2>; /* 2 mA */
387 bias-pull-down; /* PULL DOWN */
388 };
389 };
390 };
391
392 pmx_sde_te {
393 sde_te_active: sde_te_active {
394 mux {
395 pins = "gpio10";
396 function = "mdp_vsync";
397 };
398
399 config {
400 pins = "gpio10";
401 drive-strength = <2>; /* 2 mA */
402 bias-pull-down; /* PULL DOWN */
403 };
404 };
405
406 sde_te_suspend: sde_te_suspend {
407 mux {
408 pins = "gpio10";
409 function = "mdp_vsync";
410 };
411
412 config {
413 pins = "gpio10";
414 drive-strength = <2>; /* 2 mA */
415 bias-pull-down; /* PULL DOWN */
416 };
417 };
418 };
419
Banajit Goswamib016de92017-02-15 21:02:30 -0800420 sec_aux_pcm {
421 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
422 mux {
423 pins = "gpio80", "gpio81";
424 function = "gpio";
425 };
426
427 config {
428 pins = "gpio80", "gpio81";
429 drive-strength = <2>; /* 2 mA */
430 bias-pull-down; /* PULL DOWN */
431 input-enable;
432 };
433 };
434
435 sec_aux_pcm_active: sec_aux_pcm_active {
436 mux {
437 pins = "gpio80", "gpio81";
438 function = "sec_mi2s";
439 };
440
441 config {
442 pins = "gpio80", "gpio81";
443 drive-strength = <8>; /* 8 mA */
444 bias-disable; /* NO PULL */
445 };
446 };
447 };
448
449 sec_aux_pcm_din {
450 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
451 mux {
452 pins = "gpio82";
453 function = "gpio";
454 };
455
456 config {
457 pins = "gpio82";
458 drive-strength = <2>; /* 2 mA */
459 bias-pull-down; /* PULL DOWN */
460 input-enable;
461 };
462 };
463
464 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
465 mux {
466 pins = "gpio82";
467 function = "sec_mi2s";
468 };
469
470 config {
471 pins = "gpio82";
472 drive-strength = <8>; /* 8 mA */
473 bias-disable; /* NO PULL */
474 };
475 };
476 };
477
478 sec_aux_pcm_dout {
479 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
480 mux {
481 pins = "gpio83";
482 function = "gpio";
483 };
484
485 config {
486 pins = "gpio83";
487 drive-strength = <2>; /* 2 mA */
488 bias-pull-down; /* PULL DOWN */
489 input-enable;
490 };
491 };
492
493 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
494 mux {
495 pins = "gpio83";
496 function = "sec_mi2s";
497 };
498
499 config {
500 pins = "gpio83";
501 drive-strength = <8>; /* 8 mA */
502 bias-disable; /* NO PULL */
503 };
504 };
505 };
506
507 tert_aux_pcm {
508 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
509 mux {
510 pins = "gpio75", "gpio76";
511 function = "gpio";
512 };
513
514 config {
515 pins = "gpio75", "gpio76";
516 drive-strength = <2>; /* 2 mA */
517 bias-pull-down; /* PULL DOWN */
518 input-enable;
519 };
520 };
521
522 tert_aux_pcm_active: tert_aux_pcm_active {
523 mux {
524 pins = "gpio75", "gpio76";
525 function = "ter_mi2s";
526 };
527
528 config {
529 pins = "gpio75", "gpio76";
530 drive-strength = <8>; /* 8 mA */
531 bias-disable; /* NO PULL */
532 output-high;
533 };
534 };
535 };
536
537 tert_aux_pcm_din {
538 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
539 mux {
540 pins = "gpio77";
541 function = "gpio";
542 };
543
544 config {
545 pins = "gpio77";
546 drive-strength = <2>; /* 2 mA */
547 bias-pull-down; /* PULL DOWN */
548 input-enable;
549 };
550 };
551
552 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
553 mux {
554 pins = "gpio77";
555 function = "ter_mi2s";
556 };
557
558 config {
559 pins = "gpio77";
560 drive-strength = <8>; /* 8 mA */
561 bias-disable; /* NO PULL */
562 };
563 };
564 };
565
566 tert_aux_pcm_dout {
567 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
568 mux {
569 pins = "gpio78";
570 function = "gpio";
571 };
572
573 config {
574 pins = "gpio78";
575 drive-strength = <2>; /* 2 mA */
576 bias-pull-down; /* PULL DOWN */
577 input-enable;
578 };
579 };
580
581 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
582 mux {
583 pins = "gpio78";
584 function = "ter_mi2s";
585 };
586
587 config {
588 pins = "gpio78";
589 drive-strength = <8>; /* 8 mA */
590 bias-disable; /* NO PULL */
591 };
592 };
593 };
594
595 quat_aux_pcm {
596 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
597 mux {
598 pins = "gpio58", "gpio59";
599 function = "gpio";
600 };
601
602 config {
603 pins = "gpio58", "gpio59";
604 drive-strength = <2>; /* 2 mA */
605 bias-pull-down; /* PULL DOWN */
606 input-enable;
607 };
608 };
609
610 quat_aux_pcm_active: quat_aux_pcm_active {
611 mux {
612 pins = "gpio58", "gpio59";
613 function = "qua_mi2s";
614 };
615
616 config {
617 pins = "gpio58", "gpio59";
618 drive-strength = <8>; /* 8 mA */
619 bias-disable; /* NO PULL */
620 output-high;
621 };
622 };
623 };
624
625 quat_aux_pcm_din {
626 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
627 mux {
628 pins = "gpio60";
629 function = "gpio";
630 };
631
632 config {
633 pins = "gpio60";
634 drive-strength = <2>; /* 2 mA */
635 bias-pull-down; /* PULL DOWN */
636 input-enable;
637 };
638 };
639
640 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
641 mux {
642 pins = "gpio60";
643 function = "qua_mi2s";
644 };
645
646 config {
647 pins = "gpio60";
648 drive-strength = <8>; /* 8 mA */
649 bias-disable; /* NO PULL */
650 };
651 };
652 };
653
654 quat_aux_pcm_dout {
655 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
656 mux {
657 pins = "gpio61";
658 function = "gpio";
659 };
660
661 config {
662 pins = "gpio61";
663 drive-strength = <2>; /* 2 mA */
664 bias-pull-down; /* PULL DOWN */
665 input-enable;
666 };
667 };
668
669 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
670 mux {
671 pins = "gpio61";
672 function = "qua_mi2s";
673 };
674
675 config {
676 pins = "gpio61";
677 drive-strength = <8>; /* 8 mA */
678 bias-disable; /* NO PULL */
679 };
680 };
681 };
682
683 pri_mi2s_mclk {
684 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
685 mux {
686 pins = "gpio64";
687 function = "gpio";
688 };
689
690 config {
691 pins = "gpio64";
692 drive-strength = <2>; /* 2 mA */
693 bias-pull-down; /* PULL DOWN */
694 input-enable;
695 };
696 };
697
698 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
699 mux {
700 pins = "gpio64";
701 function = "pri_mi2s";
702 };
703
704 config {
705 pins = "gpio64";
706 drive-strength = <8>; /* 8 mA */
707 bias-disable; /* NO PULL */
708 output-high;
709 };
710 };
711 };
712
713 pri_mi2s_sck {
714 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
715 mux {
716 pins = "gpio65";
717 function = "gpio";
718 };
719
720 config {
721 pins = "gpio65";
722 drive-strength = <2>; /* 2 mA */
723 bias-pull-down; /* PULL DOWN */
724 input-enable;
725 };
726 };
727
728 pri_mi2s_sck_active: pri_mi2s_sck_active {
729 mux {
730 pins = "gpio65";
731 function = "pri_mi2s";
732 };
733
734 config {
735 pins = "gpio65";
736 drive-strength = <8>; /* 8 mA */
737 bias-disable; /* NO PULL */
738 output-high;
739 };
740 };
741 };
742
743 pri_mi2s_ws {
744 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
745 mux {
746 pins = "gpio66";
747 function = "gpio";
748 };
749
750 config {
751 pins = "gpio66";
752 drive-strength = <2>; /* 2 mA */
753 bias-pull-down; /* PULL DOWN */
754 input-enable;
755 };
756 };
757
758 pri_mi2s_ws_active: pri_mi2s_ws_active {
759 mux {
760 pins = "gpio66";
761 function = "pri_mi2s_ws";
762 };
763
764 config {
765 pins = "gpio66";
766 drive-strength = <8>; /* 8 mA */
767 bias-disable; /* NO PULL */
768 output-high;
769 };
770 };
771 };
772
773 pri_mi2s_sd0 {
774 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
775 mux {
776 pins = "gpio67";
777 function = "gpio";
778 };
779
780 config {
781 pins = "gpio67";
782 drive-strength = <2>; /* 2 mA */
783 bias-pull-down; /* PULL DOWN */
784 input-enable;
785 };
786 };
787
788 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
789 mux {
790 pins = "gpio67";
791 function = "pri_mi2s";
792 };
793
794 config {
795 pins = "gpio67";
796 drive-strength = <8>; /* 8 mA */
797 bias-disable; /* NO PULL */
798 };
799 };
800 };
801
802 pri_mi2s_sd1 {
803 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
804 mux {
805 pins = "gpio68";
806 function = "gpio";
807 };
808
809 config {
810 pins = "gpio68";
811 drive-strength = <2>; /* 2 mA */
812 bias-pull-down; /* PULL DOWN */
813 input-enable;
814 };
815 };
816
817 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
818 mux {
819 pins = "gpio68";
820 function = "pri_mi2s";
821 };
822
823 config {
824 pins = "gpio68";
825 drive-strength = <8>; /* 8 mA */
826 bias-disable; /* NO PULL */
827 };
828 };
829 };
830
831 sec_mi2s_mclk {
832 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
833 mux {
834 pins = "gpio79";
835 function = "gpio";
836 };
837
838 config {
839 pins = "gpio79";
840 drive-strength = <2>; /* 2 mA */
841 bias-pull-down; /* PULL DOWN */
842 input-enable;
843 };
844 };
845
846 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
847 mux {
848 pins = "gpio79";
849 function = "sec_mi2s";
850 };
851
852 config {
853 pins = "gpio79";
854 drive-strength = <8>; /* 8 mA */
855 bias-disable; /* NO PULL */
856 };
857 };
858 };
859
860 sec_mi2s {
861 sec_mi2s_sleep: sec_mi2s_sleep {
862 mux {
863 pins = "gpio80", "gpio81";
864 function = "gpio";
865 };
866
867 config {
868 pins = "gpio80", "gpio81";
869 drive-strength = <2>; /* 2 mA */
870 bias-disable; /* NO PULL */
871 input-enable;
872 };
873 };
874
875 sec_mi2s_active: sec_mi2s_active {
876 mux {
877 pins = "gpio80", "gpio81";
878 function = "sec_mi2s";
879 };
880
881 config {
882 pins = "gpio80", "gpio81";
883 drive-strength = <8>; /* 8 mA */
884 bias-disable; /* NO PULL */
885 };
886 };
887 };
888
889 sec_mi2s_sd0 {
890 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
891 mux {
892 pins = "gpio82";
893 function = "gpio";
894 };
895
896 config {
897 pins = "gpio82";
898 drive-strength = <2>; /* 2 mA */
899 bias-pull-down; /* PULL DOWN */
900 input-enable;
901 };
902 };
903
904 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
905 mux {
906 pins = "gpio82";
907 function = "sec_mi2s";
908 };
909
910 config {
911 pins = "gpio82";
912 drive-strength = <8>; /* 8 mA */
913 bias-disable; /* NO PULL */
914 };
915 };
916 };
917
918 sec_mi2s_sd1 {
919 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
920 mux {
921 pins = "gpio83";
922 function = "gpio";
923 };
924
925 config {
926 pins = "gpio83";
927 drive-strength = <2>; /* 2 mA */
928 bias-pull-down; /* PULL DOWN */
929 input-enable;
930 };
931 };
932
933 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
934 mux {
935 pins = "gpio83";
936 function = "sec_mi2s";
937 };
938
939 config {
940 pins = "gpio83";
941 drive-strength = <8>; /* 8 mA */
942 bias-disable; /* NO PULL */
943 };
944 };
945 };
946
947 tert_mi2s_mclk {
948 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
949 mux {
950 pins = "gpio74";
951 function = "gpio";
952 };
953
954 config {
955 pins = "gpio74";
956 drive-strength = <2>; /* 2 mA */
957 bias-pull-down; /* PULL DOWN */
958 input-enable;
959 };
960 };
961
962 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
963 mux {
964 pins = "gpio74";
965 function = "ter_mi2s";
966 };
967
968 config {
969 pins = "gpio74";
970 drive-strength = <8>; /* 8 mA */
971 bias-disable; /* NO PULL */
972 };
973 };
974 };
975
976 tert_mi2s {
977 tert_mi2s_sleep: tert_mi2s_sleep {
978 mux {
979 pins = "gpio75", "gpio76";
980 function = "gpio";
981 };
982
983 config {
984 pins = "gpio75", "gpio76";
985 drive-strength = <2>; /* 2 mA */
986 bias-pull-down; /* PULL DOWN */
987 input-enable;
988 };
989 };
990
991 tert_mi2s_active: tert_mi2s_active {
992 mux {
993 pins = "gpio75", "gpio76";
994 function = "ter_mi2s";
995 };
996
997 config {
998 pins = "gpio75", "gpio76";
999 drive-strength = <8>; /* 8 mA */
1000 bias-disable; /* NO PULL */
1001 output-high;
1002 };
1003 };
1004 };
1005
1006 tert_mi2s_sd0 {
1007 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1008 mux {
1009 pins = "gpio77";
1010 function = "gpio";
1011 };
1012
1013 config {
1014 pins = "gpio77";
1015 drive-strength = <2>; /* 2 mA */
1016 bias-pull-down; /* PULL DOWN */
1017 input-enable;
1018 };
1019 };
1020
1021 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1022 mux {
1023 pins = "gpio77";
1024 function = "ter_mi2s";
1025 };
1026
1027 config {
1028 pins = "gpio77";
1029 drive-strength = <8>; /* 8 mA */
1030 bias-disable; /* NO PULL */
1031 };
1032 };
1033 };
1034
1035 tert_mi2s_sd1 {
1036 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1037 mux {
1038 pins = "gpio78";
1039 function = "gpio";
1040 };
1041
1042 config {
1043 pins = "gpio78";
1044 drive-strength = <2>; /* 2 mA */
1045 bias-pull-down; /* PULL DOWN */
1046 input-enable;
1047 };
1048 };
1049
1050 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1051 mux {
1052 pins = "gpio78";
1053 function = "ter_mi2s";
1054 };
1055
1056 config {
1057 pins = "gpio78";
1058 drive-strength = <8>; /* 8 mA */
1059 bias-disable; /* NO PULL */
1060 };
1061 };
1062 };
1063
1064 quat_mi2s_mclk {
1065 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1066 mux {
1067 pins = "gpio57";
1068 function = "gpio";
1069 };
1070
1071 config {
1072 pins = "gpio57";
1073 drive-strength = <2>; /* 2 mA */
1074 bias-pull-down; /* PULL DOWN */
1075 input-enable;
1076 };
1077 };
1078
1079 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1080 mux {
1081 pins = "gpio57";
1082 function = "qua_mi2s";
1083 };
1084
1085 config {
1086 pins = "gpio57";
1087 drive-strength = <8>; /* 8 mA */
1088 bias-disable; /* NO PULL */
1089 };
1090 };
1091 };
1092
1093 quat_mi2s {
1094 quat_mi2s_sleep: quat_mi2s_sleep {
1095 mux {
1096 pins = "gpio58", "gpio59";
1097 function = "gpio";
1098 };
1099
1100 config {
1101 pins = "gpio58", "gpio59";
1102 drive-strength = <2>; /* 2 mA */
1103 bias-pull-down; /* PULL DOWN */
1104 input-enable;
1105 };
1106 };
1107
1108 quat_mi2s_active: quat_mi2s_active {
1109 mux {
1110 pins = "gpio58", "gpio59";
1111 function = "qua_mi2s";
1112 };
1113
1114 config {
1115 pins = "gpio58", "gpio59";
1116 drive-strength = <8>; /* 8 mA */
1117 bias-disable; /* NO PULL */
1118 output-high;
1119 };
1120 };
1121 };
1122
1123 quat_mi2s_sd0 {
1124 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1125 mux {
1126 pins = "gpio60";
1127 function = "gpio";
1128 };
1129
1130 config {
1131 pins = "gpio60";
1132 drive-strength = <2>; /* 2 mA */
1133 bias-pull-down; /* PULL DOWN */
1134 input-enable;
1135 };
1136 };
1137
1138 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1139 mux {
1140 pins = "gpio60";
1141 function = "qua_mi2s";
1142 };
1143
1144 config {
1145 pins = "gpio60";
1146 drive-strength = <8>; /* 8 mA */
1147 bias-disable; /* NO PULL */
1148 };
1149 };
1150 };
1151
1152 quat_mi2s_sd1 {
1153 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1154 mux {
1155 pins = "gpio61";
1156 function = "gpio";
1157 };
1158
1159 config {
1160 pins = "gpio61";
1161 drive-strength = <2>; /* 2 mA */
1162 bias-pull-down; /* PULL DOWN */
1163 input-enable;
1164 };
1165 };
1166
1167 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1168 mux {
1169 pins = "gpio61";
1170 function = "qua_mi2s";
1171 };
1172
1173 config {
1174 pins = "gpio61";
1175 drive-strength = <8>; /* 8 mA */
1176 bias-disable; /* NO PULL */
1177 };
1178 };
1179 };
1180
1181 quat_mi2s_sd2 {
1182 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1183 mux {
1184 pins = "gpio62";
1185 function = "gpio";
1186 };
1187
1188 config {
1189 pins = "gpio62";
1190 drive-strength = <2>; /* 2 mA */
1191 bias-pull-down; /* PULL DOWN */
1192 input-enable;
1193 };
1194 };
1195
1196 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1197 mux {
1198 pins = "gpio62";
1199 function = "qua_mi2s";
1200 };
1201
1202 config {
1203 pins = "gpio62";
1204 drive-strength = <8>; /* 8 mA */
1205 bias-disable; /* NO PULL */
1206 };
1207 };
1208 };
1209
1210 quat_mi2s_sd3 {
1211 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1212 mux {
1213 pins = "gpio63";
1214 function = "gpio";
1215 };
1216
1217 config {
1218 pins = "gpio63";
1219 drive-strength = <2>; /* 2 mA */
1220 bias-pull-down; /* PULL DOWN */
1221 input-enable;
1222 };
1223 };
1224
1225 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1226 mux {
1227 pins = "gpio63";
1228 function = "qua_mi2s";
1229 };
1230
1231 config {
1232 pins = "gpio63";
1233 drive-strength = <8>; /* 8 mA */
1234 bias-disable; /* NO PULL */
1235 };
1236 };
1237 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001238
1239 /* QUPv3 South SE mappings */
1240 /* SE 0 pin mappings */
1241 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1242 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1243 mux {
1244 pins = "gpio0", "gpio1";
1245 function = "qup0";
1246 };
1247
1248 config {
1249 pins = "gpio0", "gpio1";
1250 drive-strength = <2>;
1251 bias-disable;
1252 };
1253 };
1254
1255 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1256 mux {
1257 pins = "gpio0", "gpio1";
1258 function = "gpio";
1259 };
1260
1261 config {
1262 pins = "gpio0", "gpio1";
1263 drive-strength = <2>;
1264 bias-pull-up;
1265 };
1266 };
1267 };
1268
1269 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1270 qupv3_se0_spi_active: qupv3_se0_spi_active {
1271 mux {
1272 pins = "gpio0", "gpio1", "gpio2",
1273 "gpio3";
1274 function = "qup0";
1275 };
1276
1277 config {
1278 pins = "gpio0", "gpio1", "gpio2",
1279 "gpio3";
1280 drive-strength = <6>;
1281 bias-disable;
1282 };
1283 };
1284
1285 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1286 mux {
1287 pins = "gpio0", "gpio1", "gpio2",
1288 "gpio3";
1289 function = "gpio";
1290 };
1291
1292 config {
1293 pins = "gpio0", "gpio1", "gpio2",
1294 "gpio3";
1295 drive-strength = <6>;
1296 bias-disable;
1297 };
1298 };
1299 };
1300
1301 /* SE 1 pin mappings */
1302 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1303 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1304 mux {
1305 pins = "gpio17", "gpio18";
1306 function = "qup1";
1307 };
1308
1309 config {
1310 pins = "gpio17", "gpio18";
1311 drive-strength = <2>;
1312 bias-disable;
1313 };
1314 };
1315
1316 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1317 mux {
1318 pins = "gpio17", "gpio18";
1319 function = "gpio";
1320 };
1321
1322 config {
1323 pins = "gpio17", "gpio18";
1324 drive-strength = <2>;
1325 bias-pull-up;
1326 };
1327 };
1328 };
1329
1330 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1331 qupv3_se1_spi_active: qupv3_se1_spi_active {
1332 mux {
1333 pins = "gpio17", "gpio18", "gpio19",
1334 "gpio20";
1335 function = "qup1";
1336 };
1337
1338 config {
1339 pins = "gpio17", "gpio18", "gpio19",
1340 "gpio20";
1341 drive-strength = <6>;
1342 bias-disable;
1343 };
1344 };
1345
1346 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1347 mux {
1348 pins = "gpio17", "gpio18", "gpio19",
1349 "gpio20";
1350 function = "gpio";
1351 };
1352
1353 config {
1354 pins = "gpio17", "gpio18", "gpio19",
1355 "gpio20";
1356 drive-strength = <6>;
1357 bias-disable;
1358 };
1359 };
1360 };
1361
1362 /* SE 2 pin mappings */
1363 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1364 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1365 mux {
1366 pins = "gpio27", "gpio28";
1367 function = "qup2";
1368 };
1369
1370 config {
1371 pins = "gpio27", "gpio28";
1372 drive-strength = <2>;
1373 bias-disable;
1374 };
1375 };
1376
1377 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1378 mux {
1379 pins = "gpio27", "gpio28";
1380 function = "gpio";
1381 };
1382
1383 config {
1384 pins = "gpio27", "gpio28";
1385 drive-strength = <2>;
1386 bias-pull-up;
1387 };
1388 };
1389 };
1390
1391 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1392 qupv3_se2_spi_active: qupv3_se2_spi_active {
1393 mux {
1394 pins = "gpio27", "gpio28", "gpio29",
1395 "gpio30";
1396 function = "qup2";
1397 };
1398
1399 config {
1400 pins = "gpio27", "gpio28", "gpio29",
1401 "gpio30";
1402 drive-strength = <6>;
1403 bias-disable;
1404 };
1405 };
1406
1407 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1408 mux {
1409 pins = "gpio27", "gpio28", "gpio29",
1410 "gpio30";
1411 function = "gpio";
1412 };
1413
1414 config {
1415 pins = "gpio27", "gpio28", "gpio29",
1416 "gpio30";
1417 drive-strength = <6>;
1418 bias-disable;
1419 };
1420 };
1421 };
1422
1423 /* SE 3 pin mappings */
1424 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1425 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1426 mux {
1427 pins = "gpio41", "gpio42";
1428 function = "qup3";
1429 };
1430
1431 config {
1432 pins = "gpio41", "gpio42";
1433 drive-strength = <2>;
1434 bias-disable;
1435 };
1436 };
1437
1438 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1439 mux {
1440 pins = "gpio41", "gpio42";
1441 function = "gpio";
1442 };
1443
1444 config {
1445 pins = "gpio41", "gpio42";
1446 drive-strength = <2>;
1447 bias-pull-up;
1448 };
1449 };
1450 };
1451
1452 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1453 qupv3_se3_spi_active: qupv3_se3_spi_active {
1454 mux {
1455 pins = "gpio41", "gpio42", "gpio43",
1456 "gpio44";
1457 function = "qup3";
1458 };
1459
1460 config {
1461 pins = "gpio41", "gpio42", "gpio43",
1462 "gpio44";
1463 drive-strength = <6>;
1464 bias-disable;
1465 };
1466 };
1467
1468 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1469 mux {
1470 pins = "gpio41", "gpio42", "gpio43",
1471 "gpio44";
1472 function = "gpio";
1473 };
1474
1475 config {
1476 pins = "gpio41", "gpio42", "gpio43",
1477 "gpio44";
1478 drive-strength = <6>;
1479 bias-disable;
1480 };
1481 };
1482 };
1483
1484 /* SE 4 pin mappings */
1485 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1486 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1487 mux {
1488 pins = "gpio89", "gpio90";
1489 function = "qup4";
1490 };
1491
1492 config {
1493 pins = "gpio89", "gpio90";
1494 drive-strength = <2>;
1495 bias-disable;
1496 };
1497 };
1498
1499 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1500 mux {
1501 pins = "gpio89", "gpio90";
1502 function = "gpio";
1503 };
1504
1505 config {
1506 pins = "gpio89", "gpio90";
1507 drive-strength = <2>;
1508 bias-pull-up;
1509 };
1510 };
1511 };
1512
1513 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1514 qupv3_se4_spi_active: qupv3_se4_spi_active {
1515 mux {
1516 pins = "gpio89", "gpio90", "gpio91",
1517 "gpio92";
1518 function = "qup4";
1519 };
1520
1521 config {
1522 pins = "gpio89", "gpio90", "gpio91",
1523 "gpio92";
1524 drive-strength = <6>;
1525 bias-disable;
1526 };
1527 };
1528
1529 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
1530 mux {
1531 pins = "gpio89", "gpio90", "gpio91",
1532 "gpio92";
1533 function = "gpio";
1534 };
1535
1536 config {
1537 pins = "gpio89", "gpio90", "gpio91",
1538 "gpio92";
1539 drive-strength = <6>;
1540 bias-disable;
1541 };
1542 };
1543 };
1544
1545 /* SE 5 pin mappings */
1546 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
1547 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
1548 mux {
1549 pins = "gpio85", "gpio86";
1550 function = "qup5";
1551 };
1552
1553 config {
1554 pins = "gpio85", "gpio86";
1555 drive-strength = <2>;
1556 bias-disable;
1557 };
1558 };
1559
1560 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
1561 mux {
1562 pins = "gpio85", "gpio86";
1563 function = "gpio";
1564 };
1565
1566 config {
1567 pins = "gpio85", "gpio86";
1568 drive-strength = <2>;
1569 bias-pull-up;
1570 };
1571 };
1572 };
1573
1574 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
1575 qupv3_se5_spi_active: qupv3_se5_spi_active {
1576 mux {
1577 pins = "gpio85", "gpio86", "gpio87",
1578 "gpio88";
1579 function = "qup5";
1580 };
1581
1582 config {
1583 pins = "gpio85", "gpio86", "gpio87",
1584 "gpio88";
1585 drive-strength = <6>;
1586 bias-disable;
1587 };
1588 };
1589
1590 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
1591 mux {
1592 pins = "gpio85", "gpio86", "gpio87",
1593 "gpio88";
1594 function = "gpio";
1595 };
1596
1597 config {
1598 pins = "gpio85", "gpio86", "gpio87",
1599 "gpio88";
1600 drive-strength = <6>;
1601 bias-disable;
1602 };
1603 };
1604 };
1605
1606 /* SE 6 pin mappings */
1607 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
1608 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
1609 mux {
1610 pins = "gpio45", "gpio46";
1611 function = "qup6";
1612 };
1613
1614 config {
1615 pins = "gpio45", "gpio46";
1616 drive-strength = <2>;
1617 bias-disable;
1618 };
1619 };
1620
1621 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
1622 mux {
1623 pins = "gpio45", "gpio46";
1624 function = "gpio";
1625 };
1626
1627 config {
1628 pins = "gpio45", "gpio46";
1629 drive-strength = <2>;
1630 bias-pull-up;
1631 };
1632 };
1633 };
1634
1635 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
1636 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
1637 mux {
1638 pins = "gpio45", "gpio46", "gpio47",
1639 "gpio48";
1640 function = "qup6";
1641 };
1642
1643 config {
1644 pins = "gpio45", "gpio46", "gpio47",
1645 "gpio48";
1646 drive-strength = <2>;
1647 bias-disable;
1648 };
1649 };
1650
1651 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
1652 mux {
1653 pins = "gpio45", "gpio46", "gpio47",
1654 "gpio48";
1655 function = "gpio";
1656 };
1657
1658 config {
1659 pins = "gpio45", "gpio46", "gpio47",
1660 "gpio48";
1661 drive-strength = <2>;
1662 bias-disable;
1663 };
1664 };
1665 };
1666
1667 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
1668 qupv3_se6_spi_active: qupv3_se6_spi_active {
1669 mux {
1670 pins = "gpio45", "gpio46", "gpio47",
1671 "gpio48";
1672 function = "qup6";
1673 };
1674
1675 config {
1676 pins = "gpio45", "gpio46", "gpio47",
1677 "gpio48";
1678 drive-strength = <6>;
1679 bias-disable;
1680 };
1681 };
1682
1683 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
1684 mux {
1685 pins = "gpio45", "gpio46", "gpio47",
1686 "gpio48";
1687 function = "gpio";
1688 };
1689
1690 config {
1691 pins = "gpio45", "gpio46", "gpio47",
1692 "gpio48";
1693 drive-strength = <6>;
1694 bias-disable;
1695 };
1696 };
1697 };
1698
1699 /* SE 7 pin mappings */
1700 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
1701 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
1702 mux {
1703 pins = "gpio93", "gpio94";
1704 function = "qup7";
1705 };
1706
1707 config {
1708 pins = "gpio93", "gpio94";
1709 drive-strength = <2>;
1710 bias-disable;
1711 };
1712 };
1713
1714 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
1715 mux {
1716 pins = "gpio93", "gpio94";
1717 function = "gpio";
1718 };
1719
1720 config {
1721 pins = "gpio93", "gpio94";
1722 drive-strength = <2>;
1723 bias-pull-up;
1724 };
1725 };
1726 };
1727
1728 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
1729 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
1730 mux {
1731 pins = "gpio93", "gpio94", "gpio95",
1732 "gpio96";
1733 function = "qup7";
1734 };
1735
1736 config {
1737 pins = "gpio93", "gpio94", "gpio95",
1738 "gpio96";
1739 drive-strength = <2>;
1740 bias-disable;
1741 };
1742 };
1743
1744 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
1745 mux {
1746 pins = "gpio93", "gpio94", "gpio95",
1747 "gpio96";
1748 function = "gpio";
1749 };
1750
1751 config {
1752 pins = "gpio93", "gpio94", "gpio95",
1753 "gpio96";
1754 drive-strength = <2>;
1755 bias-disable;
1756 };
1757 };
1758 };
1759
1760 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
1761 qupv3_se7_spi_active: qupv3_se7_spi_active {
1762 mux {
1763 pins = "gpio93", "gpio94", "gpio95",
1764 "gpio96";
1765 function = "qup7";
1766 };
1767
1768 config {
1769 pins = "gpio93", "gpio94", "gpio95",
1770 "gpio96";
1771 drive-strength = <6>;
1772 bias-disable;
1773 };
1774 };
1775
1776 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
1777 mux {
1778 pins = "gpio93", "gpio94", "gpio95",
1779 "gpio96";
1780 function = "gpio";
1781 };
1782
1783 config {
1784 pins = "gpio93", "gpio94", "gpio95",
1785 "gpio96";
1786 drive-strength = <6>;
1787 bias-disable;
1788 };
1789 };
1790 };
1791
1792 /* QUPv3 North instances */
1793 /* SE 8 pin mappings */
1794 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
1795 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
1796 mux {
1797 pins = "gpio65", "gpio66";
1798 function = "qup8";
1799 };
1800
1801 config {
1802 pins = "gpio65", "gpio66";
1803 drive-strength = <2>;
1804 bias-disable;
1805 };
1806 };
1807
1808 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
1809 mux {
1810 pins = "gpio65", "gpio66";
1811 function = "gpio";
1812 };
1813
1814 config {
1815 pins = "gpio65", "gpio66";
1816 drive-strength = <2>;
1817 bias-pull-up;
1818 };
1819 };
1820 };
1821
1822 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
1823 qupv3_se8_spi_active: qupv3_se8_spi_active {
1824 mux {
1825 pins = "gpio65", "gpio66", "gpio67",
1826 "gpio68";
1827 function = "qup8";
1828 };
1829
1830 config {
1831 pins = "gpio65", "gpio66", "gpio67",
1832 "gpio68";
1833 drive-strength = <6>;
1834 bias-disable;
1835 };
1836 };
1837
1838 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
1839 mux {
1840 pins = "gpio65", "gpio66", "gpio67",
1841 "gpio68";
1842 function = "gpio";
1843 };
1844
1845 config {
1846 pins = "gpio65", "gpio66", "gpio67",
1847 "gpio68";
1848 drive-strength = <6>;
1849 bias-disable;
1850 };
1851 };
1852 };
1853
1854 /* SE 9 pin mappings */
1855 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
1856 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
1857 mux {
1858 pins = "gpio6", "gpio7";
1859 function = "qup9";
1860 };
1861
1862 config {
1863 pins = "gpio6", "gpio7";
1864 drive-strength = <2>;
1865 bias-disable;
1866 };
1867 };
1868
1869 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
1870 mux {
1871 pins = "gpio6", "gpio7";
1872 function = "gpio";
1873 };
1874
1875 config {
1876 pins = "gpio6", "gpio7";
1877 drive-strength = <2>;
1878 bias-pull-up;
1879 };
1880 };
1881 };
1882
1883 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
1884 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
1885 mux {
1886 pins = "gpio4", "gpio5";
1887 function = "qup9";
1888 };
1889
1890 config {
1891 pins = "gpio4", "gpio5";
1892 drive-strength = <2>;
1893 bias-disable;
1894 };
1895 };
1896
1897 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
1898 mux {
1899 pins = "gpio4", "gpio5";
1900 function = "gpio";
1901 };
1902
1903 config {
1904 pins = "gpio4", "gpio5";
1905 drive-strength = <2>;
1906 bias-disable;
1907 };
1908 };
1909 };
1910
1911 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
1912 qupv3_se9_spi_active: qupv3_se9_spi_active {
1913 mux {
1914 pins = "gpio4", "gpio5", "gpio6",
1915 "gpio7";
1916 function = "qup9";
1917 };
1918
1919 config {
1920 pins = "gpio4", "gpio5", "gpio6",
1921 "gpio7";
1922 drive-strength = <6>;
1923 bias-disable;
1924 };
1925 };
1926
1927 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
1928 mux {
1929 pins = "gpio4", "gpio5", "gpio6",
1930 "gpio7";
1931 function = "gpio";
1932 };
1933
1934 config {
1935 pins = "gpio4", "gpio5", "gpio6",
1936 "gpio7";
1937 drive-strength = <6>;
1938 bias-disable;
1939 };
1940 };
1941 };
1942
1943 /* SE 10 pin mappings */
1944 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
1945 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
1946 mux {
1947 pins = "gpio55", "gpio56";
1948 function = "qup10";
1949 };
1950
1951 config {
1952 pins = "gpio55", "gpio56";
1953 drive-strength = <2>;
1954 bias-disable;
1955 };
1956 };
1957
1958 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
1959 mux {
1960 pins = "gpio55", "gpio56";
1961 function = "gpio";
1962 };
1963
1964 config {
1965 pins = "gpio55", "gpio56";
1966 drive-strength = <2>;
1967 bias-pull-up;
1968 };
1969 };
1970 };
1971
1972 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
1973 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
1974 mux {
1975 pins = "gpio53", "gpio54";
1976 function = "qup10";
1977 };
1978
1979 config {
1980 pins = "gpio53", "gpio54";
1981 drive-strength = <2>;
1982 bias-disable;
1983 };
1984 };
1985
1986 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
1987 mux {
1988 pins = "gpio53", "gpio54";
1989 function = "gpio";
1990 };
1991
1992 config {
1993 pins = "gpio53", "gpio54";
1994 drive-strength = <2>;
1995 bias-disable;
1996 };
1997 };
1998 };
1999
2000 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2001 qupv3_se10_spi_active: qupv3_se10_spi_active {
2002 mux {
2003 pins = "gpio53", "gpio54", "gpio55",
2004 "gpio56";
2005 function = "qup10";
2006 };
2007
2008 config {
2009 pins = "gpio53", "gpio54", "gpio55",
2010 "gpio56";
2011 drive-strength = <6>;
2012 bias-disable;
2013 };
2014 };
2015
2016 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2017 mux {
2018 pins = "gpio53", "gpio54", "gpio55",
2019 "gpio56";
2020 function = "gpio";
2021 };
2022
2023 config {
2024 pins = "gpio53", "gpio54", "gpio55",
2025 "gpio56";
2026 drive-strength = <6>;
2027 bias-disable;
2028 };
2029 };
2030 };
2031
2032 /* SE 11 pin mappings */
2033 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2034 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2035 mux {
2036 pins = "gpio31", "gpio32";
2037 function = "qup11";
2038 };
2039
2040 config {
2041 pins = "gpio31", "gpio32";
2042 drive-strength = <2>;
2043 bias-disable;
2044 };
2045 };
2046
2047 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2048 mux {
2049 pins = "gpio31", "gpio32";
2050 function = "gpio";
2051 };
2052
2053 config {
2054 pins = "gpio31", "gpio32";
2055 drive-strength = <2>;
2056 bias-pull-up;
2057 };
2058 };
2059 };
2060
2061 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2062 qupv3_se11_spi_active: qupv3_se11_spi_active {
2063 mux {
2064 pins = "gpio31", "gpio32", "gpio33",
2065 "gpio34";
2066 function = "qup11";
2067 };
2068
2069 config {
2070 pins = "gpio31", "gpio32", "gpio33",
2071 "gpio34";
2072 drive-strength = <6>;
2073 bias-disable;
2074 };
2075 };
2076
2077 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2078 mux {
2079 pins = "gpio31", "gpio32", "gpio33",
2080 "gpio34";
2081 function = "gpio";
2082 };
2083
2084 config {
2085 pins = "gpio31", "gpio32", "gpio33",
2086 "gpio34";
2087 drive-strength = <6>;
2088 bias-disable;
2089 };
2090 };
2091 };
2092
2093 /* SE 12 pin mappings */
2094 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2095 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2096 mux {
2097 pins = "gpio49", "gpio50";
2098 function = "qup12";
2099 };
2100
2101 config {
2102 pins = "gpio49", "gpio50";
2103 drive-strength = <2>;
2104 bias-disable;
2105 };
2106 };
2107
2108 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2109 mux {
2110 pins = "gpio49", "gpio50";
2111 function = "gpio";
2112 };
2113
2114 config {
2115 pins = "gpio49", "gpio50";
2116 drive-strength = <2>;
2117 bias-pull-up;
2118 };
2119 };
2120 };
2121
2122 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2123 qupv3_se12_spi_active: qupv3_se12_spi_active {
2124 mux {
2125 pins = "gpio49", "gpio50", "gpio51",
2126 "gpio52";
2127 function = "qup12";
2128 };
2129
2130 config {
2131 pins = "gpio49", "gpio50", "gpio51",
2132 "gpio52";
2133 drive-strength = <6>;
2134 bias-disable;
2135 };
2136 };
2137
2138 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2139 mux {
2140 pins = "gpio49", "gpio50", "gpio51",
2141 "gpio52";
2142 function = "gpio";
2143 };
2144
2145 config {
2146 pins = "gpio49", "gpio50", "gpio51",
2147 "gpio52";
2148 drive-strength = <6>;
2149 bias-disable;
2150 };
2151 };
2152 };
2153
2154 /* SE 13 pin mappings */
2155 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2156 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2157 mux {
2158 pins = "gpio105", "gpio106";
2159 function = "qup13";
2160 };
2161
2162 config {
2163 pins = "gpio105", "gpio106";
2164 drive-strength = <2>;
2165 bias-disable;
2166 };
2167 };
2168
2169 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2170 mux {
2171 pins = "gpio105", "gpio106";
2172 function = "gpio";
2173 };
2174
2175 config {
2176 pins = "gpio105", "gpio106";
2177 drive-strength = <2>;
2178 bias-pull-up;
2179 };
2180 };
2181 };
2182
2183 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2184 qupv3_se13_spi_active: qupv3_se13_spi_active {
2185 mux {
2186 pins = "gpio105", "gpio106", "gpio107",
2187 "gpio108";
2188 function = "qup13";
2189 };
2190
2191 config {
2192 pins = "gpio105", "gpio106", "gpio107",
2193 "gpio108";
2194 drive-strength = <6>;
2195 bias-disable;
2196 };
2197 };
2198
2199 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2200 mux {
2201 pins = "gpio105", "gpio106", "gpio107",
2202 "gpio108";
2203 function = "gpio";
2204 };
2205
2206 config {
2207 pins = "gpio105", "gpio106", "gpio107",
2208 "gpio108";
2209 drive-strength = <6>;
2210 bias-disable;
2211 };
2212 };
2213 };
2214
2215 /* SE 14 pin mappings */
2216 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2217 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2218 mux {
2219 pins = "gpio33", "gpio34";
2220 function = "qup14";
2221 };
2222
2223 config {
2224 pins = "gpio33", "gpio34";
2225 drive-strength = <2>;
2226 bias-disable;
2227 };
2228 };
2229
2230 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2231 mux {
2232 pins = "gpio33", "gpio34";
2233 function = "gpio";
2234 };
2235
2236 config {
2237 pins = "gpio33", "gpio34";
2238 drive-strength = <2>;
2239 bias-pull-up;
2240 };
2241 };
2242 };
2243
2244 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2245 qupv3_se14_spi_active: qupv3_se14_spi_active {
2246 mux {
2247 pins = "gpio31", "gpio32", "gpio33",
2248 "gpio34";
2249 function = "qup14";
2250 };
2251
2252 config {
2253 pins = "gpio31", "gpio32", "gpio33",
2254 "gpio34";
2255 drive-strength = <6>;
2256 bias-disable;
2257 };
2258 };
2259
2260 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2261 mux {
2262 pins = "gpio31", "gpio32", "gpio33",
2263 "gpio34";
2264 function = "gpio";
2265 };
2266
2267 config {
2268 pins = "gpio31", "gpio32", "gpio33",
2269 "gpio34";
2270 drive-strength = <6>;
2271 bias-disable;
2272 };
2273 };
2274 };
2275
2276 /* SE 15 pin mappings */
2277 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2278 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2279 mux {
2280 pins = "gpio81", "gpio82";
2281 function = "qup15";
2282 };
2283
2284 config {
2285 pins = "gpio81", "gpio82";
2286 drive-strength = <2>;
2287 bias-disable;
2288 };
2289 };
2290
2291 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2292 mux {
2293 pins = "gpio81", "gpio82";
2294 function = "gpio";
2295 };
2296
2297 config {
2298 pins = "gpio81", "gpio82";
2299 drive-strength = <2>;
2300 bias-pull-up;
2301 };
2302 };
2303 };
2304
2305 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2306 qupv3_se15_spi_active: qupv3_se15_spi_active {
2307 mux {
2308 pins = "gpio81", "gpio82", "gpio83",
2309 "gpio84";
2310 function = "qup15";
2311 };
2312
2313 config {
2314 pins = "gpio81", "gpio82", "gpio83",
2315 "gpio84";
2316 drive-strength = <6>;
2317 bias-disable;
2318 };
2319 };
2320
2321 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2322 mux {
2323 pins = "gpio81", "gpio82", "gpio83",
2324 "gpio84";
2325 function = "gpio";
2326 };
2327
2328 config {
2329 pins = "gpio81", "gpio82", "gpio83",
2330 "gpio84";
2331 drive-strength = <6>;
2332 bias-disable;
2333 };
2334 };
2335 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002336
2337 cci0_active: cci0_active {
2338 mux {
2339 /* CLK, DATA */
2340 pins = "gpio17","gpio18"; // Only 2
2341 function = "cci_i2c";
2342 };
2343
2344 config {
2345 pins = "gpio17","gpio18";
2346 bias-pull-up; /* PULL UP*/
2347 drive-strength = <2>; /* 2 MA */
2348 };
2349 };
2350
2351 cci0_suspend: cci0_suspend {
2352 mux {
2353 /* CLK, DATA */
2354 pins = "gpio17","gpio18";
2355 function = "cci_i2c";
2356 };
2357
2358 config {
2359 pins = "gpio17","gpio18";
2360 bias-pull-down; /* PULL DOWN */
2361 drive-strength = <2>; /* 2 MA */
2362 };
2363 };
2364
2365 cci1_active: cci1_active {
2366 mux {
2367 /* CLK, DATA */
2368 pins = "gpio19","gpio20";
2369 function = "cci_i2c";
2370 };
2371
2372 config {
2373 pins = "gpio19","gpio20";
2374 bias-pull-up; /* PULL UP*/
2375 drive-strength = <2>; /* 2 MA */
2376 };
2377 };
2378
2379 cci1_suspend: cci1_suspend {
2380 mux {
2381 /* CLK, DATA */
2382 pins = "gpio19","gpio20";
2383 function = "cci_i2c";
2384 };
2385
2386 config {
2387 pins = "gpio19","gpio20";
2388 bias-pull-down; /* PULL DOWN */
2389 drive-strength = <2>; /* 2 MA */
2390 };
2391 };
2392
2393 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2394 /* MCLK0 */
2395 mux {
2396 pins = "gpio13";
2397 function = "cam_mclk";
2398 };
2399
2400 config {
2401 pins = "gpio13";
2402 bias-disable; /* No PULL */
2403 drive-strength = <2>; /* 2 MA */
2404 };
2405 };
2406
2407 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
2408 /* MCLK0 */
2409 mux {
2410 pins = "gpio13";
2411 function = "cam_mclk";
2412 };
2413
2414 config {
2415 pins = "gpio13";
2416 bias-pull-down; /* PULL DOWN */
2417 drive-strength = <2>; /* 2 MA */
2418 };
2419 };
2420
2421 cam_sensor_rear_active: cam_sensor_rear_active {
2422 /* RESET, AVDD LDO */
2423 mux {
2424 pins = "gpio80","gpio79";
2425 function = "gpio";
2426 };
2427
2428 config {
2429 pins = "gpio80","gpio79";
2430 bias-disable; /* No PULL */
2431 drive-strength = <2>; /* 2 MA */
2432 };
2433 };
2434
2435 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
2436 /* RESET, AVDD LDO */
2437 mux {
2438 pins = "gpio80","gpio79";
2439 function = "gpio";
2440 };
2441
2442 config {
2443 pins = "gpio80","gpio79";
2444 bias-disable; /* No PULL */
2445 drive-strength = <2>; /* 2 MA */
2446 };
2447 };
2448
2449 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
2450 /* MCLK1 */
2451 mux {
2452 pins = "gpio14";
2453 function = "cam_mclk";
2454 };
2455
2456 config {
2457 pins = "gpio14";
2458 bias-disable; /* No PULL */
2459 drive-strength = <2>; /* 2 MA */
2460 };
2461 };
2462
2463 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
2464 /* MCLK1 */
2465 mux {
2466 pins = "gpio14";
2467 function = "cam_mclk";
2468 };
2469
2470 config {
2471 pins = "gpio14";
2472 bias-pull-down; /* PULL DOWN */
2473 drive-strength = <2>; /* 2 MA */
2474 };
2475 };
2476
2477 cam_sensor_front_active: cam_sensor_front_active {
2478 /* RESET AVDD_LDO*/
2479 mux {
2480 pins = "gpio28", "gpio8";
2481 function = "gpio";
2482 };
2483
2484 config {
2485 pins = "gpio28", "gpio8";
2486 bias-disable; /* No PULL */
2487 drive-strength = <2>; /* 2 MA */
2488 };
2489 };
2490
2491 cam_sensor_front_suspend: cam_sensor_front_suspend {
2492 /* RESET */
2493 mux {
2494 pins = "gpio28";
2495 function = "gpio";
2496 };
2497
2498 config {
2499 pins = "gpio28";
2500 bias-disable; /* No PULL */
2501 drive-strength = <2>; /* 2 MA */
2502 };
2503 };
2504
2505 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
2506 /* MCLK1 */
2507 mux {
2508 /* CLK, DATA */
2509 pins = "gpio15";
2510 function = "cam_mclk";
2511 };
2512
2513 config {
2514 pins = "gpio15";
2515 bias-disable; /* No PULL */
2516 drive-strength = <2>; /* 2 MA */
2517 };
2518 };
2519
2520 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
2521 /* MCLK1 */
2522 mux {
2523 /* CLK, DATA */
2524 pins = "gpio15";
2525 function = "cam_mclk";
2526 };
2527
2528 config {
2529 pins = "gpio15";
2530 bias-pull-down; /* PULL DOWN */
2531 drive-strength = <2>; /* 2 MA */
2532 };
2533 };
2534
2535 cam_sensor_rear2_active: cam_sensor_rear2_active {
2536 /* RESET, STANDBY */
2537 mux {
2538 pins = "gpio9","gpio8";
2539 function = "gpio";
2540 };
2541
2542 config {
2543 pins = "gpio9","gpio8";
2544 bias-disable; /* No PULL */
2545 drive-strength = <2>; /* 2 MA */
2546 };
2547 };
2548
2549 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
2550 /* RESET, STANDBY */
2551 mux {
2552 pins = "gpio9","gpio8";
2553 function = "gpio";
2554 };
2555 config {
2556 pins = "gpio9","gpio8";
2557 bias-disable; /* No PULL */
2558 drive-strength = <2>; /* 2 MA */
2559 };
2560 };
Kyle Yan679cbee2016-07-27 16:55:20 -07002561 };
2562};
David Collinsc6686252017-03-31 14:23:09 -07002563
2564&pm8998_gpios {
2565 key_home {
2566 key_home_default: key_home_default {
2567 pins = "gpio5";
2568 function = "normal";
2569 input-enable;
2570 bias-pull-up;
2571 power-source = <0>;
2572 };
2573 };
2574
2575 key_vol_up {
2576 key_vol_up_default: key_vol_up_default {
2577 pins = "gpio6";
2578 function = "normal";
2579 input-enable;
2580 bias-pull-up;
2581 power-source = <0>;
2582 };
2583 };
2584
2585 key_cam_snapshot {
2586 key_cam_snapshot_default: key_cam_snapshot_default {
2587 pins = "gpio7";
2588 function = "normal";
2589 input-enable;
2590 bias-pull-up;
2591 power-source = <0>;
2592 };
2593 };
2594
2595 key_cam_focus {
2596 key_cam_focus_default: key_cam_focus_default {
2597 pins = "gpio8";
2598 function = "normal";
2599 input-enable;
2600 bias-pull-up;
2601 power-source = <0>;
2602 };
2603 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002604
2605 camera_dvdd_en {
2606 camera_dvdd_en_default: camera_dvdd_en_default {
2607 pins = "gpio9";
2608 function = "normal";
2609 power-source = <0>;
2610 output-low;
2611 };
2612 };
2613
2614 camera_rear_dvdd_en {
2615 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
2616 pins = "gpio12";
2617 function = "normal";
2618 power-source = <0>;
2619 output-low;
2620 };
2621 };
David Collinsc6686252017-03-31 14:23:09 -07002622};
Jack Phamc2160c842017-04-05 09:48:59 -07002623
2624&pmi8998_gpios {
2625 usb2_vbus_boost {
2626 usb2_vbus_boost_default: usb2_vbus_boost_default {
2627 pins = "gpio2";
2628 function = "normal";
2629 output-low;
2630 power-source = <0>;
2631 };
2632 };
2633
2634 usb2_vbus_det {
2635 usb2_vbus_det_default: usb2_vbus_det_default {
2636 pins = "gpio8";
2637 function = "normal";
2638 input-enable;
2639 bias-pull-down;
2640 power-source = <1>; /* VPH input supply */
2641 };
2642 };
2643
2644 usb2_id_det {
2645 usb2_id_det_default: usb2_id_det_default {
2646 pins = "gpio9";
2647 function = "normal";
2648 input-enable;
2649 bias-pull-up;
2650 power-source = <0>;
2651 };
2652 };
2653};