Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1 | /* SuperH Ethernet device driver |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2 | * |
Hisashi Nakamura | 966d6db | 2014-11-13 15:54:05 +0900 | [diff] [blame] | 3 | * Copyright (C) 2014 Renesas Electronics Corporation |
Nobuhiro Iwamatsu | f0e81fe | 2012-03-25 18:59:51 +0000 | [diff] [blame] | 4 | * Copyright (C) 2006-2012 Nobuhiro Iwamatsu |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 5 | * Copyright (C) 2008-2014 Renesas Solutions Corp. |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 6 | * Copyright (C) 2013-2016 Cogent Embedded, Inc. |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 7 | * Copyright (C) 2014 Codethink Limited |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms and conditions of the GNU General Public License, |
| 11 | * version 2, as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 17 | * |
| 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | */ |
| 21 | |
Yoshihiro Shimoda | 0654011 | 2011-09-29 17:16:57 +0000 | [diff] [blame] | 22 | #include <linux/module.h> |
| 23 | #include <linux/kernel.h> |
| 24 | #include <linux/spinlock.h> |
David S. Miller | 823dcd2 | 2011-08-20 10:39:12 -0700 | [diff] [blame] | 25 | #include <linux/interrupt.h> |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/etherdevice.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/mdio-bitbang.h> |
| 31 | #include <linux/netdevice.h> |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 32 | #include <linux/of.h> |
| 33 | #include <linux/of_device.h> |
| 34 | #include <linux/of_irq.h> |
| 35 | #include <linux/of_net.h> |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 36 | #include <linux/phy.h> |
| 37 | #include <linux/cache.h> |
| 38 | #include <linux/io.h> |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 39 | #include <linux/pm_runtime.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 40 | #include <linux/slab.h> |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 41 | #include <linux/ethtool.h> |
Yoshihiro Shimoda | fdb37a7 | 2012-02-06 23:55:15 +0000 | [diff] [blame] | 42 | #include <linux/if_vlan.h> |
Nobuhiro Iwamatsu | f0e81fe | 2012-03-25 18:59:51 +0000 | [diff] [blame] | 43 | #include <linux/clk.h> |
Yoshihiro Shimoda | d4fa0e3 | 2011-09-27 21:49:12 +0000 | [diff] [blame] | 44 | #include <linux/sh_eth.h> |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 45 | #include <linux/of_mdio.h> |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 46 | |
| 47 | #include "sh_eth.h" |
| 48 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 49 | #define SH_ETH_DEF_MSG_ENABLE \ |
| 50 | (NETIF_MSG_LINK | \ |
| 51 | NETIF_MSG_TIMER | \ |
| 52 | NETIF_MSG_RX_ERR| \ |
| 53 | NETIF_MSG_TX_ERR) |
| 54 | |
Sergei Shtylyov | 2274d37 | 2015-12-13 01:44:50 +0300 | [diff] [blame] | 55 | #define SH_ETH_OFFSET_INVALID ((u16)~0) |
| 56 | |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 57 | #define SH_ETH_OFFSET_DEFAULTS \ |
| 58 | [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID |
| 59 | |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 60 | static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 61 | SH_ETH_OFFSET_DEFAULTS, |
| 62 | |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 63 | [EDSR] = 0x0000, |
| 64 | [EDMR] = 0x0400, |
| 65 | [EDTRR] = 0x0408, |
| 66 | [EDRRR] = 0x0410, |
| 67 | [EESR] = 0x0428, |
| 68 | [EESIPR] = 0x0430, |
| 69 | [TDLAR] = 0x0010, |
| 70 | [TDFAR] = 0x0014, |
| 71 | [TDFXR] = 0x0018, |
| 72 | [TDFFR] = 0x001c, |
| 73 | [RDLAR] = 0x0030, |
| 74 | [RDFAR] = 0x0034, |
| 75 | [RDFXR] = 0x0038, |
| 76 | [RDFFR] = 0x003c, |
| 77 | [TRSCER] = 0x0438, |
| 78 | [RMFCR] = 0x0440, |
| 79 | [TFTR] = 0x0448, |
| 80 | [FDR] = 0x0450, |
| 81 | [RMCR] = 0x0458, |
| 82 | [RPADIR] = 0x0460, |
| 83 | [FCFTR] = 0x0468, |
| 84 | [CSMR] = 0x04E4, |
| 85 | |
| 86 | [ECMR] = 0x0500, |
| 87 | [ECSR] = 0x0510, |
| 88 | [ECSIPR] = 0x0518, |
| 89 | [PIR] = 0x0520, |
| 90 | [PSR] = 0x0528, |
| 91 | [PIPR] = 0x052c, |
| 92 | [RFLR] = 0x0508, |
| 93 | [APR] = 0x0554, |
| 94 | [MPR] = 0x0558, |
| 95 | [PFTCR] = 0x055c, |
| 96 | [PFRCR] = 0x0560, |
| 97 | [TPAUSER] = 0x0564, |
| 98 | [GECMR] = 0x05b0, |
| 99 | [BCULR] = 0x05b4, |
| 100 | [MAHR] = 0x05c0, |
| 101 | [MALR] = 0x05c8, |
| 102 | [TROCR] = 0x0700, |
| 103 | [CDCR] = 0x0708, |
| 104 | [LCCR] = 0x0710, |
| 105 | [CEFCR] = 0x0740, |
| 106 | [FRECR] = 0x0748, |
| 107 | [TSFRCR] = 0x0750, |
| 108 | [TLFRCR] = 0x0758, |
| 109 | [RFCR] = 0x0760, |
| 110 | [CERCR] = 0x0768, |
| 111 | [CEECR] = 0x0770, |
| 112 | [MAFCR] = 0x0778, |
| 113 | [RMII_MII] = 0x0790, |
| 114 | |
| 115 | [ARSTR] = 0x0000, |
| 116 | [TSU_CTRST] = 0x0004, |
| 117 | [TSU_FWEN0] = 0x0010, |
| 118 | [TSU_FWEN1] = 0x0014, |
| 119 | [TSU_FCM] = 0x0018, |
| 120 | [TSU_BSYSL0] = 0x0020, |
| 121 | [TSU_BSYSL1] = 0x0024, |
| 122 | [TSU_PRISL0] = 0x0028, |
| 123 | [TSU_PRISL1] = 0x002c, |
| 124 | [TSU_FWSL0] = 0x0030, |
| 125 | [TSU_FWSL1] = 0x0034, |
| 126 | [TSU_FWSLC] = 0x0038, |
| 127 | [TSU_QTAG0] = 0x0040, |
| 128 | [TSU_QTAG1] = 0x0044, |
| 129 | [TSU_FWSR] = 0x0050, |
| 130 | [TSU_FWINMK] = 0x0054, |
| 131 | [TSU_ADQT0] = 0x0048, |
| 132 | [TSU_ADQT1] = 0x004c, |
| 133 | [TSU_VTAG0] = 0x0058, |
| 134 | [TSU_VTAG1] = 0x005c, |
| 135 | [TSU_ADSBSY] = 0x0060, |
| 136 | [TSU_TEN] = 0x0064, |
| 137 | [TSU_POST1] = 0x0070, |
| 138 | [TSU_POST2] = 0x0074, |
| 139 | [TSU_POST3] = 0x0078, |
| 140 | [TSU_POST4] = 0x007c, |
| 141 | [TSU_ADRH0] = 0x0100, |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 142 | |
| 143 | [TXNLCR0] = 0x0080, |
| 144 | [TXALCR0] = 0x0084, |
| 145 | [RXNLCR0] = 0x0088, |
| 146 | [RXALCR0] = 0x008c, |
| 147 | [FWNLCR0] = 0x0090, |
| 148 | [FWALCR0] = 0x0094, |
| 149 | [TXNLCR1] = 0x00a0, |
| 150 | [TXALCR1] = 0x00a0, |
| 151 | [RXNLCR1] = 0x00a8, |
| 152 | [RXALCR1] = 0x00ac, |
| 153 | [FWNLCR1] = 0x00b0, |
| 154 | [FWALCR1] = 0x00b4, |
| 155 | }; |
| 156 | |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 157 | static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 158 | SH_ETH_OFFSET_DEFAULTS, |
| 159 | |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 160 | [EDSR] = 0x0000, |
| 161 | [EDMR] = 0x0400, |
| 162 | [EDTRR] = 0x0408, |
| 163 | [EDRRR] = 0x0410, |
| 164 | [EESR] = 0x0428, |
| 165 | [EESIPR] = 0x0430, |
| 166 | [TDLAR] = 0x0010, |
| 167 | [TDFAR] = 0x0014, |
| 168 | [TDFXR] = 0x0018, |
| 169 | [TDFFR] = 0x001c, |
| 170 | [RDLAR] = 0x0030, |
| 171 | [RDFAR] = 0x0034, |
| 172 | [RDFXR] = 0x0038, |
| 173 | [RDFFR] = 0x003c, |
| 174 | [TRSCER] = 0x0438, |
| 175 | [RMFCR] = 0x0440, |
| 176 | [TFTR] = 0x0448, |
| 177 | [FDR] = 0x0450, |
| 178 | [RMCR] = 0x0458, |
| 179 | [RPADIR] = 0x0460, |
| 180 | [FCFTR] = 0x0468, |
| 181 | [CSMR] = 0x04E4, |
| 182 | |
| 183 | [ECMR] = 0x0500, |
| 184 | [RFLR] = 0x0508, |
| 185 | [ECSR] = 0x0510, |
| 186 | [ECSIPR] = 0x0518, |
| 187 | [PIR] = 0x0520, |
| 188 | [APR] = 0x0554, |
| 189 | [MPR] = 0x0558, |
| 190 | [PFTCR] = 0x055c, |
| 191 | [PFRCR] = 0x0560, |
| 192 | [TPAUSER] = 0x0564, |
| 193 | [MAHR] = 0x05c0, |
| 194 | [MALR] = 0x05c8, |
| 195 | [CEFCR] = 0x0740, |
| 196 | [FRECR] = 0x0748, |
| 197 | [TSFRCR] = 0x0750, |
| 198 | [TLFRCR] = 0x0758, |
| 199 | [RFCR] = 0x0760, |
| 200 | [MAFCR] = 0x0778, |
| 201 | |
| 202 | [ARSTR] = 0x0000, |
| 203 | [TSU_CTRST] = 0x0004, |
Chris Brandt | e148788 | 2016-09-07 14:57:09 -0400 | [diff] [blame] | 204 | [TSU_FWSLC] = 0x0038, |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 205 | [TSU_VTAG0] = 0x0058, |
| 206 | [TSU_ADSBSY] = 0x0060, |
| 207 | [TSU_TEN] = 0x0064, |
Chris Brandt | e148788 | 2016-09-07 14:57:09 -0400 | [diff] [blame] | 208 | [TSU_POST1] = 0x0070, |
| 209 | [TSU_POST2] = 0x0074, |
| 210 | [TSU_POST3] = 0x0078, |
| 211 | [TSU_POST4] = 0x007c, |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 212 | [TSU_ADRH0] = 0x0100, |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 213 | |
| 214 | [TXNLCR0] = 0x0080, |
| 215 | [TXALCR0] = 0x0084, |
| 216 | [RXNLCR0] = 0x0088, |
| 217 | [RXALCR0] = 0x008C, |
| 218 | }; |
| 219 | |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 220 | static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 221 | SH_ETH_OFFSET_DEFAULTS, |
| 222 | |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 223 | [ECMR] = 0x0300, |
| 224 | [RFLR] = 0x0308, |
| 225 | [ECSR] = 0x0310, |
| 226 | [ECSIPR] = 0x0318, |
| 227 | [PIR] = 0x0320, |
| 228 | [PSR] = 0x0328, |
| 229 | [RDMLR] = 0x0340, |
| 230 | [IPGR] = 0x0350, |
| 231 | [APR] = 0x0354, |
| 232 | [MPR] = 0x0358, |
| 233 | [RFCF] = 0x0360, |
| 234 | [TPAUSER] = 0x0364, |
| 235 | [TPAUSECR] = 0x0368, |
| 236 | [MAHR] = 0x03c0, |
| 237 | [MALR] = 0x03c8, |
| 238 | [TROCR] = 0x03d0, |
| 239 | [CDCR] = 0x03d4, |
| 240 | [LCCR] = 0x03d8, |
| 241 | [CNDCR] = 0x03dc, |
| 242 | [CEFCR] = 0x03e4, |
| 243 | [FRECR] = 0x03e8, |
| 244 | [TSFRCR] = 0x03ec, |
| 245 | [TLFRCR] = 0x03f0, |
| 246 | [RFCR] = 0x03f4, |
| 247 | [MAFCR] = 0x03f8, |
| 248 | |
| 249 | [EDMR] = 0x0200, |
| 250 | [EDTRR] = 0x0208, |
| 251 | [EDRRR] = 0x0210, |
| 252 | [TDLAR] = 0x0218, |
| 253 | [RDLAR] = 0x0220, |
| 254 | [EESR] = 0x0228, |
| 255 | [EESIPR] = 0x0230, |
| 256 | [TRSCER] = 0x0238, |
| 257 | [RMFCR] = 0x0240, |
| 258 | [TFTR] = 0x0248, |
| 259 | [FDR] = 0x0250, |
| 260 | [RMCR] = 0x0258, |
| 261 | [TFUCR] = 0x0264, |
| 262 | [RFOCR] = 0x0268, |
Simon Horman | 55754f1 | 2013-07-23 10:18:04 +0900 | [diff] [blame] | 263 | [RMIIMODE] = 0x026c, |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 264 | [FCFTR] = 0x0270, |
| 265 | [TRIMD] = 0x027c, |
| 266 | }; |
| 267 | |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 268 | static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 269 | SH_ETH_OFFSET_DEFAULTS, |
| 270 | |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 271 | [ECMR] = 0x0100, |
| 272 | [RFLR] = 0x0108, |
| 273 | [ECSR] = 0x0110, |
| 274 | [ECSIPR] = 0x0118, |
| 275 | [PIR] = 0x0120, |
| 276 | [PSR] = 0x0128, |
| 277 | [RDMLR] = 0x0140, |
| 278 | [IPGR] = 0x0150, |
| 279 | [APR] = 0x0154, |
| 280 | [MPR] = 0x0158, |
| 281 | [TPAUSER] = 0x0164, |
| 282 | [RFCF] = 0x0160, |
| 283 | [TPAUSECR] = 0x0168, |
| 284 | [BCFRR] = 0x016c, |
| 285 | [MAHR] = 0x01c0, |
| 286 | [MALR] = 0x01c8, |
| 287 | [TROCR] = 0x01d0, |
| 288 | [CDCR] = 0x01d4, |
| 289 | [LCCR] = 0x01d8, |
| 290 | [CNDCR] = 0x01dc, |
| 291 | [CEFCR] = 0x01e4, |
| 292 | [FRECR] = 0x01e8, |
| 293 | [TSFRCR] = 0x01ec, |
| 294 | [TLFRCR] = 0x01f0, |
| 295 | [RFCR] = 0x01f4, |
| 296 | [MAFCR] = 0x01f8, |
| 297 | [RTRATE] = 0x01fc, |
| 298 | |
| 299 | [EDMR] = 0x0000, |
| 300 | [EDTRR] = 0x0008, |
| 301 | [EDRRR] = 0x0010, |
| 302 | [TDLAR] = 0x0018, |
| 303 | [RDLAR] = 0x0020, |
| 304 | [EESR] = 0x0028, |
| 305 | [EESIPR] = 0x0030, |
| 306 | [TRSCER] = 0x0038, |
| 307 | [RMFCR] = 0x0040, |
| 308 | [TFTR] = 0x0048, |
| 309 | [FDR] = 0x0050, |
| 310 | [RMCR] = 0x0058, |
| 311 | [TFUCR] = 0x0064, |
| 312 | [RFOCR] = 0x0068, |
| 313 | [FCFTR] = 0x0070, |
| 314 | [RPADIR] = 0x0078, |
| 315 | [TRIMD] = 0x007c, |
| 316 | [RBWAR] = 0x00c8, |
| 317 | [RDFAR] = 0x00cc, |
| 318 | [TBRAR] = 0x00d4, |
| 319 | [TDFAR] = 0x00d8, |
| 320 | }; |
| 321 | |
| 322 | static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 323 | SH_ETH_OFFSET_DEFAULTS, |
| 324 | |
Sergei Shtylyov | d8b0426 | 2014-06-03 23:42:26 +0400 | [diff] [blame] | 325 | [EDMR] = 0x0000, |
| 326 | [EDTRR] = 0x0004, |
| 327 | [EDRRR] = 0x0008, |
| 328 | [TDLAR] = 0x000c, |
| 329 | [RDLAR] = 0x0010, |
| 330 | [EESR] = 0x0014, |
| 331 | [EESIPR] = 0x0018, |
| 332 | [TRSCER] = 0x001c, |
| 333 | [RMFCR] = 0x0020, |
| 334 | [TFTR] = 0x0024, |
| 335 | [FDR] = 0x0028, |
| 336 | [RMCR] = 0x002c, |
| 337 | [EDOCR] = 0x0030, |
| 338 | [FCFTR] = 0x0034, |
| 339 | [RPADIR] = 0x0038, |
| 340 | [TRIMD] = 0x003c, |
| 341 | [RBWAR] = 0x0040, |
| 342 | [RDFAR] = 0x0044, |
| 343 | [TBRAR] = 0x004c, |
| 344 | [TDFAR] = 0x0050, |
| 345 | |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 346 | [ECMR] = 0x0160, |
| 347 | [ECSR] = 0x0164, |
| 348 | [ECSIPR] = 0x0168, |
| 349 | [PIR] = 0x016c, |
| 350 | [MAHR] = 0x0170, |
| 351 | [MALR] = 0x0174, |
| 352 | [RFLR] = 0x0178, |
| 353 | [PSR] = 0x017c, |
| 354 | [TROCR] = 0x0180, |
| 355 | [CDCR] = 0x0184, |
| 356 | [LCCR] = 0x0188, |
| 357 | [CNDCR] = 0x018c, |
| 358 | [CEFCR] = 0x0194, |
| 359 | [FRECR] = 0x0198, |
| 360 | [TSFRCR] = 0x019c, |
| 361 | [TLFRCR] = 0x01a0, |
| 362 | [RFCR] = 0x01a4, |
| 363 | [MAFCR] = 0x01a8, |
| 364 | [IPGR] = 0x01b4, |
| 365 | [APR] = 0x01b8, |
| 366 | [MPR] = 0x01bc, |
| 367 | [TPAUSER] = 0x01c4, |
| 368 | [BCFR] = 0x01cc, |
| 369 | |
| 370 | [ARSTR] = 0x0000, |
| 371 | [TSU_CTRST] = 0x0004, |
| 372 | [TSU_FWEN0] = 0x0010, |
| 373 | [TSU_FWEN1] = 0x0014, |
| 374 | [TSU_FCM] = 0x0018, |
| 375 | [TSU_BSYSL0] = 0x0020, |
| 376 | [TSU_BSYSL1] = 0x0024, |
| 377 | [TSU_PRISL0] = 0x0028, |
| 378 | [TSU_PRISL1] = 0x002c, |
| 379 | [TSU_FWSL0] = 0x0030, |
| 380 | [TSU_FWSL1] = 0x0034, |
| 381 | [TSU_FWSLC] = 0x0038, |
| 382 | [TSU_QTAGM0] = 0x0040, |
| 383 | [TSU_QTAGM1] = 0x0044, |
| 384 | [TSU_ADQT0] = 0x0048, |
| 385 | [TSU_ADQT1] = 0x004c, |
| 386 | [TSU_FWSR] = 0x0050, |
| 387 | [TSU_FWINMK] = 0x0054, |
| 388 | [TSU_ADSBSY] = 0x0060, |
| 389 | [TSU_TEN] = 0x0064, |
| 390 | [TSU_POST1] = 0x0070, |
| 391 | [TSU_POST2] = 0x0074, |
| 392 | [TSU_POST3] = 0x0078, |
| 393 | [TSU_POST4] = 0x007c, |
| 394 | |
| 395 | [TXNLCR0] = 0x0080, |
| 396 | [TXALCR0] = 0x0084, |
| 397 | [RXNLCR0] = 0x0088, |
| 398 | [RXALCR0] = 0x008c, |
| 399 | [FWNLCR0] = 0x0090, |
| 400 | [FWALCR0] = 0x0094, |
| 401 | [TXNLCR1] = 0x00a0, |
| 402 | [TXALCR1] = 0x00a0, |
| 403 | [RXNLCR1] = 0x00a8, |
| 404 | [RXALCR1] = 0x00ac, |
| 405 | [FWNLCR1] = 0x00b0, |
| 406 | [FWALCR1] = 0x00b4, |
| 407 | |
| 408 | [TSU_ADRH0] = 0x0100, |
Sergei Shtylyov | c0013f6 | 2013-03-28 11:48:26 +0000 | [diff] [blame] | 409 | }; |
| 410 | |
Ben Hutchings | 740c7f3 | 2015-01-27 00:49:32 +0000 | [diff] [blame] | 411 | static void sh_eth_rcv_snd_disable(struct net_device *ndev); |
| 412 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); |
| 413 | |
Sergei Shtylyov | 2274d37 | 2015-12-13 01:44:50 +0300 | [diff] [blame] | 414 | static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) |
| 415 | { |
| 416 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 417 | u16 offset = mdp->reg_offset[enum_index]; |
| 418 | |
| 419 | if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) |
| 420 | return; |
| 421 | |
| 422 | iowrite32(data, mdp->addr + offset); |
| 423 | } |
| 424 | |
| 425 | static u32 sh_eth_read(struct net_device *ndev, int enum_index) |
| 426 | { |
| 427 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 428 | u16 offset = mdp->reg_offset[enum_index]; |
| 429 | |
| 430 | if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) |
| 431 | return ~0U; |
| 432 | |
| 433 | return ioread32(mdp->addr + offset); |
| 434 | } |
| 435 | |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 436 | static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, |
| 437 | u32 set) |
| 438 | { |
| 439 | sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, |
| 440 | enum_index); |
| 441 | } |
| 442 | |
Simon Horman | 504c8ca | 2014-01-17 09:22:27 +0900 | [diff] [blame] | 443 | static bool sh_eth_is_gether(struct sh_eth_private *mdp) |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 444 | { |
Simon Horman | 504c8ca | 2014-01-17 09:22:27 +0900 | [diff] [blame] | 445 | return mdp->reg_offset == sh_eth_offset_gigabit; |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 446 | } |
| 447 | |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 448 | static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) |
| 449 | { |
| 450 | return mdp->reg_offset == sh_eth_offset_fast_rz; |
| 451 | } |
| 452 | |
Sergei Shtylyov | 8e99440 | 2013-06-12 03:07:29 +0400 | [diff] [blame] | 453 | static void sh_eth_select_mii(struct net_device *ndev) |
Nobuhiro Iwamatsu | 5e7a76b | 2012-06-25 17:34:14 +0000 | [diff] [blame] | 454 | { |
Nobuhiro Iwamatsu | 5e7a76b | 2012-06-25 17:34:14 +0000 | [diff] [blame] | 455 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Sergei Shtylyov | 4fa8c3c | 2016-03-13 01:29:45 +0300 | [diff] [blame] | 456 | u32 value; |
Nobuhiro Iwamatsu | 5e7a76b | 2012-06-25 17:34:14 +0000 | [diff] [blame] | 457 | |
| 458 | switch (mdp->phy_interface) { |
| 459 | case PHY_INTERFACE_MODE_GMII: |
| 460 | value = 0x2; |
| 461 | break; |
| 462 | case PHY_INTERFACE_MODE_MII: |
| 463 | value = 0x1; |
| 464 | break; |
| 465 | case PHY_INTERFACE_MODE_RMII: |
| 466 | value = 0x0; |
| 467 | break; |
| 468 | default: |
Sergei Shtylyov | f75f14e | 2014-03-15 03:27:54 +0300 | [diff] [blame] | 469 | netdev_warn(ndev, |
| 470 | "PHY interface mode was not setup. Set to MII.\n"); |
Nobuhiro Iwamatsu | 5e7a76b | 2012-06-25 17:34:14 +0000 | [diff] [blame] | 471 | value = 0x1; |
| 472 | break; |
| 473 | } |
| 474 | |
| 475 | sh_eth_write(ndev, value, RMII_MII); |
| 476 | } |
Nobuhiro Iwamatsu | 5e7a76b | 2012-06-25 17:34:14 +0000 | [diff] [blame] | 477 | |
Sergei Shtylyov | 8e99440 | 2013-06-12 03:07:29 +0400 | [diff] [blame] | 478 | static void sh_eth_set_duplex(struct net_device *ndev) |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 479 | { |
| 480 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 481 | |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 482 | sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 483 | } |
| 484 | |
Geert Uytterhoeven | 99f84be | 2015-11-24 15:40:57 +0100 | [diff] [blame] | 485 | static void sh_eth_chip_reset(struct net_device *ndev) |
| 486 | { |
| 487 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 488 | |
| 489 | /* reset device */ |
Sergei Shtylyov | ec65cfc | 2016-04-24 23:46:15 +0300 | [diff] [blame] | 490 | sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); |
Geert Uytterhoeven | 99f84be | 2015-11-24 15:40:57 +0100 | [diff] [blame] | 491 | mdelay(1); |
| 492 | } |
| 493 | |
Geert Uytterhoeven | a0f48be | 2015-11-24 15:40:59 +0100 | [diff] [blame] | 494 | static void sh_eth_set_rate_gether(struct net_device *ndev) |
| 495 | { |
| 496 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 497 | |
| 498 | switch (mdp->speed) { |
| 499 | case 10: /* 10BASE */ |
| 500 | sh_eth_write(ndev, GECMR_10, GECMR); |
| 501 | break; |
| 502 | case 100:/* 100BASE */ |
| 503 | sh_eth_write(ndev, GECMR_100, GECMR); |
| 504 | break; |
| 505 | case 1000: /* 1000BASE */ |
| 506 | sh_eth_write(ndev, GECMR_1000, GECMR); |
| 507 | break; |
Geert Uytterhoeven | a0f48be | 2015-11-24 15:40:59 +0100 | [diff] [blame] | 508 | } |
| 509 | } |
| 510 | |
Geert Uytterhoeven | 99f84be | 2015-11-24 15:40:57 +0100 | [diff] [blame] | 511 | #ifdef CONFIG_OF |
| 512 | /* R7S72100 */ |
| 513 | static struct sh_eth_cpu_data r7s72100_data = { |
| 514 | .chip_reset = sh_eth_chip_reset, |
| 515 | .set_duplex = sh_eth_set_duplex, |
| 516 | |
| 517 | .register_type = SH_ETH_REG_FAST_RZ, |
| 518 | |
| 519 | .ecsr_value = ECSR_ICD, |
| 520 | .ecsipr_value = ECSIPR_ICDIP, |
Chris Brandt | 33d446d | 2016-12-01 13:32:14 -0500 | [diff] [blame] | 521 | .eesipr_value = 0xe77f009f, |
Geert Uytterhoeven | 99f84be | 2015-11-24 15:40:57 +0100 | [diff] [blame] | 522 | |
| 523 | .tx_check = EESR_TC1 | EESR_FTC, |
| 524 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
| 525 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | |
| 526 | EESR_TDE | EESR_ECI, |
| 527 | .fdr_value = 0x0000070f, |
| 528 | |
| 529 | .no_psr = 1, |
| 530 | .apr = 1, |
| 531 | .mpr = 1, |
| 532 | .tpauser = 1, |
| 533 | .hw_swap = 1, |
| 534 | .rpadir = 1, |
| 535 | .rpadir_value = 2 << 16, |
| 536 | .no_trimd = 1, |
| 537 | .no_ade = 1, |
| 538 | .hw_crc = 1, |
| 539 | .tsu = 1, |
| 540 | .shift_rd0 = 1, |
| 541 | }; |
Geert Uytterhoeven | a0f48be | 2015-11-24 15:40:59 +0100 | [diff] [blame] | 542 | |
| 543 | static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) |
| 544 | { |
Sergei Shtylyov | c66b258 | 2016-05-07 14:09:01 -0700 | [diff] [blame] | 545 | sh_eth_chip_reset(ndev); |
Geert Uytterhoeven | a0f48be | 2015-11-24 15:40:59 +0100 | [diff] [blame] | 546 | |
| 547 | sh_eth_select_mii(ndev); |
| 548 | } |
| 549 | |
| 550 | /* R8A7740 */ |
| 551 | static struct sh_eth_cpu_data r8a7740_data = { |
| 552 | .chip_reset = sh_eth_chip_reset_r8a7740, |
| 553 | .set_duplex = sh_eth_set_duplex, |
| 554 | .set_rate = sh_eth_set_rate_gether, |
| 555 | |
| 556 | .register_type = SH_ETH_REG_GIGABIT, |
| 557 | |
| 558 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
| 559 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| 560 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| 561 | |
| 562 | .tx_check = EESR_TC1 | EESR_FTC, |
| 563 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
| 564 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | |
| 565 | EESR_TDE | EESR_ECI, |
| 566 | .fdr_value = 0x0000070f, |
| 567 | |
| 568 | .apr = 1, |
| 569 | .mpr = 1, |
| 570 | .tpauser = 1, |
| 571 | .bculr = 1, |
| 572 | .hw_swap = 1, |
| 573 | .rpadir = 1, |
| 574 | .rpadir_value = 2 << 16, |
| 575 | .no_trimd = 1, |
| 576 | .no_ade = 1, |
Sergei Shtylyov | bfe384e | 2017-01-05 00:29:32 +0300 | [diff] [blame] | 577 | .hw_crc = 1, |
Geert Uytterhoeven | a0f48be | 2015-11-24 15:40:59 +0100 | [diff] [blame] | 578 | .tsu = 1, |
| 579 | .select_mii = 1, |
| 580 | .shift_rd0 = 1, |
| 581 | }; |
Geert Uytterhoeven | 99f84be | 2015-11-24 15:40:57 +0100 | [diff] [blame] | 582 | |
Nobuhiro Iwamatsu | 04b0ed2 | 2013-06-06 09:45:25 +0000 | [diff] [blame] | 583 | /* There is CPU dependent code */ |
Sergei Shtylyov | 589ebde | 2013-06-07 14:05:59 +0000 | [diff] [blame] | 584 | static void sh_eth_set_rate_r8a777x(struct net_device *ndev) |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 585 | { |
| 586 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 587 | |
| 588 | switch (mdp->speed) { |
| 589 | case 10: /* 10BASE */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 590 | sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 591 | break; |
| 592 | case 100:/* 100BASE */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 593 | sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 594 | break; |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 595 | } |
| 596 | } |
| 597 | |
Sergei Shtylyov | 674853b | 2013-04-27 10:44:24 +0000 | [diff] [blame] | 598 | /* R8A7778/9 */ |
Sergei Shtylyov | 589ebde | 2013-06-07 14:05:59 +0000 | [diff] [blame] | 599 | static struct sh_eth_cpu_data r8a777x_data = { |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 600 | .set_duplex = sh_eth_set_duplex, |
Sergei Shtylyov | 589ebde | 2013-06-07 14:05:59 +0000 | [diff] [blame] | 601 | .set_rate = sh_eth_set_rate_r8a777x, |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 602 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 603 | .register_type = SH_ETH_REG_FAST_RCAR, |
| 604 | |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 605 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
| 606 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, |
| 607 | .eesipr_value = 0x01ff009f, |
| 608 | |
| 609 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, |
Sergei Shtylyov | ca8c358 | 2013-06-21 01:12:21 +0400 | [diff] [blame] | 610 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
| 611 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | |
| 612 | EESR_ECI, |
Nobuhiro Iwamatsu | d407bc0 | 2015-01-07 14:40:15 +0900 | [diff] [blame] | 613 | .fdr_value = 0x00000f0f, |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 614 | |
| 615 | .apr = 1, |
| 616 | .mpr = 1, |
| 617 | .tpauser = 1, |
| 618 | .hw_swap = 1, |
| 619 | }; |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 620 | |
Sergei Shtylyov | 94a12b1 | 2013-12-08 02:59:18 +0300 | [diff] [blame] | 621 | /* R8A7790/1 */ |
| 622 | static struct sh_eth_cpu_data r8a779x_data = { |
Simon Horman | e18dbf7 | 2013-07-23 10:18:05 +0900 | [diff] [blame] | 623 | .set_duplex = sh_eth_set_duplex, |
| 624 | .set_rate = sh_eth_set_rate_r8a777x, |
| 625 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 626 | .register_type = SH_ETH_REG_FAST_RCAR, |
| 627 | |
Simon Horman | e18dbf7 | 2013-07-23 10:18:05 +0900 | [diff] [blame] | 628 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
| 629 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, |
| 630 | .eesipr_value = 0x01ff009f, |
| 631 | |
| 632 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, |
Laurent Pinchart | ba361cb | 2013-07-31 16:42:11 +0900 | [diff] [blame] | 633 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
| 634 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | |
| 635 | EESR_ECI, |
Nobuhiro Iwamatsu | d407bc0 | 2015-01-07 14:40:15 +0900 | [diff] [blame] | 636 | .fdr_value = 0x00000f0f, |
Simon Horman | e18dbf7 | 2013-07-23 10:18:05 +0900 | [diff] [blame] | 637 | |
Geert Uytterhoeven | 01fbd3f | 2015-01-15 11:52:19 +0100 | [diff] [blame] | 638 | .trscer_err_mask = DESC_I_RINT8, |
| 639 | |
Simon Horman | e18dbf7 | 2013-07-23 10:18:05 +0900 | [diff] [blame] | 640 | .apr = 1, |
| 641 | .mpr = 1, |
| 642 | .tpauser = 1, |
| 643 | .hw_swap = 1, |
| 644 | .rmiimode = 1, |
| 645 | }; |
Geert Uytterhoeven | c74a224 | 2015-11-24 15:40:58 +0100 | [diff] [blame] | 646 | #endif /* CONFIG_OF */ |
Simon Horman | e18dbf7 | 2013-07-23 10:18:05 +0900 | [diff] [blame] | 647 | |
Sergei Shtylyov | 9c3beaa | 2013-06-07 14:03:37 +0000 | [diff] [blame] | 648 | static void sh_eth_set_rate_sh7724(struct net_device *ndev) |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 649 | { |
| 650 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 651 | |
| 652 | switch (mdp->speed) { |
| 653 | case 10: /* 10BASE */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 654 | sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 655 | break; |
| 656 | case 100:/* 100BASE */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 657 | sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 658 | break; |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 659 | } |
| 660 | } |
| 661 | |
| 662 | /* SH7724 */ |
Sergei Shtylyov | 9c3beaa | 2013-06-07 14:03:37 +0000 | [diff] [blame] | 663 | static struct sh_eth_cpu_data sh7724_data = { |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 664 | .set_duplex = sh_eth_set_duplex, |
Sergei Shtylyov | 9c3beaa | 2013-06-07 14:03:37 +0000 | [diff] [blame] | 665 | .set_rate = sh_eth_set_rate_sh7724, |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 666 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 667 | .register_type = SH_ETH_REG_FAST_SH4, |
| 668 | |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 669 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
| 670 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, |
Sergei Shtylyov | a80c3de | 2013-06-20 02:24:54 +0400 | [diff] [blame] | 671 | .eesipr_value = 0x01ff009f, |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 672 | |
| 673 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, |
Sergei Shtylyov | ca8c358 | 2013-06-21 01:12:21 +0400 | [diff] [blame] | 674 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
| 675 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | |
| 676 | EESR_ECI, |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 677 | |
| 678 | .apr = 1, |
| 679 | .mpr = 1, |
| 680 | .tpauser = 1, |
| 681 | .hw_swap = 1, |
Magnus Damm | 503914c | 2009-12-15 21:16:55 -0800 | [diff] [blame] | 682 | .rpadir = 1, |
| 683 | .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 684 | }; |
Nobuhiro Iwamatsu | 5cee1d3 | 2012-06-25 17:35:12 +0000 | [diff] [blame] | 685 | |
Sergei Shtylyov | 24549e2 | 2013-06-07 13:59:21 +0000 | [diff] [blame] | 686 | static void sh_eth_set_rate_sh7757(struct net_device *ndev) |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 687 | { |
| 688 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 689 | |
| 690 | switch (mdp->speed) { |
| 691 | case 10: /* 10BASE */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 692 | sh_eth_write(ndev, 0, RTRATE); |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 693 | break; |
| 694 | case 100:/* 100BASE */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 695 | sh_eth_write(ndev, 1, RTRATE); |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 696 | break; |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 697 | } |
| 698 | } |
| 699 | |
| 700 | /* SH7757 */ |
Sergei Shtylyov | 24549e2 | 2013-06-07 13:59:21 +0000 | [diff] [blame] | 701 | static struct sh_eth_cpu_data sh7757_data = { |
| 702 | .set_duplex = sh_eth_set_duplex, |
| 703 | .set_rate = sh_eth_set_rate_sh7757, |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 704 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 705 | .register_type = SH_ETH_REG_FAST_SH4, |
| 706 | |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 707 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 708 | |
| 709 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, |
Sergei Shtylyov | ca8c358 | 2013-06-21 01:12:21 +0400 | [diff] [blame] | 710 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
| 711 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | |
| 712 | EESR_ECI, |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 713 | |
Nobuhiro Iwamatsu | 5b3dfd1 | 2013-06-06 09:49:30 +0000 | [diff] [blame] | 714 | .irq_flags = IRQF_SHARED, |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 715 | .apr = 1, |
| 716 | .mpr = 1, |
| 717 | .tpauser = 1, |
| 718 | .hw_swap = 1, |
| 719 | .no_ade = 1, |
Yoshihiro Shimoda | 2e98e79 | 2011-07-05 20:33:57 +0000 | [diff] [blame] | 720 | .rpadir = 1, |
| 721 | .rpadir_value = 2 << 16, |
Ben Hutchings | 6b4b4fe | 2015-02-26 20:34:35 +0000 | [diff] [blame] | 722 | .rtrate = 1, |
Yoshihiro Shimoda | f29a3d0 | 2010-07-05 18:32:50 +0000 | [diff] [blame] | 723 | }; |
Yoshihiro Shimoda | 65ac885 | 2009-05-24 23:54:30 +0000 | [diff] [blame] | 724 | |
David S. Miller | e403d29 | 2013-06-07 23:40:41 -0700 | [diff] [blame] | 725 | #define SH_GIGA_ETH_BASE 0xfee00000UL |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 726 | #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) |
| 727 | #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) |
| 728 | static void sh_eth_chip_reset_giga(struct net_device *ndev) |
| 729 | { |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 730 | u32 mahr[2], malr[2]; |
Sergei Shtylyov | 7927092 | 2016-05-08 00:08:05 +0300 | [diff] [blame] | 731 | int i; |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 732 | |
| 733 | /* save MAHR and MALR */ |
| 734 | for (i = 0; i < 2; i++) { |
Yoshihiro Shimoda | ae70644 | 2011-09-27 21:48:58 +0000 | [diff] [blame] | 735 | malr[i] = ioread32((void *)GIGA_MALR(i)); |
| 736 | mahr[i] = ioread32((void *)GIGA_MAHR(i)); |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 737 | } |
| 738 | |
Sergei Shtylyov | c66b258 | 2016-05-07 14:09:01 -0700 | [diff] [blame] | 739 | sh_eth_chip_reset(ndev); |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 740 | |
| 741 | /* restore MAHR and MALR */ |
| 742 | for (i = 0; i < 2; i++) { |
Yoshihiro Shimoda | ae70644 | 2011-09-27 21:48:58 +0000 | [diff] [blame] | 743 | iowrite32(malr[i], (void *)GIGA_MALR(i)); |
| 744 | iowrite32(mahr[i], (void *)GIGA_MAHR(i)); |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 745 | } |
| 746 | } |
| 747 | |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 748 | static void sh_eth_set_rate_giga(struct net_device *ndev) |
| 749 | { |
| 750 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 751 | |
| 752 | switch (mdp->speed) { |
| 753 | case 10: /* 10BASE */ |
| 754 | sh_eth_write(ndev, 0x00000000, GECMR); |
| 755 | break; |
| 756 | case 100:/* 100BASE */ |
| 757 | sh_eth_write(ndev, 0x00000010, GECMR); |
| 758 | break; |
| 759 | case 1000: /* 1000BASE */ |
| 760 | sh_eth_write(ndev, 0x00000020, GECMR); |
| 761 | break; |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 762 | } |
| 763 | } |
| 764 | |
| 765 | /* SH7757(GETHERC) */ |
Sergei Shtylyov | 24549e2 | 2013-06-07 13:59:21 +0000 | [diff] [blame] | 766 | static struct sh_eth_cpu_data sh7757_data_giga = { |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 767 | .chip_reset = sh_eth_chip_reset_giga, |
Nobuhiro Iwamatsu | 04b0ed2 | 2013-06-06 09:45:25 +0000 | [diff] [blame] | 768 | .set_duplex = sh_eth_set_duplex, |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 769 | .set_rate = sh_eth_set_rate_giga, |
| 770 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 771 | .register_type = SH_ETH_REG_GIGABIT, |
| 772 | |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 773 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
| 774 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
| 775 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| 776 | |
| 777 | .tx_check = EESR_TC1 | EESR_FTC, |
Sergei Shtylyov | ca8c358 | 2013-06-21 01:12:21 +0400 | [diff] [blame] | 778 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
| 779 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | |
| 780 | EESR_TDE | EESR_ECI, |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 781 | .fdr_value = 0x0000072f, |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 782 | |
Nobuhiro Iwamatsu | 5b3dfd1 | 2013-06-06 09:49:30 +0000 | [diff] [blame] | 783 | .irq_flags = IRQF_SHARED, |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 784 | .apr = 1, |
| 785 | .mpr = 1, |
| 786 | .tpauser = 1, |
| 787 | .bculr = 1, |
| 788 | .hw_swap = 1, |
| 789 | .rpadir = 1, |
| 790 | .rpadir_value = 2 << 16, |
| 791 | .no_trimd = 1, |
| 792 | .no_ade = 1, |
Yoshihiro Shimoda | 3acbc97 | 2012-02-15 17:54:51 +0000 | [diff] [blame] | 793 | .tsu = 1, |
Yoshihiro Shimoda | 8fcd496 | 2011-03-07 21:59:49 +0000 | [diff] [blame] | 794 | }; |
| 795 | |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 796 | /* SH7734 */ |
| 797 | static struct sh_eth_cpu_data sh7734_data = { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 798 | .chip_reset = sh_eth_chip_reset, |
| 799 | .set_duplex = sh_eth_set_duplex, |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 800 | .set_rate = sh_eth_set_rate_gether, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 801 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 802 | .register_type = SH_ETH_REG_GIGABIT, |
| 803 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 804 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
| 805 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
Sergei Shtylyov | 2d4fef7 | 2017-01-04 22:18:24 +0300 | [diff] [blame] | 806 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 807 | |
| 808 | .tx_check = EESR_TC1 | EESR_FTC, |
Sergei Shtylyov | ca8c358 | 2013-06-21 01:12:21 +0400 | [diff] [blame] | 809 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
| 810 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | |
| 811 | EESR_TDE | EESR_ECI, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 812 | |
| 813 | .apr = 1, |
| 814 | .mpr = 1, |
| 815 | .tpauser = 1, |
| 816 | .bculr = 1, |
| 817 | .hw_swap = 1, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 818 | .no_trimd = 1, |
| 819 | .no_ade = 1, |
Yoshihiro Shimoda | 4986b99 | 2011-03-07 21:59:34 +0000 | [diff] [blame] | 820 | .tsu = 1, |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 821 | .hw_crc = 1, |
| 822 | .select_mii = 1, |
Sergei Shtylyov | f10e206 | 2017-01-04 23:10:23 +0300 | [diff] [blame] | 823 | .shift_rd0 = 1, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 824 | }; |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 825 | |
| 826 | /* SH7763 */ |
| 827 | static struct sh_eth_cpu_data sh7763_data = { |
| 828 | .chip_reset = sh_eth_chip_reset, |
| 829 | .set_duplex = sh_eth_set_duplex, |
| 830 | .set_rate = sh_eth_set_rate_gether, |
| 831 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 832 | .register_type = SH_ETH_REG_GIGABIT, |
| 833 | |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 834 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
| 835 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, |
Sergei Shtylyov | 2d4fef7 | 2017-01-04 22:18:24 +0300 | [diff] [blame] | 836 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff, |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 837 | |
| 838 | .tx_check = EESR_TC1 | EESR_FTC, |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 839 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
| 840 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 841 | EESR_ECI, |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 842 | |
| 843 | .apr = 1, |
| 844 | .mpr = 1, |
| 845 | .tpauser = 1, |
| 846 | .bculr = 1, |
| 847 | .hw_swap = 1, |
| 848 | .no_trimd = 1, |
| 849 | .no_ade = 1, |
| 850 | .tsu = 1, |
| 851 | .irq_flags = IRQF_SHARED, |
| 852 | }; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 853 | |
Sergei Shtylyov | c18a79a | 2013-06-07 13:56:05 +0000 | [diff] [blame] | 854 | static struct sh_eth_cpu_data sh7619_data = { |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 855 | .register_type = SH_ETH_REG_FAST_SH3_SH2, |
| 856 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 857 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
| 858 | |
| 859 | .apr = 1, |
| 860 | .mpr = 1, |
| 861 | .tpauser = 1, |
| 862 | .hw_swap = 1, |
| 863 | }; |
Sergei Shtylyov | 7bbe150 | 2013-06-07 13:55:08 +0000 | [diff] [blame] | 864 | |
| 865 | static struct sh_eth_cpu_data sh771x_data = { |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 866 | .register_type = SH_ETH_REG_FAST_SH3_SH2, |
| 867 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 868 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
Yoshihiro Shimoda | 4986b99 | 2011-03-07 21:59:34 +0000 | [diff] [blame] | 869 | .tsu = 1, |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 870 | }; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 871 | |
| 872 | static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) |
| 873 | { |
| 874 | if (!cd->ecsr_value) |
| 875 | cd->ecsr_value = DEFAULT_ECSR_INIT; |
| 876 | |
| 877 | if (!cd->ecsipr_value) |
| 878 | cd->ecsipr_value = DEFAULT_ECSIPR_INIT; |
| 879 | |
| 880 | if (!cd->fcftr_value) |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 881 | cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 882 | DEFAULT_FIFO_F_D_RFD; |
| 883 | |
| 884 | if (!cd->fdr_value) |
| 885 | cd->fdr_value = DEFAULT_FDR_INIT; |
| 886 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 887 | if (!cd->tx_check) |
| 888 | cd->tx_check = DEFAULT_TX_CHECK; |
| 889 | |
| 890 | if (!cd->eesr_err_check) |
| 891 | cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; |
Nobuhiro Iwamatsu | b284fbe | 2015-01-08 15:25:07 +0900 | [diff] [blame] | 892 | |
| 893 | if (!cd->trscer_err_mask) |
| 894 | cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 895 | } |
| 896 | |
Nobuhiro Iwamatsu | 5cee1d3 | 2012-06-25 17:35:12 +0000 | [diff] [blame] | 897 | static int sh_eth_check_reset(struct net_device *ndev) |
| 898 | { |
| 899 | int ret = 0; |
| 900 | int cnt = 100; |
| 901 | |
| 902 | while (cnt > 0) { |
Sergei Shtylyov | 97717ed | 2016-04-24 23:45:23 +0300 | [diff] [blame] | 903 | if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) |
Nobuhiro Iwamatsu | 5cee1d3 | 2012-06-25 17:35:12 +0000 | [diff] [blame] | 904 | break; |
| 905 | mdelay(1); |
| 906 | cnt--; |
| 907 | } |
Sergei Shtylyov | 9f8c426 | 2013-06-05 23:54:01 +0400 | [diff] [blame] | 908 | if (cnt <= 0) { |
Sergei Shtylyov | f75f14e | 2014-03-15 03:27:54 +0300 | [diff] [blame] | 909 | netdev_err(ndev, "Device reset failed\n"); |
Nobuhiro Iwamatsu | 5cee1d3 | 2012-06-25 17:35:12 +0000 | [diff] [blame] | 910 | ret = -ETIMEDOUT; |
| 911 | } |
| 912 | return ret; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 913 | } |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 914 | |
| 915 | static int sh_eth_reset(struct net_device *ndev) |
| 916 | { |
| 917 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 918 | int ret = 0; |
| 919 | |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 920 | if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 921 | sh_eth_write(ndev, EDSR_ENALL, EDSR); |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 922 | sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 923 | |
| 924 | ret = sh_eth_check_reset(ndev); |
| 925 | if (ret) |
Laurent Pinchart | f738a13 | 2014-03-20 15:00:35 +0100 | [diff] [blame] | 926 | return ret; |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 927 | |
| 928 | /* Table Init */ |
| 929 | sh_eth_write(ndev, 0x0, TDLAR); |
| 930 | sh_eth_write(ndev, 0x0, TDFAR); |
| 931 | sh_eth_write(ndev, 0x0, TDFXR); |
| 932 | sh_eth_write(ndev, 0x0, TDFFR); |
| 933 | sh_eth_write(ndev, 0x0, RDLAR); |
| 934 | sh_eth_write(ndev, 0x0, RDFAR); |
| 935 | sh_eth_write(ndev, 0x0, RDFXR); |
| 936 | sh_eth_write(ndev, 0x0, RDFFR); |
| 937 | |
| 938 | /* Reset HW CRC register */ |
| 939 | if (mdp->cd->hw_crc) |
| 940 | sh_eth_write(ndev, 0x0, CSMR); |
| 941 | |
| 942 | /* Select MII mode */ |
| 943 | if (mdp->cd->select_mii) |
| 944 | sh_eth_select_mii(ndev); |
| 945 | } else { |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 946 | sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 947 | mdelay(3); |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 948 | sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 949 | } |
| 950 | |
Nobuhiro Iwamatsu | dabdde9 | 2013-06-06 09:51:39 +0000 | [diff] [blame] | 951 | return ret; |
| 952 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 953 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 954 | static void sh_eth_set_receive_align(struct sk_buff *skb) |
| 955 | { |
Mitsuhiro Kimura | 4d6a949 | 2014-11-27 20:34:00 +0900 | [diff] [blame] | 956 | uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 957 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 958 | if (reserve) |
Mitsuhiro Kimura | 4d6a949 | 2014-11-27 20:34:00 +0900 | [diff] [blame] | 959 | skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 960 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 961 | |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 962 | /* Program the hardware MAC address from dev->dev_addr. */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 963 | static void update_mac_address(struct net_device *ndev) |
| 964 | { |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 965 | sh_eth_write(ndev, |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 966 | (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | |
| 967 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 968 | sh_eth_write(ndev, |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 969 | (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 970 | } |
| 971 | |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 972 | /* Get MAC address from SuperH MAC address register |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 973 | * |
| 974 | * SuperH's Ethernet device doesn't have 'ROM' to MAC address. |
| 975 | * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). |
| 976 | * When you want use this device, you must set MAC address in bootloader. |
| 977 | * |
| 978 | */ |
Magnus Damm | 748031f | 2009-10-09 00:17:14 +0000 | [diff] [blame] | 979 | static void read_mac_address(struct net_device *ndev, unsigned char *mac) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 980 | { |
Magnus Damm | 748031f | 2009-10-09 00:17:14 +0000 | [diff] [blame] | 981 | if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { |
Joe Perches | d458cdf | 2013-10-01 19:04:40 -0700 | [diff] [blame] | 982 | memcpy(ndev->dev_addr, mac, ETH_ALEN); |
Magnus Damm | 748031f | 2009-10-09 00:17:14 +0000 | [diff] [blame] | 983 | } else { |
Sergei Shtylyov | 37742f0 | 2015-12-05 00:58:57 +0300 | [diff] [blame] | 984 | u32 mahr = sh_eth_read(ndev, MAHR); |
| 985 | u32 malr = sh_eth_read(ndev, MALR); |
| 986 | |
| 987 | ndev->dev_addr[0] = (mahr >> 24) & 0xFF; |
| 988 | ndev->dev_addr[1] = (mahr >> 16) & 0xFF; |
| 989 | ndev->dev_addr[2] = (mahr >> 8) & 0xFF; |
| 990 | ndev->dev_addr[3] = (mahr >> 0) & 0xFF; |
| 991 | ndev->dev_addr[4] = (malr >> 8) & 0xFF; |
| 992 | ndev->dev_addr[5] = (malr >> 0) & 0xFF; |
Magnus Damm | 748031f | 2009-10-09 00:17:14 +0000 | [diff] [blame] | 993 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 994 | } |
| 995 | |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 996 | static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 997 | { |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 998 | if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 999 | return EDTRR_TRNS_GETHER; |
| 1000 | else |
| 1001 | return EDTRR_TRNS_ETHER; |
| 1002 | } |
| 1003 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1004 | struct bb_info { |
Yoshihiro Shimoda | ae70644 | 2011-09-27 21:48:58 +0000 | [diff] [blame] | 1005 | void (*set_gate)(void *addr); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1006 | struct mdiobb_ctrl ctrl; |
Yoshihiro Shimoda | ae70644 | 2011-09-27 21:48:58 +0000 | [diff] [blame] | 1007 | void *addr; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1008 | }; |
| 1009 | |
Sergei Shtylyov | 39b4b06 | 2015-12-08 00:40:57 +0300 | [diff] [blame] | 1010 | static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1011 | { |
| 1012 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); |
Sergei Shtylyov | 78fa3c5 | 2015-12-08 00:41:43 +0300 | [diff] [blame] | 1013 | u32 pir; |
Yoshihiro Shimoda | b3017e6 | 2011-03-07 21:59:55 +0000 | [diff] [blame] | 1014 | |
| 1015 | if (bitbang->set_gate) |
| 1016 | bitbang->set_gate(bitbang->addr); |
| 1017 | |
Sergei Shtylyov | 78fa3c5 | 2015-12-08 00:41:43 +0300 | [diff] [blame] | 1018 | pir = ioread32(bitbang->addr); |
Sergei Shtylyov | 39b4b06 | 2015-12-08 00:40:57 +0300 | [diff] [blame] | 1019 | if (set) |
Sergei Shtylyov | 78fa3c5 | 2015-12-08 00:41:43 +0300 | [diff] [blame] | 1020 | pir |= mask; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1021 | else |
Sergei Shtylyov | 78fa3c5 | 2015-12-08 00:41:43 +0300 | [diff] [blame] | 1022 | pir &= ~mask; |
| 1023 | iowrite32(pir, bitbang->addr); |
Sergei Shtylyov | 39b4b06 | 2015-12-08 00:40:57 +0300 | [diff] [blame] | 1024 | } |
| 1025 | |
| 1026 | /* Data I/O pin control */ |
| 1027 | static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) |
| 1028 | { |
| 1029 | sh_mdio_ctrl(ctrl, PIR_MMD, bit); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1030 | } |
| 1031 | |
| 1032 | /* Set bit data*/ |
| 1033 | static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) |
| 1034 | { |
Sergei Shtylyov | 39b4b06 | 2015-12-08 00:40:57 +0300 | [diff] [blame] | 1035 | sh_mdio_ctrl(ctrl, PIR_MDO, bit); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1036 | } |
| 1037 | |
| 1038 | /* Get bit data*/ |
| 1039 | static int sh_get_mdio(struct mdiobb_ctrl *ctrl) |
| 1040 | { |
| 1041 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); |
Yoshihiro Shimoda | b3017e6 | 2011-03-07 21:59:55 +0000 | [diff] [blame] | 1042 | |
| 1043 | if (bitbang->set_gate) |
| 1044 | bitbang->set_gate(bitbang->addr); |
| 1045 | |
Sergei Shtylyov | 78fa3c5 | 2015-12-08 00:41:43 +0300 | [diff] [blame] | 1046 | return (ioread32(bitbang->addr) & PIR_MDI) != 0; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | /* MDC pin control */ |
| 1050 | static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) |
| 1051 | { |
Sergei Shtylyov | 39b4b06 | 2015-12-08 00:40:57 +0300 | [diff] [blame] | 1052 | sh_mdio_ctrl(ctrl, PIR_MDC, bit); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1053 | } |
| 1054 | |
| 1055 | /* mdio bus control struct */ |
| 1056 | static struct mdiobb_ops bb_ops = { |
| 1057 | .owner = THIS_MODULE, |
| 1058 | .set_mdc = sh_mdc_ctrl, |
| 1059 | .set_mdio_dir = sh_mmd_ctrl, |
| 1060 | .set_mdio_data = sh_set_mdio, |
| 1061 | .get_mdio_data = sh_get_mdio, |
| 1062 | }; |
| 1063 | |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 1064 | /* free Tx skb function */ |
| 1065 | static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) |
| 1066 | { |
| 1067 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1068 | struct sh_eth_txdesc *txdesc; |
| 1069 | int free_num = 0; |
| 1070 | int entry; |
| 1071 | bool sent; |
| 1072 | |
| 1073 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { |
| 1074 | entry = mdp->dirty_tx % mdp->num_tx_ring; |
| 1075 | txdesc = &mdp->tx_ring[entry]; |
| 1076 | sent = !(txdesc->status & cpu_to_le32(TD_TACT)); |
| 1077 | if (sent_only && !sent) |
| 1078 | break; |
| 1079 | /* TACT bit must be checked before all the following reads */ |
| 1080 | dma_rmb(); |
| 1081 | netif_info(mdp, tx_done, ndev, |
| 1082 | "tx entry %d status 0x%08x\n", |
| 1083 | entry, le32_to_cpu(txdesc->status)); |
| 1084 | /* Free the original skb. */ |
| 1085 | if (mdp->tx_skbuff[entry]) { |
| 1086 | dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr), |
| 1087 | le32_to_cpu(txdesc->len) >> 16, |
| 1088 | DMA_TO_DEVICE); |
| 1089 | dev_kfree_skb_irq(mdp->tx_skbuff[entry]); |
| 1090 | mdp->tx_skbuff[entry] = NULL; |
| 1091 | free_num++; |
| 1092 | } |
| 1093 | txdesc->status = cpu_to_le32(TD_TFP); |
| 1094 | if (entry >= mdp->num_tx_ring - 1) |
| 1095 | txdesc->status |= cpu_to_le32(TD_TDLE); |
| 1096 | |
| 1097 | if (sent) { |
| 1098 | ndev->stats.tx_packets++; |
| 1099 | ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; |
| 1100 | } |
| 1101 | } |
| 1102 | return free_num; |
| 1103 | } |
| 1104 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1105 | /* free skb and descriptor buffer */ |
| 1106 | static void sh_eth_ring_free(struct net_device *ndev) |
| 1107 | { |
| 1108 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1109 | int ringsize, i; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1110 | |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 1111 | if (mdp->rx_ring) { |
| 1112 | for (i = 0; i < mdp->num_rx_ring; i++) { |
| 1113 | if (mdp->rx_skbuff[i]) { |
| 1114 | struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; |
| 1115 | |
| 1116 | dma_unmap_single(&ndev->dev, |
| 1117 | le32_to_cpu(rxdesc->addr), |
| 1118 | ALIGN(mdp->rx_buf_sz, 32), |
| 1119 | DMA_FROM_DEVICE); |
| 1120 | } |
| 1121 | } |
| 1122 | ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; |
| 1123 | dma_free_coherent(NULL, ringsize, mdp->rx_ring, |
| 1124 | mdp->rx_desc_dma); |
| 1125 | mdp->rx_ring = NULL; |
| 1126 | } |
| 1127 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1128 | /* Free Rx skb ringbuffer */ |
| 1129 | if (mdp->rx_skbuff) { |
Sergei Shtylyov | 179d80a | 2014-06-28 04:10:00 +0400 | [diff] [blame] | 1130 | for (i = 0; i < mdp->num_rx_ring; i++) |
| 1131 | dev_kfree_skb(mdp->rx_skbuff[i]); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1132 | } |
| 1133 | kfree(mdp->rx_skbuff); |
Yoshihiro Shimoda | 91c7755 | 2012-06-26 20:00:01 +0000 | [diff] [blame] | 1134 | mdp->rx_skbuff = NULL; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1135 | |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1136 | if (mdp->tx_ring) { |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 1137 | sh_eth_tx_free(ndev, false); |
| 1138 | |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1139 | ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; |
| 1140 | dma_free_coherent(NULL, ringsize, mdp->tx_ring, |
| 1141 | mdp->tx_desc_dma); |
| 1142 | mdp->tx_ring = NULL; |
| 1143 | } |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 1144 | |
| 1145 | /* Free Tx skb ringbuffer */ |
| 1146 | kfree(mdp->tx_skbuff); |
| 1147 | mdp->tx_skbuff = NULL; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | /* format skb and descriptor buffer */ |
| 1151 | static void sh_eth_ring_format(struct net_device *ndev) |
| 1152 | { |
| 1153 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1154 | int i; |
| 1155 | struct sk_buff *skb; |
| 1156 | struct sh_eth_rxdesc *rxdesc = NULL; |
| 1157 | struct sh_eth_txdesc *txdesc = NULL; |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1158 | int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; |
| 1159 | int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; |
Sergei Shtylyov | cb36859 | 2015-10-24 00:46:40 +0300 | [diff] [blame] | 1160 | int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; |
Ben Hutchings | 52b9fa3 | 2015-01-27 00:50:24 +0000 | [diff] [blame] | 1161 | dma_addr_t dma_addr; |
Sergei Shtylyov | 5cbf20c | 2015-12-20 01:48:04 +0300 | [diff] [blame] | 1162 | u32 buf_len; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1163 | |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1164 | mdp->cur_rx = 0; |
| 1165 | mdp->cur_tx = 0; |
| 1166 | mdp->dirty_rx = 0; |
| 1167 | mdp->dirty_tx = 0; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1168 | |
| 1169 | memset(mdp->rx_ring, 0, rx_ringsize); |
| 1170 | |
| 1171 | /* build Rx ring buffer */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1172 | for (i = 0; i < mdp->num_rx_ring; i++) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1173 | /* skb */ |
| 1174 | mdp->rx_skbuff[i] = NULL; |
Mitsuhiro Kimura | 4d6a949 | 2014-11-27 20:34:00 +0900 | [diff] [blame] | 1175 | skb = netdev_alloc_skb(ndev, skbuff_size); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1176 | if (skb == NULL) |
| 1177 | break; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1178 | sh_eth_set_receive_align(skb); |
| 1179 | |
Sergei Shtylyov | ab85791 | 2015-10-24 00:46:03 +0300 | [diff] [blame] | 1180 | /* The size of the buffer is a multiple of 32 bytes. */ |
Sergei Shtylyov | 5cbf20c | 2015-12-20 01:48:04 +0300 | [diff] [blame] | 1181 | buf_len = ALIGN(mdp->rx_buf_sz, 32); |
Sergei Shtylyov | 5cbf20c | 2015-12-20 01:48:04 +0300 | [diff] [blame] | 1182 | dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len, |
Ben Hutchings | 52b9fa3 | 2015-01-27 00:50:24 +0000 | [diff] [blame] | 1183 | DMA_FROM_DEVICE); |
| 1184 | if (dma_mapping_error(&ndev->dev, dma_addr)) { |
| 1185 | kfree_skb(skb); |
| 1186 | break; |
| 1187 | } |
| 1188 | mdp->rx_skbuff[i] = skb; |
Sergei Shtylyov | d0ba913 | 2016-03-08 01:37:09 +0300 | [diff] [blame] | 1189 | |
| 1190 | /* RX descriptor */ |
| 1191 | rxdesc = &mdp->rx_ring[i]; |
| 1192 | rxdesc->len = cpu_to_le32(buf_len << 16); |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1193 | rxdesc->addr = cpu_to_le32(dma_addr); |
| 1194 | rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1195 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1196 | /* Rx descriptor address set */ |
| 1197 | if (i == 0) { |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1198 | sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 1199 | if (sh_eth_is_gether(mdp) || |
| 1200 | sh_eth_is_rz_fast_ether(mdp)) |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 1201 | sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1202 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1203 | } |
| 1204 | |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1205 | mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1206 | |
| 1207 | /* Mark the last entry as wrapping the ring. */ |
Sergei Shtylyov | c1b7fca | 2016-03-08 01:36:28 +0300 | [diff] [blame] | 1208 | if (rxdesc) |
| 1209 | rxdesc->status |= cpu_to_le32(RD_RDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1210 | |
| 1211 | memset(mdp->tx_ring, 0, tx_ringsize); |
| 1212 | |
| 1213 | /* build Tx ring buffer */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1214 | for (i = 0; i < mdp->num_tx_ring; i++) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1215 | mdp->tx_skbuff[i] = NULL; |
| 1216 | txdesc = &mdp->tx_ring[i]; |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1217 | txdesc->status = cpu_to_le32(TD_TFP); |
| 1218 | txdesc->len = cpu_to_le32(0); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1219 | if (i == 0) { |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 1220 | /* Tx descriptor address set */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1221 | sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 1222 | if (sh_eth_is_gether(mdp) || |
| 1223 | sh_eth_is_rz_fast_ether(mdp)) |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 1224 | sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1225 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1226 | } |
| 1227 | |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1228 | txdesc->status |= cpu_to_le32(TD_TDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1229 | } |
| 1230 | |
| 1231 | /* Get skb and descriptor buffer */ |
| 1232 | static int sh_eth_ring_init(struct net_device *ndev) |
| 1233 | { |
| 1234 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1235 | int rx_ringsize, tx_ringsize; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1236 | |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1237 | /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1238 | * card needs room to do 8 byte alignment, +2 so we can reserve |
| 1239 | * the first 2 bytes, and +16 gets room for the status word from the |
| 1240 | * card. |
| 1241 | */ |
| 1242 | mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : |
| 1243 | (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); |
Magnus Damm | 503914c | 2009-12-15 21:16:55 -0800 | [diff] [blame] | 1244 | if (mdp->cd->rpadir) |
| 1245 | mdp->rx_buf_sz += NET_IP_ALIGN; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1246 | |
| 1247 | /* Allocate RX and TX skb rings */ |
Sergei Shtylyov | 2c94e85 | 2015-10-31 02:05:56 +0300 | [diff] [blame] | 1248 | mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), |
| 1249 | GFP_KERNEL); |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1250 | if (!mdp->rx_skbuff) |
| 1251 | return -ENOMEM; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1252 | |
Sergei Shtylyov | 2c94e85 | 2015-10-31 02:05:56 +0300 | [diff] [blame] | 1253 | mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), |
| 1254 | GFP_KERNEL); |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1255 | if (!mdp->tx_skbuff) |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1256 | goto ring_free; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1257 | |
| 1258 | /* Allocate all Rx descriptors. */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1259 | rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1260 | mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, |
Joe Perches | d0320f7 | 2013-03-14 13:07:21 +0000 | [diff] [blame] | 1261 | GFP_KERNEL); |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1262 | if (!mdp->rx_ring) |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1263 | goto ring_free; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1264 | |
| 1265 | mdp->dirty_rx = 0; |
| 1266 | |
| 1267 | /* Allocate all Tx descriptors. */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1268 | tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1269 | mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, |
Joe Perches | d0320f7 | 2013-03-14 13:07:21 +0000 | [diff] [blame] | 1270 | GFP_KERNEL); |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1271 | if (!mdp->tx_ring) |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1272 | goto ring_free; |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1273 | return 0; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1274 | |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 1275 | ring_free: |
| 1276 | /* Free Rx and Tx skb ring buffer and DMA buffer */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1277 | sh_eth_ring_free(ndev); |
| 1278 | |
Sergei Shtylyov | 91d8068 | 2015-11-04 00:17:08 +0300 | [diff] [blame] | 1279 | return -ENOMEM; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1280 | } |
| 1281 | |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 1282 | static int sh_eth_dev_init(struct net_device *ndev) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1283 | { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1284 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Sergei Shtylyov | 4fa8c3c | 2016-03-13 01:29:45 +0300 | [diff] [blame] | 1285 | int ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1286 | |
| 1287 | /* Soft Reset */ |
Nobuhiro Iwamatsu | 5cee1d3 | 2012-06-25 17:35:12 +0000 | [diff] [blame] | 1288 | ret = sh_eth_reset(ndev); |
| 1289 | if (ret) |
Laurent Pinchart | f738a13 | 2014-03-20 15:00:35 +0100 | [diff] [blame] | 1290 | return ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1291 | |
Simon Horman | 55754f1 | 2013-07-23 10:18:04 +0900 | [diff] [blame] | 1292 | if (mdp->cd->rmiimode) |
| 1293 | sh_eth_write(ndev, 0x1, RMIIMODE); |
| 1294 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1295 | /* Descriptor format */ |
| 1296 | sh_eth_ring_format(ndev); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1297 | if (mdp->cd->rpadir) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1298 | sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1299 | |
| 1300 | /* all sh_eth int mask */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1301 | sh_eth_write(ndev, 0, EESIPR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1302 | |
Yoshihiro Shimoda | 10b9194 | 2012-03-29 19:32:08 +0000 | [diff] [blame] | 1303 | #if defined(__LITTLE_ENDIAN) |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1304 | if (mdp->cd->hw_swap) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1305 | sh_eth_write(ndev, EDMR_EL, EDMR); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1306 | else |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1307 | #endif |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1308 | sh_eth_write(ndev, 0, EDMR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1309 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1310 | /* FIFO size set */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1311 | sh_eth_write(ndev, mdp->cd->fdr_value, FDR); |
| 1312 | sh_eth_write(ndev, 0, TFTR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1313 | |
Ben Dooks | 530aa2d | 2014-06-03 12:21:13 +0100 | [diff] [blame] | 1314 | /* Frame recv control (enable multiple-packets per rx irq) */ |
| 1315 | sh_eth_write(ndev, RMCR_RNC, RMCR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1316 | |
Nobuhiro Iwamatsu | b284fbe | 2015-01-08 15:25:07 +0900 | [diff] [blame] | 1317 | sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1318 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1319 | if (mdp->cd->bculr) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1320 | sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1321 | |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1322 | sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1323 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1324 | if (!mdp->cd->no_trimd) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1325 | sh_eth_write(ndev, 0, TRIMD); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1326 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1327 | /* Recv frame limit set register */ |
Yoshihiro Shimoda | fdb37a7 | 2012-02-06 23:55:15 +0000 | [diff] [blame] | 1328 | sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, |
| 1329 | RFLR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1330 | |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 1331 | sh_eth_modify(ndev, EESR, 0, 0); |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 1332 | mdp->irq_enabled = true; |
| 1333 | sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1334 | |
| 1335 | /* PAUSE Prohibition */ |
Sergei Shtylyov | bffa731 | 2016-01-11 00:28:14 +0300 | [diff] [blame] | 1336 | sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | |
| 1337 | ECMR_TE | ECMR_RE, ECMR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1338 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1339 | if (mdp->cd->set_rate) |
| 1340 | mdp->cd->set_rate(ndev); |
| 1341 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1342 | /* E-MAC Status Register clear */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1343 | sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1344 | |
| 1345 | /* E-MAC Interrupt Enable register */ |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 1346 | sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1347 | |
| 1348 | /* Set MAC address */ |
| 1349 | update_mac_address(ndev); |
| 1350 | |
| 1351 | /* mask reset */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1352 | if (mdp->cd->apr) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1353 | sh_eth_write(ndev, APR_AP, APR); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1354 | if (mdp->cd->mpr) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1355 | sh_eth_write(ndev, MPR_MP, MPR); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1356 | if (mdp->cd->tpauser) |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1357 | sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1358 | |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 1359 | /* Setting the Rx mode will start the Rx process. */ |
| 1360 | sh_eth_write(ndev, EDRRR_R, EDRRR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1361 | |
| 1362 | return ret; |
| 1363 | } |
| 1364 | |
Ben Hutchings | 740c7f3 | 2015-01-27 00:49:32 +0000 | [diff] [blame] | 1365 | static void sh_eth_dev_exit(struct net_device *ndev) |
| 1366 | { |
| 1367 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1368 | int i; |
| 1369 | |
| 1370 | /* Deactivate all TX descriptors, so DMA should stop at next |
| 1371 | * packet boundary if it's currently running |
| 1372 | */ |
| 1373 | for (i = 0; i < mdp->num_tx_ring; i++) |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1374 | mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); |
Ben Hutchings | 740c7f3 | 2015-01-27 00:49:32 +0000 | [diff] [blame] | 1375 | |
| 1376 | /* Disable TX FIFO egress to MAC */ |
| 1377 | sh_eth_rcv_snd_disable(ndev); |
| 1378 | |
| 1379 | /* Stop RX DMA at next packet boundary */ |
| 1380 | sh_eth_write(ndev, 0, EDRRR); |
| 1381 | |
| 1382 | /* Aside from TX DMA, we can't tell when the hardware is |
| 1383 | * really stopped, so we need to reset to make sure. |
| 1384 | * Before doing that, wait for long enough to *probably* |
| 1385 | * finish transmitting the last packet and poll stats. |
| 1386 | */ |
| 1387 | msleep(2); /* max frame time at 10 Mbps < 1250 us */ |
| 1388 | sh_eth_get_stats(ndev); |
| 1389 | sh_eth_reset(ndev); |
Geert Uytterhoeven | a14c7d1 | 2015-02-27 17:16:26 +0100 | [diff] [blame] | 1390 | |
| 1391 | /* Set MAC address again */ |
| 1392 | update_mac_address(ndev); |
Ben Hutchings | 740c7f3 | 2015-01-27 00:49:32 +0000 | [diff] [blame] | 1393 | } |
| 1394 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1395 | /* Packet receive function */ |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1396 | static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1397 | { |
| 1398 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1399 | struct sh_eth_rxdesc *rxdesc; |
| 1400 | |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1401 | int entry = mdp->cur_rx % mdp->num_rx_ring; |
| 1402 | int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; |
Mitsuhiro Kimura | 319cd52 | 2014-12-09 21:23:42 +0900 | [diff] [blame] | 1403 | int limit; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1404 | struct sk_buff *skb; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1405 | u32 desc_status; |
Sergei Shtylyov | cb36859 | 2015-10-24 00:46:40 +0300 | [diff] [blame] | 1406 | int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; |
Ben Hutchings | 52b9fa3 | 2015-01-27 00:50:24 +0000 | [diff] [blame] | 1407 | dma_addr_t dma_addr; |
Sergei Shtylyov | 4fa8c3c | 2016-03-13 01:29:45 +0300 | [diff] [blame] | 1408 | u16 pkt_len; |
Sergei Shtylyov | 5cbf20c | 2015-12-20 01:48:04 +0300 | [diff] [blame] | 1409 | u32 buf_len; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1410 | |
Mitsuhiro Kimura | 319cd52 | 2014-12-09 21:23:42 +0900 | [diff] [blame] | 1411 | boguscnt = min(boguscnt, *quota); |
| 1412 | limit = boguscnt; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1413 | rxdesc = &mdp->rx_ring[entry]; |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1414 | while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { |
Ben Hutchings | 7d7355f | 2015-03-03 00:52:00 +0000 | [diff] [blame] | 1415 | /* RACT bit must be checked before all the following reads */ |
Sergei Shtylyov | f32bfb9 | 2015-11-03 22:36:04 +0300 | [diff] [blame] | 1416 | dma_rmb(); |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1417 | desc_status = le32_to_cpu(rxdesc->status); |
| 1418 | pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1419 | |
| 1420 | if (--boguscnt < 0) |
| 1421 | break; |
| 1422 | |
Ben Hutchings | e5fd13f | 2015-02-26 20:34:46 +0000 | [diff] [blame] | 1423 | netif_info(mdp, rx_status, ndev, |
| 1424 | "rx entry %d status 0x%08x len %d\n", |
| 1425 | entry, desc_status, pkt_len); |
| 1426 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1427 | if (!(desc_status & RDFEND)) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1428 | ndev->stats.rx_length_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1429 | |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1430 | /* In case of almost all GETHER/ETHERs, the Receive Frame State |
Yoshihiro Shimoda | dd01989 | 2013-06-13 10:15:45 +0900 | [diff] [blame] | 1431 | * (RFS) bits in the Receive Descriptor 0 are from bit 9 to |
Ben Hutchings | 9b4a636 | 2015-03-03 00:52:39 +0000 | [diff] [blame] | 1432 | * bit 0. However, in case of the R8A7740 and R7S72100 |
| 1433 | * the RFS bits are from bit 25 to bit 16. So, the |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 1434 | * driver needs right shifting by 16. |
Yoshihiro Shimoda | dd01989 | 2013-06-13 10:15:45 +0900 | [diff] [blame] | 1435 | */ |
Sergei Shtylyov | ac8025a | 2013-06-13 22:12:45 +0400 | [diff] [blame] | 1436 | if (mdp->cd->shift_rd0) |
| 1437 | desc_status >>= 16; |
Yoshihiro Shimoda | dd01989 | 2013-06-13 10:15:45 +0900 | [diff] [blame] | 1438 | |
Sergei Shtylyov | 248be83 | 2015-12-04 01:45:40 +0300 | [diff] [blame] | 1439 | skb = mdp->rx_skbuff[entry]; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1440 | if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | |
| 1441 | RD_RFS5 | RD_RFS6 | RD_RFS10)) { |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1442 | ndev->stats.rx_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1443 | if (desc_status & RD_RFS1) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1444 | ndev->stats.rx_crc_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1445 | if (desc_status & RD_RFS2) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1446 | ndev->stats.rx_frame_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1447 | if (desc_status & RD_RFS3) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1448 | ndev->stats.rx_length_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1449 | if (desc_status & RD_RFS4) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1450 | ndev->stats.rx_length_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1451 | if (desc_status & RD_RFS6) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1452 | ndev->stats.rx_missed_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1453 | if (desc_status & RD_RFS10) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1454 | ndev->stats.rx_over_errors++; |
Sergei Shtylyov | 248be83 | 2015-12-04 01:45:40 +0300 | [diff] [blame] | 1455 | } else if (skb) { |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1456 | dma_addr = le32_to_cpu(rxdesc->addr); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1457 | if (!mdp->cd->hw_swap) |
| 1458 | sh_eth_soft_swap( |
Sergei Shtylyov | 1299653 | 2015-12-13 23:05:07 +0300 | [diff] [blame] | 1459 | phys_to_virt(ALIGN(dma_addr, 4)), |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1460 | pkt_len + 2); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1461 | mdp->rx_skbuff[entry] = NULL; |
Magnus Damm | 503914c | 2009-12-15 21:16:55 -0800 | [diff] [blame] | 1462 | if (mdp->cd->rpadir) |
| 1463 | skb_reserve(skb, NET_IP_ALIGN); |
Sergei Shtylyov | 1299653 | 2015-12-13 23:05:07 +0300 | [diff] [blame] | 1464 | dma_unmap_single(&ndev->dev, dma_addr, |
Sergei Shtylyov | ab85791 | 2015-10-24 00:46:03 +0300 | [diff] [blame] | 1465 | ALIGN(mdp->rx_buf_sz, 32), |
Ben Hutchings | 52b9fa3 | 2015-01-27 00:50:24 +0000 | [diff] [blame] | 1466 | DMA_FROM_DEVICE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1467 | skb_put(skb, pkt_len); |
| 1468 | skb->protocol = eth_type_trans(skb, ndev); |
Sergei Shtylyov | a8e9fd0 | 2013-09-03 03:03:10 +0400 | [diff] [blame] | 1469 | netif_receive_skb(skb); |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1470 | ndev->stats.rx_packets++; |
| 1471 | ndev->stats.rx_bytes += pkt_len; |
Ben Hutchings | 25b77ad | 2015-02-26 20:33:30 +0000 | [diff] [blame] | 1472 | if (desc_status & RD_RFS8) |
| 1473 | ndev->stats.multicast++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1474 | } |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1475 | entry = (++mdp->cur_rx) % mdp->num_rx_ring; |
Yoshihiro Shimoda | 862df49 | 2009-05-24 23:53:40 +0000 | [diff] [blame] | 1476 | rxdesc = &mdp->rx_ring[entry]; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1477 | } |
| 1478 | |
| 1479 | /* Refill the Rx ring buffers. */ |
| 1480 | for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1481 | entry = mdp->dirty_rx % mdp->num_rx_ring; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1482 | rxdesc = &mdp->rx_ring[entry]; |
Sergei Shtylyov | ab85791 | 2015-10-24 00:46:03 +0300 | [diff] [blame] | 1483 | /* The size of the buffer is 32 byte boundary. */ |
Sergei Shtylyov | 5cbf20c | 2015-12-20 01:48:04 +0300 | [diff] [blame] | 1484 | buf_len = ALIGN(mdp->rx_buf_sz, 32); |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1485 | rxdesc->len = cpu_to_le32(buf_len << 16); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1486 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1487 | if (mdp->rx_skbuff[entry] == NULL) { |
Mitsuhiro Kimura | 4d6a949 | 2014-11-27 20:34:00 +0900 | [diff] [blame] | 1488 | skb = netdev_alloc_skb(ndev, skbuff_size); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1489 | if (skb == NULL) |
| 1490 | break; /* Better luck next round. */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1491 | sh_eth_set_receive_align(skb); |
Ben Hutchings | 52b9fa3 | 2015-01-27 00:50:24 +0000 | [diff] [blame] | 1492 | dma_addr = dma_map_single(&ndev->dev, skb->data, |
Sergei Shtylyov | 5cbf20c | 2015-12-20 01:48:04 +0300 | [diff] [blame] | 1493 | buf_len, DMA_FROM_DEVICE); |
Ben Hutchings | 52b9fa3 | 2015-01-27 00:50:24 +0000 | [diff] [blame] | 1494 | if (dma_mapping_error(&ndev->dev, dma_addr)) { |
| 1495 | kfree_skb(skb); |
| 1496 | break; |
| 1497 | } |
| 1498 | mdp->rx_skbuff[entry] = skb; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1499 | |
Eric Dumazet | bc8acf2 | 2010-09-02 13:07:41 -0700 | [diff] [blame] | 1500 | skb_checksum_none_assert(skb); |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1501 | rxdesc->addr = cpu_to_le32(dma_addr); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1502 | } |
Sergei Shtylyov | f32bfb9 | 2015-11-03 22:36:04 +0300 | [diff] [blame] | 1503 | dma_wmb(); /* RACT bit must be set after all the above writes */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 1504 | if (entry >= mdp->num_rx_ring - 1) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1505 | rxdesc->status |= |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1506 | cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1507 | else |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 1508 | rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1509 | } |
| 1510 | |
| 1511 | /* Restart Rx engine if stopped. */ |
| 1512 | /* If we don't need to check status, don't. -KDU */ |
Yoshihiro Shimoda | 79fba9f | 2012-05-28 23:07:55 +0000 | [diff] [blame] | 1513 | if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { |
Yoshihiro Shimoda | a18e08b | 2012-06-20 15:26:34 +0000 | [diff] [blame] | 1514 | /* fix the values for the next receiving if RDE is set */ |
Ben Hutchings | 3365711 | 2015-02-26 20:34:14 +0000 | [diff] [blame] | 1515 | if (intr_status & EESR_RDE && |
| 1516 | mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1517 | u32 count = (sh_eth_read(ndev, RDFAR) - |
| 1518 | sh_eth_read(ndev, RDLAR)) >> 4; |
| 1519 | |
| 1520 | mdp->cur_rx = count; |
| 1521 | mdp->dirty_rx = count; |
| 1522 | } |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1523 | sh_eth_write(ndev, EDRRR_R, EDRRR); |
Yoshihiro Shimoda | 79fba9f | 2012-05-28 23:07:55 +0000 | [diff] [blame] | 1524 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1525 | |
Mitsuhiro Kimura | 319cd52 | 2014-12-09 21:23:42 +0900 | [diff] [blame] | 1526 | *quota -= limit - boguscnt - 1; |
| 1527 | |
Yoshihiro Shimoda | 4f809ce | 2014-06-10 09:40:14 +0900 | [diff] [blame] | 1528 | return *quota <= 0; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1529 | } |
| 1530 | |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1531 | static void sh_eth_rcv_snd_disable(struct net_device *ndev) |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1532 | { |
| 1533 | /* disable tx and rx */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 1534 | sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1535 | } |
| 1536 | |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1537 | static void sh_eth_rcv_snd_enable(struct net_device *ndev) |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1538 | { |
| 1539 | /* enable tx and rx */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 1540 | sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1541 | } |
| 1542 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1543 | /* error control function */ |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 1544 | static void sh_eth_error(struct net_device *ndev, u32 intr_status) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1545 | { |
| 1546 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1547 | u32 felic_stat; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1548 | u32 link_stat; |
| 1549 | u32 mask; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1550 | |
| 1551 | if (intr_status & EESR_ECI) { |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1552 | felic_stat = sh_eth_read(ndev, ECSR); |
| 1553 | sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1554 | if (felic_stat & ECSR_ICD) |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1555 | ndev->stats.tx_carrier_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1556 | if (felic_stat & ECSR_LCHNG) { |
| 1557 | /* Link Changed */ |
Yoshihiro Shimoda | 4923576 | 2009-08-27 23:25:03 +0000 | [diff] [blame] | 1558 | if (mdp->cd->no_psr || mdp->no_ether_link) { |
Sergei Shtylyov | 1e1b812 | 2013-03-31 09:50:07 +0000 | [diff] [blame] | 1559 | goto ignore_link; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1560 | } else { |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1561 | link_stat = (sh_eth_read(ndev, PSR)); |
Yoshihiro Shimoda | 4923576 | 2009-08-27 23:25:03 +0000 | [diff] [blame] | 1562 | if (mdp->ether_link_active_low) |
| 1563 | link_stat = ~link_stat; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1564 | } |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1565 | if (!(link_stat & PHY_ST_LINK)) { |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1566 | sh_eth_rcv_snd_disable(ndev); |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1567 | } else { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1568 | /* Link Up */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 1569 | sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0); |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 1570 | /* clear int */ |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 1571 | sh_eth_modify(ndev, ECSR, 0, 0); |
| 1572 | sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, |
| 1573 | DMAC_M_ECI); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1574 | /* enable tx and rx */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1575 | sh_eth_rcv_snd_enable(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1576 | } |
| 1577 | } |
| 1578 | } |
| 1579 | |
Sergei Shtylyov | 1e1b812 | 2013-03-31 09:50:07 +0000 | [diff] [blame] | 1580 | ignore_link: |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1581 | if (intr_status & EESR_TWB) { |
Sergei Shtylyov | 4eb313a | 2013-06-21 01:13:42 +0400 | [diff] [blame] | 1582 | /* Unused write back interrupt */ |
| 1583 | if (intr_status & EESR_TABT) { /* Transmit Abort int */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1584 | ndev->stats.tx_aborted_errors++; |
Sergei Shtylyov | 8d5009f | 2014-03-15 03:30:59 +0300 | [diff] [blame] | 1585 | netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); |
Sergei Shtylyov | 4eb313a | 2013-06-21 01:13:42 +0400 | [diff] [blame] | 1586 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1587 | } |
| 1588 | |
| 1589 | if (intr_status & EESR_RABT) { |
| 1590 | /* Receive Abort int */ |
| 1591 | if (intr_status & EESR_RFRMER) { |
| 1592 | /* Receive Frame Overflow int */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1593 | ndev->stats.rx_frame_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1594 | } |
| 1595 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1596 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1597 | if (intr_status & EESR_TDE) { |
| 1598 | /* Transmit Descriptor Empty int */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1599 | ndev->stats.tx_fifo_errors++; |
Sergei Shtylyov | 8d5009f | 2014-03-15 03:30:59 +0300 | [diff] [blame] | 1600 | netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1601 | } |
| 1602 | |
| 1603 | if (intr_status & EESR_TFE) { |
| 1604 | /* FIFO under flow */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1605 | ndev->stats.tx_fifo_errors++; |
Sergei Shtylyov | 8d5009f | 2014-03-15 03:30:59 +0300 | [diff] [blame] | 1606 | netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1607 | } |
| 1608 | |
| 1609 | if (intr_status & EESR_RDE) { |
| 1610 | /* Receive Descriptor Empty int */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1611 | ndev->stats.rx_over_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1612 | } |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1613 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1614 | if (intr_status & EESR_RFE) { |
| 1615 | /* Receive FIFO Overflow int */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1616 | ndev->stats.rx_fifo_errors++; |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1617 | } |
| 1618 | |
| 1619 | if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { |
| 1620 | /* Address Error */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 1621 | ndev->stats.tx_fifo_errors++; |
Sergei Shtylyov | 8d5009f | 2014-03-15 03:30:59 +0300 | [diff] [blame] | 1622 | netif_err(mdp, tx_err, ndev, "Address Error\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1623 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1624 | |
| 1625 | mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; |
| 1626 | if (mdp->cd->no_ade) |
| 1627 | mask &= ~EESR_ADE; |
| 1628 | if (intr_status & mask) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1629 | /* Tx error */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1630 | u32 edtrr = sh_eth_read(ndev, EDTRR); |
Sergei Shtylyov | 090d560 | 2014-01-11 02:41:49 +0300 | [diff] [blame] | 1631 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1632 | /* dmesg */ |
Sergei Shtylyov | da24685 | 2014-03-15 03:29:14 +0300 | [diff] [blame] | 1633 | netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", |
| 1634 | intr_status, mdp->cur_tx, mdp->dirty_tx, |
| 1635 | (u32)ndev->state, edtrr); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1636 | /* dirty buffer free */ |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 1637 | sh_eth_tx_free(ndev, true); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1638 | |
| 1639 | /* SH7712 BUG */ |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 1640 | if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1641 | /* tx dma start */ |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 1642 | sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1643 | } |
| 1644 | /* wakeup */ |
| 1645 | netif_wake_queue(ndev); |
| 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | static irqreturn_t sh_eth_interrupt(int irq, void *netdev) |
| 1650 | { |
| 1651 | struct net_device *ndev = netdev; |
| 1652 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1653 | struct sh_eth_cpu_data *cd = mdp->cd; |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 1654 | irqreturn_t ret = IRQ_NONE; |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 1655 | u32 intr_status, intr_enable; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1656 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1657 | spin_lock(&mdp->lock); |
| 1658 | |
Sergei Shtylyov | 3893b27345 | 2013-03-31 09:54:20 +0000 | [diff] [blame] | 1659 | /* Get interrupt status */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1660 | intr_status = sh_eth_read(ndev, EESR); |
Sergei Shtylyov | 3893b27345 | 2013-03-31 09:54:20 +0000 | [diff] [blame] | 1661 | /* Mask it with the interrupt mask, forcing ECI interrupt to be always |
| 1662 | * enabled since it's the one that comes thru regardless of the mask, |
| 1663 | * and we need to fully handle it in sh_eth_error() in order to quench |
| 1664 | * it as it doesn't get cleared by just writing 1 to the ECI bit... |
| 1665 | */ |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1666 | intr_enable = sh_eth_read(ndev, EESIPR); |
| 1667 | intr_status &= intr_enable | DMAC_M_ECI; |
| 1668 | if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 1669 | ret = IRQ_HANDLED; |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1670 | else |
Ben Hutchings | 283e38d | 2015-01-22 12:44:08 +0000 | [diff] [blame] | 1671 | goto out; |
| 1672 | |
| 1673 | if (!likely(mdp->irq_enabled)) { |
| 1674 | sh_eth_write(ndev, 0, EESIPR); |
| 1675 | goto out; |
| 1676 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1677 | |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1678 | if (intr_status & EESR_RX_CHECK) { |
| 1679 | if (napi_schedule_prep(&mdp->napi)) { |
| 1680 | /* Mask Rx interrupts */ |
| 1681 | sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, |
| 1682 | EESIPR); |
| 1683 | __napi_schedule(&mdp->napi); |
| 1684 | } else { |
Sergei Shtylyov | da24685 | 2014-03-15 03:29:14 +0300 | [diff] [blame] | 1685 | netdev_warn(ndev, |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 1686 | "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", |
Sergei Shtylyov | da24685 | 2014-03-15 03:29:14 +0300 | [diff] [blame] | 1687 | intr_status, intr_enable); |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1688 | } |
| 1689 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1690 | |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 1691 | /* Tx Check */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1692 | if (intr_status & cd->tx_check) { |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1693 | /* Clear Tx interrupts */ |
| 1694 | sh_eth_write(ndev, intr_status & cd->tx_check, EESR); |
| 1695 | |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 1696 | sh_eth_tx_free(ndev, true); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1697 | netif_wake_queue(ndev); |
| 1698 | } |
| 1699 | |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1700 | if (intr_status & cd->eesr_err_check) { |
| 1701 | /* Clear error interrupts */ |
| 1702 | sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); |
| 1703 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1704 | sh_eth_error(ndev, intr_status); |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1705 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1706 | |
Ben Hutchings | 283e38d | 2015-01-22 12:44:08 +0000 | [diff] [blame] | 1707 | out: |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1708 | spin_unlock(&mdp->lock); |
| 1709 | |
Nobuhiro Iwamatsu | 0e0fde3 | 2009-03-16 19:50:57 +0000 | [diff] [blame] | 1710 | return ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1711 | } |
| 1712 | |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1713 | static int sh_eth_poll(struct napi_struct *napi, int budget) |
| 1714 | { |
| 1715 | struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, |
| 1716 | napi); |
| 1717 | struct net_device *ndev = napi->dev; |
| 1718 | int quota = budget; |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 1719 | u32 intr_status; |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1720 | |
| 1721 | for (;;) { |
| 1722 | intr_status = sh_eth_read(ndev, EESR); |
| 1723 | if (!(intr_status & EESR_RX_CHECK)) |
| 1724 | break; |
| 1725 | /* Clear Rx interrupts */ |
| 1726 | sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); |
| 1727 | |
| 1728 | if (sh_eth_rx(ndev, intr_status, "a)) |
| 1729 | goto out; |
| 1730 | } |
| 1731 | |
| 1732 | napi_complete(napi); |
| 1733 | |
| 1734 | /* Reenable Rx interrupts */ |
Ben Hutchings | 283e38d | 2015-01-22 12:44:08 +0000 | [diff] [blame] | 1735 | if (mdp->irq_enabled) |
| 1736 | sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 1737 | out: |
| 1738 | return budget - quota; |
| 1739 | } |
| 1740 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1741 | /* PHY state control function */ |
| 1742 | static void sh_eth_adjust_link(struct net_device *ndev) |
| 1743 | { |
| 1744 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 1745 | struct phy_device *phydev = ndev->phydev; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1746 | int new_state = 0; |
| 1747 | |
Sergei Shtylyov | 3340d2a | 2013-03-31 10:11:04 +0000 | [diff] [blame] | 1748 | if (phydev->link) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1749 | if (phydev->duplex != mdp->duplex) { |
| 1750 | new_state = 1; |
| 1751 | mdp->duplex = phydev->duplex; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1752 | if (mdp->cd->set_duplex) |
| 1753 | mdp->cd->set_duplex(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1754 | } |
| 1755 | |
| 1756 | if (phydev->speed != mdp->speed) { |
| 1757 | new_state = 1; |
| 1758 | mdp->speed = phydev->speed; |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1759 | if (mdp->cd->set_rate) |
| 1760 | mdp->cd->set_rate(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1761 | } |
Sergei Shtylyov | 3340d2a | 2013-03-31 10:11:04 +0000 | [diff] [blame] | 1762 | if (!mdp->link) { |
Sergei Shtylyov | b2b14d2 | 2016-02-10 01:38:28 +0300 | [diff] [blame] | 1763 | sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1764 | new_state = 1; |
| 1765 | mdp->link = phydev->link; |
Sergei Shtylyov | 1e1b812 | 2013-03-31 09:50:07 +0000 | [diff] [blame] | 1766 | if (mdp->cd->no_psr || mdp->no_ether_link) |
| 1767 | sh_eth_rcv_snd_enable(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1768 | } |
| 1769 | } else if (mdp->link) { |
| 1770 | new_state = 1; |
Sergei Shtylyov | 3340d2a | 2013-03-31 10:11:04 +0000 | [diff] [blame] | 1771 | mdp->link = 0; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1772 | mdp->speed = 0; |
| 1773 | mdp->duplex = -1; |
Sergei Shtylyov | 1e1b812 | 2013-03-31 09:50:07 +0000 | [diff] [blame] | 1774 | if (mdp->cd->no_psr || mdp->no_ether_link) |
| 1775 | sh_eth_rcv_snd_disable(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1776 | } |
| 1777 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1778 | if (new_state && netif_msg_link(mdp)) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1779 | phy_print_status(phydev); |
| 1780 | } |
| 1781 | |
| 1782 | /* PHY init function */ |
| 1783 | static int sh_eth_phy_init(struct net_device *ndev) |
| 1784 | { |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 1785 | struct device_node *np = ndev->dev.parent->of_node; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1786 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Sergei Shtylyov | 4fa8c3c | 2016-03-13 01:29:45 +0300 | [diff] [blame] | 1787 | struct phy_device *phydev; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1788 | |
Sergei Shtylyov | 3340d2a | 2013-03-31 10:11:04 +0000 | [diff] [blame] | 1789 | mdp->link = 0; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1790 | mdp->speed = 0; |
| 1791 | mdp->duplex = -1; |
| 1792 | |
| 1793 | /* Try connect to PHY */ |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 1794 | if (np) { |
| 1795 | struct device_node *pn; |
| 1796 | |
| 1797 | pn = of_parse_phandle(np, "phy-handle", 0); |
| 1798 | phydev = of_phy_connect(ndev, pn, |
| 1799 | sh_eth_adjust_link, 0, |
| 1800 | mdp->phy_interface); |
| 1801 | |
Peter Chen | 8da703d | 2016-08-01 15:02:40 +0800 | [diff] [blame] | 1802 | of_node_put(pn); |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 1803 | if (!phydev) |
| 1804 | phydev = ERR_PTR(-ENOENT); |
| 1805 | } else { |
| 1806 | char phy_id[MII_BUS_ID_SIZE + 3]; |
| 1807 | |
| 1808 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, |
| 1809 | mdp->mii_bus->id, mdp->phy_id); |
| 1810 | |
| 1811 | phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, |
| 1812 | mdp->phy_interface); |
| 1813 | } |
| 1814 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1815 | if (IS_ERR(phydev)) { |
Sergei Shtylyov | da24685 | 2014-03-15 03:29:14 +0300 | [diff] [blame] | 1816 | netdev_err(ndev, "failed to connect PHY\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1817 | return PTR_ERR(phydev); |
| 1818 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 1819 | |
Andrew Lunn | 2220943 | 2016-01-06 20:11:13 +0100 | [diff] [blame] | 1820 | phy_attached_info(phydev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1821 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1822 | return 0; |
| 1823 | } |
| 1824 | |
| 1825 | /* PHY control start function */ |
| 1826 | static int sh_eth_phy_start(struct net_device *ndev) |
| 1827 | { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1828 | int ret; |
| 1829 | |
| 1830 | ret = sh_eth_phy_init(ndev); |
| 1831 | if (ret) |
| 1832 | return ret; |
| 1833 | |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 1834 | phy_start(ndev->phydev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 1835 | |
| 1836 | return 0; |
| 1837 | } |
| 1838 | |
Philippe Reynes | f08aff4 | 2016-08-10 00:04:49 +0200 | [diff] [blame] | 1839 | static int sh_eth_get_link_ksettings(struct net_device *ndev, |
| 1840 | struct ethtool_link_ksettings *cmd) |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1841 | { |
| 1842 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1843 | unsigned long flags; |
| 1844 | int ret; |
| 1845 | |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 1846 | if (!ndev->phydev) |
Ben Hutchings | 4f9dce23 | 2015-01-16 17:51:25 +0000 | [diff] [blame] | 1847 | return -ENODEV; |
| 1848 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1849 | spin_lock_irqsave(&mdp->lock, flags); |
Philippe Reynes | f08aff4 | 2016-08-10 00:04:49 +0200 | [diff] [blame] | 1850 | ret = phy_ethtool_ksettings_get(ndev->phydev, cmd); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1851 | spin_unlock_irqrestore(&mdp->lock, flags); |
| 1852 | |
| 1853 | return ret; |
| 1854 | } |
| 1855 | |
Philippe Reynes | f08aff4 | 2016-08-10 00:04:49 +0200 | [diff] [blame] | 1856 | static int sh_eth_set_link_ksettings(struct net_device *ndev, |
| 1857 | const struct ethtool_link_ksettings *cmd) |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1858 | { |
| 1859 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1860 | unsigned long flags; |
| 1861 | int ret; |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1862 | |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 1863 | if (!ndev->phydev) |
Ben Hutchings | 4f9dce23 | 2015-01-16 17:51:25 +0000 | [diff] [blame] | 1864 | return -ENODEV; |
| 1865 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1866 | spin_lock_irqsave(&mdp->lock, flags); |
| 1867 | |
| 1868 | /* disable tx and rx */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1869 | sh_eth_rcv_snd_disable(ndev); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1870 | |
Philippe Reynes | f08aff4 | 2016-08-10 00:04:49 +0200 | [diff] [blame] | 1871 | ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1872 | if (ret) |
| 1873 | goto error_exit; |
| 1874 | |
Philippe Reynes | f08aff4 | 2016-08-10 00:04:49 +0200 | [diff] [blame] | 1875 | if (cmd->base.duplex == DUPLEX_FULL) |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1876 | mdp->duplex = 1; |
| 1877 | else |
| 1878 | mdp->duplex = 0; |
| 1879 | |
| 1880 | if (mdp->cd->set_duplex) |
| 1881 | mdp->cd->set_duplex(ndev); |
| 1882 | |
| 1883 | error_exit: |
| 1884 | mdelay(1); |
| 1885 | |
| 1886 | /* enable tx and rx */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 1887 | sh_eth_rcv_snd_enable(ndev); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 1888 | |
| 1889 | spin_unlock_irqrestore(&mdp->lock, flags); |
| 1890 | |
| 1891 | return ret; |
| 1892 | } |
| 1893 | |
Ben Hutchings | 6b4b4fe | 2015-02-26 20:34:35 +0000 | [diff] [blame] | 1894 | /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the |
| 1895 | * version must be bumped as well. Just adding registers up to that |
| 1896 | * limit is fine, as long as the existing register indices don't |
| 1897 | * change. |
| 1898 | */ |
| 1899 | #define SH_ETH_REG_DUMP_VERSION 1 |
| 1900 | #define SH_ETH_REG_DUMP_MAX_REGS 256 |
| 1901 | |
| 1902 | static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) |
| 1903 | { |
| 1904 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 1905 | struct sh_eth_cpu_data *cd = mdp->cd; |
| 1906 | u32 *valid_map; |
| 1907 | size_t len; |
| 1908 | |
| 1909 | BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); |
| 1910 | |
| 1911 | /* Dump starts with a bitmap that tells ethtool which |
| 1912 | * registers are defined for this chip. |
| 1913 | */ |
| 1914 | len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); |
| 1915 | if (buf) { |
| 1916 | valid_map = buf; |
| 1917 | buf += len; |
| 1918 | } else { |
| 1919 | valid_map = NULL; |
| 1920 | } |
| 1921 | |
| 1922 | /* Add a register to the dump, if it has a defined offset. |
| 1923 | * This automatically skips most undefined registers, but for |
| 1924 | * some it is also necessary to check a capability flag in |
| 1925 | * struct sh_eth_cpu_data. |
| 1926 | */ |
| 1927 | #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) |
| 1928 | #define add_reg_from(reg, read_expr) do { \ |
| 1929 | if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ |
| 1930 | if (buf) { \ |
| 1931 | mark_reg_valid(reg); \ |
| 1932 | *buf++ = read_expr; \ |
| 1933 | } \ |
| 1934 | ++len; \ |
| 1935 | } \ |
| 1936 | } while (0) |
| 1937 | #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) |
| 1938 | #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) |
| 1939 | |
| 1940 | add_reg(EDSR); |
| 1941 | add_reg(EDMR); |
| 1942 | add_reg(EDTRR); |
| 1943 | add_reg(EDRRR); |
| 1944 | add_reg(EESR); |
| 1945 | add_reg(EESIPR); |
| 1946 | add_reg(TDLAR); |
| 1947 | add_reg(TDFAR); |
| 1948 | add_reg(TDFXR); |
| 1949 | add_reg(TDFFR); |
| 1950 | add_reg(RDLAR); |
| 1951 | add_reg(RDFAR); |
| 1952 | add_reg(RDFXR); |
| 1953 | add_reg(RDFFR); |
| 1954 | add_reg(TRSCER); |
| 1955 | add_reg(RMFCR); |
| 1956 | add_reg(TFTR); |
| 1957 | add_reg(FDR); |
| 1958 | add_reg(RMCR); |
| 1959 | add_reg(TFUCR); |
| 1960 | add_reg(RFOCR); |
| 1961 | if (cd->rmiimode) |
| 1962 | add_reg(RMIIMODE); |
| 1963 | add_reg(FCFTR); |
| 1964 | if (cd->rpadir) |
| 1965 | add_reg(RPADIR); |
| 1966 | if (!cd->no_trimd) |
| 1967 | add_reg(TRIMD); |
| 1968 | add_reg(ECMR); |
| 1969 | add_reg(ECSR); |
| 1970 | add_reg(ECSIPR); |
| 1971 | add_reg(PIR); |
| 1972 | if (!cd->no_psr) |
| 1973 | add_reg(PSR); |
| 1974 | add_reg(RDMLR); |
| 1975 | add_reg(RFLR); |
| 1976 | add_reg(IPGR); |
| 1977 | if (cd->apr) |
| 1978 | add_reg(APR); |
| 1979 | if (cd->mpr) |
| 1980 | add_reg(MPR); |
| 1981 | add_reg(RFCR); |
| 1982 | add_reg(RFCF); |
| 1983 | if (cd->tpauser) |
| 1984 | add_reg(TPAUSER); |
| 1985 | add_reg(TPAUSECR); |
| 1986 | add_reg(GECMR); |
| 1987 | if (cd->bculr) |
| 1988 | add_reg(BCULR); |
| 1989 | add_reg(MAHR); |
| 1990 | add_reg(MALR); |
| 1991 | add_reg(TROCR); |
| 1992 | add_reg(CDCR); |
| 1993 | add_reg(LCCR); |
| 1994 | add_reg(CNDCR); |
| 1995 | add_reg(CEFCR); |
| 1996 | add_reg(FRECR); |
| 1997 | add_reg(TSFRCR); |
| 1998 | add_reg(TLFRCR); |
| 1999 | add_reg(CERCR); |
| 2000 | add_reg(CEECR); |
| 2001 | add_reg(MAFCR); |
| 2002 | if (cd->rtrate) |
| 2003 | add_reg(RTRATE); |
| 2004 | if (cd->hw_crc) |
| 2005 | add_reg(CSMR); |
| 2006 | if (cd->select_mii) |
| 2007 | add_reg(RMII_MII); |
| 2008 | add_reg(ARSTR); |
| 2009 | if (cd->tsu) { |
| 2010 | add_tsu_reg(TSU_CTRST); |
| 2011 | add_tsu_reg(TSU_FWEN0); |
| 2012 | add_tsu_reg(TSU_FWEN1); |
| 2013 | add_tsu_reg(TSU_FCM); |
| 2014 | add_tsu_reg(TSU_BSYSL0); |
| 2015 | add_tsu_reg(TSU_BSYSL1); |
| 2016 | add_tsu_reg(TSU_PRISL0); |
| 2017 | add_tsu_reg(TSU_PRISL1); |
| 2018 | add_tsu_reg(TSU_FWSL0); |
| 2019 | add_tsu_reg(TSU_FWSL1); |
| 2020 | add_tsu_reg(TSU_FWSLC); |
| 2021 | add_tsu_reg(TSU_QTAG0); |
| 2022 | add_tsu_reg(TSU_QTAG1); |
| 2023 | add_tsu_reg(TSU_QTAGM0); |
| 2024 | add_tsu_reg(TSU_QTAGM1); |
| 2025 | add_tsu_reg(TSU_FWSR); |
| 2026 | add_tsu_reg(TSU_FWINMK); |
| 2027 | add_tsu_reg(TSU_ADQT0); |
| 2028 | add_tsu_reg(TSU_ADQT1); |
| 2029 | add_tsu_reg(TSU_VTAG0); |
| 2030 | add_tsu_reg(TSU_VTAG1); |
| 2031 | add_tsu_reg(TSU_ADSBSY); |
| 2032 | add_tsu_reg(TSU_TEN); |
| 2033 | add_tsu_reg(TSU_POST1); |
| 2034 | add_tsu_reg(TSU_POST2); |
| 2035 | add_tsu_reg(TSU_POST3); |
| 2036 | add_tsu_reg(TSU_POST4); |
| 2037 | if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { |
| 2038 | /* This is the start of a table, not just a single |
| 2039 | * register. |
| 2040 | */ |
| 2041 | if (buf) { |
| 2042 | unsigned int i; |
| 2043 | |
| 2044 | mark_reg_valid(TSU_ADRH0); |
| 2045 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) |
| 2046 | *buf++ = ioread32( |
| 2047 | mdp->tsu_addr + |
| 2048 | mdp->reg_offset[TSU_ADRH0] + |
| 2049 | i * 4); |
| 2050 | } |
| 2051 | len += SH_ETH_TSU_CAM_ENTRIES * 2; |
| 2052 | } |
| 2053 | } |
| 2054 | |
| 2055 | #undef mark_reg_valid |
| 2056 | #undef add_reg_from |
| 2057 | #undef add_reg |
| 2058 | #undef add_tsu_reg |
| 2059 | |
| 2060 | return len * 4; |
| 2061 | } |
| 2062 | |
| 2063 | static int sh_eth_get_regs_len(struct net_device *ndev) |
| 2064 | { |
| 2065 | return __sh_eth_get_regs(ndev, NULL); |
| 2066 | } |
| 2067 | |
| 2068 | static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, |
| 2069 | void *buf) |
| 2070 | { |
| 2071 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2072 | |
| 2073 | regs->version = SH_ETH_REG_DUMP_VERSION; |
| 2074 | |
| 2075 | pm_runtime_get_sync(&mdp->pdev->dev); |
| 2076 | __sh_eth_get_regs(ndev, buf); |
| 2077 | pm_runtime_put_sync(&mdp->pdev->dev); |
| 2078 | } |
| 2079 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2080 | static int sh_eth_nway_reset(struct net_device *ndev) |
| 2081 | { |
| 2082 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2083 | unsigned long flags; |
| 2084 | int ret; |
| 2085 | |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 2086 | if (!ndev->phydev) |
Ben Hutchings | 4f9dce23 | 2015-01-16 17:51:25 +0000 | [diff] [blame] | 2087 | return -ENODEV; |
| 2088 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2089 | spin_lock_irqsave(&mdp->lock, flags); |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 2090 | ret = phy_start_aneg(ndev->phydev); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2091 | spin_unlock_irqrestore(&mdp->lock, flags); |
| 2092 | |
| 2093 | return ret; |
| 2094 | } |
| 2095 | |
| 2096 | static u32 sh_eth_get_msglevel(struct net_device *ndev) |
| 2097 | { |
| 2098 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2099 | return mdp->msg_enable; |
| 2100 | } |
| 2101 | |
| 2102 | static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) |
| 2103 | { |
| 2104 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2105 | mdp->msg_enable = value; |
| 2106 | } |
| 2107 | |
| 2108 | static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { |
| 2109 | "rx_current", "tx_current", |
| 2110 | "rx_dirty", "tx_dirty", |
| 2111 | }; |
| 2112 | #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) |
| 2113 | |
| 2114 | static int sh_eth_get_sset_count(struct net_device *netdev, int sset) |
| 2115 | { |
| 2116 | switch (sset) { |
| 2117 | case ETH_SS_STATS: |
| 2118 | return SH_ETH_STATS_LEN; |
| 2119 | default: |
| 2120 | return -EOPNOTSUPP; |
| 2121 | } |
| 2122 | } |
| 2123 | |
| 2124 | static void sh_eth_get_ethtool_stats(struct net_device *ndev, |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 2125 | struct ethtool_stats *stats, u64 *data) |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2126 | { |
| 2127 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2128 | int i = 0; |
| 2129 | |
| 2130 | /* device-specific stats */ |
| 2131 | data[i++] = mdp->cur_rx; |
| 2132 | data[i++] = mdp->cur_tx; |
| 2133 | data[i++] = mdp->dirty_rx; |
| 2134 | data[i++] = mdp->dirty_tx; |
| 2135 | } |
| 2136 | |
| 2137 | static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) |
| 2138 | { |
| 2139 | switch (stringset) { |
| 2140 | case ETH_SS_STATS: |
| 2141 | memcpy(data, *sh_eth_gstrings_stats, |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 2142 | sizeof(sh_eth_gstrings_stats)); |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2143 | break; |
| 2144 | } |
| 2145 | } |
| 2146 | |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2147 | static void sh_eth_get_ringparam(struct net_device *ndev, |
| 2148 | struct ethtool_ringparam *ring) |
| 2149 | { |
| 2150 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2151 | |
| 2152 | ring->rx_max_pending = RX_RING_MAX; |
| 2153 | ring->tx_max_pending = TX_RING_MAX; |
| 2154 | ring->rx_pending = mdp->num_rx_ring; |
| 2155 | ring->tx_pending = mdp->num_tx_ring; |
| 2156 | } |
| 2157 | |
| 2158 | static int sh_eth_set_ringparam(struct net_device *ndev, |
| 2159 | struct ethtool_ringparam *ring) |
| 2160 | { |
| 2161 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2162 | int ret; |
| 2163 | |
| 2164 | if (ring->tx_pending > TX_RING_MAX || |
| 2165 | ring->rx_pending > RX_RING_MAX || |
| 2166 | ring->tx_pending < TX_RING_MIN || |
| 2167 | ring->rx_pending < RX_RING_MIN) |
| 2168 | return -EINVAL; |
| 2169 | if (ring->rx_mini_pending || ring->rx_jumbo_pending) |
| 2170 | return -EINVAL; |
| 2171 | |
| 2172 | if (netif_running(ndev)) { |
Ben Hutchings | bd88891 | 2015-01-22 12:40:25 +0000 | [diff] [blame] | 2173 | netif_device_detach(ndev); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2174 | netif_tx_disable(ndev); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2175 | |
Ben Hutchings | 283e38d | 2015-01-22 12:44:08 +0000 | [diff] [blame] | 2176 | /* Serialise with the interrupt handler and NAPI, then |
| 2177 | * disable interrupts. We have to clear the |
| 2178 | * irq_enabled flag first to ensure that interrupts |
| 2179 | * won't be re-enabled. |
| 2180 | */ |
| 2181 | mdp->irq_enabled = false; |
| 2182 | synchronize_irq(ndev->irq); |
| 2183 | napi_synchronize(&mdp->napi); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2184 | sh_eth_write(ndev, 0x0000, EESIPR); |
Ben Hutchings | 283e38d | 2015-01-22 12:44:08 +0000 | [diff] [blame] | 2185 | |
Ben Hutchings | 740c7f3 | 2015-01-27 00:49:32 +0000 | [diff] [blame] | 2186 | sh_eth_dev_exit(ndev); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2187 | |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 2188 | /* Free all the skbuffs in the Rx queue and the DMA buffers. */ |
Ben Hutchings | 084236d | 2015-01-22 12:41:34 +0000 | [diff] [blame] | 2189 | sh_eth_ring_free(ndev); |
Ben Hutchings | 084236d | 2015-01-22 12:41:34 +0000 | [diff] [blame] | 2190 | } |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2191 | |
| 2192 | /* Set new parameters */ |
| 2193 | mdp->num_rx_ring = ring->rx_pending; |
| 2194 | mdp->num_tx_ring = ring->tx_pending; |
| 2195 | |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2196 | if (netif_running(ndev)) { |
Ben Hutchings | 084236d | 2015-01-22 12:41:34 +0000 | [diff] [blame] | 2197 | ret = sh_eth_ring_init(ndev); |
| 2198 | if (ret < 0) { |
| 2199 | netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", |
| 2200 | __func__); |
| 2201 | return ret; |
| 2202 | } |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 2203 | ret = sh_eth_dev_init(ndev); |
Ben Hutchings | 084236d | 2015-01-22 12:41:34 +0000 | [diff] [blame] | 2204 | if (ret < 0) { |
| 2205 | netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", |
| 2206 | __func__); |
| 2207 | return ret; |
| 2208 | } |
| 2209 | |
Ben Hutchings | bd88891 | 2015-01-22 12:40:25 +0000 | [diff] [blame] | 2210 | netif_device_attach(ndev); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2211 | } |
| 2212 | |
| 2213 | return 0; |
| 2214 | } |
| 2215 | |
stephen hemminger | 9b07be4 | 2012-01-04 12:59:49 +0000 | [diff] [blame] | 2216 | static const struct ethtool_ops sh_eth_ethtool_ops = { |
Ben Hutchings | 6b4b4fe | 2015-02-26 20:34:35 +0000 | [diff] [blame] | 2217 | .get_regs_len = sh_eth_get_regs_len, |
| 2218 | .get_regs = sh_eth_get_regs, |
stephen hemminger | 9b07be4 | 2012-01-04 12:59:49 +0000 | [diff] [blame] | 2219 | .nway_reset = sh_eth_nway_reset, |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2220 | .get_msglevel = sh_eth_get_msglevel, |
| 2221 | .set_msglevel = sh_eth_set_msglevel, |
stephen hemminger | 9b07be4 | 2012-01-04 12:59:49 +0000 | [diff] [blame] | 2222 | .get_link = ethtool_op_get_link, |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2223 | .get_strings = sh_eth_get_strings, |
| 2224 | .get_ethtool_stats = sh_eth_get_ethtool_stats, |
| 2225 | .get_sset_count = sh_eth_get_sset_count, |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2226 | .get_ringparam = sh_eth_get_ringparam, |
| 2227 | .set_ringparam = sh_eth_set_ringparam, |
Philippe Reynes | f08aff4 | 2016-08-10 00:04:49 +0200 | [diff] [blame] | 2228 | .get_link_ksettings = sh_eth_get_link_ksettings, |
| 2229 | .set_link_ksettings = sh_eth_set_link_ksettings, |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 2230 | }; |
| 2231 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2232 | /* network device open function */ |
| 2233 | static int sh_eth_open(struct net_device *ndev) |
| 2234 | { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2235 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Sergei Shtylyov | 4fa8c3c | 2016-03-13 01:29:45 +0300 | [diff] [blame] | 2236 | int ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2237 | |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 2238 | pm_runtime_get_sync(&mdp->pdev->dev); |
| 2239 | |
Sergei Shtylyov | d2779e9 | 2013-09-04 02:41:27 +0400 | [diff] [blame] | 2240 | napi_enable(&mdp->napi); |
| 2241 | |
Joe Perches | a0607fd | 2009-11-18 23:29:17 -0800 | [diff] [blame] | 2242 | ret = request_irq(ndev->irq, sh_eth_interrupt, |
Nobuhiro Iwamatsu | 5b3dfd1 | 2013-06-06 09:49:30 +0000 | [diff] [blame] | 2243 | mdp->cd->irq_flags, ndev->name, ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2244 | if (ret) { |
Sergei Shtylyov | da24685 | 2014-03-15 03:29:14 +0300 | [diff] [blame] | 2245 | netdev_err(ndev, "Can not assign IRQ number\n"); |
Sergei Shtylyov | d2779e9 | 2013-09-04 02:41:27 +0400 | [diff] [blame] | 2246 | goto out_napi_off; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2247 | } |
| 2248 | |
| 2249 | /* Descriptor set */ |
| 2250 | ret = sh_eth_ring_init(ndev); |
| 2251 | if (ret) |
| 2252 | goto out_free_irq; |
| 2253 | |
| 2254 | /* device init */ |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 2255 | ret = sh_eth_dev_init(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2256 | if (ret) |
| 2257 | goto out_free_irq; |
| 2258 | |
| 2259 | /* PHY control start*/ |
| 2260 | ret = sh_eth_phy_start(ndev); |
| 2261 | if (ret) |
| 2262 | goto out_free_irq; |
| 2263 | |
Sergei Shtylyov | ad846aa | 2016-03-14 01:09:53 +0300 | [diff] [blame] | 2264 | netif_start_queue(ndev); |
| 2265 | |
Mitsuhiro Kimura | 7fa2955 | 2014-11-28 10:04:15 +0900 | [diff] [blame] | 2266 | mdp->is_opened = 1; |
| 2267 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2268 | return ret; |
| 2269 | |
| 2270 | out_free_irq: |
| 2271 | free_irq(ndev->irq, ndev); |
Sergei Shtylyov | d2779e9 | 2013-09-04 02:41:27 +0400 | [diff] [blame] | 2272 | out_napi_off: |
| 2273 | napi_disable(&mdp->napi); |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 2274 | pm_runtime_put_sync(&mdp->pdev->dev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2275 | return ret; |
| 2276 | } |
| 2277 | |
| 2278 | /* Timeout function */ |
| 2279 | static void sh_eth_tx_timeout(struct net_device *ndev) |
| 2280 | { |
| 2281 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2282 | struct sh_eth_rxdesc *rxdesc; |
| 2283 | int i; |
| 2284 | |
| 2285 | netif_stop_queue(ndev); |
| 2286 | |
Sergei Shtylyov | 8d5009f | 2014-03-15 03:30:59 +0300 | [diff] [blame] | 2287 | netif_err(mdp, timer, ndev, |
| 2288 | "transmit timed out, status %8.8x, resetting...\n", |
Geert Uytterhoeven | 0799c2d | 2015-01-15 11:54:28 +0100 | [diff] [blame] | 2289 | sh_eth_read(ndev, EESR)); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2290 | |
| 2291 | /* tx_errors count up */ |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 2292 | ndev->stats.tx_errors++; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2293 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2294 | /* Free all the skbuffs in the Rx queue. */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2295 | for (i = 0; i < mdp->num_rx_ring; i++) { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2296 | rxdesc = &mdp->rx_ring[i]; |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 2297 | rxdesc->status = cpu_to_le32(0); |
| 2298 | rxdesc->addr = cpu_to_le32(0xBADF00D0); |
Sergei Shtylyov | 179d80a | 2014-06-28 04:10:00 +0400 | [diff] [blame] | 2299 | dev_kfree_skb(mdp->rx_skbuff[i]); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2300 | mdp->rx_skbuff[i] = NULL; |
| 2301 | } |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2302 | for (i = 0; i < mdp->num_tx_ring; i++) { |
Sergei Shtylyov | 179d80a | 2014-06-28 04:10:00 +0400 | [diff] [blame] | 2303 | dev_kfree_skb(mdp->tx_skbuff[i]); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2304 | mdp->tx_skbuff[i] = NULL; |
| 2305 | } |
| 2306 | |
| 2307 | /* device init */ |
Sergei Shtylyov | f796721 | 2016-04-24 19:11:07 +0300 | [diff] [blame] | 2308 | sh_eth_dev_init(ndev); |
Sergei Shtylyov | ad846aa | 2016-03-14 01:09:53 +0300 | [diff] [blame] | 2309 | |
| 2310 | netif_start_queue(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2311 | } |
| 2312 | |
| 2313 | /* Packet transmit function */ |
| 2314 | static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
| 2315 | { |
| 2316 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2317 | struct sh_eth_txdesc *txdesc; |
Sergei Shtylyov | 1299653 | 2015-12-13 23:05:07 +0300 | [diff] [blame] | 2318 | dma_addr_t dma_addr; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2319 | u32 entry; |
Nobuhiro Iwamatsu | fb5e2f9 | 2008-11-17 20:29:58 +0000 | [diff] [blame] | 2320 | unsigned long flags; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2321 | |
| 2322 | spin_lock_irqsave(&mdp->lock, flags); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2323 | if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { |
Sergei Shtylyov | e344e97 | 2017-04-17 15:55:22 +0300 | [diff] [blame] | 2324 | if (!sh_eth_tx_free(ndev, true)) { |
Sergei Shtylyov | 8d5009f | 2014-03-15 03:30:59 +0300 | [diff] [blame] | 2325 | netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2326 | netif_stop_queue(ndev); |
| 2327 | spin_unlock_irqrestore(&mdp->lock, flags); |
Patrick McHardy | 5b54814 | 2009-06-12 06:22:29 +0000 | [diff] [blame] | 2328 | return NETDEV_TX_BUSY; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2329 | } |
| 2330 | } |
| 2331 | spin_unlock_irqrestore(&mdp->lock, flags); |
| 2332 | |
Ben Hutchings | dacc73e | 2015-03-03 00:53:08 +0000 | [diff] [blame] | 2333 | if (skb_put_padto(skb, ETH_ZLEN)) |
Ben Hutchings | eebfb64 | 2015-01-22 12:40:13 +0000 | [diff] [blame] | 2334 | return NETDEV_TX_OK; |
| 2335 | |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2336 | entry = mdp->cur_tx % mdp->num_tx_ring; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2337 | mdp->tx_skbuff[entry] = skb; |
| 2338 | txdesc = &mdp->tx_ring[entry]; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2339 | /* soft swap. */ |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 2340 | if (!mdp->cd->hw_swap) |
Sergei Shtylyov | 3e23099 | 2015-12-13 21:27:04 +0300 | [diff] [blame] | 2341 | sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); |
Sergei Shtylyov | 1299653 | 2015-12-13 23:05:07 +0300 | [diff] [blame] | 2342 | dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len, |
| 2343 | DMA_TO_DEVICE); |
| 2344 | if (dma_mapping_error(&ndev->dev, dma_addr)) { |
Ben Hutchings | aa3933b | 2015-01-27 00:49:47 +0000 | [diff] [blame] | 2345 | kfree_skb(skb); |
| 2346 | return NETDEV_TX_OK; |
| 2347 | } |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 2348 | txdesc->addr = cpu_to_le32(dma_addr); |
| 2349 | txdesc->len = cpu_to_le32(skb->len << 16); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2350 | |
Sergei Shtylyov | f32bfb9 | 2015-11-03 22:36:04 +0300 | [diff] [blame] | 2351 | dma_wmb(); /* TACT bit must be set after all the above writes */ |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 2352 | if (entry >= mdp->num_tx_ring - 1) |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 2353 | txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2354 | else |
Sergei Shtylyov | 7cf7247 | 2015-12-28 02:10:47 +0300 | [diff] [blame] | 2355 | txdesc->status |= cpu_to_le32(TD_TACT); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2356 | |
| 2357 | mdp->cur_tx++; |
| 2358 | |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 2359 | if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) |
| 2360 | sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); |
Nobuhiro Iwamatsu | b0ca2a2 | 2008-06-30 11:08:17 +0900 | [diff] [blame] | 2361 | |
Patrick McHardy | 6ed1065 | 2009-06-23 06:03:08 +0000 | [diff] [blame] | 2362 | return NETDEV_TX_OK; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2363 | } |
| 2364 | |
Ben Hutchings | 4398f9c | 2015-02-26 20:35:05 +0000 | [diff] [blame] | 2365 | /* The statistics registers have write-clear behaviour, which means we |
| 2366 | * will lose any increment between the read and write. We mitigate |
| 2367 | * this by only clearing when we read a non-zero value, so we will |
| 2368 | * never falsely report a total of zero. |
| 2369 | */ |
| 2370 | static void |
| 2371 | sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) |
| 2372 | { |
| 2373 | u32 delta = sh_eth_read(ndev, reg); |
| 2374 | |
| 2375 | if (delta) { |
| 2376 | *stat += delta; |
| 2377 | sh_eth_write(ndev, 0, reg); |
| 2378 | } |
| 2379 | } |
| 2380 | |
Mitsuhiro Kimura | 7fa2955 | 2014-11-28 10:04:15 +0900 | [diff] [blame] | 2381 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) |
| 2382 | { |
| 2383 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2384 | |
| 2385 | if (sh_eth_is_rz_fast_ether(mdp)) |
| 2386 | return &ndev->stats; |
| 2387 | |
| 2388 | if (!mdp->is_opened) |
| 2389 | return &ndev->stats; |
| 2390 | |
Ben Hutchings | 4398f9c | 2015-02-26 20:35:05 +0000 | [diff] [blame] | 2391 | sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); |
| 2392 | sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); |
| 2393 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); |
Mitsuhiro Kimura | 7fa2955 | 2014-11-28 10:04:15 +0900 | [diff] [blame] | 2394 | |
| 2395 | if (sh_eth_is_gether(mdp)) { |
Ben Hutchings | 4398f9c | 2015-02-26 20:35:05 +0000 | [diff] [blame] | 2396 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, |
| 2397 | CERCR); |
| 2398 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, |
| 2399 | CEECR); |
Mitsuhiro Kimura | 7fa2955 | 2014-11-28 10:04:15 +0900 | [diff] [blame] | 2400 | } else { |
Ben Hutchings | 4398f9c | 2015-02-26 20:35:05 +0000 | [diff] [blame] | 2401 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, |
| 2402 | CNDCR); |
Mitsuhiro Kimura | 7fa2955 | 2014-11-28 10:04:15 +0900 | [diff] [blame] | 2403 | } |
| 2404 | |
| 2405 | return &ndev->stats; |
| 2406 | } |
| 2407 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2408 | /* device close function */ |
| 2409 | static int sh_eth_close(struct net_device *ndev) |
| 2410 | { |
| 2411 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2412 | |
| 2413 | netif_stop_queue(ndev); |
| 2414 | |
Ben Hutchings | 283e38d | 2015-01-22 12:44:08 +0000 | [diff] [blame] | 2415 | /* Serialise with the interrupt handler and NAPI, then disable |
| 2416 | * interrupts. We have to clear the irq_enabled flag first to |
| 2417 | * ensure that interrupts won't be re-enabled. |
| 2418 | */ |
| 2419 | mdp->irq_enabled = false; |
| 2420 | synchronize_irq(ndev->irq); |
| 2421 | napi_disable(&mdp->napi); |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2422 | sh_eth_write(ndev, 0x0000, EESIPR); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2423 | |
Ben Hutchings | 740c7f3 | 2015-01-27 00:49:32 +0000 | [diff] [blame] | 2424 | sh_eth_dev_exit(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2425 | |
| 2426 | /* PHY Disconnect */ |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 2427 | if (ndev->phydev) { |
| 2428 | phy_stop(ndev->phydev); |
| 2429 | phy_disconnect(ndev->phydev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2430 | } |
| 2431 | |
| 2432 | free_irq(ndev->irq, ndev); |
| 2433 | |
Sergei Shtylyov | 8e03a5e | 2015-11-04 00:55:13 +0300 | [diff] [blame] | 2434 | /* Free all the skbuffs in the Rx queue and the DMA buffer. */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2435 | sh_eth_ring_free(ndev); |
| 2436 | |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 2437 | pm_runtime_put_sync(&mdp->pdev->dev); |
| 2438 | |
Mitsuhiro Kimura | 7fa2955 | 2014-11-28 10:04:15 +0900 | [diff] [blame] | 2439 | mdp->is_opened = 0; |
| 2440 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2441 | return 0; |
| 2442 | } |
| 2443 | |
Eric Dumazet | bb7d92e | 2012-02-06 22:17:21 +0000 | [diff] [blame] | 2444 | /* ioctl to device function */ |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 2445 | static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2446 | { |
Philippe Reynes | 9fd0375 | 2016-08-10 00:04:48 +0200 | [diff] [blame] | 2447 | struct phy_device *phydev = ndev->phydev; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2448 | |
| 2449 | if (!netif_running(ndev)) |
| 2450 | return -EINVAL; |
| 2451 | |
| 2452 | if (!phydev) |
| 2453 | return -ENODEV; |
| 2454 | |
Richard Cochran | 28b0411 | 2010-07-17 08:48:55 +0000 | [diff] [blame] | 2455 | return phy_mii_ioctl(phydev, rq, cmd); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2456 | } |
| 2457 | |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2458 | /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ |
| 2459 | static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, |
| 2460 | int entry) |
| 2461 | { |
| 2462 | return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); |
| 2463 | } |
| 2464 | |
| 2465 | static u32 sh_eth_tsu_get_post_mask(int entry) |
| 2466 | { |
| 2467 | return 0x0f << (28 - ((entry % 8) * 4)); |
| 2468 | } |
| 2469 | |
| 2470 | static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) |
| 2471 | { |
| 2472 | return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); |
| 2473 | } |
| 2474 | |
| 2475 | static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, |
| 2476 | int entry) |
| 2477 | { |
| 2478 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2479 | u32 tmp; |
| 2480 | void *reg_offset; |
| 2481 | |
| 2482 | reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); |
| 2483 | tmp = ioread32(reg_offset); |
| 2484 | iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); |
| 2485 | } |
| 2486 | |
| 2487 | static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, |
| 2488 | int entry) |
| 2489 | { |
| 2490 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2491 | u32 post_mask, ref_mask, tmp; |
| 2492 | void *reg_offset; |
| 2493 | |
| 2494 | reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); |
| 2495 | post_mask = sh_eth_tsu_get_post_mask(entry); |
| 2496 | ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; |
| 2497 | |
| 2498 | tmp = ioread32(reg_offset); |
| 2499 | iowrite32(tmp & ~post_mask, reg_offset); |
| 2500 | |
| 2501 | /* If other port enables, the function returns "true" */ |
| 2502 | return tmp & ref_mask; |
| 2503 | } |
| 2504 | |
| 2505 | static int sh_eth_tsu_busy(struct net_device *ndev) |
| 2506 | { |
| 2507 | int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; |
| 2508 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2509 | |
| 2510 | while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { |
| 2511 | udelay(10); |
| 2512 | timeout--; |
| 2513 | if (timeout <= 0) { |
Sergei Shtylyov | da24685 | 2014-03-15 03:29:14 +0300 | [diff] [blame] | 2514 | netdev_err(ndev, "%s: timeout\n", __func__); |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2515 | return -ETIMEDOUT; |
| 2516 | } |
| 2517 | } |
| 2518 | |
| 2519 | return 0; |
| 2520 | } |
| 2521 | |
| 2522 | static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, |
| 2523 | const u8 *addr) |
| 2524 | { |
| 2525 | u32 val; |
| 2526 | |
| 2527 | val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; |
| 2528 | iowrite32(val, reg); |
| 2529 | if (sh_eth_tsu_busy(ndev) < 0) |
| 2530 | return -EBUSY; |
| 2531 | |
| 2532 | val = addr[4] << 8 | addr[5]; |
| 2533 | iowrite32(val, reg + 4); |
| 2534 | if (sh_eth_tsu_busy(ndev) < 0) |
| 2535 | return -EBUSY; |
| 2536 | |
| 2537 | return 0; |
| 2538 | } |
| 2539 | |
| 2540 | static void sh_eth_tsu_read_entry(void *reg, u8 *addr) |
| 2541 | { |
| 2542 | u32 val; |
| 2543 | |
| 2544 | val = ioread32(reg); |
| 2545 | addr[0] = (val >> 24) & 0xff; |
| 2546 | addr[1] = (val >> 16) & 0xff; |
| 2547 | addr[2] = (val >> 8) & 0xff; |
| 2548 | addr[3] = val & 0xff; |
| 2549 | val = ioread32(reg + 4); |
| 2550 | addr[4] = (val >> 8) & 0xff; |
| 2551 | addr[5] = val & 0xff; |
| 2552 | } |
| 2553 | |
| 2554 | |
| 2555 | static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) |
| 2556 | { |
| 2557 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2558 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); |
| 2559 | int i; |
| 2560 | u8 c_addr[ETH_ALEN]; |
| 2561 | |
| 2562 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { |
| 2563 | sh_eth_tsu_read_entry(reg_offset, c_addr); |
dingtianhong | c4bde29 | 2013-12-30 15:41:17 +0800 | [diff] [blame] | 2564 | if (ether_addr_equal(addr, c_addr)) |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2565 | return i; |
| 2566 | } |
| 2567 | |
| 2568 | return -ENOENT; |
| 2569 | } |
| 2570 | |
| 2571 | static int sh_eth_tsu_find_empty(struct net_device *ndev) |
| 2572 | { |
| 2573 | u8 blank[ETH_ALEN]; |
| 2574 | int entry; |
| 2575 | |
| 2576 | memset(blank, 0, sizeof(blank)); |
| 2577 | entry = sh_eth_tsu_find_entry(ndev, blank); |
| 2578 | return (entry < 0) ? -ENOMEM : entry; |
| 2579 | } |
| 2580 | |
| 2581 | static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, |
| 2582 | int entry) |
| 2583 | { |
| 2584 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2585 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); |
| 2586 | int ret; |
| 2587 | u8 blank[ETH_ALEN]; |
| 2588 | |
| 2589 | sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & |
| 2590 | ~(1 << (31 - entry)), TSU_TEN); |
| 2591 | |
| 2592 | memset(blank, 0, sizeof(blank)); |
| 2593 | ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); |
| 2594 | if (ret < 0) |
| 2595 | return ret; |
| 2596 | return 0; |
| 2597 | } |
| 2598 | |
| 2599 | static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) |
| 2600 | { |
| 2601 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2602 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); |
| 2603 | int i, ret; |
| 2604 | |
| 2605 | if (!mdp->cd->tsu) |
| 2606 | return 0; |
| 2607 | |
| 2608 | i = sh_eth_tsu_find_entry(ndev, addr); |
| 2609 | if (i < 0) { |
| 2610 | /* No entry found, create one */ |
| 2611 | i = sh_eth_tsu_find_empty(ndev); |
| 2612 | if (i < 0) |
| 2613 | return -ENOMEM; |
| 2614 | ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); |
| 2615 | if (ret < 0) |
| 2616 | return ret; |
| 2617 | |
| 2618 | /* Enable the entry */ |
| 2619 | sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | |
| 2620 | (1 << (31 - i)), TSU_TEN); |
| 2621 | } |
| 2622 | |
| 2623 | /* Entry found or created, enable POST */ |
| 2624 | sh_eth_tsu_enable_cam_entry_post(ndev, i); |
| 2625 | |
| 2626 | return 0; |
| 2627 | } |
| 2628 | |
| 2629 | static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) |
| 2630 | { |
| 2631 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2632 | int i, ret; |
| 2633 | |
| 2634 | if (!mdp->cd->tsu) |
| 2635 | return 0; |
| 2636 | |
| 2637 | i = sh_eth_tsu_find_entry(ndev, addr); |
| 2638 | if (i) { |
| 2639 | /* Entry found */ |
| 2640 | if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) |
| 2641 | goto done; |
| 2642 | |
| 2643 | /* Disable the entry if both ports was disabled */ |
| 2644 | ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); |
| 2645 | if (ret < 0) |
| 2646 | return ret; |
| 2647 | } |
| 2648 | done: |
| 2649 | return 0; |
| 2650 | } |
| 2651 | |
| 2652 | static int sh_eth_tsu_purge_all(struct net_device *ndev) |
| 2653 | { |
| 2654 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2655 | int i, ret; |
| 2656 | |
Ben Hutchings | b37feed | 2015-01-16 17:51:12 +0000 | [diff] [blame] | 2657 | if (!mdp->cd->tsu) |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2658 | return 0; |
| 2659 | |
| 2660 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { |
| 2661 | if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) |
| 2662 | continue; |
| 2663 | |
| 2664 | /* Disable the entry if both ports was disabled */ |
| 2665 | ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); |
| 2666 | if (ret < 0) |
| 2667 | return ret; |
| 2668 | } |
| 2669 | |
| 2670 | return 0; |
| 2671 | } |
| 2672 | |
| 2673 | static void sh_eth_tsu_purge_mcast(struct net_device *ndev) |
| 2674 | { |
| 2675 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2676 | u8 addr[ETH_ALEN]; |
| 2677 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); |
| 2678 | int i; |
| 2679 | |
Ben Hutchings | b37feed | 2015-01-16 17:51:12 +0000 | [diff] [blame] | 2680 | if (!mdp->cd->tsu) |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2681 | return; |
| 2682 | |
| 2683 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { |
| 2684 | sh_eth_tsu_read_entry(reg_offset, addr); |
| 2685 | if (is_multicast_ether_addr(addr)) |
| 2686 | sh_eth_tsu_del_entry(ndev, addr); |
| 2687 | } |
| 2688 | } |
| 2689 | |
Ben Hutchings | b37feed | 2015-01-16 17:51:12 +0000 | [diff] [blame] | 2690 | /* Update promiscuous flag and multicast filter */ |
| 2691 | static void sh_eth_set_rx_mode(struct net_device *ndev) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2692 | { |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2693 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2694 | u32 ecmr_bits; |
| 2695 | int mcast_all = 0; |
| 2696 | unsigned long flags; |
| 2697 | |
| 2698 | spin_lock_irqsave(&mdp->lock, flags); |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 2699 | /* Initial condition is MCT = 1, PRM = 0. |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2700 | * Depending on ndev->flags, set PRM or clear MCT |
| 2701 | */ |
Ben Hutchings | b37feed | 2015-01-16 17:51:12 +0000 | [diff] [blame] | 2702 | ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; |
| 2703 | if (mdp->cd->tsu) |
| 2704 | ecmr_bits |= ECMR_MCT; |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2705 | |
| 2706 | if (!(ndev->flags & IFF_MULTICAST)) { |
| 2707 | sh_eth_tsu_purge_mcast(ndev); |
| 2708 | mcast_all = 1; |
| 2709 | } |
| 2710 | if (ndev->flags & IFF_ALLMULTI) { |
| 2711 | sh_eth_tsu_purge_mcast(ndev); |
| 2712 | ecmr_bits &= ~ECMR_MCT; |
| 2713 | mcast_all = 1; |
| 2714 | } |
| 2715 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2716 | if (ndev->flags & IFF_PROMISC) { |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2717 | sh_eth_tsu_purge_all(ndev); |
| 2718 | ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; |
| 2719 | } else if (mdp->cd->tsu) { |
| 2720 | struct netdev_hw_addr *ha; |
| 2721 | netdev_for_each_mc_addr(ha, ndev) { |
| 2722 | if (mcast_all && is_multicast_ether_addr(ha->addr)) |
| 2723 | continue; |
| 2724 | |
| 2725 | if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { |
| 2726 | if (!mcast_all) { |
| 2727 | sh_eth_tsu_purge_mcast(ndev); |
| 2728 | ecmr_bits &= ~ECMR_MCT; |
| 2729 | mcast_all = 1; |
| 2730 | } |
| 2731 | } |
| 2732 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2733 | } |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 2734 | |
| 2735 | /* update the ethernet mode */ |
| 2736 | sh_eth_write(ndev, ecmr_bits, ECMR); |
| 2737 | |
| 2738 | spin_unlock_irqrestore(&mdp->lock, flags); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2739 | } |
Yoshihiro Shimoda | 71cc7c3 | 2012-02-15 17:55:06 +0000 | [diff] [blame] | 2740 | |
| 2741 | static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) |
| 2742 | { |
| 2743 | if (!mdp->port) |
| 2744 | return TSU_VTAG0; |
| 2745 | else |
| 2746 | return TSU_VTAG1; |
| 2747 | } |
| 2748 | |
Patrick McHardy | 80d5c36 | 2013-04-19 02:04:28 +0000 | [diff] [blame] | 2749 | static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, |
| 2750 | __be16 proto, u16 vid) |
Yoshihiro Shimoda | 71cc7c3 | 2012-02-15 17:55:06 +0000 | [diff] [blame] | 2751 | { |
| 2752 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2753 | int vtag_reg_index = sh_eth_get_vtag_index(mdp); |
| 2754 | |
| 2755 | if (unlikely(!mdp->cd->tsu)) |
| 2756 | return -EPERM; |
| 2757 | |
| 2758 | /* No filtering if vid = 0 */ |
| 2759 | if (!vid) |
| 2760 | return 0; |
| 2761 | |
| 2762 | mdp->vlan_num_ids++; |
| 2763 | |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 2764 | /* The controller has one VLAN tag HW filter. So, if the filter is |
Yoshihiro Shimoda | 71cc7c3 | 2012-02-15 17:55:06 +0000 | [diff] [blame] | 2765 | * already enabled, the driver disables it and the filte |
| 2766 | */ |
| 2767 | if (mdp->vlan_num_ids > 1) { |
| 2768 | /* disable VLAN filter */ |
| 2769 | sh_eth_tsu_write(mdp, 0, vtag_reg_index); |
| 2770 | return 0; |
| 2771 | } |
| 2772 | |
| 2773 | sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), |
| 2774 | vtag_reg_index); |
| 2775 | |
| 2776 | return 0; |
| 2777 | } |
| 2778 | |
Patrick McHardy | 80d5c36 | 2013-04-19 02:04:28 +0000 | [diff] [blame] | 2779 | static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, |
| 2780 | __be16 proto, u16 vid) |
Yoshihiro Shimoda | 71cc7c3 | 2012-02-15 17:55:06 +0000 | [diff] [blame] | 2781 | { |
| 2782 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 2783 | int vtag_reg_index = sh_eth_get_vtag_index(mdp); |
| 2784 | |
| 2785 | if (unlikely(!mdp->cd->tsu)) |
| 2786 | return -EPERM; |
| 2787 | |
| 2788 | /* No filtering if vid = 0 */ |
| 2789 | if (!vid) |
| 2790 | return 0; |
| 2791 | |
| 2792 | mdp->vlan_num_ids--; |
| 2793 | sh_eth_tsu_write(mdp, 0, vtag_reg_index); |
| 2794 | |
| 2795 | return 0; |
| 2796 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2797 | |
| 2798 | /* SuperH's TSU register init function */ |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2799 | static void sh_eth_tsu_init(struct sh_eth_private *mdp) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2800 | { |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 2801 | if (sh_eth_is_rz_fast_ether(mdp)) { |
| 2802 | sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ |
Chris Brandt | e148788 | 2016-09-07 14:57:09 -0400 | [diff] [blame] | 2803 | sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, |
| 2804 | TSU_FWSLC); /* Enable POST registers */ |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 2805 | return; |
| 2806 | } |
| 2807 | |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2808 | sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ |
| 2809 | sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ |
| 2810 | sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ |
| 2811 | sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); |
| 2812 | sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); |
| 2813 | sh_eth_tsu_write(mdp, 0, TSU_PRISL0); |
| 2814 | sh_eth_tsu_write(mdp, 0, TSU_PRISL1); |
| 2815 | sh_eth_tsu_write(mdp, 0, TSU_FWSL0); |
| 2816 | sh_eth_tsu_write(mdp, 0, TSU_FWSL1); |
| 2817 | sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); |
Yoshihiro Shimoda | c5ed536 | 2011-03-07 21:59:38 +0000 | [diff] [blame] | 2818 | if (sh_eth_is_gether(mdp)) { |
| 2819 | sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ |
| 2820 | sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ |
| 2821 | } else { |
| 2822 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ |
| 2823 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ |
| 2824 | } |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2825 | sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ |
| 2826 | sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ |
| 2827 | sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ |
| 2828 | sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ |
| 2829 | sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ |
| 2830 | sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ |
| 2831 | sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2832 | } |
| 2833 | |
| 2834 | /* MDIO bus release function */ |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2835 | static int sh_mdio_release(struct sh_eth_private *mdp) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2836 | { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2837 | /* unregister mdio bus */ |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2838 | mdiobus_unregister(mdp->mii_bus); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2839 | |
| 2840 | /* free bitbang info */ |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2841 | free_mdio_bitbang(mdp->mii_bus); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2842 | |
| 2843 | return 0; |
| 2844 | } |
| 2845 | |
| 2846 | /* MDIO bus init function */ |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2847 | static int sh_mdio_init(struct sh_eth_private *mdp, |
Yoshihiro Shimoda | b3017e6 | 2011-03-07 21:59:55 +0000 | [diff] [blame] | 2848 | struct sh_eth_plat_data *pd) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2849 | { |
Andrew Lunn | e7f4dc3 | 2016-01-06 20:11:15 +0100 | [diff] [blame] | 2850 | int ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2851 | struct bb_info *bitbang; |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2852 | struct platform_device *pdev = mdp->pdev; |
Laurent Pinchart | aa8d422 | 2014-03-20 15:00:31 +0100 | [diff] [blame] | 2853 | struct device *dev = &mdp->pdev->dev; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2854 | |
| 2855 | /* create bit control struct for PHY */ |
Laurent Pinchart | aa8d422 | 2014-03-20 15:00:31 +0100 | [diff] [blame] | 2856 | bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); |
Laurent Pinchart | f738a13 | 2014-03-20 15:00:35 +0100 | [diff] [blame] | 2857 | if (!bitbang) |
| 2858 | return -ENOMEM; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2859 | |
| 2860 | /* bitbang init */ |
Yoshihiro Shimoda | ae70644 | 2011-09-27 21:48:58 +0000 | [diff] [blame] | 2861 | bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; |
Yoshihiro Shimoda | b3017e6 | 2011-03-07 21:59:55 +0000 | [diff] [blame] | 2862 | bitbang->set_gate = pd->set_mdio_gate; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2863 | bitbang->ctrl.ops = &bb_ops; |
| 2864 | |
Stefan Weil | c2e07b3 | 2010-08-03 19:44:52 +0200 | [diff] [blame] | 2865 | /* MII controller setting */ |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2866 | mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); |
Laurent Pinchart | f738a13 | 2014-03-20 15:00:35 +0100 | [diff] [blame] | 2867 | if (!mdp->mii_bus) |
| 2868 | return -ENOMEM; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2869 | |
| 2870 | /* Hook up MII support for ethtool */ |
| 2871 | mdp->mii_bus->name = "sh_mii"; |
Laurent Pinchart | a5bd6060 | 2014-03-20 15:00:32 +0100 | [diff] [blame] | 2872 | mdp->mii_bus->parent = dev; |
Florian Fainelli | 5278fb5 | 2012-01-09 23:59:17 +0000 | [diff] [blame] | 2873 | snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2874 | pdev->name, pdev->id); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2875 | |
Laurent Pinchart | bd920ff | 2014-03-20 15:00:33 +0100 | [diff] [blame] | 2876 | /* register MDIO bus */ |
| 2877 | if (dev->of_node) { |
| 2878 | ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 2879 | } else { |
Ben Dooks | 702eca0 | 2014-03-12 17:47:40 +0000 | [diff] [blame] | 2880 | if (pd->phy_irq > 0) |
| 2881 | mdp->mii_bus->irq[pd->phy] = pd->phy_irq; |
| 2882 | |
| 2883 | ret = mdiobus_register(mdp->mii_bus); |
| 2884 | } |
| 2885 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2886 | if (ret) |
Sergei Shtylyov | d5e07e6 | 2013-03-21 10:41:11 +0000 | [diff] [blame] | 2887 | goto out_free_bus; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2888 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2889 | return 0; |
| 2890 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2891 | out_free_bus: |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 2892 | free_mdio_bitbang(mdp->mii_bus); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2893 | return ret; |
| 2894 | } |
| 2895 | |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2896 | static const u16 *sh_eth_get_register_offset(int register_type) |
| 2897 | { |
| 2898 | const u16 *reg_offset = NULL; |
| 2899 | |
| 2900 | switch (register_type) { |
| 2901 | case SH_ETH_REG_GIGABIT: |
| 2902 | reg_offset = sh_eth_offset_gigabit; |
| 2903 | break; |
Simon Horman | db89347 | 2014-01-17 09:22:28 +0900 | [diff] [blame] | 2904 | case SH_ETH_REG_FAST_RZ: |
| 2905 | reg_offset = sh_eth_offset_fast_rz; |
| 2906 | break; |
Sergei Shtylyov | a3f109b | 2013-03-28 11:51:31 +0000 | [diff] [blame] | 2907 | case SH_ETH_REG_FAST_RCAR: |
| 2908 | reg_offset = sh_eth_offset_fast_rcar; |
| 2909 | break; |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2910 | case SH_ETH_REG_FAST_SH4: |
| 2911 | reg_offset = sh_eth_offset_fast_sh4; |
| 2912 | break; |
| 2913 | case SH_ETH_REG_FAST_SH3_SH2: |
| 2914 | reg_offset = sh_eth_offset_fast_sh3_sh2; |
| 2915 | break; |
Yoshihiro Shimoda | 4a55530 | 2011-03-07 21:59:26 +0000 | [diff] [blame] | 2916 | } |
| 2917 | |
| 2918 | return reg_offset; |
| 2919 | } |
| 2920 | |
Sergei Shtylyov | 8f728d7 | 2013-06-13 00:55:34 +0400 | [diff] [blame] | 2921 | static const struct net_device_ops sh_eth_netdev_ops = { |
Alexander Beregalov | ebf84ea | 2009-04-11 07:40:49 +0000 | [diff] [blame] | 2922 | .ndo_open = sh_eth_open, |
| 2923 | .ndo_stop = sh_eth_close, |
| 2924 | .ndo_start_xmit = sh_eth_start_xmit, |
| 2925 | .ndo_get_stats = sh_eth_get_stats, |
Ben Hutchings | b37feed | 2015-01-16 17:51:12 +0000 | [diff] [blame] | 2926 | .ndo_set_rx_mode = sh_eth_set_rx_mode, |
Alexander Beregalov | ebf84ea | 2009-04-11 07:40:49 +0000 | [diff] [blame] | 2927 | .ndo_tx_timeout = sh_eth_tx_timeout, |
| 2928 | .ndo_do_ioctl = sh_eth_do_ioctl, |
| 2929 | .ndo_validate_addr = eth_validate_addr, |
| 2930 | .ndo_set_mac_address = eth_mac_addr, |
| 2931 | .ndo_change_mtu = eth_change_mtu, |
| 2932 | }; |
| 2933 | |
Sergei Shtylyov | 8f728d7 | 2013-06-13 00:55:34 +0400 | [diff] [blame] | 2934 | static const struct net_device_ops sh_eth_netdev_ops_tsu = { |
| 2935 | .ndo_open = sh_eth_open, |
| 2936 | .ndo_stop = sh_eth_close, |
| 2937 | .ndo_start_xmit = sh_eth_start_xmit, |
| 2938 | .ndo_get_stats = sh_eth_get_stats, |
Ben Hutchings | b37feed | 2015-01-16 17:51:12 +0000 | [diff] [blame] | 2939 | .ndo_set_rx_mode = sh_eth_set_rx_mode, |
Sergei Shtylyov | 8f728d7 | 2013-06-13 00:55:34 +0400 | [diff] [blame] | 2940 | .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, |
| 2941 | .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, |
| 2942 | .ndo_tx_timeout = sh_eth_tx_timeout, |
| 2943 | .ndo_do_ioctl = sh_eth_do_ioctl, |
| 2944 | .ndo_validate_addr = eth_validate_addr, |
| 2945 | .ndo_set_mac_address = eth_mac_addr, |
| 2946 | .ndo_change_mtu = eth_change_mtu, |
| 2947 | }; |
| 2948 | |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 2949 | #ifdef CONFIG_OF |
| 2950 | static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) |
| 2951 | { |
| 2952 | struct device_node *np = dev->of_node; |
| 2953 | struct sh_eth_plat_data *pdata; |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 2954 | const char *mac_addr; |
| 2955 | |
| 2956 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 2957 | if (!pdata) |
| 2958 | return NULL; |
| 2959 | |
| 2960 | pdata->phy_interface = of_get_phy_mode(np); |
| 2961 | |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 2962 | mac_addr = of_get_mac_address(np); |
| 2963 | if (mac_addr) |
| 2964 | memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); |
| 2965 | |
| 2966 | pdata->no_ether_link = |
| 2967 | of_property_read_bool(np, "renesas,no-ether-link"); |
| 2968 | pdata->ether_link_active_low = |
| 2969 | of_property_read_bool(np, "renesas,ether-link-active-low"); |
| 2970 | |
| 2971 | return pdata; |
| 2972 | } |
| 2973 | |
| 2974 | static const struct of_device_id sh_eth_match_table[] = { |
| 2975 | { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, |
Sergei Shtylyov | c099ff3 | 2016-09-27 01:23:26 +0300 | [diff] [blame] | 2976 | { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data }, |
| 2977 | { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data }, |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 2978 | { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, |
| 2979 | { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, |
| 2980 | { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, |
| 2981 | { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, |
Hisashi Nakamura | 9488e1e | 2014-11-13 15:59:07 +0900 | [diff] [blame] | 2982 | { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data }, |
Hisashi Nakamura | 0f76b9d | 2014-08-01 17:03:00 +0200 | [diff] [blame] | 2983 | { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data }, |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 2984 | { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, |
| 2985 | { } |
| 2986 | }; |
| 2987 | MODULE_DEVICE_TABLE(of, sh_eth_match_table); |
| 2988 | #else |
| 2989 | static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) |
| 2990 | { |
| 2991 | return NULL; |
| 2992 | } |
| 2993 | #endif |
| 2994 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2995 | static int sh_eth_drv_probe(struct platform_device *pdev) |
| 2996 | { |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 2997 | struct resource *res; |
Jingoo Han | 0b76b86 | 2013-08-30 14:00:11 +0900 | [diff] [blame] | 2998 | struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); |
Sergei Shtylyov | afe391a | 2013-06-07 13:54:02 +0000 | [diff] [blame] | 2999 | const struct platform_device_id *id = platform_get_device_id(pdev); |
Sergei Shtylyov | 4fa8c3c | 2016-03-13 01:29:45 +0300 | [diff] [blame] | 3000 | struct sh_eth_private *mdp; |
| 3001 | struct net_device *ndev; |
| 3002 | int ret, devno; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3003 | |
| 3004 | /* get base addr */ |
| 3005 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3006 | |
| 3007 | ndev = alloc_etherdev(sizeof(struct sh_eth_private)); |
Laurent Pinchart | f738a13 | 2014-03-20 15:00:35 +0100 | [diff] [blame] | 3008 | if (!ndev) |
| 3009 | return -ENOMEM; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3010 | |
Ben Dooks | b5893a0 | 2014-03-21 12:09:14 +0100 | [diff] [blame] | 3011 | pm_runtime_enable(&pdev->dev); |
| 3012 | pm_runtime_get_sync(&pdev->dev); |
| 3013 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3014 | devno = pdev->id; |
| 3015 | if (devno < 0) |
| 3016 | devno = 0; |
| 3017 | |
roel kluin | cc3c080 | 2008-09-10 19:22:44 +0200 | [diff] [blame] | 3018 | ret = platform_get_irq(pdev, 0); |
Sergei Shtylyov | 7a468ac | 2015-08-28 16:56:01 +0300 | [diff] [blame] | 3019 | if (ret < 0) |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3020 | goto out_release; |
roel kluin | cc3c080 | 2008-09-10 19:22:44 +0200 | [diff] [blame] | 3021 | ndev->irq = ret; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3022 | |
| 3023 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 3024 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3025 | mdp = netdev_priv(ndev); |
Yoshihiro Shimoda | 525b807 | 2012-06-26 20:00:03 +0000 | [diff] [blame] | 3026 | mdp->num_tx_ring = TX_RING_SIZE; |
| 3027 | mdp->num_rx_ring = RX_RING_SIZE; |
Sergei Shtylyov | d5e07e6 | 2013-03-21 10:41:11 +0000 | [diff] [blame] | 3028 | mdp->addr = devm_ioremap_resource(&pdev->dev, res); |
| 3029 | if (IS_ERR(mdp->addr)) { |
| 3030 | ret = PTR_ERR(mdp->addr); |
Yoshihiro Shimoda | ae70644 | 2011-09-27 21:48:58 +0000 | [diff] [blame] | 3031 | goto out_release; |
| 3032 | } |
| 3033 | |
Varka Bhadram | c960804 | 2014-10-24 07:42:09 +0530 | [diff] [blame] | 3034 | ndev->base_addr = res->start; |
| 3035 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3036 | spin_lock_init(&mdp->lock); |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 3037 | mdp->pdev = pdev; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3038 | |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 3039 | if (pdev->dev.of_node) |
| 3040 | pd = sh_eth_parse_dt(&pdev->dev); |
Sergei Shtylyov | 3b4c5cb | 2013-10-30 23:30:19 +0300 | [diff] [blame] | 3041 | if (!pd) { |
| 3042 | dev_err(&pdev->dev, "no platform data\n"); |
| 3043 | ret = -EINVAL; |
| 3044 | goto out_release; |
| 3045 | } |
| 3046 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3047 | /* get PHY ID */ |
Yoshinori Sato | 71557a3 | 2008-08-06 19:49:00 -0400 | [diff] [blame] | 3048 | mdp->phy_id = pd->phy; |
Yoshihiro Shimoda | e47c905 | 2011-03-07 21:59:45 +0000 | [diff] [blame] | 3049 | mdp->phy_interface = pd->phy_interface; |
Yoshihiro Shimoda | 4923576 | 2009-08-27 23:25:03 +0000 | [diff] [blame] | 3050 | mdp->no_ether_link = pd->no_ether_link; |
| 3051 | mdp->ether_link_active_low = pd->ether_link_active_low; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3052 | |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 3053 | /* set cpu data */ |
Wolfram Sang | 42a67c9 | 2016-03-01 17:37:59 +0100 | [diff] [blame] | 3054 | if (id) |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 3055 | mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; |
Wolfram Sang | 42a67c9 | 2016-03-01 17:37:59 +0100 | [diff] [blame] | 3056 | else |
| 3057 | mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 3058 | |
Sergei Shtylyov | a3153d8 | 2013-08-18 03:11:28 +0400 | [diff] [blame] | 3059 | mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); |
Sergei Shtylyov | 264be2f | 2014-03-15 03:11:24 +0300 | [diff] [blame] | 3060 | if (!mdp->reg_offset) { |
| 3061 | dev_err(&pdev->dev, "Unknown register type (%d)\n", |
| 3062 | mdp->cd->register_type); |
| 3063 | ret = -EINVAL; |
| 3064 | goto out_release; |
| 3065 | } |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 3066 | sh_eth_set_default_cpu_data(mdp->cd); |
| 3067 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3068 | /* set function */ |
Sergei Shtylyov | 8f728d7 | 2013-06-13 00:55:34 +0400 | [diff] [blame] | 3069 | if (mdp->cd->tsu) |
| 3070 | ndev->netdev_ops = &sh_eth_netdev_ops_tsu; |
| 3071 | else |
| 3072 | ndev->netdev_ops = &sh_eth_netdev_ops; |
Wilfried Klaebe | 7ad24ea | 2014-05-11 00:12:32 +0000 | [diff] [blame] | 3073 | ndev->ethtool_ops = &sh_eth_ethtool_ops; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3074 | ndev->watchdog_timeo = TX_TIMEOUT; |
| 3075 | |
Nobuhiro Iwamatsu | dc19e4e | 2011-02-15 21:17:32 +0000 | [diff] [blame] | 3076 | /* debug message level */ |
| 3077 | mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3078 | |
| 3079 | /* read and set MAC address */ |
Magnus Damm | 748031f | 2009-10-09 00:17:14 +0000 | [diff] [blame] | 3080 | read_mac_address(ndev, pd->mac_addr); |
Sergei Shtylyov | ff6e722 | 2013-04-29 09:49:42 +0000 | [diff] [blame] | 3081 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
| 3082 | dev_warn(&pdev->dev, |
| 3083 | "no valid MAC address supplied, using a random one.\n"); |
| 3084 | eth_hw_addr_random(ndev); |
| 3085 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3086 | |
Yoshihiro Shimoda | 6ba8802 | 2012-02-15 17:55:01 +0000 | [diff] [blame] | 3087 | /* ioremap the TSU registers */ |
| 3088 | if (mdp->cd->tsu) { |
| 3089 | struct resource *rtsu; |
Sergei Shtylyov | eb2f80e | 2018-01-03 20:09:49 +0300 | [diff] [blame] | 3090 | |
Yoshihiro Shimoda | 6ba8802 | 2012-02-15 17:55:01 +0000 | [diff] [blame] | 3091 | rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
Sergei Shtylyov | eb2f80e | 2018-01-03 20:09:49 +0300 | [diff] [blame] | 3092 | if (!rtsu) { |
| 3093 | dev_err(&pdev->dev, "no TSU resource\n"); |
| 3094 | ret = -ENODEV; |
| 3095 | goto out_release; |
| 3096 | } |
| 3097 | /* We can only request the TSU region for the first port |
| 3098 | * of the two sharing this TSU for the probe to succeed... |
| 3099 | */ |
| 3100 | if (devno % 2 == 0 && |
| 3101 | !devm_request_mem_region(&pdev->dev, rtsu->start, |
| 3102 | resource_size(rtsu), |
| 3103 | dev_name(&pdev->dev))) { |
| 3104 | dev_err(&pdev->dev, "can't request TSU resource.\n"); |
| 3105 | ret = -EBUSY; |
| 3106 | goto out_release; |
| 3107 | } |
| 3108 | mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, |
| 3109 | resource_size(rtsu)); |
| 3110 | if (!mdp->tsu_addr) { |
| 3111 | dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); |
| 3112 | ret = -ENOMEM; |
Sergei Shtylyov | fc0c090 | 2013-03-19 13:41:32 +0000 | [diff] [blame] | 3113 | goto out_release; |
| 3114 | } |
Yoshihiro Shimoda | 6743fe6 | 2012-02-15 17:55:03 +0000 | [diff] [blame] | 3115 | mdp->port = devno % 2; |
Patrick McHardy | f646968 | 2013-04-19 02:04:27 +0000 | [diff] [blame] | 3116 | ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; |
Yoshihiro Shimoda | 6ba8802 | 2012-02-15 17:55:01 +0000 | [diff] [blame] | 3117 | } |
| 3118 | |
Sergei Shtylyov | 7f4226f | 2018-01-04 21:06:49 +0300 | [diff] [blame] | 3119 | /* Need to init only the first port of the two sharing a TSU */ |
| 3120 | if (devno % 2 == 0) { |
Yoshihiro Shimoda | 380af9e | 2009-05-24 23:54:21 +0000 | [diff] [blame] | 3121 | if (mdp->cd->chip_reset) |
| 3122 | mdp->cd->chip_reset(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3123 | |
Yoshihiro Shimoda | 4986b99 | 2011-03-07 21:59:34 +0000 | [diff] [blame] | 3124 | if (mdp->cd->tsu) { |
| 3125 | /* TSU init (Init only)*/ |
| 3126 | sh_eth_tsu_init(mdp); |
| 3127 | } |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3128 | } |
| 3129 | |
Hisashi Nakamura | 966d6db | 2014-11-13 15:54:05 +0900 | [diff] [blame] | 3130 | if (mdp->cd->rmiimode) |
| 3131 | sh_eth_write(ndev, 0x1, RMIIMODE); |
| 3132 | |
Laurent Pinchart | daacf03 | 2014-03-20 15:00:34 +0100 | [diff] [blame] | 3133 | /* MDIO bus init */ |
| 3134 | ret = sh_mdio_init(mdp, pd); |
| 3135 | if (ret) { |
Geert Uytterhoeven | eed386e | 2017-05-18 15:01:34 +0200 | [diff] [blame] | 3136 | dev_err(&pdev->dev, "failed to initialise MDIO\n"); |
Laurent Pinchart | daacf03 | 2014-03-20 15:00:34 +0100 | [diff] [blame] | 3137 | goto out_release; |
| 3138 | } |
| 3139 | |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 3140 | netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); |
| 3141 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3142 | /* network device register */ |
| 3143 | ret = register_netdev(ndev); |
| 3144 | if (ret) |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 3145 | goto out_napi_del; |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3146 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 3147 | /* print device information */ |
Sergei Shtylyov | f75f14e | 2014-03-15 03:27:54 +0300 | [diff] [blame] | 3148 | netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", |
| 3149 | (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3150 | |
Ben Dooks | b5893a0 | 2014-03-21 12:09:14 +0100 | [diff] [blame] | 3151 | pm_runtime_put(&pdev->dev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3152 | platform_set_drvdata(pdev, ndev); |
| 3153 | |
| 3154 | return ret; |
| 3155 | |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 3156 | out_napi_del: |
| 3157 | netif_napi_del(&mdp->napi); |
Laurent Pinchart | daacf03 | 2014-03-20 15:00:34 +0100 | [diff] [blame] | 3158 | sh_mdio_release(mdp); |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 3159 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3160 | out_release: |
| 3161 | /* net_dev free */ |
| 3162 | if (ndev) |
| 3163 | free_netdev(ndev); |
| 3164 | |
Ben Dooks | b5893a0 | 2014-03-21 12:09:14 +0100 | [diff] [blame] | 3165 | pm_runtime_put(&pdev->dev); |
| 3166 | pm_runtime_disable(&pdev->dev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3167 | return ret; |
| 3168 | } |
| 3169 | |
| 3170 | static int sh_eth_drv_remove(struct platform_device *pdev) |
| 3171 | { |
| 3172 | struct net_device *ndev = platform_get_drvdata(pdev); |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 3173 | struct sh_eth_private *mdp = netdev_priv(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3174 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3175 | unregister_netdev(ndev); |
Sergei Shtylyov | 3719109 | 2013-06-19 23:30:23 +0400 | [diff] [blame] | 3176 | netif_napi_del(&mdp->napi); |
Laurent Pinchart | daacf03 | 2014-03-20 15:00:34 +0100 | [diff] [blame] | 3177 | sh_mdio_release(mdp); |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 3178 | pm_runtime_disable(&pdev->dev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3179 | free_netdev(ndev); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3180 | |
| 3181 | return 0; |
| 3182 | } |
| 3183 | |
Nobuhiro Iwamatsu | 540ad1b | 2013-06-06 09:52:37 +0000 | [diff] [blame] | 3184 | #ifdef CONFIG_PM |
Mikhail Ulyanov | b71af04 | 2015-01-22 01:19:48 +0300 | [diff] [blame] | 3185 | #ifdef CONFIG_PM_SLEEP |
| 3186 | static int sh_eth_suspend(struct device *dev) |
| 3187 | { |
| 3188 | struct net_device *ndev = dev_get_drvdata(dev); |
| 3189 | int ret = 0; |
| 3190 | |
| 3191 | if (netif_running(ndev)) { |
| 3192 | netif_device_detach(ndev); |
| 3193 | ret = sh_eth_close(ndev); |
| 3194 | } |
| 3195 | |
| 3196 | return ret; |
| 3197 | } |
| 3198 | |
| 3199 | static int sh_eth_resume(struct device *dev) |
| 3200 | { |
| 3201 | struct net_device *ndev = dev_get_drvdata(dev); |
| 3202 | int ret = 0; |
| 3203 | |
| 3204 | if (netif_running(ndev)) { |
| 3205 | ret = sh_eth_open(ndev); |
| 3206 | if (ret < 0) |
| 3207 | return ret; |
| 3208 | netif_device_attach(ndev); |
| 3209 | } |
| 3210 | |
| 3211 | return ret; |
| 3212 | } |
| 3213 | #endif |
| 3214 | |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 3215 | static int sh_eth_runtime_nop(struct device *dev) |
| 3216 | { |
Sergei Shtylyov | 128296f | 2014-01-03 15:52:22 +0300 | [diff] [blame] | 3217 | /* Runtime PM callback shared between ->runtime_suspend() |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 3218 | * and ->runtime_resume(). Simply returns success. |
| 3219 | * |
| 3220 | * This driver re-initializes all registers after |
| 3221 | * pm_runtime_get_sync() anyway so there is no need |
| 3222 | * to save and restore registers here. |
| 3223 | */ |
| 3224 | return 0; |
| 3225 | } |
| 3226 | |
Nobuhiro Iwamatsu | 540ad1b | 2013-06-06 09:52:37 +0000 | [diff] [blame] | 3227 | static const struct dev_pm_ops sh_eth_dev_pm_ops = { |
Mikhail Ulyanov | b71af04 | 2015-01-22 01:19:48 +0300 | [diff] [blame] | 3228 | SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) |
Mikhail Ulyanov | e7d7e89 | 2015-01-22 01:18:44 +0300 | [diff] [blame] | 3229 | SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 3230 | }; |
Nobuhiro Iwamatsu | 540ad1b | 2013-06-06 09:52:37 +0000 | [diff] [blame] | 3231 | #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) |
| 3232 | #else |
| 3233 | #define SH_ETH_PM_OPS NULL |
| 3234 | #endif |
Magnus Damm | bcd5149 | 2009-10-09 00:20:04 +0000 | [diff] [blame] | 3235 | |
Sergei Shtylyov | afe391a | 2013-06-07 13:54:02 +0000 | [diff] [blame] | 3236 | static struct platform_device_id sh_eth_id_table[] = { |
Sergei Shtylyov | c18a79a | 2013-06-07 13:56:05 +0000 | [diff] [blame] | 3237 | { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, |
Sergei Shtylyov | 7bbe150 | 2013-06-07 13:55:08 +0000 | [diff] [blame] | 3238 | { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, |
Sergei Shtylyov | 9c3beaa | 2013-06-07 14:03:37 +0000 | [diff] [blame] | 3239 | { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 3240 | { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, |
Sergei Shtylyov | 24549e2 | 2013-06-07 13:59:21 +0000 | [diff] [blame] | 3241 | { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, |
| 3242 | { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, |
Sergei Shtylyov | f5d1276 | 2013-06-07 13:58:18 +0000 | [diff] [blame] | 3243 | { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, |
Sergei Shtylyov | afe391a | 2013-06-07 13:54:02 +0000 | [diff] [blame] | 3244 | { } |
| 3245 | }; |
| 3246 | MODULE_DEVICE_TABLE(platform, sh_eth_id_table); |
| 3247 | |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3248 | static struct platform_driver sh_eth_driver = { |
| 3249 | .probe = sh_eth_drv_probe, |
| 3250 | .remove = sh_eth_drv_remove, |
Sergei Shtylyov | afe391a | 2013-06-07 13:54:02 +0000 | [diff] [blame] | 3251 | .id_table = sh_eth_id_table, |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3252 | .driver = { |
| 3253 | .name = CARDNAME, |
Nobuhiro Iwamatsu | 540ad1b | 2013-06-06 09:52:37 +0000 | [diff] [blame] | 3254 | .pm = SH_ETH_PM_OPS, |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 3255 | .of_match_table = of_match_ptr(sh_eth_match_table), |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3256 | }, |
| 3257 | }; |
| 3258 | |
Axel Lin | db62f68 | 2011-11-27 16:44:17 +0000 | [diff] [blame] | 3259 | module_platform_driver(sh_eth_driver); |
Nobuhiro Iwamatsu | 86a74ff | 2008-06-09 16:33:56 -0700 | [diff] [blame] | 3260 | |
| 3261 | MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); |
| 3262 | MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); |
| 3263 | MODULE_LICENSE("GPL v2"); |