Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1 | #include "r8192U.h" |
| 2 | #include "r8192U_hw.h" |
| 3 | #include "r819xU_phy.h" |
| 4 | #include "r819xU_phyreg.h" |
| 5 | #include "r8190_rtl8256.h" |
| 6 | #include "r8192U_dm.h" |
| 7 | #include "r819xU_firmware_img.h" |
| 8 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 9 | #include "dot11d.h" |
Xenia Ragiadakou | 391c72a | 2013-06-15 07:29:01 +0300 | [diff] [blame] | 10 | #include <linux/bitops.h> |
| 11 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 12 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { |
| 13 | 0, |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 14 | 0x085c, /* 2412 1 */ |
| 15 | 0x08dc, /* 2417 2 */ |
| 16 | 0x095c, /* 2422 3 */ |
| 17 | 0x09dc, /* 2427 4 */ |
| 18 | 0x0a5c, /* 2432 5 */ |
| 19 | 0x0adc, /* 2437 6 */ |
| 20 | 0x0b5c, /* 2442 7 */ |
| 21 | 0x0bdc, /* 2447 8 */ |
| 22 | 0x0c5c, /* 2452 9 */ |
| 23 | 0x0cdc, /* 2457 10 */ |
| 24 | 0x0d5c, /* 2462 11 */ |
| 25 | 0x0ddc, /* 2467 12 */ |
| 26 | 0x0e5c, /* 2472 13 */ |
| 27 | 0x0f72, /* 2484 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | |
| 31 | #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray |
| 32 | #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG |
| 33 | #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array |
| 34 | #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array |
| 35 | #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array |
| 36 | #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array |
| 37 | #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array |
| 38 | #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array |
| 39 | |
| 40 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 41 | * function: This function reads BB parameters from header file we generate, |
| 42 | * and does register read/write |
| 43 | * input: u32 bitmask //taget bit pos in the addr to be modified |
| 44 | * output: none |
| 45 | * return: u32 return the shift bit position of the mask |
| 46 | ******************************************************************************/ |
Xenia Ragiadakou | 9f66ddb | 2013-06-18 05:29:40 +0300 | [diff] [blame] | 47 | u32 rtl8192_CalculateBitShift(u32 bitmask) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 48 | { |
| 49 | u32 i; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 50 | |
Xenia Ragiadakou | 9f66ddb | 2013-06-18 05:29:40 +0300 | [diff] [blame] | 51 | i = ffs(bitmask) - 1; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 52 | return i; |
| 53 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 54 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 55 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 56 | * function: This function checks different RF type to execute legal judgement. |
| 57 | * If RF Path is illegal, we will return false. |
| 58 | * input: net_device *dev |
| 59 | * u32 eRFPath |
| 60 | * output: none |
| 61 | * return: 0(illegal, false), 1(legal, true) |
| 62 | *****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 63 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 64 | { |
| 65 | u8 ret = 1; |
| 66 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 67 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 68 | if (priv->rf_type == RF_2T4R) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 69 | ret = 0; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 70 | } else if (priv->rf_type == RF_1T2R) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 71 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
| 72 | ret = 1; |
| 73 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) |
| 74 | ret = 0; |
| 75 | } |
| 76 | return ret; |
| 77 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 78 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 79 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 80 | * function: This function sets specific bits to BB register |
| 81 | * input: net_device *dev |
| 82 | * u32 reg_addr //target addr to be modified |
| 83 | * u32 bitmask //taget bit pos to be modified |
| 84 | * u32 data //value to be write |
| 85 | * output: none |
| 86 | * return: none |
| 87 | * notice: |
| 88 | ******************************************************************************/ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 89 | void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, |
| 90 | u32 data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 91 | { |
| 92 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 93 | u32 reg, bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 94 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 95 | if (bitmask != bMaskDWord) { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 96 | read_nic_dword(dev, reg_addr, ®); |
| 97 | bitshift = rtl8192_CalculateBitShift(bitmask); |
Xenia Ragiadakou | 9f66ddb | 2013-06-18 05:29:40 +0300 | [diff] [blame] | 98 | reg &= ~bitmask; |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 99 | reg |= data << bitshift; |
| 100 | write_nic_dword(dev, reg_addr, reg); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 101 | } else { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 102 | write_nic_dword(dev, reg_addr, data); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 103 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 104 | return; |
| 105 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 106 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 107 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 108 | * function: This function reads specific bits from BB register |
| 109 | * input: net_device *dev |
| 110 | * u32 reg_addr //target addr to be readback |
| 111 | * u32 bitmask //taget bit pos to be readback |
| 112 | * output: none |
| 113 | * return: u32 data //the readback register value |
| 114 | * notice: |
| 115 | ******************************************************************************/ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 116 | u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 117 | { |
Xenia Ragiadakou | c4b5eb8 | 2013-06-19 04:58:05 +0300 | [diff] [blame] | 118 | u32 reg, bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 119 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 120 | read_nic_dword(dev, reg_addr, ®); |
| 121 | bitshift = rtl8192_CalculateBitShift(bitmask); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 122 | |
Xenia Ragiadakou | c4b5eb8 | 2013-06-19 04:58:05 +0300 | [diff] [blame] | 123 | return (reg & bitmask) >> bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 124 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 125 | |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 126 | static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 127 | u32 offset); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 128 | |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 129 | static void phy_FwRFSerialWrite(struct net_device *dev, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 130 | RF90_RADIO_PATH_E eRFPath, u32 offset, |
| 131 | u32 data); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 132 | |
| 133 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 134 | * function: This function reads register from RF chip |
| 135 | * input: net_device *dev |
| 136 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
| 137 | * u32 offset //target address to be read |
| 138 | * output: none |
| 139 | * return: u32 readback value |
| 140 | * notice: There are three types of serial operations: |
| 141 | * (1) Software serial write. |
| 142 | * (2)Hardware LSSI-Low Speed Serial Interface. |
| 143 | * (3)Hardware HSSI-High speed serial write. |
| 144 | * Driver here need to implement (1) and (2) |
| 145 | * ---need more spec for this information. |
| 146 | ******************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 147 | u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 148 | u32 offset) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 149 | { |
| 150 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 151 | u32 ret = 0; |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 152 | u32 new_offset = 0; |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 153 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 154 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 155 | rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 156 | /* Make sure RF register offset is correct */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 157 | offset &= 0x3f; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 158 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 159 | /* Switch page for 8256 RF IC */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 160 | if (priv->rf_chip == RF_8256) { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 161 | if (offset >= 31) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 162 | priv->RfReg0Value[eRFPath] |= 0x140; |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 163 | /* Switch to Reg_Mode2 for Reg 31-45 */ |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 164 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
| 165 | bMaskDWord, |
| 166 | priv->RfReg0Value[eRFPath]<<16); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 167 | /* Modify offset */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 168 | new_offset = offset - 30; |
| 169 | } else if (offset >= 16) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 170 | priv->RfReg0Value[eRFPath] |= 0x100; |
| 171 | priv->RfReg0Value[eRFPath] &= (~0x40); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 172 | /* Switch to Reg_Mode1 for Reg16-30 */ |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 173 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
| 174 | bMaskDWord, |
| 175 | priv->RfReg0Value[eRFPath]<<16); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 176 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 177 | new_offset = offset - 15; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 178 | } else { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 179 | new_offset = offset; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 180 | } |
| 181 | } else { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 182 | RT_TRACE((COMP_PHY|COMP_ERR), |
| 183 | "check RF type here, need to be 8256\n"); |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 184 | new_offset = offset; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 185 | } |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 186 | /* Put desired read addr to LSSI control Register */ |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 187 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, |
| 188 | new_offset); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 189 | /* Issue a posedge trigger */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 190 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
| 191 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); |
| 192 | |
| 193 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 194 | /* TODO: we should not delay such a long time. Ask for help from SD3 */ |
Xenia Ragiadakou | 26f3561 | 2013-06-23 06:15:18 +0300 | [diff] [blame] | 195 | usleep_range(1000, 1000); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 196 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 197 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, |
| 198 | bLSSIReadBackData); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 199 | |
| 200 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 201 | /* Switch back to Reg_Mode0 */ |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 202 | if (priv->rf_chip == RF_8256) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 203 | priv->RfReg0Value[eRFPath] &= 0xebf; |
| 204 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 205 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, |
| 206 | priv->RfReg0Value[eRFPath] << 16); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | return ret; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 213 | * function: This function writes data to RF register |
| 214 | * input: net_device *dev |
| 215 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
| 216 | * u32 offset //target address to be written |
| 217 | * u32 data //the new register data to be written |
| 218 | * output: none |
| 219 | * return: none |
| 220 | * notice: For RF8256 only. |
| 221 | * =========================================================================== |
| 222 | * Reg Mode RegCTL[1] RegCTL[0] Note |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 223 | * (Reg00[12]) (Reg00[10]) |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 224 | * =========================================================================== |
| 225 | * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf) |
| 226 | * --------------------------------------------------------------------------- |
| 227 | * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf) |
| 228 | * --------------------------------------------------------------------------- |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 229 | * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 230 | * --------------------------------------------------------------------------- |
| 231 | *****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 232 | void rtl8192_phy_RFSerialWrite(struct net_device *dev, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 233 | RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 234 | { |
| 235 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 236 | u32 DataAndAddr = 0, new_offset = 0; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 237 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
| 238 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 239 | offset &= 0x3f; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 240 | if (priv->rf_chip == RF_8256) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 241 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 242 | if (offset >= 31) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 243 | priv->RfReg0Value[eRFPath] |= 0x140; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 244 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
| 245 | bMaskDWord, |
| 246 | priv->RfReg0Value[eRFPath] << 16); |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 247 | new_offset = offset - 30; |
| 248 | } else if (offset >= 16) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 249 | priv->RfReg0Value[eRFPath] |= 0x100; |
| 250 | priv->RfReg0Value[eRFPath] &= (~0x40); |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 251 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
| 252 | bMaskDWord, |
| 253 | priv->RfReg0Value[eRFPath]<<16); |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 254 | new_offset = offset - 15; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 255 | } else { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 256 | new_offset = offset; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 257 | } |
| 258 | } else { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 259 | RT_TRACE((COMP_PHY|COMP_ERR), |
| 260 | "check RF type here, need to be 8256\n"); |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 261 | new_offset = offset; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 262 | } |
| 263 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 264 | /* Put write addr in [5:0] and write data in [31:16] */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 265 | DataAndAddr = (data<<16) | (new_offset&0x3f); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 266 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 267 | /* Write operation */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 268 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); |
| 269 | |
| 270 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 271 | if (offset == 0x0) |
| 272 | priv->RfReg0Value[eRFPath] = data; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 273 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 274 | /* Switch back to Reg_Mode0 */ |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 275 | if (priv->rf_chip == RF_8256) { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 276 | if (offset != 0) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 277 | priv->RfReg0Value[eRFPath] &= 0xebf; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 278 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
| 279 | bMaskDWord, |
| 280 | priv->RfReg0Value[eRFPath] << 16); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 281 | } |
| 282 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 283 | return; |
| 284 | } |
| 285 | |
| 286 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 287 | * function: This function set specific bits to RF register |
| 288 | * input: net_device dev |
| 289 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
| 290 | * u32 reg_addr //target addr to be modified |
| 291 | * u32 bitmask //taget bit pos to be modified |
| 292 | * u32 data //value to be written |
| 293 | * output: none |
| 294 | * return: none |
| 295 | * notice: |
| 296 | *****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 297 | void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 298 | u32 reg_addr, u32 bitmask, u32 data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 299 | { |
| 300 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 301 | u32 reg, bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 302 | |
| 303 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 304 | return; |
| 305 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 306 | if (priv->Rf_Mode == RF_OP_By_FW) { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 307 | if (bitmask != bMask12Bits) { |
| 308 | /* RF data is 12 bits only */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 309 | reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); |
| 310 | bitshift = rtl8192_CalculateBitShift(bitmask); |
Xenia Ragiadakou | 9f66ddb | 2013-06-18 05:29:40 +0300 | [diff] [blame] | 311 | reg &= ~bitmask; |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 312 | reg |= data << bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 313 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 314 | phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 315 | } else { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 316 | phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 317 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 318 | |
| 319 | udelay(200); |
| 320 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 321 | } else { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 322 | if (bitmask != bMask12Bits) { |
| 323 | /* RF data is 12 bits only */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 324 | reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); |
| 325 | bitshift = rtl8192_CalculateBitShift(bitmask); |
Xenia Ragiadakou | 9f66ddb | 2013-06-18 05:29:40 +0300 | [diff] [blame] | 326 | reg &= ~bitmask; |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 327 | reg |= data << bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 328 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 329 | rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 330 | } else { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 331 | rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 332 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 333 | } |
| 334 | return; |
| 335 | } |
| 336 | |
| 337 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 338 | * function: This function reads specific bits from RF register |
| 339 | * input: net_device *dev |
| 340 | * u32 reg_addr //target addr to be readback |
| 341 | * u32 bitmask //taget bit pos to be readback |
| 342 | * output: none |
| 343 | * return: u32 data //the readback register value |
| 344 | * notice: |
| 345 | *****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 346 | u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 347 | u32 reg_addr, u32 bitmask) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 348 | { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 349 | u32 reg, bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 350 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 351 | |
| 352 | |
| 353 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 354 | return 0; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 355 | if (priv->Rf_Mode == RF_OP_By_FW) { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 356 | reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); |
| 357 | bitshift = rtl8192_CalculateBitShift(bitmask); |
| 358 | reg = (reg & bitmask) >> bitshift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 359 | udelay(200); |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 360 | return reg; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 361 | } else { |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 362 | reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); |
| 363 | bitshift = rtl8192_CalculateBitShift(bitmask); |
| 364 | reg = (reg & bitmask) >> bitshift; |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 365 | return reg; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 366 | } |
| 367 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 368 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 369 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 370 | * function: We support firmware to execute RF-R/W. |
| 371 | * input: net_device *dev |
| 372 | * RF90_RADIO_PATH_E eRFPath |
| 373 | * u32 offset |
| 374 | * output: none |
| 375 | * return: u32 |
| 376 | * notice: |
| 377 | ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 378 | static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 379 | u32 offset) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 380 | { |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 381 | u32 reg = 0; |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 382 | u32 data = 0; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 383 | u8 time = 0; |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 384 | u32 tmp; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 385 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 386 | /* Firmware RF Write control. |
| 387 | * We can not execute the scheme in the initial step. |
| 388 | * Otherwise, RF-R/W will waste much time. |
| 389 | * This is only for site survey. */ |
| 390 | /* 1. Read operation need not insert data. bit 0-11 */ |
| 391 | /* 2. Write RF register address. bit 12-19 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 392 | data |= ((offset&0xFF)<<12); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 393 | /* 3. Write RF path. bit 20-21 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 394 | data |= ((eRFPath&0x3)<<20); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 395 | /* 4. Set RF read indicator. bit 22=0 */ |
| 396 | /* 5. Trigger Fw to operate the command. bit 31 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 397 | data |= 0x80000000; |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 398 | /* 6. We can not execute read operation if bit 31 is 1. */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 399 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 400 | while (tmp & 0x80000000) { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 401 | /* If FW can not finish RF-R/W for more than ?? times. |
| 402 | We must reset FW. */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 403 | if (time++ < 100) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 404 | udelay(10); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 405 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 406 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 407 | break; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 408 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 409 | } |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 410 | /* 7. Execute read operation. */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 411 | write_nic_dword(dev, QPNR, data); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 412 | /* 8. Check if firmware send back RF content. */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 413 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 414 | while (tmp & 0x80000000) { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 415 | /* If FW can not finish RF-R/W for more than ?? times. |
| 416 | We must reset FW. */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 417 | if (time++ < 100) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 418 | udelay(10); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 419 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 420 | } else { |
Xenia Ragiadakou | 4c8dd92 | 2013-06-15 07:29:03 +0300 | [diff] [blame] | 421 | return 0; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 422 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 423 | } |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 424 | read_nic_dword(dev, RF_DATA, ®); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 425 | |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 426 | return reg; |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 427 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 428 | |
| 429 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 430 | * function: We support firmware to execute RF-R/W. |
| 431 | * input: net_device *dev |
| 432 | * RF90_RADIO_PATH_E eRFPath |
| 433 | * u32 offset |
| 434 | * u32 data |
| 435 | * output: none |
| 436 | * return: none |
| 437 | * notice: |
| 438 | ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 439 | static void phy_FwRFSerialWrite(struct net_device *dev, |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 440 | RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 441 | { |
| 442 | u8 time = 0; |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 443 | u32 tmp; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 444 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 445 | /* Firmware RF Write control. |
| 446 | * We can not execute the scheme in the initial step. |
| 447 | * Otherwise, RF-R/W will waste much time. |
| 448 | * This is only for site survey. */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 449 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 450 | /* 1. Set driver write bit and 12 bit data. bit 0-11 */ |
| 451 | /* 2. Write RF register address. bit 12-19 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 452 | data |= ((offset&0xFF)<<12); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 453 | /* 3. Write RF path. bit 20-21 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 454 | data |= ((eRFPath&0x3)<<20); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 455 | /* 4. Set RF write indicator. bit 22=1 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 456 | data |= 0x400000; |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 457 | /* 5. Trigger Fw to operate the command. bit 31=1 */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 458 | data |= 0x80000000; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 459 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 460 | /* 6. Write operation. We can not write if bit 31 is 1. */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 461 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 462 | while (tmp & 0x80000000) { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 463 | /* If FW can not finish RF-R/W for more than ?? times. |
| 464 | We must reset FW. */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 465 | if (time++ < 100) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 466 | udelay(10); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 467 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 468 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 469 | break; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 470 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 471 | } |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 472 | /* 7. No matter check bit. We always force the write. |
| 473 | Because FW will not accept the command. */ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 474 | write_nic_dword(dev, QPNR, data); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 475 | /* According to test, we must delay 20us to wait firmware |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 476 | to finish RF write operation. */ |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 477 | /* We support delay in firmware side now. */ |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 478 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 479 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 480 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 481 | * function: This function reads BB parameters from header file we generate, |
| 482 | * and do register read/write |
| 483 | * input: net_device *dev |
| 484 | * output: none |
| 485 | * return: none |
| 486 | * notice: BB parameters may change all the time, so please make |
| 487 | * sure it has been synced with the newest. |
| 488 | *****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 489 | void rtl8192_phy_configmac(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 490 | { |
| 491 | u32 dwArrayLen = 0, i; |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 492 | u32 *pdwArray = NULL; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 493 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 494 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 495 | if (priv->btxpowerdata_readfromEEPORM) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 496 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); |
| 497 | dwArrayLen = MACPHY_Array_PGLength; |
| 498 | pdwArray = rtl819XMACPHY_Array_PG; |
| 499 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 500 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 501 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); |
| 502 | dwArrayLen = MACPHY_ArrayLength; |
| 503 | pdwArray = rtl819XMACPHY_Array; |
| 504 | } |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 505 | for (i = 0; i < dwArrayLen; i = i+3) { |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 506 | if (pdwArray[i] == 0x318) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 507 | pdwArray[i+2] = 0x00000800; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 508 | } |
| 509 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 510 | RT_TRACE(COMP_DBG, |
| 511 | "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n", |
| 512 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); |
| 513 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], |
| 514 | pdwArray[i+2]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 515 | } |
| 516 | return; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 517 | } |
| 518 | |
| 519 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 520 | * function: This function does dirty work |
| 521 | * input: net_device *dev |
| 522 | * u8 ConfigType |
| 523 | * output: none |
| 524 | * return: none |
| 525 | * notice: BB parameters may change all the time, so please make |
| 526 | * sure it has been synced with the newest. |
| 527 | *****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 528 | void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 529 | { |
| 530 | u32 i; |
| 531 | |
| 532 | #ifdef TO_DO_LIST |
| 533 | u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 534 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 535 | if (Adapter->bInHctTest) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 536 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; |
| 537 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; |
| 538 | Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; |
| 539 | Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; |
| 540 | } |
| 541 | #endif |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 542 | if (ConfigType == BaseBand_Config_PHY_REG) { |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 543 | for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 544 | rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], |
| 545 | bMaskDWord, |
| 546 | rtl819XPHY_REG_1T2RArray[i+1]); |
| 547 | RT_TRACE(COMP_DBG, |
| 548 | "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n", |
| 549 | i, rtl819XPHY_REG_1T2RArray[i], |
| 550 | rtl819XPHY_REG_1T2RArray[i+1]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 551 | } |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 552 | } else if (ConfigType == BaseBand_Config_AGC_TAB) { |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 553 | for (i = 0; i < AGCTAB_ArrayLength; i += 2) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 554 | rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], |
| 555 | bMaskDWord, rtl819XAGCTAB_Array[i+1]); |
| 556 | RT_TRACE(COMP_DBG, |
| 557 | "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n", |
| 558 | i, rtl819XAGCTAB_Array[i], |
| 559 | rtl819XAGCTAB_Array[i+1]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 560 | } |
| 561 | } |
| 562 | return; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 563 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 564 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 565 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 566 | * function: This function initializes Register definition offset for |
| 567 | * Radio Path A/B/C/D |
| 568 | * input: net_device *dev |
| 569 | * output: none |
| 570 | * return: none |
| 571 | * notice: Initialization value here is constant and it should never |
| 572 | * be changed |
| 573 | *****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 574 | void rtl8192_InitBBRFRegDef(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 575 | { |
| 576 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 577 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 578 | /* RF Interface Software Control */ |
| 579 | /* 16 LSBs if read 32-bit from 0x870 */ |
| 580 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; |
| 581 | /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ |
| 582 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; |
| 583 | /* 16 LSBs if read 32-bit from 0x874 */ |
| 584 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; |
| 585 | /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ |
| 586 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 587 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 588 | /* RF Interface Readback Value */ |
| 589 | /* 16 LSBs if read 32-bit from 0x8E0 */ |
| 590 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; |
| 591 | /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ |
| 592 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; |
| 593 | /* 16 LSBs if read 32-bit from 0x8E4 */ |
| 594 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; |
| 595 | /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ |
| 596 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 597 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 598 | /* RF Interface Output (and Enable) */ |
| 599 | /* 16 LSBs if read 32-bit from 0x860 */ |
| 600 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; |
| 601 | /* 16 LSBs if read 32-bit from 0x864 */ |
| 602 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; |
| 603 | /* 16 LSBs if read 32-bit from 0x868 */ |
| 604 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; |
| 605 | /* 16 LSBs if read 32-bit from 0x86C */ |
| 606 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 607 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 608 | /* RF Interface (Output and) Enable */ |
| 609 | /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ |
| 610 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; |
| 611 | /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ |
| 612 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; |
| 613 | /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */ |
| 614 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; |
| 615 | /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */ |
| 616 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 617 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 618 | /* Addr of LSSI. Write RF register by driver */ |
| 619 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 620 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; |
| 621 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; |
| 622 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; |
| 623 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 624 | /* RF parameter */ |
| 625 | /* BB Band Select */ |
| 626 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 627 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
| 628 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 629 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 630 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 631 | /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ |
| 632 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; |
| 633 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; |
| 634 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; |
| 635 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 636 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 637 | /* Tranceiver A~D HSSI Parameter-1 */ |
| 638 | /* wire control parameter1 */ |
| 639 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; |
| 640 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; |
| 641 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; |
| 642 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 643 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 644 | /* Tranceiver A~D HSSI Parameter-2 */ |
| 645 | /* wire control parameter2 */ |
| 646 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; |
| 647 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; |
| 648 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; |
| 649 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 650 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 651 | /* RF Switch Control */ |
| 652 | /* TR/Ant switch control */ |
| 653 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 654 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
| 655 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 656 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 657 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 658 | /* AGC control 1 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 659 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; |
| 660 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; |
| 661 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; |
| 662 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; |
| 663 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 664 | /* AGC control 2 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 665 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; |
| 666 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; |
| 667 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; |
| 668 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; |
| 669 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 670 | /* RX AFE control 1 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 671 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; |
| 672 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; |
| 673 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; |
| 674 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; |
| 675 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 676 | /* RX AFE control 1 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 677 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; |
| 678 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; |
| 679 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; |
| 680 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; |
| 681 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 682 | /* Tx AFE control 1 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 683 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; |
| 684 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; |
| 685 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; |
| 686 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; |
| 687 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 688 | /* Tx AFE control 2 */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 689 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; |
| 690 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; |
| 691 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; |
| 692 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; |
| 693 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 694 | /* Tranceiver LSSI Readback */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 695 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; |
| 696 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; |
| 697 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; |
| 698 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 699 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 700 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 701 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 702 | * function: This function is to write register and then readback to make |
| 703 | * sure whether BB and RF is OK |
| 704 | * input: net_device *dev |
| 705 | * HW90_BLOCK_E CheckBlock |
| 706 | * RF90_RADIO_PATH_E eRFPath //only used when checkblock is |
| 707 | * //HW90_BLOCK_RF |
| 708 | * output: none |
| 709 | * return: return whether BB and RF is ok (0:OK, 1:Fail) |
| 710 | * notice: This function may be removed in the ASIC |
| 711 | ******************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 712 | u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, |
| 713 | RF90_RADIO_PATH_E eRFPath) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 714 | { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 715 | u8 ret = 0; |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 716 | u32 i, CheckTimes = 4, reg = 0; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 717 | u32 WriteAddr[4]; |
| 718 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 719 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 720 | /* Initialize register address offset to be checked */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 721 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
| 722 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; |
| 723 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; |
| 724 | WriteAddr[HW90_BLOCK_RF] = 0x3; |
Xenia Ragiadakou | 08a4cde | 2013-06-23 06:15:16 +0300 | [diff] [blame] | 725 | RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock); |
Xenia Ragiadakou | 111857c | 2013-06-18 05:29:37 +0300 | [diff] [blame] | 726 | for (i = 0; i < CheckTimes; i++) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 727 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 728 | /* Write data to register and readback */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 729 | switch (CheckBlock) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 730 | case HW90_BLOCK_MAC: |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 731 | RT_TRACE(COMP_ERR, |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 732 | "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 733 | break; |
| 734 | |
| 735 | case HW90_BLOCK_PHY0: |
| 736 | case HW90_BLOCK_PHY1: |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 737 | write_nic_dword(dev, WriteAddr[CheckBlock], |
| 738 | WriteData[i]); |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 739 | read_nic_dword(dev, WriteAddr[CheckBlock], ®); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 740 | break; |
| 741 | |
| 742 | case HW90_BLOCK_RF: |
| 743 | WriteData[i] &= 0xfff; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 744 | rtl8192_phy_SetRFReg(dev, eRFPath, |
| 745 | WriteAddr[HW90_BLOCK_RF], |
| 746 | bMask12Bits, WriteData[i]); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 747 | /* TODO: we should not delay for such a long time. |
| 748 | Ask SD3 */ |
Xenia Ragiadakou | 26f3561 | 2013-06-23 06:15:18 +0300 | [diff] [blame] | 749 | usleep_range(1000, 1000); |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 750 | reg = rtl8192_phy_QueryRFReg(dev, eRFPath, |
| 751 | WriteAddr[HW90_BLOCK_RF], |
| 752 | bMask12Bits); |
Xenia Ragiadakou | 26f3561 | 2013-06-23 06:15:18 +0300 | [diff] [blame] | 753 | usleep_range(1000, 1000); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 754 | break; |
| 755 | |
| 756 | default: |
| 757 | ret = 1; |
| 758 | break; |
| 759 | } |
| 760 | |
| 761 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 762 | /* Check whether readback data is correct */ |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 763 | if (reg != WriteData[i]) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 764 | RT_TRACE((COMP_PHY|COMP_ERR), |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 765 | "error reg: %x, WriteData: %x\n", |
| 766 | reg, WriteData[i]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 767 | ret = 1; |
| 768 | break; |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | return ret; |
| 773 | } |
| 774 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 775 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 776 | * function: This function initializes BB&RF |
| 777 | * input: net_device *dev |
| 778 | * output: none |
| 779 | * return: none |
| 780 | * notice: Initialization value may change all the time, so please make |
| 781 | * sure it has been synced with the newest. |
| 782 | ******************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 783 | void rtl8192_BB_Config_ParaFile(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 784 | { |
| 785 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 786 | u8 reg_u8 = 0, eCheckItem = 0, status = 0; |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 787 | u32 reg_u32 = 0; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 788 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 789 | /************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 790 | * <1> Initialize BaseBand |
| 791 | *************************************/ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 792 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 793 | /* --set BB Global Reset-- */ |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 794 | read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8); |
Xenia Ragiadakou | 83e6d9e | 2013-06-19 04:58:06 +0300 | [diff] [blame] | 795 | write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 796 | mdelay(50); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 797 | /* ---set BB reset Active--- */ |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 798 | read_nic_dword(dev, CPU_GEN, ®_u32); |
| 799 | write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST))); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 800 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 801 | /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */ |
| 802 | /* TODO: this function should be removed on ASIC */ |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 803 | for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0; |
| 804 | eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { |
| 805 | /* don't care RF path */ |
Xenia Ragiadakou | a60d4d6 | 2013-06-23 06:15:17 +0300 | [diff] [blame] | 806 | status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, |
| 807 | (RF90_RADIO_PATH_E)0); |
| 808 | if (status != 0) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 809 | RT_TRACE((COMP_ERR | COMP_PHY), |
| 810 | "PHY_RF8256_Config(): Check PHY%d Fail!!\n", |
| 811 | eCheckItem-1); |
Xenia Ragiadakou | 111857c | 2013-06-18 05:29:37 +0300 | [diff] [blame] | 812 | return; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 813 | } |
| 814 | } |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 815 | /* ---- Set CCK and OFDM Block "OFF"---- */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 816 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 817 | /* ----BB Register Initilazation---- */ |
| 818 | /* ==m==>Set PHY REG From Header<==m== */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 819 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); |
| 820 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 821 | /* ----Set BB reset de-Active---- */ |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 822 | read_nic_dword(dev, CPU_GEN, ®_u32); |
| 823 | write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 824 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 825 | /* ----BB AGC table Initialization---- */ |
| 826 | /* ==m==>Set PHY REG From Header<==m== */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 827 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); |
| 828 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 829 | /* ----Enable XSTAL ---- */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 830 | write_nic_byte_E(dev, 0x5e, 0x00); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 831 | if (priv->card_8192_version == (u8)VERSION_819xU_A) { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 832 | /* Antenna gain offset from B/C/D to A */ |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 833 | reg_u32 = (priv->AntennaTxPwDiff[1]<<4 | |
| 834 | priv->AntennaTxPwDiff[0]); |
| 835 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), |
| 836 | reg_u32); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 837 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 838 | /* XSTALLCap */ |
Xenia Ragiadakou | 07ecbbf | 2013-06-18 05:29:39 +0300 | [diff] [blame] | 839 | reg_u32 = priv->CrystalCap & 0xf; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 840 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, |
| 841 | reg_u32); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 842 | } |
| 843 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 844 | /* Check if the CCK HighPower is turned ON. |
| 845 | This is used to calculate PWDB. */ |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 846 | priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev, |
| 847 | rFPGA0_XA_HSSIParameter2, |
| 848 | 0x200); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 849 | return; |
| 850 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 851 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 852 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 853 | * function: This function initializes BB&RF |
| 854 | * input: net_device *dev |
| 855 | * output: none |
| 856 | * return: none |
| 857 | * notice: Initialization value may change all the time, so please make |
| 858 | * sure it has been synced with the newest. |
| 859 | *****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 860 | void rtl8192_BBConfig(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 861 | { |
| 862 | rtl8192_InitBBRFRegDef(dev); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 863 | /* config BB&RF. As hardCode based initialization has not been well |
| 864 | * implemented, so use file first. |
| 865 | * FIXME: should implement it for hardcode? */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 866 | rtl8192_BB_Config_ParaFile(dev); |
| 867 | return; |
| 868 | } |
| 869 | |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 870 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 871 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 872 | * function: This function obtains the initialization value of Tx power Level |
| 873 | * offset |
| 874 | * input: net_device *dev |
| 875 | * output: none |
| 876 | * return: none |
| 877 | *****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 878 | void rtl8192_phy_getTxPower(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 879 | { |
| 880 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 881 | u8 tmp; |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 882 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 883 | read_nic_dword(dev, rTxAGC_Rate18_06, |
| 884 | &priv->MCSTxPowerLevelOriginalOffset[0]); |
| 885 | read_nic_dword(dev, rTxAGC_Rate54_24, |
| 886 | &priv->MCSTxPowerLevelOriginalOffset[1]); |
| 887 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, |
| 888 | &priv->MCSTxPowerLevelOriginalOffset[2]); |
| 889 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, |
| 890 | &priv->MCSTxPowerLevelOriginalOffset[3]); |
| 891 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, |
| 892 | &priv->MCSTxPowerLevelOriginalOffset[4]); |
| 893 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, |
| 894 | &priv->MCSTxPowerLevelOriginalOffset[5]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 895 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 896 | /* Read rx initial gain */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 897 | read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]); |
| 898 | read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]); |
| 899 | read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]); |
| 900 | read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]); |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 901 | RT_TRACE(COMP_INIT, |
| 902 | "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", |
| 903 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
| 904 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 905 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 906 | /* Read framesync */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 907 | read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync); |
| 908 | read_nic_byte(dev, rOFDM0_RxDetector2, &tmp); |
| 909 | priv->framesyncC34 = tmp; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 910 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", |
| 911 | rOFDM0_RxDetector3, priv->framesync); |
| 912 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 913 | /* Read SIFS (save the value read fome MACPHY_REG.txt) */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 914 | read_nic_word(dev, SIFS, &priv->SifsTime); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 915 | |
| 916 | return; |
| 917 | } |
| 918 | |
| 919 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 920 | * function: This function sets the initialization value of Tx power Level |
| 921 | * offset |
| 922 | * input: net_device *dev |
| 923 | * u8 channel |
| 924 | * output: none |
| 925 | * return: none |
| 926 | ******************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 927 | void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 928 | { |
| 929 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 930 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; |
| 931 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; |
| 932 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 933 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 934 | case RF_8256: |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 935 | /* need further implement */ |
| 936 | PHY_SetRF8256CCKTxPower(dev, powerlevel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 937 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
| 938 | break; |
| 939 | default: |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 940 | RT_TRACE((COMP_PHY|COMP_ERR), |
| 941 | "error RF chipID(8225 or 8258) in function %s()\n", |
Xenia Ragiadakou | 08a4cde | 2013-06-23 06:15:16 +0300 | [diff] [blame] | 942 | __func__); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 943 | break; |
| 944 | } |
| 945 | return; |
| 946 | } |
| 947 | |
| 948 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 949 | * function: This function checks Rf chip to do RF config |
| 950 | * input: net_device *dev |
| 951 | * output: none |
| 952 | * return: only 8256 is supported |
| 953 | ******************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 954 | void rtl8192_phy_RFConfig(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 955 | { |
| 956 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 957 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 958 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 959 | case RF_8256: |
| 960 | PHY_RF8256_Config(dev); |
| 961 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 962 | default: |
| 963 | RT_TRACE(COMP_ERR, "error chip id\n"); |
| 964 | break; |
| 965 | } |
| 966 | return; |
| 967 | } |
| 968 | |
| 969 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 970 | * function: This function updates Initial gain |
| 971 | * input: net_device *dev |
| 972 | * output: none |
| 973 | * return: As Windows has not implemented this, wait for complement |
| 974 | ******************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 975 | void rtl8192_phy_updateInitGain(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 976 | { |
| 977 | return; |
| 978 | } |
| 979 | |
| 980 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 981 | * function: This function read RF parameters from general head file, |
| 982 | * and do RF 3-wire |
| 983 | * input: net_device *dev |
| 984 | * RF90_RADIO_PATH_E eRFPath |
| 985 | * output: none |
| 986 | * return: return code show if RF configuration is successful(0:pass, 1:fail) |
| 987 | * notice: Delay may be required for RF configuration |
| 988 | *****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 989 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, |
| 990 | RF90_RADIO_PATH_E eRFPath) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 991 | { |
| 992 | |
| 993 | int i; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 994 | u8 ret = 0; |
| 995 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 996 | switch (eRFPath) { |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 997 | case RF90_PATH_A: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 998 | for (i = 0; i < RadioA_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 999 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1000 | if (rtl819XRadioA_Array[i] == 0xfe) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1001 | mdelay(100); |
| 1002 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1003 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1004 | rtl8192_phy_SetRFReg(dev, eRFPath, |
| 1005 | rtl819XRadioA_Array[i], |
| 1006 | bMask12Bits, |
| 1007 | rtl819XRadioA_Array[i+1]); |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1008 | mdelay(1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1009 | |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1010 | } |
| 1011 | break; |
| 1012 | case RF90_PATH_B: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 1013 | for (i = 0; i < RadioB_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1014 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1015 | if (rtl819XRadioB_Array[i] == 0xfe) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1016 | mdelay(100); |
| 1017 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1018 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1019 | rtl8192_phy_SetRFReg(dev, eRFPath, |
| 1020 | rtl819XRadioB_Array[i], |
| 1021 | bMask12Bits, |
| 1022 | rtl819XRadioB_Array[i+1]); |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1023 | mdelay(1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1024 | |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1025 | } |
| 1026 | break; |
| 1027 | case RF90_PATH_C: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 1028 | for (i = 0; i < RadioC_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1029 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1030 | if (rtl819XRadioC_Array[i] == 0xfe) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1031 | mdelay(100); |
| 1032 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1033 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1034 | rtl8192_phy_SetRFReg(dev, eRFPath, |
| 1035 | rtl819XRadioC_Array[i], |
| 1036 | bMask12Bits, |
| 1037 | rtl819XRadioC_Array[i+1]); |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1038 | mdelay(1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1039 | |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1040 | } |
| 1041 | break; |
| 1042 | case RF90_PATH_D: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 1043 | for (i = 0; i < RadioD_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1044 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1045 | if (rtl819XRadioD_Array[i] == 0xfe) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1046 | mdelay(100); |
| 1047 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1048 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1049 | rtl8192_phy_SetRFReg(dev, eRFPath, |
| 1050 | rtl819XRadioD_Array[i], |
| 1051 | bMask12Bits, |
| 1052 | rtl819XRadioD_Array[i+1]); |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 1053 | mdelay(1); |
| 1054 | |
| 1055 | } |
| 1056 | break; |
| 1057 | default: |
| 1058 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1059 | } |
| 1060 | |
Joe Perches | 859171c | 2010-11-14 19:04:48 -0800 | [diff] [blame] | 1061 | return ret; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1062 | |
| 1063 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1064 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1065 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1066 | * function: This function sets Tx Power of the channel |
| 1067 | * input: net_device *dev |
| 1068 | * u8 channel |
| 1069 | * output: none |
| 1070 | * return: none |
| 1071 | * notice: |
| 1072 | ******************************************************************************/ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1073 | void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) |
| 1074 | { |
| 1075 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1076 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; |
| 1077 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; |
| 1078 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1079 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1080 | case RF_8225: |
| 1081 | #ifdef TO_DO_LIST |
| 1082 | PHY_SetRF8225CckTxPower(Adapter, powerlevel); |
| 1083 | PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); |
| 1084 | #endif |
| 1085 | break; |
| 1086 | |
| 1087 | case RF_8256: |
| 1088 | PHY_SetRF8256CCKTxPower(dev, powerlevel); |
| 1089 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
| 1090 | break; |
| 1091 | |
| 1092 | case RF_8258: |
| 1093 | break; |
| 1094 | default: |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1095 | RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1096 | break; |
| 1097 | } |
| 1098 | return; |
| 1099 | } |
| 1100 | |
| 1101 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1102 | * function: This function sets RF state on or off |
| 1103 | * input: net_device *dev |
| 1104 | * RT_RF_POWER_STATE eRFPowerState //Power State to set |
| 1105 | * output: none |
| 1106 | * return: none |
| 1107 | * notice: |
| 1108 | *****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 1109 | bool rtl8192_SetRFPowerState(struct net_device *dev, |
| 1110 | RT_RF_POWER_STATE eRFPowerState) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1111 | { |
| 1112 | bool bResult = true; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1113 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1114 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1115 | if (eRFPowerState == priv->ieee80211->eRFPowerState) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1116 | return false; |
| 1117 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1118 | if (priv->SetRFPowerStateInProgress == true) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1119 | return false; |
| 1120 | |
| 1121 | priv->SetRFPowerStateInProgress = true; |
| 1122 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1123 | switch (priv->rf_chip) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1124 | case RF_8256: |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1125 | switch (eRFPowerState) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1126 | case eRfOn: |
| 1127 | /* RF-A, RF-B */ |
| 1128 | /* enable RF-Chip A/B - 0x860[4] */ |
| 1129 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, |
| 1130 | 0x1); |
| 1131 | /* analog to digital on - 0x88c[9:8] */ |
| 1132 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, |
| 1133 | 0x3); |
| 1134 | /* digital to analog on - 0x880[4:3] */ |
| 1135 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, |
| 1136 | 0x3); |
| 1137 | /* rx antenna on - 0xc04[1:0] */ |
| 1138 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); |
| 1139 | /* rx antenna on - 0xd04[1:0] */ |
| 1140 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); |
| 1141 | /* analog to digital part2 on - 0x880[6:5] */ |
| 1142 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, |
| 1143 | 0x3); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1144 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1145 | break; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1146 | |
| 1147 | case eRfSleep: |
| 1148 | |
| 1149 | break; |
| 1150 | |
| 1151 | case eRfOff: |
| 1152 | /* RF-A, RF-B */ |
| 1153 | /* disable RF-Chip A/B - 0x860[4] */ |
| 1154 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, |
| 1155 | 0x0); |
| 1156 | /* analog to digital off, for power save */ |
| 1157 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, |
| 1158 | 0x0); /* 0x88c[11:8] */ |
| 1159 | /* digital to analog off, for power save - 0x880[4:3] */ |
| 1160 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, |
| 1161 | 0x0); |
| 1162 | /* rx antenna off - 0xc04[3:0] */ |
| 1163 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); |
| 1164 | /* rx antenna off - 0xd04[3:0] */ |
| 1165 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); |
| 1166 | /* analog to digital part2 off, for power save */ |
| 1167 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, |
| 1168 | 0x0); /* 0x880[6:5] */ |
| 1169 | |
| 1170 | break; |
| 1171 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1172 | default: |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1173 | bResult = false; |
| 1174 | RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n", |
| 1175 | __func__, eRFPowerState); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1176 | break; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1177 | } |
| 1178 | break; |
| 1179 | default: |
| 1180 | RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); |
| 1181 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1182 | } |
| 1183 | #ifdef TO_DO_LIST |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1184 | if (bResult) { |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1185 | /* Update current RF state variable. */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1186 | pHalData->eRFPowerState = eRFPowerState; |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1187 | switch (pHalData->RFChipID) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1188 | case RF_8256: |
| 1189 | switch (pHalData->eRFPowerState) { |
| 1190 | case eRfOff: |
| 1191 | /* If Rf off reason is from IPS, |
| 1192 | LED should blink with no link */ |
| 1193 | if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS) |
| 1194 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); |
| 1195 | else |
| 1196 | /* Turn off LED if RF is not ON. */ |
| 1197 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1198 | break; |
| 1199 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1200 | case eRfOn: |
| 1201 | /* Turn on RF we are still linked, which might |
| 1202 | happen when we quickly turn off and on HW RF. |
| 1203 | */ |
| 1204 | if (pMgntInfo->bMediaConnect == TRUE) |
| 1205 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); |
| 1206 | else |
| 1207 | /* Turn off LED if RF is not ON. */ |
| 1208 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); |
| 1209 | break; |
| 1210 | |
| 1211 | default: |
| 1212 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1213 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1214 | break; |
| 1215 | |
| 1216 | default: |
| 1217 | RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n", |
| 1218 | __func__); |
| 1219 | break; |
| 1220 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1221 | |
| 1222 | } |
| 1223 | #endif |
| 1224 | priv->SetRFPowerStateInProgress = false; |
| 1225 | |
| 1226 | return bResult; |
| 1227 | } |
| 1228 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1229 | /****************************************************************************** |
| 1230 | * function: This function sets command table variable (struct SwChnlCmd). |
| 1231 | * input: SwChnlCmd *CmdTable //table to be set |
| 1232 | * u32 CmdTableIdx //variable index in table to be set |
| 1233 | * u32 CmdTableSz //table size |
| 1234 | * SwChnlCmdID CmdID //command ID to set |
| 1235 | * u32 Para1 |
| 1236 | * u32 Para2 |
| 1237 | * u32 msDelay |
| 1238 | * output: |
| 1239 | * return: true if finished, false otherwise |
| 1240 | * notice: |
| 1241 | ******************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 1242 | u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx, |
| 1243 | u32 CmdTableSz, SwChnlCmdID CmdID, u32 Para1, |
| 1244 | u32 Para2, u32 msDelay) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1245 | { |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 1246 | SwChnlCmd *pCmd; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1247 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1248 | if (CmdTable == NULL) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1249 | RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1250 | return false; |
| 1251 | } |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1252 | if (CmdTableIdx >= CmdTableSz) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1253 | RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", |
| 1254 | __func__, CmdTableIdx, CmdTableSz); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1255 | return false; |
| 1256 | } |
| 1257 | |
| 1258 | pCmd = CmdTable + CmdTableIdx; |
| 1259 | pCmd->CmdID = CmdID; |
| 1260 | pCmd->Para1 = Para1; |
| 1261 | pCmd->Para2 = Para2; |
| 1262 | pCmd->msDelay = msDelay; |
| 1263 | |
| 1264 | return true; |
| 1265 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1266 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1267 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1268 | * function: This function sets channel step by step |
| 1269 | * input: net_device *dev |
| 1270 | * u8 channel |
| 1271 | * u8 *stage //3 stages |
| 1272 | * u8 *step |
| 1273 | * u32 *delay //whether need to delay |
| 1274 | * output: store new stage, step and delay for next step |
| 1275 | * (combine with function above) |
| 1276 | * return: true if finished, false otherwise |
| 1277 | * notice: Wait for simpler function to replace it |
| 1278 | *****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 1279 | u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, |
| 1280 | u8 *step, u32 *delay) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1281 | { |
| 1282 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1283 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; |
| 1284 | u32 PreCommonCmdCnt; |
| 1285 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; |
| 1286 | u32 PostCommonCmdCnt; |
| 1287 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; |
| 1288 | u32 RfDependCmdCnt; |
| 1289 | SwChnlCmd *CurrentCmd = NULL; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1290 | u8 eRFPath; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1291 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1292 | RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n", |
Xenia Ragiadakou | 08a4cde | 2013-06-23 06:15:16 +0300 | [diff] [blame] | 1293 | __func__, *stage, *step, channel); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1294 | if (!IsLegalChannel(priv->ieee80211, channel)) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1295 | RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel); |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1296 | /* return true to tell upper caller function this channel |
| 1297 | setting is finished! Or it will in while loop. */ |
| 1298 | return true; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1299 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1300 | /* FIXME: need to check whether channel is legal or not here */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1301 | |
| 1302 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1303 | /* <1> Fill up pre common command. */ |
| 1304 | PreCommonCmdCnt = 0; |
| 1305 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, |
| 1306 | MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, |
| 1307 | 0, 0, 0); |
| 1308 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, |
| 1309 | MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1310 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1311 | /* <2> Fill up post common command. */ |
| 1312 | PostCommonCmdCnt = 0; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1313 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1314 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, |
| 1315 | MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1316 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1317 | /* <3> Fill up RF dependent command. */ |
| 1318 | RfDependCmdCnt = 0; |
| 1319 | switch (priv->rf_chip) { |
| 1320 | case RF_8225: |
| 1321 | if (!(channel >= 1 && channel <= 14)) { |
| 1322 | RT_TRACE(COMP_ERR, |
| 1323 | "illegal channel for Zebra 8225: %d\n", |
| 1324 | channel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1325 | return true; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1326 | } |
| 1327 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, |
| 1328 | MAX_RFDEPENDCMD_CNT, |
| 1329 | CmdID_RF_WriteReg, |
| 1330 | rZebra1_Channel, |
| 1331 | RF_CHANNEL_TABLE_ZEBRA[channel], |
| 1332 | 10); |
| 1333 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, |
| 1334 | MAX_RFDEPENDCMD_CNT, |
| 1335 | CmdID_End, 0, 0, 0); |
| 1336 | break; |
| 1337 | |
| 1338 | case RF_8256: |
| 1339 | /* TEST!! This is not the table for 8256!! */ |
| 1340 | if (!(channel >= 1 && channel <= 14)) { |
| 1341 | RT_TRACE(COMP_ERR, |
| 1342 | "illegal channel for Zebra 8256: %d\n", |
| 1343 | channel); |
| 1344 | return true; |
| 1345 | } |
| 1346 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, |
| 1347 | MAX_RFDEPENDCMD_CNT, |
| 1348 | CmdID_RF_WriteReg, |
| 1349 | rZebra1_Channel, channel, 10); |
| 1350 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, |
| 1351 | MAX_RFDEPENDCMD_CNT, |
| 1352 | CmdID_End, 0, 0, 0); |
| 1353 | break; |
| 1354 | |
| 1355 | case RF_8258: |
| 1356 | break; |
| 1357 | |
| 1358 | default: |
| 1359 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); |
| 1360 | return true; |
| 1361 | break; |
| 1362 | } |
| 1363 | |
| 1364 | |
| 1365 | do { |
| 1366 | switch (*stage) { |
| 1367 | case 0: |
| 1368 | CurrentCmd = &PreCommonCmd[*step]; |
| 1369 | break; |
| 1370 | case 1: |
| 1371 | CurrentCmd = &RfDependCmd[*step]; |
| 1372 | break; |
| 1373 | case 2: |
| 1374 | CurrentCmd = &PostCommonCmd[*step]; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1375 | break; |
| 1376 | } |
| 1377 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1378 | if (CurrentCmd->CmdID == CmdID_End) { |
| 1379 | if ((*stage) == 2) { |
| 1380 | (*delay) = CurrentCmd->msDelay; |
| 1381 | return true; |
| 1382 | } else { |
| 1383 | (*stage)++; |
| 1384 | (*step) = 0; |
| 1385 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1386 | } |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1387 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1388 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1389 | switch (CurrentCmd->CmdID) { |
| 1390 | case CmdID_SetTxPowerLevel: |
| 1391 | if (priv->card_8192_version == (u8)VERSION_819xU_A) |
| 1392 | /* consider it later! */ |
| 1393 | rtl8192_SetTxPowerLevel(dev, channel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1394 | break; |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1395 | case CmdID_WritePortUlong: |
| 1396 | write_nic_dword(dev, CurrentCmd->Para1, |
| 1397 | CurrentCmd->Para2); |
| 1398 | break; |
| 1399 | case CmdID_WritePortUshort: |
| 1400 | write_nic_word(dev, CurrentCmd->Para1, |
| 1401 | (u16)CurrentCmd->Para2); |
| 1402 | break; |
| 1403 | case CmdID_WritePortUchar: |
| 1404 | write_nic_byte(dev, CurrentCmd->Para1, |
| 1405 | (u8)CurrentCmd->Para2); |
| 1406 | break; |
| 1407 | case CmdID_RF_WriteReg: |
| 1408 | for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { |
| 1409 | rtl8192_phy_SetRFReg(dev, |
| 1410 | (RF90_RADIO_PATH_E)eRFPath, |
| 1411 | CurrentCmd->Para1, |
| 1412 | bZebra1_ChannelNum, |
| 1413 | CurrentCmd->Para2); |
| 1414 | } |
| 1415 | break; |
| 1416 | default: |
| 1417 | break; |
| 1418 | } |
| 1419 | |
| 1420 | break; |
| 1421 | } while (true); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1422 | |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1423 | (*delay) = CurrentCmd->msDelay; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1424 | (*step)++; |
| 1425 | return false; |
| 1426 | } |
| 1427 | |
| 1428 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1429 | * function: This function does actually set channel work |
| 1430 | * input: net_device *dev |
| 1431 | * u8 channel |
| 1432 | * output: none |
| 1433 | * return: none |
| 1434 | * notice: We should not call this function directly |
| 1435 | *****************************************************************************/ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1436 | void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) |
| 1437 | { |
| 1438 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1439 | u32 delay = 0; |
| 1440 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1441 | while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, |
| 1442 | &priv->SwChnlStep, &delay)) { |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1443 | if (!priv->up) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1444 | break; |
| 1445 | } |
| 1446 | } |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1447 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1448 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1449 | * function: Callback routine of the work item for switch channel. |
| 1450 | * input: net_device *dev |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1451 | * |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1452 | * output: none |
| 1453 | * return: none |
| 1454 | *****************************************************************************/ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1455 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) |
| 1456 | { |
| 1457 | |
| 1458 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1459 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1460 | RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", |
| 1461 | priv->chan); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1462 | |
| 1463 | |
Xenia Ragiadakou | 83e6d9e | 2013-06-19 04:58:06 +0300 | [diff] [blame] | 1464 | rtl8192_phy_FinishSwChnlNow(dev, priv->chan); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1465 | |
| 1466 | RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); |
| 1467 | } |
| 1468 | |
| 1469 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1470 | * function: This function scheduled actual work item to set channel |
| 1471 | * input: net_device *dev |
| 1472 | * u8 channel //channel to set |
| 1473 | * output: none |
| 1474 | * return: return code show if workitem is scheduled (1:pass, 0:fail) |
| 1475 | * notice: Delay may be required for RF configuration |
| 1476 | ******************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 1477 | u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1478 | { |
| 1479 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 08a4cde | 2013-06-23 06:15:16 +0300 | [diff] [blame] | 1480 | RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__, |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1481 | priv->SwChnlInProgress); |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1482 | if (!priv->up) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1483 | return false; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1484 | if (priv->SwChnlInProgress) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1485 | return false; |
| 1486 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1487 | /* -------------------------------------------- */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1488 | switch (priv->ieee80211->mode) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1489 | case WIRELESS_MODE_A: |
| 1490 | case WIRELESS_MODE_N_5G: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 1491 | if (channel <= 14) { |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1492 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1493 | return false; |
| 1494 | } |
| 1495 | break; |
| 1496 | case WIRELESS_MODE_B: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 1497 | if (channel > 14) { |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1498 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1499 | return false; |
| 1500 | } |
| 1501 | break; |
| 1502 | case WIRELESS_MODE_G: |
| 1503 | case WIRELESS_MODE_N_24G: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame] | 1504 | if (channel > 14) { |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1505 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1506 | return false; |
| 1507 | } |
| 1508 | break; |
| 1509 | } |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1510 | /* -------------------------------------------- */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1511 | |
| 1512 | priv->SwChnlInProgress = true; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1513 | if (channel == 0) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1514 | channel = 1; |
| 1515 | |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1516 | priv->chan = channel; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1517 | |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1518 | priv->SwChnlStage = 0; |
| 1519 | priv->SwChnlStep = 0; |
Xenia Ragiadakou | d75340e | 2013-06-15 07:29:06 +0300 | [diff] [blame] | 1520 | if (priv->up) |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1521 | rtl8192_SwChnl_WorkItem(dev); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1522 | |
| 1523 | priv->SwChnlInProgress = false; |
| 1524 | return true; |
| 1525 | } |
| 1526 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1527 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1528 | * function: Callback routine of the work item for set bandwidth mode. |
| 1529 | * input: net_device *dev |
| 1530 | * output: none |
| 1531 | * return: none |
| 1532 | * notice: I doubt whether SetBWModeInProgress flag is necessary as we can |
| 1533 | * test whether current work in the queue or not.//do I? |
| 1534 | *****************************************************************************/ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1535 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) |
| 1536 | { |
| 1537 | |
| 1538 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1539 | u8 regBwOpMode; |
| 1540 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1541 | RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__, |
Xenia Ragiadakou | 4a8d113 | 2013-06-09 14:38:43 +0300 | [diff] [blame] | 1542 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1543 | |
| 1544 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1545 | if (priv->rf_chip == RF_PSEUDO_11N) { |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1546 | priv->SetBWModeInProgress = false; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1547 | return; |
| 1548 | } |
| 1549 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1550 | /* <1> Set MAC register */ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 1551 | read_nic_byte(dev, BW_OPMODE, ®BwOpMode); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1552 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1553 | switch (priv->CurrentChannelBW) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1554 | case HT_CHANNEL_WIDTH_20: |
| 1555 | regBwOpMode |= BW_OPMODE_20MHZ; |
| 1556 | /* We have not verify whether this register works */ |
| 1557 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 1558 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1559 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1560 | case HT_CHANNEL_WIDTH_20_40: |
| 1561 | regBwOpMode &= ~BW_OPMODE_20MHZ; |
| 1562 | /* We have not verify whether this register works */ |
| 1563 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 1564 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1565 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1566 | default: |
| 1567 | RT_TRACE(COMP_ERR, |
| 1568 | "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", |
| 1569 | priv->CurrentChannelBW); |
| 1570 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1571 | } |
| 1572 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1573 | /* <2> Set PHY related register */ |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1574 | switch (priv->CurrentChannelBW) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1575 | case HT_CHANNEL_WIDTH_20: |
| 1576 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); |
| 1577 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); |
| 1578 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, |
| 1579 | 0x00100000, 1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1580 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1581 | /* Correct the tx power for CCK rate in 20M. */ |
| 1582 | priv->cck_present_attentuation = |
| 1583 | priv->cck_present_attentuation_20Mdefault + |
| 1584 | priv->cck_present_attentuation_difference; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1585 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1586 | if (priv->cck_present_attentuation > 22) |
| 1587 | priv->cck_present_attentuation = 22; |
| 1588 | if (priv->cck_present_attentuation < 0) |
| 1589 | priv->cck_present_attentuation = 0; |
| 1590 | RT_TRACE(COMP_INIT, |
| 1591 | "20M, pHalData->CCKPresentAttentuation = %d\n", |
| 1592 | priv->cck_present_attentuation); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1593 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1594 | if (priv->chan == 14 && !priv->bcck_in_ch14) { |
| 1595 | priv->bcck_in_ch14 = TRUE; |
| 1596 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1597 | } else if (priv->chan != 14 && priv->bcck_in_ch14) { |
| 1598 | priv->bcck_in_ch14 = FALSE; |
| 1599 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1600 | } else { |
| 1601 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1602 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1603 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1604 | break; |
| 1605 | case HT_CHANNEL_WIDTH_20_40: |
| 1606 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); |
| 1607 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); |
| 1608 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, |
| 1609 | priv->nCur40MhzPrimeSC>>1); |
| 1610 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); |
| 1611 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, |
| 1612 | priv->nCur40MhzPrimeSC); |
| 1613 | priv->cck_present_attentuation = |
| 1614 | priv->cck_present_attentuation_40Mdefault + |
| 1615 | priv->cck_present_attentuation_difference; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1616 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1617 | if (priv->cck_present_attentuation > 22) |
| 1618 | priv->cck_present_attentuation = 22; |
| 1619 | if (priv->cck_present_attentuation < 0) |
| 1620 | priv->cck_present_attentuation = 0; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1621 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1622 | RT_TRACE(COMP_INIT, |
| 1623 | "40M, pHalData->CCKPresentAttentuation = %d\n", |
| 1624 | priv->cck_present_attentuation); |
| 1625 | if (priv->chan == 14 && !priv->bcck_in_ch14) { |
| 1626 | priv->bcck_in_ch14 = true; |
| 1627 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1628 | } else if (priv->chan != 14 && priv->bcck_in_ch14) { |
| 1629 | priv->bcck_in_ch14 = false; |
| 1630 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1631 | } else { |
| 1632 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
| 1633 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1634 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1635 | break; |
| 1636 | default: |
| 1637 | RT_TRACE(COMP_ERR, |
| 1638 | "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", |
| 1639 | priv->CurrentChannelBW); |
| 1640 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1641 | |
| 1642 | } |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1643 | /* Skip over setting of J-mode in BB register here. |
| 1644 | Default value is "None J mode". */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1645 | |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1646 | /* <3> Set RF related register */ |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1647 | switch (priv->rf_chip) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1648 | case RF_8225: |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1649 | #ifdef TO_DO_LIST |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1650 | PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1651 | #endif |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1652 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1653 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1654 | case RF_8256: |
| 1655 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); |
| 1656 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1657 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1658 | case RF_8258: |
| 1659 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1660 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1661 | case RF_PSEUDO_11N: |
| 1662 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1663 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1664 | default: |
| 1665 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); |
| 1666 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1667 | } |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1668 | priv->SetBWModeInProgress = false; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1669 | |
Xenia Ragiadakou | 0081fcc | 2013-06-25 02:28:57 +0300 | [diff] [blame] | 1670 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n", |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1671 | atomic_read(&priv->ieee80211->atm_swbw)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1672 | } |
| 1673 | |
| 1674 | /****************************************************************************** |
Xenia Ragiadakou | 5f2392b | 2013-06-19 04:58:07 +0300 | [diff] [blame] | 1675 | * function: This function schedules bandwidth switch work. |
| 1676 | * input: struct net_deviceq *dev |
| 1677 | * HT_CHANNEL_WIDTH bandwidth //20M or 40M |
| 1678 | * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care |
| 1679 | * output: none |
| 1680 | * return: none |
| 1681 | * notice: I doubt whether SetBWModeInProgress flag is necessary as we can |
| 1682 | * test whether current work in the queue or not.//do I? |
| 1683 | *****************************************************************************/ |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 1684 | void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth, |
| 1685 | HT_EXTCHNL_OFFSET offset) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1686 | { |
| 1687 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1688 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1689 | if (priv->SetBWModeInProgress) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1690 | return; |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1691 | priv->SetBWModeInProgress = true; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1692 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 1693 | priv->CurrentChannelBW = bandwidth; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1694 | |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 1695 | if (offset == HT_EXTCHNL_OFFSET_LOWER) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1696 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
Xenia Ragiadakou | 7993163 | 2013-06-18 05:29:41 +0300 | [diff] [blame] | 1697 | else if (offset == HT_EXTCHNL_OFFSET_UPPER) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1698 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
| 1699 | else |
| 1700 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; |
| 1701 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1702 | rtl8192_SetBWModeWorkItem(dev); |
| 1703 | |
| 1704 | } |
| 1705 | |
| 1706 | void InitialGain819xUsb(struct net_device *dev, u8 Operation) |
| 1707 | { |
| 1708 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1709 | |
| 1710 | priv->InitialGainOperateType = Operation; |
| 1711 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1712 | if (priv->up) |
Xenia Ragiadakou | 83e6d9e | 2013-06-19 04:58:06 +0300 | [diff] [blame] | 1713 | queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1714 | } |
| 1715 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1716 | extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) |
| 1717 | { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1718 | struct delayed_work *dwork = container_of(work, struct delayed_work, |
| 1719 | work); |
| 1720 | struct r8192_priv *priv = container_of(dwork, struct r8192_priv, |
| 1721 | initialgain_operate_wq); |
| 1722 | struct net_device *dev = priv->ieee80211->dev; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1723 | #define SCAN_RX_INITIAL_GAIN 0x17 |
| 1724 | #define POWER_DETECTION_TH 0x08 |
Xenia Ragiadakou | 9f66ddb | 2013-06-18 05:29:40 +0300 | [diff] [blame] | 1725 | u32 bitmask; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1726 | u8 initial_gain; |
| 1727 | u8 Operation; |
| 1728 | |
| 1729 | Operation = priv->InitialGainOperateType; |
| 1730 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1731 | switch (Operation) { |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1732 | case IG_Backup: |
| 1733 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); |
| 1734 | initial_gain = SCAN_RX_INITIAL_GAIN; |
| 1735 | bitmask = bMaskByte0; |
| 1736 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 1737 | /* FW DIG OFF */ |
| 1738 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); |
| 1739 | priv->initgain_backup.xaagccore1 = |
| 1740 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask); |
| 1741 | priv->initgain_backup.xbagccore1 = |
| 1742 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask); |
| 1743 | priv->initgain_backup.xcagccore1 = |
| 1744 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask); |
| 1745 | priv->initgain_backup.xdagccore1 = |
| 1746 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask); |
| 1747 | bitmask = bMaskByte2; |
| 1748 | priv->initgain_backup.cca = |
| 1749 | (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1750 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1751 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n", |
| 1752 | priv->initgain_backup.xaagccore1); |
| 1753 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n", |
| 1754 | priv->initgain_backup.xbagccore1); |
| 1755 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n", |
| 1756 | priv->initgain_backup.xcagccore1); |
| 1757 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n", |
| 1758 | priv->initgain_backup.xdagccore1); |
| 1759 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n", |
| 1760 | priv->initgain_backup.cca); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1761 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1762 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", |
| 1763 | initial_gain); |
| 1764 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); |
| 1765 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); |
| 1766 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); |
| 1767 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); |
| 1768 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", |
| 1769 | POWER_DETECTION_TH); |
| 1770 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); |
| 1771 | break; |
| 1772 | case IG_Restore: |
| 1773 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); |
| 1774 | bitmask = 0x7f; /* Bit0 ~ Bit6 */ |
| 1775 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 1776 | /* FW DIG OFF */ |
| 1777 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1778 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1779 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, |
| 1780 | (u32)priv->initgain_backup.xaagccore1); |
| 1781 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, |
| 1782 | (u32)priv->initgain_backup.xbagccore1); |
| 1783 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask, |
| 1784 | (u32)priv->initgain_backup.xcagccore1); |
| 1785 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask, |
| 1786 | (u32)priv->initgain_backup.xdagccore1); |
| 1787 | bitmask = bMaskByte2; |
| 1788 | rtl8192_setBBreg(dev, rCCK0_CCA, bitmask, |
| 1789 | (u32)priv->initgain_backup.cca); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1790 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1791 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n", |
| 1792 | priv->initgain_backup.xaagccore1); |
| 1793 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n", |
| 1794 | priv->initgain_backup.xbagccore1); |
| 1795 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n", |
| 1796 | priv->initgain_backup.xcagccore1); |
| 1797 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n", |
| 1798 | priv->initgain_backup.xdagccore1); |
| 1799 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n", |
| 1800 | priv->initgain_backup.cca); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1801 | |
| 1802 | #ifdef RTL8190P |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1803 | SetTxPowerLevel8190(Adapter, priv->CurrentChannel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1804 | #endif |
| 1805 | #ifdef RTL8192E |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1806 | SetTxPowerLevel8190(Adapter, priv->CurrentChannel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1807 | #endif |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1808 | rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1809 | |
Xenia Ragiadakou | 1db5aa0 | 2013-06-23 06:15:15 +0300 | [diff] [blame] | 1810 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 1811 | /* FW DIG ON */ |
| 1812 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); |
| 1813 | break; |
| 1814 | default: |
| 1815 | RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); |
| 1816 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1817 | } |
| 1818 | } |