Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge |
| 3 | * |
| 4 | * Copyright 2011 Integrated Device Technology, Inc. |
| 5 | * Alexandre Bounine <alexandre.bounine@idt.com> |
| 6 | * Chul Kim <chul.kim@idt.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the Free |
| 10 | * Software Foundation; either version 2 of the License, or (at your option) |
| 11 | * any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 21 | */ |
| 22 | |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/ioport.h> |
| 27 | #include <linux/kernel.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/pci.h> |
| 30 | #include <linux/rio.h> |
| 31 | #include <linux/rio_drv.h> |
| 32 | #include <linux/dma-mapping.h> |
| 33 | #include <linux/interrupt.h> |
| 34 | #include <linux/kfifo.h> |
| 35 | #include <linux/delay.h> |
| 36 | |
| 37 | #include "tsi721.h" |
| 38 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 39 | #ifdef DEBUG |
Alexandre Bounine | cb782cd | 2016-08-02 14:06:40 -0700 | [diff] [blame] | 40 | u32 dbg_level; |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 41 | module_param(dbg_level, uint, S_IWUSR | S_IRUGO); |
| 42 | MODULE_PARM_DESC(dbg_level, "Debugging output level (default 0 = none)"); |
| 43 | #endif |
| 44 | |
Alexandre Bounine | cb782cd | 2016-08-02 14:06:40 -0700 | [diff] [blame] | 45 | static int pcie_mrrs = -1; |
| 46 | module_param(pcie_mrrs, int, S_IRUGO); |
| 47 | MODULE_PARM_DESC(pcie_mrrs, "PCIe MRRS override value (0...5)"); |
| 48 | |
Alexandre Bounine | e519685 | 2016-08-02 14:06:43 -0700 | [diff] [blame^] | 49 | static u8 mbox_sel = 0x0f; |
| 50 | module_param(mbox_sel, byte, S_IRUGO); |
| 51 | MODULE_PARM_DESC(mbox_sel, |
| 52 | "RIO Messaging MBOX Selection Mask (default: 0x0f = all)"); |
| 53 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 54 | static void tsi721_omsg_handler(struct tsi721_device *priv, int ch); |
| 55 | static void tsi721_imsg_handler(struct tsi721_device *priv, int ch); |
| 56 | |
| 57 | /** |
| 58 | * tsi721_lcread - read from local SREP config space |
| 59 | * @mport: RapidIO master port info |
| 60 | * @index: ID of RapdiIO interface |
| 61 | * @offset: Offset into configuration space |
| 62 | * @len: Length (in bytes) of the maintenance transaction |
| 63 | * @data: Value to be read into |
| 64 | * |
| 65 | * Generates a local SREP space read. Returns %0 on |
| 66 | * success or %-EINVAL on failure. |
| 67 | */ |
| 68 | static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset, |
| 69 | int len, u32 *data) |
| 70 | { |
| 71 | struct tsi721_device *priv = mport->priv; |
| 72 | |
| 73 | if (len != sizeof(u32)) |
| 74 | return -EINVAL; /* only 32-bit access is supported */ |
| 75 | |
| 76 | *data = ioread32(priv->regs + offset); |
| 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | /** |
| 82 | * tsi721_lcwrite - write into local SREP config space |
| 83 | * @mport: RapidIO master port info |
| 84 | * @index: ID of RapdiIO interface |
| 85 | * @offset: Offset into configuration space |
| 86 | * @len: Length (in bytes) of the maintenance transaction |
| 87 | * @data: Value to be written |
| 88 | * |
| 89 | * Generates a local write into SREP configuration space. Returns %0 on |
| 90 | * success or %-EINVAL on failure. |
| 91 | */ |
| 92 | static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset, |
| 93 | int len, u32 data) |
| 94 | { |
| 95 | struct tsi721_device *priv = mport->priv; |
| 96 | |
| 97 | if (len != sizeof(u32)) |
| 98 | return -EINVAL; /* only 32-bit access is supported */ |
| 99 | |
| 100 | iowrite32(data, priv->regs + offset); |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | /** |
| 106 | * tsi721_maint_dma - Helper function to generate RapidIO maintenance |
| 107 | * transactions using designated Tsi721 DMA channel. |
| 108 | * @priv: pointer to tsi721 private data |
| 109 | * @sys_size: RapdiIO transport system size |
| 110 | * @destid: Destination ID of transaction |
| 111 | * @hopcount: Number of hops to target device |
| 112 | * @offset: Offset into configuration space |
| 113 | * @len: Length (in bytes) of the maintenance transaction |
| 114 | * @data: Location to be read from or write into |
| 115 | * @do_wr: Operation flag (1 == MAINT_WR) |
| 116 | * |
| 117 | * Generates a RapidIO maintenance transaction (Read or Write). |
| 118 | * Returns %0 on success and %-EINVAL or %-EFAULT on failure. |
| 119 | */ |
| 120 | static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size, |
| 121 | u16 destid, u8 hopcount, u32 offset, int len, |
| 122 | u32 *data, int do_wr) |
| 123 | { |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 124 | void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 125 | struct tsi721_dma_desc *bd_ptr; |
| 126 | u32 rd_count, swr_ptr, ch_stat; |
| 127 | int i, err = 0; |
| 128 | u32 op = do_wr ? MAINT_WR : MAINT_RD; |
| 129 | |
| 130 | if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32))) |
| 131 | return -EINVAL; |
| 132 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 133 | bd_ptr = priv->mdma.bd_base; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 134 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 135 | rd_count = ioread32(regs + TSI721_DMAC_DRDCNT); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 136 | |
| 137 | /* Initialize DMA descriptor */ |
| 138 | bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid); |
| 139 | bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04); |
| 140 | bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset); |
| 141 | bd_ptr[0].raddr_hi = 0; |
| 142 | if (do_wr) |
| 143 | bd_ptr[0].data[0] = cpu_to_be32p(data); |
| 144 | else |
| 145 | bd_ptr[0].data[0] = 0xffffffff; |
| 146 | |
| 147 | mb(); |
| 148 | |
| 149 | /* Start DMA operation */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 150 | iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT); |
| 151 | ioread32(regs + TSI721_DMAC_DWRCNT); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 152 | i = 0; |
| 153 | |
| 154 | /* Wait until DMA transfer is finished */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 155 | while ((ch_stat = ioread32(regs + TSI721_DMAC_STS)) |
| 156 | & TSI721_DMAC_STS_RUN) { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 157 | udelay(1); |
| 158 | if (++i >= 5000000) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 159 | tsi_debug(MAINT, &priv->pdev->dev, |
| 160 | "DMA[%d] read timeout ch_status=%x", |
| 161 | priv->mdma.ch_id, ch_stat); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 162 | if (!do_wr) |
| 163 | *data = 0xffffffff; |
| 164 | err = -EIO; |
| 165 | goto err_out; |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | if (ch_stat & TSI721_DMAC_STS_ABORT) { |
| 170 | /* If DMA operation aborted due to error, |
| 171 | * reinitialize DMA channel |
| 172 | */ |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 173 | tsi_debug(MAINT, &priv->pdev->dev, "DMA ABORT ch_stat=%x", |
| 174 | ch_stat); |
| 175 | tsi_debug(MAINT, &priv->pdev->dev, |
| 176 | "OP=%d : destid=%x hc=%x off=%x", |
| 177 | do_wr ? MAINT_WR : MAINT_RD, |
| 178 | destid, hopcount, offset); |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 179 | iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT); |
| 180 | iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 181 | udelay(10); |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 182 | iowrite32(0, regs + TSI721_DMAC_DWRCNT); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 183 | udelay(1); |
| 184 | if (!do_wr) |
| 185 | *data = 0xffffffff; |
| 186 | err = -EIO; |
| 187 | goto err_out; |
| 188 | } |
| 189 | |
| 190 | if (!do_wr) |
| 191 | *data = be32_to_cpu(bd_ptr[0].data[0]); |
| 192 | |
| 193 | /* |
| 194 | * Update descriptor status FIFO RD pointer. |
| 195 | * NOTE: Skipping check and clear FIFO entries because we are waiting |
| 196 | * for transfer to be completed. |
| 197 | */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 198 | swr_ptr = ioread32(regs + TSI721_DMAC_DSWP); |
| 199 | iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 200 | err_out: |
| 201 | |
| 202 | return err; |
| 203 | } |
| 204 | |
| 205 | /** |
| 206 | * tsi721_cread_dma - Generate a RapidIO maintenance read transaction |
| 207 | * using Tsi721 BDMA engine. |
| 208 | * @mport: RapidIO master port control structure |
| 209 | * @index: ID of RapdiIO interface |
| 210 | * @destid: Destination ID of transaction |
| 211 | * @hopcount: Number of hops to target device |
| 212 | * @offset: Offset into configuration space |
| 213 | * @len: Length (in bytes) of the maintenance transaction |
| 214 | * @val: Location to be read into |
| 215 | * |
| 216 | * Generates a RapidIO maintenance read transaction. |
| 217 | * Returns %0 on success and %-EINVAL or %-EFAULT on failure. |
| 218 | */ |
| 219 | static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid, |
| 220 | u8 hopcount, u32 offset, int len, u32 *data) |
| 221 | { |
| 222 | struct tsi721_device *priv = mport->priv; |
| 223 | |
| 224 | return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount, |
| 225 | offset, len, data, 0); |
| 226 | } |
| 227 | |
| 228 | /** |
| 229 | * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction |
| 230 | * using Tsi721 BDMA engine |
| 231 | * @mport: RapidIO master port control structure |
| 232 | * @index: ID of RapdiIO interface |
| 233 | * @destid: Destination ID of transaction |
| 234 | * @hopcount: Number of hops to target device |
| 235 | * @offset: Offset into configuration space |
| 236 | * @len: Length (in bytes) of the maintenance transaction |
| 237 | * @val: Value to be written |
| 238 | * |
| 239 | * Generates a RapidIO maintenance write transaction. |
| 240 | * Returns %0 on success and %-EINVAL or %-EFAULT on failure. |
| 241 | */ |
| 242 | static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid, |
| 243 | u8 hopcount, u32 offset, int len, u32 data) |
| 244 | { |
| 245 | struct tsi721_device *priv = mport->priv; |
| 246 | u32 temp = data; |
| 247 | |
| 248 | return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount, |
| 249 | offset, len, &temp, 1); |
| 250 | } |
| 251 | |
| 252 | /** |
| 253 | * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 254 | * @priv: tsi721 device private structure |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 255 | * |
| 256 | * Handles inbound port-write interrupts. Copies PW message from an internal |
| 257 | * buffer into PW message FIFO and schedules deferred routine to process |
| 258 | * queued messages. |
| 259 | */ |
| 260 | static int |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 261 | tsi721_pw_handler(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 262 | { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 263 | u32 pw_stat; |
| 264 | u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)]; |
| 265 | |
| 266 | |
| 267 | pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT); |
| 268 | |
| 269 | if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) { |
| 270 | pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0)); |
| 271 | pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1)); |
| 272 | pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2)); |
| 273 | pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3)); |
| 274 | |
| 275 | /* Queue PW message (if there is room in FIFO), |
| 276 | * otherwise discard it. |
| 277 | */ |
| 278 | spin_lock(&priv->pw_fifo_lock); |
| 279 | if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE) |
| 280 | kfifo_in(&priv->pw_fifo, pw_buf, |
| 281 | TSI721_RIO_PW_MSG_SIZE); |
| 282 | else |
| 283 | priv->pw_discard_count++; |
| 284 | spin_unlock(&priv->pw_fifo_lock); |
| 285 | } |
| 286 | |
| 287 | /* Clear pending PW interrupts */ |
| 288 | iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL, |
| 289 | priv->regs + TSI721_RIO_PW_RX_STAT); |
| 290 | |
| 291 | schedule_work(&priv->pw_work); |
| 292 | |
| 293 | return 0; |
| 294 | } |
| 295 | |
| 296 | static void tsi721_pw_dpc(struct work_struct *work) |
| 297 | { |
| 298 | struct tsi721_device *priv = container_of(work, struct tsi721_device, |
| 299 | pw_work); |
Alexandre Bounine | 9a0b062 | 2016-03-22 14:26:44 -0700 | [diff] [blame] | 300 | union rio_pw_msg pwmsg; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 301 | |
| 302 | /* |
| 303 | * Process port-write messages |
| 304 | */ |
Alexandre Bounine | 9a0b062 | 2016-03-22 14:26:44 -0700 | [diff] [blame] | 305 | while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)&pwmsg, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 306 | TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 307 | /* Pass the port-write message to RIO core for processing */ |
Alexandre Bounine | 9a0b062 | 2016-03-22 14:26:44 -0700 | [diff] [blame] | 308 | rio_inb_pwrite_handler(&priv->mport, &pwmsg); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 309 | } |
| 310 | } |
| 311 | |
| 312 | /** |
| 313 | * tsi721_pw_enable - enable/disable port-write interface init |
| 314 | * @mport: Master port implementing the port write unit |
| 315 | * @enable: 1=enable; 0=disable port-write message handling |
| 316 | */ |
| 317 | static int tsi721_pw_enable(struct rio_mport *mport, int enable) |
| 318 | { |
| 319 | struct tsi721_device *priv = mport->priv; |
| 320 | u32 rval; |
| 321 | |
| 322 | rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE); |
| 323 | |
| 324 | if (enable) |
| 325 | rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX; |
| 326 | else |
| 327 | rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX; |
| 328 | |
| 329 | /* Clear pending PW interrupts */ |
| 330 | iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL, |
| 331 | priv->regs + TSI721_RIO_PW_RX_STAT); |
| 332 | /* Update enable bits */ |
| 333 | iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE); |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | /** |
| 339 | * tsi721_dsend - Send a RapidIO doorbell |
| 340 | * @mport: RapidIO master port info |
| 341 | * @index: ID of RapidIO interface |
| 342 | * @destid: Destination ID of target device |
| 343 | * @data: 16-bit info field of RapidIO doorbell |
| 344 | * |
| 345 | * Sends a RapidIO doorbell message. Always returns %0. |
| 346 | */ |
| 347 | static int tsi721_dsend(struct rio_mport *mport, int index, |
| 348 | u16 destid, u16 data) |
| 349 | { |
| 350 | struct tsi721_device *priv = mport->priv; |
| 351 | u32 offset; |
| 352 | |
| 353 | offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) | |
| 354 | (destid << 2); |
| 355 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 356 | tsi_debug(DBELL, &priv->pdev->dev, |
| 357 | "Send Doorbell 0x%04x to destID 0x%x", data, destid); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 358 | iowrite16be(data, priv->odb_base + offset); |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | /** |
| 364 | * tsi721_dbell_handler - Tsi721 doorbell interrupt handler |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 365 | * @priv: tsi721 device-specific data structure |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 366 | * |
| 367 | * Handles inbound doorbell interrupts. Copies doorbell entry from an internal |
| 368 | * buffer into DB message FIFO and schedules deferred routine to process |
| 369 | * queued DBs. |
| 370 | */ |
| 371 | static int |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 372 | tsi721_dbell_handler(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 373 | { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 374 | u32 regval; |
| 375 | |
| 376 | /* Disable IDB interrupts */ |
| 377 | regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); |
| 378 | regval &= ~TSI721_SR_CHINT_IDBQRCV; |
| 379 | iowrite32(regval, |
| 380 | priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); |
| 381 | |
| 382 | schedule_work(&priv->idb_work); |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | static void tsi721_db_dpc(struct work_struct *work) |
| 388 | { |
| 389 | struct tsi721_device *priv = container_of(work, struct tsi721_device, |
| 390 | idb_work); |
| 391 | struct rio_mport *mport; |
| 392 | struct rio_dbell *dbell; |
| 393 | int found = 0; |
| 394 | u32 wr_ptr, rd_ptr; |
| 395 | u64 *idb_entry; |
| 396 | u32 regval; |
| 397 | union { |
| 398 | u64 msg; |
| 399 | u8 bytes[8]; |
| 400 | } idb; |
| 401 | |
| 402 | /* |
| 403 | * Process queued inbound doorbells |
| 404 | */ |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 405 | mport = &priv->mport; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 406 | |
Alexandre Bounine | b24823e | 2012-03-05 14:59:21 -0800 | [diff] [blame] | 407 | wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; |
| 408 | rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 409 | |
| 410 | while (wr_ptr != rd_ptr) { |
| 411 | idb_entry = (u64 *)(priv->idb_base + |
| 412 | (TSI721_IDB_ENTRY_SIZE * rd_ptr)); |
| 413 | rd_ptr++; |
Alexandre Bounine | b24823e | 2012-03-05 14:59:21 -0800 | [diff] [blame] | 414 | rd_ptr %= IDB_QSIZE; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 415 | idb.msg = *idb_entry; |
| 416 | *idb_entry = 0; |
| 417 | |
| 418 | /* Process one doorbell */ |
| 419 | list_for_each_entry(dbell, &mport->dbells, node) { |
| 420 | if ((dbell->res->start <= DBELL_INF(idb.bytes)) && |
| 421 | (dbell->res->end >= DBELL_INF(idb.bytes))) { |
| 422 | found = 1; |
| 423 | break; |
| 424 | } |
| 425 | } |
| 426 | |
| 427 | if (found) { |
| 428 | dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes), |
| 429 | DBELL_TID(idb.bytes), DBELL_INF(idb.bytes)); |
| 430 | } else { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 431 | tsi_debug(DBELL, &priv->pdev->dev, |
| 432 | "spurious IDB sid %2.2x tid %2.2x info %4.4x", |
| 433 | DBELL_SID(idb.bytes), DBELL_TID(idb.bytes), |
| 434 | DBELL_INF(idb.bytes)); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 435 | } |
Alexandre Bounine | 3670e7e | 2012-08-21 16:16:11 -0700 | [diff] [blame] | 436 | |
| 437 | wr_ptr = ioread32(priv->regs + |
| 438 | TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | iowrite32(rd_ptr & (IDB_QSIZE - 1), |
| 442 | priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); |
| 443 | |
| 444 | /* Re-enable IDB interrupts */ |
| 445 | regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); |
| 446 | regval |= TSI721_SR_CHINT_IDBQRCV; |
| 447 | iowrite32(regval, |
| 448 | priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); |
Alexandre Bounine | 3670e7e | 2012-08-21 16:16:11 -0700 | [diff] [blame] | 449 | |
| 450 | wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; |
| 451 | if (wr_ptr != rd_ptr) |
| 452 | schedule_work(&priv->idb_work); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | /** |
| 456 | * tsi721_irqhandler - Tsi721 interrupt handler |
| 457 | * @irq: Linux interrupt number |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 458 | * @ptr: Pointer to interrupt-specific data (tsi721_device structure) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 459 | * |
| 460 | * Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported |
| 461 | * interrupt events and calls an event-specific handler(s). |
| 462 | */ |
| 463 | static irqreturn_t tsi721_irqhandler(int irq, void *ptr) |
| 464 | { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 465 | struct tsi721_device *priv = (struct tsi721_device *)ptr; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 466 | u32 dev_int; |
| 467 | u32 dev_ch_int; |
| 468 | u32 intval; |
| 469 | u32 ch_inte; |
| 470 | |
Alexandre Bounine | 1ccc819 | 2013-05-24 15:55:17 -0700 | [diff] [blame] | 471 | /* For MSI mode disable all device-level interrupts */ |
| 472 | if (priv->flags & TSI721_USING_MSI) |
| 473 | iowrite32(0, priv->regs + TSI721_DEV_INTE); |
| 474 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 475 | dev_int = ioread32(priv->regs + TSI721_DEV_INT); |
| 476 | if (!dev_int) |
| 477 | return IRQ_NONE; |
| 478 | |
| 479 | dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT); |
| 480 | |
| 481 | if (dev_int & TSI721_DEV_INT_SR2PC_CH) { |
| 482 | /* Service SR2PC Channel interrupts */ |
| 483 | if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) { |
| 484 | /* Service Inbound Doorbell interrupt */ |
| 485 | intval = ioread32(priv->regs + |
| 486 | TSI721_SR_CHINT(IDB_QUEUE)); |
| 487 | if (intval & TSI721_SR_CHINT_IDBQRCV) |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 488 | tsi721_dbell_handler(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 489 | else |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 490 | tsi_info(&priv->pdev->dev, |
| 491 | "Unsupported SR_CH_INT %x", intval); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 492 | |
| 493 | /* Clear interrupts */ |
| 494 | iowrite32(intval, |
| 495 | priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); |
| 496 | ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | if (dev_int & TSI721_DEV_INT_SMSG_CH) { |
| 501 | int ch; |
| 502 | |
| 503 | /* |
| 504 | * Service channel interrupts from Messaging Engine |
| 505 | */ |
| 506 | |
| 507 | if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */ |
| 508 | /* Disable signaled OB MSG Channel interrupts */ |
| 509 | ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 510 | ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M); |
| 511 | iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); |
| 512 | |
| 513 | /* |
| 514 | * Process Inbound Message interrupt for each MBOX |
| 515 | */ |
| 516 | for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) { |
| 517 | if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch))) |
| 518 | continue; |
| 519 | tsi721_imsg_handler(priv, ch); |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */ |
| 524 | /* Disable signaled OB MSG Channel interrupts */ |
| 525 | ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 526 | ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M); |
| 527 | iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); |
| 528 | |
| 529 | /* |
| 530 | * Process Outbound Message interrupts for each MBOX |
| 531 | */ |
| 532 | |
| 533 | for (ch = 0; ch < RIO_MAX_MBOX; ch++) { |
| 534 | if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch))) |
| 535 | continue; |
| 536 | tsi721_omsg_handler(priv, ch); |
| 537 | } |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | if (dev_int & TSI721_DEV_INT_SRIO) { |
| 542 | /* Service SRIO MAC interrupts */ |
| 543 | intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT); |
| 544 | if (intval & TSI721_RIO_EM_INT_STAT_PW_RX) |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 545 | tsi721_pw_handler(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 546 | } |
| 547 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 548 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
| 549 | if (dev_int & TSI721_DEV_INT_BDMA_CH) { |
| 550 | int ch; |
| 551 | |
| 552 | if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 553 | tsi_debug(DMA, &priv->pdev->dev, |
| 554 | "IRQ from DMA channel 0x%08x", dev_ch_int); |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 555 | |
| 556 | for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) { |
| 557 | if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch))) |
| 558 | continue; |
| 559 | tsi721_bdma_handler(&priv->bdma[ch]); |
| 560 | } |
| 561 | } |
| 562 | } |
| 563 | #endif |
Alexandre Bounine | 1ccc819 | 2013-05-24 15:55:17 -0700 | [diff] [blame] | 564 | |
| 565 | /* For MSI mode re-enable device-level interrupts */ |
| 566 | if (priv->flags & TSI721_USING_MSI) { |
| 567 | dev_int = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO | |
| 568 | TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH; |
| 569 | iowrite32(dev_int, priv->regs + TSI721_DEV_INTE); |
| 570 | } |
| 571 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 572 | return IRQ_HANDLED; |
| 573 | } |
| 574 | |
| 575 | static void tsi721_interrupts_init(struct tsi721_device *priv) |
| 576 | { |
| 577 | u32 intr; |
| 578 | |
| 579 | /* Enable IDB interrupts */ |
| 580 | iowrite32(TSI721_SR_CHINT_ALL, |
| 581 | priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); |
| 582 | iowrite32(TSI721_SR_CHINT_IDBQRCV, |
| 583 | priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 584 | |
| 585 | /* Enable SRIO MAC interrupts */ |
| 586 | iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT, |
| 587 | priv->regs + TSI721_RIO_EM_DEV_INT_EN); |
| 588 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 589 | /* Enable interrupts from channels in use */ |
| 590 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
| 591 | intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) | |
| 592 | (TSI721_INT_BDMA_CHAN_M & |
| 593 | ~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT)); |
| 594 | #else |
| 595 | intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE); |
| 596 | #endif |
| 597 | iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE); |
| 598 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 599 | if (priv->flags & TSI721_USING_MSIX) |
| 600 | intr = TSI721_DEV_INT_SRIO; |
| 601 | else |
| 602 | intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 603 | TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 604 | |
| 605 | iowrite32(intr, priv->regs + TSI721_DEV_INTE); |
| 606 | ioread32(priv->regs + TSI721_DEV_INTE); |
| 607 | } |
| 608 | |
| 609 | #ifdef CONFIG_PCI_MSI |
| 610 | /** |
| 611 | * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging |
| 612 | * @irq: Linux interrupt number |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 613 | * @ptr: Pointer to interrupt-specific data (tsi721_device structure) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 614 | * |
| 615 | * Handles outbound messaging interrupts signaled using MSI-X. |
| 616 | */ |
| 617 | static irqreturn_t tsi721_omsg_msix(int irq, void *ptr) |
| 618 | { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 619 | struct tsi721_device *priv = (struct tsi721_device *)ptr; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 620 | int mbox; |
| 621 | |
| 622 | mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX; |
| 623 | tsi721_omsg_handler(priv, mbox); |
| 624 | return IRQ_HANDLED; |
| 625 | } |
| 626 | |
| 627 | /** |
| 628 | * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging |
| 629 | * @irq: Linux interrupt number |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 630 | * @ptr: Pointer to interrupt-specific data (tsi721_device structure) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 631 | * |
| 632 | * Handles inbound messaging interrupts signaled using MSI-X. |
| 633 | */ |
| 634 | static irqreturn_t tsi721_imsg_msix(int irq, void *ptr) |
| 635 | { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 636 | struct tsi721_device *priv = (struct tsi721_device *)ptr; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 637 | int mbox; |
| 638 | |
| 639 | mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX; |
| 640 | tsi721_imsg_handler(priv, mbox + 4); |
| 641 | return IRQ_HANDLED; |
| 642 | } |
| 643 | |
| 644 | /** |
| 645 | * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler |
| 646 | * @irq: Linux interrupt number |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 647 | * @ptr: Pointer to interrupt-specific data (tsi721_device structure) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 648 | * |
| 649 | * Handles Tsi721 interrupts from SRIO MAC. |
| 650 | */ |
| 651 | static irqreturn_t tsi721_srio_msix(int irq, void *ptr) |
| 652 | { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 653 | struct tsi721_device *priv = (struct tsi721_device *)ptr; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 654 | u32 srio_int; |
| 655 | |
| 656 | /* Service SRIO MAC interrupts */ |
| 657 | srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT); |
| 658 | if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX) |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 659 | tsi721_pw_handler(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 660 | |
| 661 | return IRQ_HANDLED; |
| 662 | } |
| 663 | |
| 664 | /** |
| 665 | * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler |
| 666 | * @irq: Linux interrupt number |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 667 | * @ptr: Pointer to interrupt-specific data (tsi721_device structure) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 668 | * |
| 669 | * Handles Tsi721 interrupts from SR2PC Channel. |
| 670 | * NOTE: At this moment services only one SR2PC channel associated with inbound |
| 671 | * doorbells. |
| 672 | */ |
| 673 | static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr) |
| 674 | { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 675 | struct tsi721_device *priv = (struct tsi721_device *)ptr; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 676 | u32 sr_ch_int; |
| 677 | |
| 678 | /* Service Inbound DB interrupt from SR2PC channel */ |
| 679 | sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); |
| 680 | if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV) |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 681 | tsi721_dbell_handler(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 682 | |
| 683 | /* Clear interrupts */ |
| 684 | iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); |
| 685 | /* Read back to ensure that interrupt was cleared */ |
| 686 | sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); |
| 687 | |
| 688 | return IRQ_HANDLED; |
| 689 | } |
| 690 | |
| 691 | /** |
| 692 | * tsi721_request_msix - register interrupt service for MSI-X mode. |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 693 | * @priv: tsi721 device-specific data structure |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 694 | * |
| 695 | * Registers MSI-X interrupt service routines for interrupts that are active |
| 696 | * immediately after mport initialization. Messaging interrupt service routines |
| 697 | * should be registered during corresponding open requests. |
| 698 | */ |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 699 | static int tsi721_request_msix(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 700 | { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 701 | int err = 0; |
| 702 | |
| 703 | err = request_irq(priv->msix[TSI721_VECT_IDB].vector, |
| 704 | tsi721_sr2pc_ch_msix, 0, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 705 | priv->msix[TSI721_VECT_IDB].irq_name, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 706 | if (err) |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 707 | return err; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 708 | |
| 709 | err = request_irq(priv->msix[TSI721_VECT_PWRX].vector, |
| 710 | tsi721_srio_msix, 0, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 711 | priv->msix[TSI721_VECT_PWRX].irq_name, (void *)priv); |
| 712 | if (err) { |
| 713 | free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv); |
| 714 | return err; |
| 715 | } |
| 716 | |
| 717 | return 0; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 718 | } |
| 719 | |
| 720 | /** |
| 721 | * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721. |
| 722 | * @priv: pointer to tsi721 private data |
| 723 | * |
| 724 | * Configures MSI-X support for Tsi721. Supports only an exact number |
| 725 | * of requested vectors. |
| 726 | */ |
| 727 | static int tsi721_enable_msix(struct tsi721_device *priv) |
| 728 | { |
| 729 | struct msix_entry entries[TSI721_VECT_MAX]; |
| 730 | int err; |
| 731 | int i; |
| 732 | |
| 733 | entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE); |
| 734 | entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT; |
| 735 | |
| 736 | /* |
| 737 | * Initialize MSI-X entries for Messaging Engine: |
| 738 | * this driver supports four RIO mailboxes (inbound and outbound) |
| 739 | * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore |
| 740 | * offset +4 is added to IB MBOX number. |
| 741 | */ |
| 742 | for (i = 0; i < RIO_MAX_MBOX; i++) { |
| 743 | entries[TSI721_VECT_IMB0_RCV + i].entry = |
| 744 | TSI721_MSIX_IMSG_DQ_RCV(i + 4); |
| 745 | entries[TSI721_VECT_IMB0_INT + i].entry = |
| 746 | TSI721_MSIX_IMSG_INT(i + 4); |
| 747 | entries[TSI721_VECT_OMB0_DONE + i].entry = |
| 748 | TSI721_MSIX_OMSG_DONE(i); |
| 749 | entries[TSI721_VECT_OMB0_INT + i].entry = |
| 750 | TSI721_MSIX_OMSG_INT(i); |
| 751 | } |
| 752 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 753 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
| 754 | /* |
| 755 | * Initialize MSI-X entries for Block DMA Engine: |
| 756 | * this driver supports XXX DMA channels |
| 757 | * (one is reserved for SRIO maintenance transactions) |
| 758 | */ |
| 759 | for (i = 0; i < TSI721_DMA_CHNUM; i++) { |
| 760 | entries[TSI721_VECT_DMA0_DONE + i].entry = |
| 761 | TSI721_MSIX_DMACH_DONE(i); |
| 762 | entries[TSI721_VECT_DMA0_INT + i].entry = |
| 763 | TSI721_MSIX_DMACH_INT(i); |
| 764 | } |
| 765 | #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ |
| 766 | |
Alexander Gordeev | 1c92ab1 | 2014-06-06 14:37:16 -0700 | [diff] [blame] | 767 | err = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries)); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 768 | if (err) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 769 | tsi_err(&priv->pdev->dev, |
| 770 | "Failed to enable MSI-X (err=%d)", err); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 771 | return err; |
| 772 | } |
| 773 | |
| 774 | /* |
| 775 | * Copy MSI-X vector information into tsi721 private structure |
| 776 | */ |
| 777 | priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector; |
| 778 | snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX, |
| 779 | DRV_NAME "-idb@pci:%s", pci_name(priv->pdev)); |
| 780 | priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector; |
| 781 | snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX, |
| 782 | DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev)); |
| 783 | |
| 784 | for (i = 0; i < RIO_MAX_MBOX; i++) { |
| 785 | priv->msix[TSI721_VECT_IMB0_RCV + i].vector = |
| 786 | entries[TSI721_VECT_IMB0_RCV + i].vector; |
| 787 | snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name, |
| 788 | IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s", |
| 789 | i, pci_name(priv->pdev)); |
| 790 | |
| 791 | priv->msix[TSI721_VECT_IMB0_INT + i].vector = |
| 792 | entries[TSI721_VECT_IMB0_INT + i].vector; |
| 793 | snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name, |
| 794 | IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s", |
| 795 | i, pci_name(priv->pdev)); |
| 796 | |
| 797 | priv->msix[TSI721_VECT_OMB0_DONE + i].vector = |
| 798 | entries[TSI721_VECT_OMB0_DONE + i].vector; |
| 799 | snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name, |
| 800 | IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s", |
| 801 | i, pci_name(priv->pdev)); |
| 802 | |
| 803 | priv->msix[TSI721_VECT_OMB0_INT + i].vector = |
| 804 | entries[TSI721_VECT_OMB0_INT + i].vector; |
| 805 | snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name, |
| 806 | IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s", |
| 807 | i, pci_name(priv->pdev)); |
| 808 | } |
| 809 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 810 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
| 811 | for (i = 0; i < TSI721_DMA_CHNUM; i++) { |
| 812 | priv->msix[TSI721_VECT_DMA0_DONE + i].vector = |
| 813 | entries[TSI721_VECT_DMA0_DONE + i].vector; |
| 814 | snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name, |
| 815 | IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s", |
| 816 | i, pci_name(priv->pdev)); |
| 817 | |
| 818 | priv->msix[TSI721_VECT_DMA0_INT + i].vector = |
| 819 | entries[TSI721_VECT_DMA0_INT + i].vector; |
| 820 | snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name, |
| 821 | IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s", |
| 822 | i, pci_name(priv->pdev)); |
| 823 | } |
| 824 | #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ |
| 825 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 826 | return 0; |
| 827 | } |
| 828 | #endif /* CONFIG_PCI_MSI */ |
| 829 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 830 | static int tsi721_request_irq(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 831 | { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 832 | int err; |
| 833 | |
| 834 | #ifdef CONFIG_PCI_MSI |
| 835 | if (priv->flags & TSI721_USING_MSIX) |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 836 | err = tsi721_request_msix(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 837 | else |
| 838 | #endif |
| 839 | err = request_irq(priv->pdev->irq, tsi721_irqhandler, |
| 840 | (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 841 | DRV_NAME, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 842 | |
| 843 | if (err) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 844 | tsi_err(&priv->pdev->dev, |
| 845 | "Unable to allocate interrupt, err=%d", err); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 846 | |
| 847 | return err; |
| 848 | } |
| 849 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 850 | static void tsi721_free_irq(struct tsi721_device *priv) |
| 851 | { |
| 852 | #ifdef CONFIG_PCI_MSI |
| 853 | if (priv->flags & TSI721_USING_MSIX) { |
| 854 | free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv); |
| 855 | free_irq(priv->msix[TSI721_VECT_PWRX].vector, (void *)priv); |
| 856 | } else |
| 857 | #endif |
| 858 | free_irq(priv->pdev->irq, (void *)priv); |
| 859 | } |
| 860 | |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 861 | static int |
| 862 | tsi721_obw_alloc(struct tsi721_device *priv, struct tsi721_obw_bar *pbar, |
| 863 | u32 size, int *win_id) |
| 864 | { |
| 865 | u64 win_base; |
| 866 | u64 bar_base; |
| 867 | u64 bar_end; |
| 868 | u32 align; |
| 869 | struct tsi721_ob_win *win; |
| 870 | struct tsi721_ob_win *new_win = NULL; |
| 871 | int new_win_idx = -1; |
| 872 | int i = 0; |
| 873 | |
| 874 | bar_base = pbar->base; |
| 875 | bar_end = bar_base + pbar->size; |
| 876 | win_base = bar_base; |
| 877 | align = size/TSI721_PC2SR_ZONES; |
| 878 | |
| 879 | while (i < TSI721_IBWIN_NUM) { |
| 880 | for (i = 0; i < TSI721_IBWIN_NUM; i++) { |
| 881 | if (!priv->ob_win[i].active) { |
| 882 | if (new_win == NULL) { |
| 883 | new_win = &priv->ob_win[i]; |
| 884 | new_win_idx = i; |
| 885 | } |
| 886 | continue; |
| 887 | } |
| 888 | |
| 889 | /* |
| 890 | * If this window belongs to the current BAR check it |
| 891 | * for overlap |
| 892 | */ |
| 893 | win = &priv->ob_win[i]; |
| 894 | |
| 895 | if (win->base >= bar_base && win->base < bar_end) { |
| 896 | if (win_base < (win->base + win->size) && |
| 897 | (win_base + size) > win->base) { |
| 898 | /* Overlap detected */ |
| 899 | win_base = win->base + win->size; |
| 900 | win_base = ALIGN(win_base, align); |
| 901 | break; |
| 902 | } |
| 903 | } |
| 904 | } |
| 905 | } |
| 906 | |
| 907 | if (win_base + size > bar_end) |
| 908 | return -ENOMEM; |
| 909 | |
| 910 | if (!new_win) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 911 | tsi_err(&priv->pdev->dev, "OBW count tracking failed"); |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 912 | return -EIO; |
| 913 | } |
| 914 | |
| 915 | new_win->active = true; |
| 916 | new_win->base = win_base; |
| 917 | new_win->size = size; |
| 918 | new_win->pbar = pbar; |
| 919 | priv->obwin_cnt--; |
| 920 | pbar->free -= size; |
| 921 | *win_id = new_win_idx; |
| 922 | return 0; |
| 923 | } |
| 924 | |
| 925 | static int tsi721_map_outb_win(struct rio_mport *mport, u16 destid, u64 rstart, |
| 926 | u32 size, u32 flags, dma_addr_t *laddr) |
| 927 | { |
| 928 | struct tsi721_device *priv = mport->priv; |
| 929 | int i; |
| 930 | struct tsi721_obw_bar *pbar; |
| 931 | struct tsi721_ob_win *ob_win; |
| 932 | int obw = -1; |
| 933 | u32 rval; |
| 934 | u64 rio_addr; |
| 935 | u32 zsize; |
| 936 | int ret = -ENOMEM; |
| 937 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 938 | tsi_debug(OBW, &priv->pdev->dev, |
| 939 | "did=%d ra=0x%llx sz=0x%x", destid, rstart, size); |
| 940 | |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 941 | if (!is_power_of_2(size) || (size < 0x8000) || (rstart & (size - 1))) |
| 942 | return -EINVAL; |
| 943 | |
| 944 | if (priv->obwin_cnt == 0) |
| 945 | return -EBUSY; |
| 946 | |
| 947 | for (i = 0; i < 2; i++) { |
| 948 | if (priv->p2r_bar[i].free >= size) { |
| 949 | pbar = &priv->p2r_bar[i]; |
| 950 | ret = tsi721_obw_alloc(priv, pbar, size, &obw); |
| 951 | if (!ret) |
| 952 | break; |
| 953 | } |
| 954 | } |
| 955 | |
| 956 | if (ret) |
| 957 | return ret; |
| 958 | |
| 959 | WARN_ON(obw == -1); |
| 960 | ob_win = &priv->ob_win[obw]; |
| 961 | ob_win->destid = destid; |
| 962 | ob_win->rstart = rstart; |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 963 | tsi_debug(OBW, &priv->pdev->dev, |
| 964 | "allocated OBW%d @%llx", obw, ob_win->base); |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 965 | |
| 966 | /* |
| 967 | * Configure Outbound Window |
| 968 | */ |
| 969 | |
| 970 | zsize = size/TSI721_PC2SR_ZONES; |
| 971 | rio_addr = rstart; |
| 972 | |
| 973 | /* |
| 974 | * Program Address Translation Zones: |
| 975 | * This implementation uses all 8 zones associated wit window. |
| 976 | */ |
| 977 | for (i = 0; i < TSI721_PC2SR_ZONES; i++) { |
| 978 | |
| 979 | while (ioread32(priv->regs + TSI721_ZONE_SEL) & |
| 980 | TSI721_ZONE_SEL_GO) { |
| 981 | udelay(1); |
| 982 | } |
| 983 | |
| 984 | rval = (u32)(rio_addr & TSI721_LUT_DATA0_ADD) | |
| 985 | TSI721_LUT_DATA0_NREAD | TSI721_LUT_DATA0_NWR; |
| 986 | iowrite32(rval, priv->regs + TSI721_LUT_DATA0); |
| 987 | rval = (u32)(rio_addr >> 32); |
| 988 | iowrite32(rval, priv->regs + TSI721_LUT_DATA1); |
| 989 | rval = destid; |
| 990 | iowrite32(rval, priv->regs + TSI721_LUT_DATA2); |
| 991 | |
| 992 | rval = TSI721_ZONE_SEL_GO | (obw << 3) | i; |
| 993 | iowrite32(rval, priv->regs + TSI721_ZONE_SEL); |
| 994 | |
| 995 | rio_addr += zsize; |
| 996 | } |
| 997 | |
| 998 | iowrite32(TSI721_OBWIN_SIZE(size) << 8, |
| 999 | priv->regs + TSI721_OBWINSZ(obw)); |
| 1000 | iowrite32((u32)(ob_win->base >> 32), priv->regs + TSI721_OBWINUB(obw)); |
| 1001 | iowrite32((u32)(ob_win->base & TSI721_OBWINLB_BA) | TSI721_OBWINLB_WEN, |
| 1002 | priv->regs + TSI721_OBWINLB(obw)); |
| 1003 | |
| 1004 | *laddr = ob_win->base; |
| 1005 | return 0; |
| 1006 | } |
| 1007 | |
| 1008 | static void tsi721_unmap_outb_win(struct rio_mport *mport, |
| 1009 | u16 destid, u64 rstart) |
| 1010 | { |
| 1011 | struct tsi721_device *priv = mport->priv; |
| 1012 | struct tsi721_ob_win *ob_win; |
| 1013 | int i; |
| 1014 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1015 | tsi_debug(OBW, &priv->pdev->dev, "did=%d ra=0x%llx", destid, rstart); |
| 1016 | |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 1017 | for (i = 0; i < TSI721_OBWIN_NUM; i++) { |
| 1018 | ob_win = &priv->ob_win[i]; |
| 1019 | |
| 1020 | if (ob_win->active && |
| 1021 | ob_win->destid == destid && ob_win->rstart == rstart) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1022 | tsi_debug(OBW, &priv->pdev->dev, |
| 1023 | "free OBW%d @%llx", i, ob_win->base); |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 1024 | ob_win->active = false; |
| 1025 | iowrite32(0, priv->regs + TSI721_OBWINLB(i)); |
| 1026 | ob_win->pbar->free += ob_win->size; |
| 1027 | priv->obwin_cnt++; |
| 1028 | break; |
| 1029 | } |
| 1030 | } |
| 1031 | } |
| 1032 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1033 | /** |
| 1034 | * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO) |
| 1035 | * translation regions. |
| 1036 | * @priv: pointer to tsi721 private data |
| 1037 | * |
| 1038 | * Disables SREP translation regions. |
| 1039 | */ |
| 1040 | static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv) |
| 1041 | { |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 1042 | int i, z; |
| 1043 | u32 rval; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1044 | |
| 1045 | /* Disable all PC2SR translation windows */ |
| 1046 | for (i = 0; i < TSI721_OBWIN_NUM; i++) |
| 1047 | iowrite32(0, priv->regs + TSI721_OBWINLB(i)); |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 1048 | |
| 1049 | /* Initialize zone lookup tables to avoid ECC errors on reads */ |
| 1050 | iowrite32(0, priv->regs + TSI721_LUT_DATA0); |
| 1051 | iowrite32(0, priv->regs + TSI721_LUT_DATA1); |
| 1052 | iowrite32(0, priv->regs + TSI721_LUT_DATA2); |
| 1053 | |
| 1054 | for (i = 0; i < TSI721_OBWIN_NUM; i++) { |
| 1055 | for (z = 0; z < TSI721_PC2SR_ZONES; z++) { |
| 1056 | while (ioread32(priv->regs + TSI721_ZONE_SEL) & |
| 1057 | TSI721_ZONE_SEL_GO) { |
| 1058 | udelay(1); |
| 1059 | } |
| 1060 | rval = TSI721_ZONE_SEL_GO | (i << 3) | z; |
| 1061 | iowrite32(rval, priv->regs + TSI721_ZONE_SEL); |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | if (priv->p2r_bar[0].size == 0 && priv->p2r_bar[1].size == 0) { |
| 1066 | priv->obwin_cnt = 0; |
| 1067 | return; |
| 1068 | } |
| 1069 | |
| 1070 | priv->p2r_bar[0].free = priv->p2r_bar[0].size; |
| 1071 | priv->p2r_bar[1].free = priv->p2r_bar[1].size; |
| 1072 | |
| 1073 | for (i = 0; i < TSI721_OBWIN_NUM; i++) |
| 1074 | priv->ob_win[i].active = false; |
| 1075 | |
| 1076 | priv->obwin_cnt = TSI721_OBWIN_NUM; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1077 | } |
| 1078 | |
| 1079 | /** |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1080 | * tsi721_rio_map_inb_mem -- Mapping inbound memory region. |
| 1081 | * @mport: RapidIO master port |
| 1082 | * @lstart: Local memory space start address. |
| 1083 | * @rstart: RapidIO space start address. |
| 1084 | * @size: The mapping region size. |
| 1085 | * @flags: Flags for mapping. 0 for using default flags. |
| 1086 | * |
| 1087 | * Return: 0 -- Success. |
| 1088 | * |
| 1089 | * This function will create the inbound mapping |
| 1090 | * from rstart to lstart. |
| 1091 | */ |
| 1092 | static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart, |
| 1093 | u64 rstart, u32 size, u32 flags) |
| 1094 | { |
| 1095 | struct tsi721_device *priv = mport->priv; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1096 | int i, avail = -1; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1097 | u32 regval; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1098 | struct tsi721_ib_win *ib_win; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1099 | bool direct = (lstart == rstart); |
| 1100 | u64 ibw_size; |
| 1101 | dma_addr_t loc_start; |
| 1102 | u64 ibw_start; |
| 1103 | struct tsi721_ib_win_mapping *map = NULL; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1104 | int ret = -EBUSY; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1105 | |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1106 | if (direct) { |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1107 | /* Calculate minimal acceptable window size and base address */ |
| 1108 | |
| 1109 | ibw_size = roundup_pow_of_two(size); |
| 1110 | ibw_start = lstart & ~(ibw_size - 1); |
| 1111 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1112 | tsi_debug(IBW, &priv->pdev->dev, |
Joe Perches | ea87b8e | 2016-08-02 14:06:28 -0700 | [diff] [blame] | 1113 | "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%x, ibw_start = 0x%llx", |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1114 | rstart, &lstart, size, ibw_start); |
| 1115 | |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1116 | while ((lstart + size) > (ibw_start + ibw_size)) { |
| 1117 | ibw_size *= 2; |
| 1118 | ibw_start = lstart & ~(ibw_size - 1); |
| 1119 | if (ibw_size > 0x80000000) { /* Limit max size to 2GB */ |
| 1120 | return -EBUSY; |
| 1121 | } |
| 1122 | } |
| 1123 | |
| 1124 | loc_start = ibw_start; |
| 1125 | |
| 1126 | map = kzalloc(sizeof(struct tsi721_ib_win_mapping), GFP_ATOMIC); |
| 1127 | if (map == NULL) |
| 1128 | return -ENOMEM; |
| 1129 | |
| 1130 | } else { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1131 | tsi_debug(IBW, &priv->pdev->dev, |
Joe Perches | ea87b8e | 2016-08-02 14:06:28 -0700 | [diff] [blame] | 1132 | "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%x", |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1133 | rstart, &lstart, size); |
| 1134 | |
| 1135 | if (!is_power_of_2(size) || size < 0x1000 || |
| 1136 | ((u64)lstart & (size - 1)) || (rstart & (size - 1))) |
| 1137 | return -EINVAL; |
| 1138 | if (priv->ibwin_cnt == 0) |
| 1139 | return -EBUSY; |
| 1140 | ibw_start = rstart; |
| 1141 | ibw_size = size; |
| 1142 | loc_start = lstart; |
| 1143 | } |
| 1144 | |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1145 | /* |
| 1146 | * Scan for overlapping with active regions and mark the first available |
| 1147 | * IB window at the same time. |
| 1148 | */ |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1149 | for (i = 0; i < TSI721_IBWIN_NUM; i++) { |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1150 | ib_win = &priv->ib_win[i]; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1151 | |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1152 | if (!ib_win->active) { |
| 1153 | if (avail == -1) { |
| 1154 | avail = i; |
| 1155 | ret = 0; |
| 1156 | } |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1157 | } else if (ibw_start < (ib_win->rstart + ib_win->size) && |
| 1158 | (ibw_start + ibw_size) > ib_win->rstart) { |
| 1159 | /* Return error if address translation involved */ |
| 1160 | if (direct && ib_win->xlat) { |
| 1161 | ret = -EFAULT; |
| 1162 | break; |
| 1163 | } |
| 1164 | |
| 1165 | /* |
| 1166 | * Direct mappings usually are larger than originally |
| 1167 | * requested fragments - check if this new request fits |
| 1168 | * into it. |
| 1169 | */ |
| 1170 | if (rstart >= ib_win->rstart && |
| 1171 | (rstart + size) <= (ib_win->rstart + |
| 1172 | ib_win->size)) { |
| 1173 | /* We are in - no further mapping required */ |
| 1174 | map->lstart = lstart; |
| 1175 | list_add_tail(&map->node, &ib_win->mappings); |
| 1176 | return 0; |
| 1177 | } |
| 1178 | |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1179 | ret = -EFAULT; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1180 | break; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1181 | } |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1182 | } |
| 1183 | |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1184 | if (ret) |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1185 | goto out; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1186 | i = avail; |
| 1187 | |
| 1188 | /* Sanity check: available IB window must be disabled at this point */ |
| 1189 | regval = ioread32(priv->regs + TSI721_IBWIN_LB(i)); |
| 1190 | if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) { |
| 1191 | ret = -EIO; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1192 | goto out; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1193 | } |
| 1194 | |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1195 | ib_win = &priv->ib_win[i]; |
| 1196 | ib_win->active = true; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1197 | ib_win->rstart = ibw_start; |
| 1198 | ib_win->lstart = loc_start; |
| 1199 | ib_win->size = ibw_size; |
| 1200 | ib_win->xlat = (lstart != rstart); |
| 1201 | INIT_LIST_HEAD(&ib_win->mappings); |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1202 | |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1203 | /* |
| 1204 | * When using direct IBW mapping and have larger than requested IBW size |
| 1205 | * we can have multiple local memory blocks mapped through the same IBW |
| 1206 | * To handle this situation we maintain list of "clients" for such IBWs. |
| 1207 | */ |
| 1208 | if (direct) { |
| 1209 | map->lstart = lstart; |
| 1210 | list_add_tail(&map->node, &ib_win->mappings); |
| 1211 | } |
| 1212 | |
| 1213 | iowrite32(TSI721_IBWIN_SIZE(ibw_size) << 8, |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1214 | priv->regs + TSI721_IBWIN_SZ(i)); |
| 1215 | |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1216 | iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i)); |
| 1217 | iowrite32(((u64)loc_start & TSI721_IBWIN_TLA_ADD), |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1218 | priv->regs + TSI721_IBWIN_TLA(i)); |
| 1219 | |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1220 | iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i)); |
| 1221 | iowrite32((ibw_start & TSI721_IBWIN_LB_BA) | TSI721_IBWIN_LB_WEN, |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1222 | priv->regs + TSI721_IBWIN_LB(i)); |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1223 | |
| 1224 | priv->ibwin_cnt--; |
| 1225 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1226 | tsi_debug(IBW, &priv->pdev->dev, |
Joe Perches | ea87b8e | 2016-08-02 14:06:28 -0700 | [diff] [blame] | 1227 | "Configured IBWIN%d (RIO_0x%llx -> PCIe_%pad), size=0x%llx", |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1228 | i, ibw_start, &loc_start, ibw_size); |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1229 | |
| 1230 | return 0; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1231 | out: |
| 1232 | kfree(map); |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1233 | return ret; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1234 | } |
| 1235 | |
| 1236 | /** |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1237 | * tsi721_rio_unmap_inb_mem -- Unmapping inbound memory region. |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1238 | * @mport: RapidIO master port |
| 1239 | * @lstart: Local memory space start address. |
| 1240 | */ |
| 1241 | static void tsi721_rio_unmap_inb_mem(struct rio_mport *mport, |
| 1242 | dma_addr_t lstart) |
| 1243 | { |
| 1244 | struct tsi721_device *priv = mport->priv; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1245 | struct tsi721_ib_win *ib_win; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1246 | int i; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1247 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1248 | tsi_debug(IBW, &priv->pdev->dev, |
Joe Perches | ea87b8e | 2016-08-02 14:06:28 -0700 | [diff] [blame] | 1249 | "Unmap IBW mapped to PCIe_%pad", &lstart); |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1250 | |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1251 | /* Search for matching active inbound translation window */ |
| 1252 | for (i = 0; i < TSI721_IBWIN_NUM; i++) { |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1253 | ib_win = &priv->ib_win[i]; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1254 | |
| 1255 | /* Address translating IBWs must to be an exact march */ |
| 1256 | if (!ib_win->active || |
| 1257 | (ib_win->xlat && lstart != ib_win->lstart)) |
| 1258 | continue; |
| 1259 | |
| 1260 | if (lstart >= ib_win->lstart && |
| 1261 | lstart < (ib_win->lstart + ib_win->size)) { |
| 1262 | |
| 1263 | if (!ib_win->xlat) { |
| 1264 | struct tsi721_ib_win_mapping *map; |
| 1265 | int found = 0; |
| 1266 | |
| 1267 | list_for_each_entry(map, |
| 1268 | &ib_win->mappings, node) { |
| 1269 | if (map->lstart == lstart) { |
| 1270 | list_del(&map->node); |
| 1271 | kfree(map); |
| 1272 | found = 1; |
| 1273 | break; |
| 1274 | } |
| 1275 | } |
| 1276 | |
| 1277 | if (!found) |
| 1278 | continue; |
| 1279 | |
| 1280 | if (!list_empty(&ib_win->mappings)) |
| 1281 | break; |
| 1282 | } |
| 1283 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1284 | tsi_debug(IBW, &priv->pdev->dev, "Disable IBWIN_%d", i); |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1285 | iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); |
| 1286 | ib_win->active = false; |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1287 | priv->ibwin_cnt++; |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1288 | break; |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1289 | } |
| 1290 | } |
Alexandre Bounine | ba5d141 | 2016-03-22 14:25:51 -0700 | [diff] [blame] | 1291 | |
| 1292 | if (i == TSI721_IBWIN_NUM) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1293 | tsi_debug(IBW, &priv->pdev->dev, |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1294 | "IB window mapped to %pad not found", &lstart); |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1295 | } |
| 1296 | |
| 1297 | /** |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1298 | * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe) |
| 1299 | * translation regions. |
| 1300 | * @priv: pointer to tsi721 private data |
| 1301 | * |
| 1302 | * Disables inbound windows. |
| 1303 | */ |
| 1304 | static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv) |
| 1305 | { |
| 1306 | int i; |
| 1307 | |
| 1308 | /* Disable all SR2PC inbound windows */ |
| 1309 | for (i = 0; i < TSI721_IBWIN_NUM; i++) |
Alexandre Bounine | 71afe34 | 2012-10-04 17:16:00 -0700 | [diff] [blame] | 1310 | iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); |
Alexandre Bounine | 9673b88 | 2016-03-22 14:25:54 -0700 | [diff] [blame] | 1311 | priv->ibwin_cnt = TSI721_IBWIN_NUM; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1312 | } |
| 1313 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1314 | /* |
| 1315 | * tsi721_close_sr2pc_mapping - closes all active inbound (SRIO->PCIe) |
| 1316 | * translation regions. |
| 1317 | * @priv: pointer to tsi721 device private data |
| 1318 | */ |
| 1319 | static void tsi721_close_sr2pc_mapping(struct tsi721_device *priv) |
| 1320 | { |
| 1321 | struct tsi721_ib_win *ib_win; |
| 1322 | int i; |
| 1323 | |
| 1324 | /* Disable all active SR2PC inbound windows */ |
| 1325 | for (i = 0; i < TSI721_IBWIN_NUM; i++) { |
| 1326 | ib_win = &priv->ib_win[i]; |
| 1327 | if (ib_win->active) { |
| 1328 | iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); |
| 1329 | ib_win->active = false; |
| 1330 | } |
| 1331 | } |
| 1332 | } |
| 1333 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1334 | /** |
| 1335 | * tsi721_port_write_init - Inbound port write interface init |
| 1336 | * @priv: pointer to tsi721 private data |
| 1337 | * |
| 1338 | * Initializes inbound port write handler. |
| 1339 | * Returns %0 on success or %-ENOMEM on failure. |
| 1340 | */ |
| 1341 | static int tsi721_port_write_init(struct tsi721_device *priv) |
| 1342 | { |
| 1343 | priv->pw_discard_count = 0; |
| 1344 | INIT_WORK(&priv->pw_work, tsi721_pw_dpc); |
| 1345 | spin_lock_init(&priv->pw_fifo_lock); |
| 1346 | if (kfifo_alloc(&priv->pw_fifo, |
| 1347 | TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1348 | tsi_err(&priv->pdev->dev, "PW FIFO allocation failed"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1349 | return -ENOMEM; |
| 1350 | } |
| 1351 | |
| 1352 | /* Use reliable port-write capture mode */ |
| 1353 | iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL); |
| 1354 | return 0; |
| 1355 | } |
| 1356 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1357 | static void tsi721_port_write_free(struct tsi721_device *priv) |
| 1358 | { |
| 1359 | kfifo_free(&priv->pw_fifo); |
| 1360 | } |
| 1361 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1362 | static int tsi721_doorbell_init(struct tsi721_device *priv) |
| 1363 | { |
| 1364 | /* Outbound Doorbells do not require any setup. |
| 1365 | * Tsi721 uses dedicated PCI BAR1 to generate doorbells. |
| 1366 | * That BAR1 was mapped during the probe routine. |
| 1367 | */ |
| 1368 | |
| 1369 | /* Initialize Inbound Doorbell processing DPC and queue */ |
| 1370 | priv->db_discard_count = 0; |
| 1371 | INIT_WORK(&priv->idb_work, tsi721_db_dpc); |
| 1372 | |
| 1373 | /* Allocate buffer for inbound doorbells queue */ |
Alexandre Bounine | ceb9639 | 2011-12-08 14:34:35 -0800 | [diff] [blame] | 1374 | priv->idb_base = dma_zalloc_coherent(&priv->pdev->dev, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1375 | IDB_QSIZE * TSI721_IDB_ENTRY_SIZE, |
| 1376 | &priv->idb_dma, GFP_KERNEL); |
| 1377 | if (!priv->idb_base) |
| 1378 | return -ENOMEM; |
| 1379 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1380 | tsi_debug(DBELL, &priv->pdev->dev, |
| 1381 | "Allocated IDB buffer @ %p (phys = %pad)", |
| 1382 | priv->idb_base, &priv->idb_dma); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1383 | |
| 1384 | iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE), |
| 1385 | priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE)); |
| 1386 | iowrite32(((u64)priv->idb_dma >> 32), |
| 1387 | priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE)); |
| 1388 | iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR), |
| 1389 | priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE)); |
| 1390 | /* Enable accepting all inbound doorbells */ |
| 1391 | iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE)); |
| 1392 | |
| 1393 | iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE)); |
| 1394 | |
| 1395 | iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); |
| 1396 | |
| 1397 | return 0; |
| 1398 | } |
| 1399 | |
| 1400 | static void tsi721_doorbell_free(struct tsi721_device *priv) |
| 1401 | { |
| 1402 | if (priv->idb_base == NULL) |
| 1403 | return; |
| 1404 | |
| 1405 | /* Free buffer allocated for inbound doorbell queue */ |
| 1406 | dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE, |
| 1407 | priv->idb_base, priv->idb_dma); |
| 1408 | priv->idb_base = NULL; |
| 1409 | } |
| 1410 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1411 | /** |
| 1412 | * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel. |
| 1413 | * @priv: pointer to tsi721 private data |
| 1414 | * |
| 1415 | * Initialize BDMA channel allocated for RapidIO maintenance read/write |
| 1416 | * request generation |
| 1417 | * Returns %0 on success or %-ENOMEM on failure. |
| 1418 | */ |
| 1419 | static int tsi721_bdma_maint_init(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1420 | { |
| 1421 | struct tsi721_dma_desc *bd_ptr; |
| 1422 | u64 *sts_ptr; |
| 1423 | dma_addr_t bd_phys, sts_phys; |
| 1424 | int sts_size; |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1425 | int bd_num = 2; |
| 1426 | void __iomem *regs; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1427 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1428 | tsi_debug(MAINT, &priv->pdev->dev, |
| 1429 | "Init BDMA_%d Maintenance requests", TSI721_DMACH_MAINT); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1430 | |
| 1431 | /* |
| 1432 | * Initialize DMA channel for maintenance requests |
| 1433 | */ |
| 1434 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1435 | priv->mdma.ch_id = TSI721_DMACH_MAINT; |
| 1436 | regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT); |
| 1437 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1438 | /* Allocate space for DMA descriptors */ |
Alexandre Bounine | ceb9639 | 2011-12-08 14:34:35 -0800 | [diff] [blame] | 1439 | bd_ptr = dma_zalloc_coherent(&priv->pdev->dev, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1440 | bd_num * sizeof(struct tsi721_dma_desc), |
| 1441 | &bd_phys, GFP_KERNEL); |
| 1442 | if (!bd_ptr) |
| 1443 | return -ENOMEM; |
| 1444 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1445 | priv->mdma.bd_num = bd_num; |
| 1446 | priv->mdma.bd_phys = bd_phys; |
| 1447 | priv->mdma.bd_base = bd_ptr; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1448 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1449 | tsi_debug(MAINT, &priv->pdev->dev, "DMA descriptors @ %p (phys = %pad)", |
| 1450 | bd_ptr, &bd_phys); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1451 | |
| 1452 | /* Allocate space for descriptor status FIFO */ |
| 1453 | sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ? |
| 1454 | bd_num : TSI721_DMA_MINSTSSZ; |
| 1455 | sts_size = roundup_pow_of_two(sts_size); |
Alexandre Bounine | ceb9639 | 2011-12-08 14:34:35 -0800 | [diff] [blame] | 1456 | sts_ptr = dma_zalloc_coherent(&priv->pdev->dev, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1457 | sts_size * sizeof(struct tsi721_dma_sts), |
| 1458 | &sts_phys, GFP_KERNEL); |
| 1459 | if (!sts_ptr) { |
| 1460 | /* Free space allocated for DMA descriptors */ |
| 1461 | dma_free_coherent(&priv->pdev->dev, |
| 1462 | bd_num * sizeof(struct tsi721_dma_desc), |
| 1463 | bd_ptr, bd_phys); |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1464 | priv->mdma.bd_base = NULL; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1465 | return -ENOMEM; |
| 1466 | } |
| 1467 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1468 | priv->mdma.sts_phys = sts_phys; |
| 1469 | priv->mdma.sts_base = sts_ptr; |
| 1470 | priv->mdma.sts_size = sts_size; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1471 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1472 | tsi_debug(MAINT, &priv->pdev->dev, |
| 1473 | "desc status FIFO @ %p (phys = %pad) size=0x%x", |
| 1474 | sts_ptr, &sts_phys, sts_size); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1475 | |
| 1476 | /* Initialize DMA descriptors ring */ |
| 1477 | bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29); |
| 1478 | bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys & |
| 1479 | TSI721_DMAC_DPTRL_MASK); |
| 1480 | bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32); |
| 1481 | |
| 1482 | /* Setup DMA descriptor pointers */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1483 | iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1484 | iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK), |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1485 | regs + TSI721_DMAC_DPTRL); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1486 | |
| 1487 | /* Setup descriptor status FIFO */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1488 | iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1489 | iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK), |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1490 | regs + TSI721_DMAC_DSBL); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1491 | iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size), |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1492 | regs + TSI721_DMAC_DSSZ); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1493 | |
| 1494 | /* Clear interrupt bits */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1495 | iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1496 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1497 | ioread32(regs + TSI721_DMAC_INT); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1498 | |
| 1499 | /* Toggle DMA channel initialization */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1500 | iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); |
| 1501 | ioread32(regs + TSI721_DMAC_CTL); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1502 | udelay(10); |
| 1503 | |
| 1504 | return 0; |
| 1505 | } |
| 1506 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1507 | static int tsi721_bdma_maint_free(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1508 | { |
| 1509 | u32 ch_stat; |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1510 | struct tsi721_bdma_maint *mdma = &priv->mdma; |
| 1511 | void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1512 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1513 | if (mdma->bd_base == NULL) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1514 | return 0; |
| 1515 | |
| 1516 | /* Check if DMA channel still running */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1517 | ch_stat = ioread32(regs + TSI721_DMAC_STS); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1518 | if (ch_stat & TSI721_DMAC_STS_RUN) |
| 1519 | return -EFAULT; |
| 1520 | |
| 1521 | /* Put DMA channel into init state */ |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1522 | iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1523 | |
| 1524 | /* Free space allocated for DMA descriptors */ |
| 1525 | dma_free_coherent(&priv->pdev->dev, |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1526 | mdma->bd_num * sizeof(struct tsi721_dma_desc), |
| 1527 | mdma->bd_base, mdma->bd_phys); |
| 1528 | mdma->bd_base = NULL; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1529 | |
| 1530 | /* Free space allocated for status FIFO */ |
| 1531 | dma_free_coherent(&priv->pdev->dev, |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 1532 | mdma->sts_size * sizeof(struct tsi721_dma_sts), |
| 1533 | mdma->sts_base, mdma->sts_phys); |
| 1534 | mdma->sts_base = NULL; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1535 | return 0; |
| 1536 | } |
| 1537 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1538 | /* Enable Inbound Messaging Interrupts */ |
| 1539 | static void |
| 1540 | tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch, |
| 1541 | u32 inte_mask) |
| 1542 | { |
| 1543 | u32 rval; |
| 1544 | |
| 1545 | if (!inte_mask) |
| 1546 | return; |
| 1547 | |
| 1548 | /* Clear pending Inbound Messaging interrupts */ |
| 1549 | iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch)); |
| 1550 | |
| 1551 | /* Enable Inbound Messaging interrupts */ |
| 1552 | rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch)); |
| 1553 | iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch)); |
| 1554 | |
| 1555 | if (priv->flags & TSI721_USING_MSIX) |
| 1556 | return; /* Finished if we are in MSI-X mode */ |
| 1557 | |
| 1558 | /* |
| 1559 | * For MSI and INTA interrupt signalling we need to enable next levels |
| 1560 | */ |
| 1561 | |
| 1562 | /* Enable Device Channel Interrupt */ |
| 1563 | rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 1564 | iowrite32(rval | TSI721_INT_IMSG_CHAN(ch), |
| 1565 | priv->regs + TSI721_DEV_CHAN_INTE); |
| 1566 | } |
| 1567 | |
| 1568 | /* Disable Inbound Messaging Interrupts */ |
| 1569 | static void |
| 1570 | tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch, |
| 1571 | u32 inte_mask) |
| 1572 | { |
| 1573 | u32 rval; |
| 1574 | |
| 1575 | if (!inte_mask) |
| 1576 | return; |
| 1577 | |
| 1578 | /* Clear pending Inbound Messaging interrupts */ |
| 1579 | iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch)); |
| 1580 | |
| 1581 | /* Disable Inbound Messaging interrupts */ |
| 1582 | rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch)); |
| 1583 | rval &= ~inte_mask; |
| 1584 | iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch)); |
| 1585 | |
| 1586 | if (priv->flags & TSI721_USING_MSIX) |
| 1587 | return; /* Finished if we are in MSI-X mode */ |
| 1588 | |
| 1589 | /* |
| 1590 | * For MSI and INTA interrupt signalling we need to disable next levels |
| 1591 | */ |
| 1592 | |
| 1593 | /* Disable Device Channel Interrupt */ |
| 1594 | rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 1595 | rval &= ~TSI721_INT_IMSG_CHAN(ch); |
| 1596 | iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE); |
| 1597 | } |
| 1598 | |
| 1599 | /* Enable Outbound Messaging interrupts */ |
| 1600 | static void |
| 1601 | tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch, |
| 1602 | u32 inte_mask) |
| 1603 | { |
| 1604 | u32 rval; |
| 1605 | |
| 1606 | if (!inte_mask) |
| 1607 | return; |
| 1608 | |
| 1609 | /* Clear pending Outbound Messaging interrupts */ |
| 1610 | iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch)); |
| 1611 | |
| 1612 | /* Enable Outbound Messaging channel interrupts */ |
| 1613 | rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch)); |
| 1614 | iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch)); |
| 1615 | |
| 1616 | if (priv->flags & TSI721_USING_MSIX) |
| 1617 | return; /* Finished if we are in MSI-X mode */ |
| 1618 | |
| 1619 | /* |
| 1620 | * For MSI and INTA interrupt signalling we need to enable next levels |
| 1621 | */ |
| 1622 | |
| 1623 | /* Enable Device Channel Interrupt */ |
| 1624 | rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 1625 | iowrite32(rval | TSI721_INT_OMSG_CHAN(ch), |
| 1626 | priv->regs + TSI721_DEV_CHAN_INTE); |
| 1627 | } |
| 1628 | |
| 1629 | /* Disable Outbound Messaging interrupts */ |
| 1630 | static void |
| 1631 | tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch, |
| 1632 | u32 inte_mask) |
| 1633 | { |
| 1634 | u32 rval; |
| 1635 | |
| 1636 | if (!inte_mask) |
| 1637 | return; |
| 1638 | |
| 1639 | /* Clear pending Outbound Messaging interrupts */ |
| 1640 | iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch)); |
| 1641 | |
| 1642 | /* Disable Outbound Messaging interrupts */ |
| 1643 | rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch)); |
| 1644 | rval &= ~inte_mask; |
| 1645 | iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch)); |
| 1646 | |
| 1647 | if (priv->flags & TSI721_USING_MSIX) |
| 1648 | return; /* Finished if we are in MSI-X mode */ |
| 1649 | |
| 1650 | /* |
| 1651 | * For MSI and INTA interrupt signalling we need to disable next levels |
| 1652 | */ |
| 1653 | |
| 1654 | /* Disable Device Channel Interrupt */ |
| 1655 | rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 1656 | rval &= ~TSI721_INT_OMSG_CHAN(ch); |
| 1657 | iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE); |
| 1658 | } |
| 1659 | |
| 1660 | /** |
| 1661 | * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue |
| 1662 | * @mport: Master port with outbound message queue |
| 1663 | * @rdev: Target of outbound message |
| 1664 | * @mbox: Outbound mailbox |
| 1665 | * @buffer: Message to add to outbound queue |
| 1666 | * @len: Length of message |
| 1667 | */ |
| 1668 | static int |
| 1669 | tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, |
| 1670 | void *buffer, size_t len) |
| 1671 | { |
| 1672 | struct tsi721_device *priv = mport->priv; |
| 1673 | struct tsi721_omsg_desc *desc; |
| 1674 | u32 tx_slot; |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1675 | unsigned long flags; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1676 | |
| 1677 | if (!priv->omsg_init[mbox] || |
| 1678 | len > TSI721_MSG_MAX_SIZE || len < 8) |
| 1679 | return -EINVAL; |
| 1680 | |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1681 | spin_lock_irqsave(&priv->omsg_ring[mbox].lock, flags); |
| 1682 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1683 | tx_slot = priv->omsg_ring[mbox].tx_slot; |
| 1684 | |
| 1685 | /* Copy copy message into transfer buffer */ |
| 1686 | memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len); |
| 1687 | |
| 1688 | if (len & 0x7) |
| 1689 | len += 8; |
| 1690 | |
| 1691 | /* Build descriptor associated with buffer */ |
| 1692 | desc = priv->omsg_ring[mbox].omd_base; |
| 1693 | desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid); |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1694 | #ifdef TSI721_OMSG_DESC_INT |
| 1695 | /* Request IOF_DONE interrupt generation for each N-th frame in queue */ |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1696 | if (tx_slot % 4 == 0) |
| 1697 | desc[tx_slot].type_id |= cpu_to_le32(TSI721_OMD_IOF); |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1698 | #endif |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1699 | desc[tx_slot].msg_info = |
| 1700 | cpu_to_le32((mport->sys_size << 26) | (mbox << 22) | |
| 1701 | (0xe << 12) | (len & 0xff8)); |
| 1702 | desc[tx_slot].bufptr_lo = |
| 1703 | cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] & |
| 1704 | 0xffffffff); |
| 1705 | desc[tx_slot].bufptr_hi = |
| 1706 | cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32); |
| 1707 | |
| 1708 | priv->omsg_ring[mbox].wr_count++; |
| 1709 | |
| 1710 | /* Go to next descriptor */ |
| 1711 | if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) { |
| 1712 | priv->omsg_ring[mbox].tx_slot = 0; |
| 1713 | /* Move through the ring link descriptor at the end */ |
| 1714 | priv->omsg_ring[mbox].wr_count++; |
| 1715 | } |
| 1716 | |
| 1717 | mb(); |
| 1718 | |
| 1719 | /* Set new write count value */ |
| 1720 | iowrite32(priv->omsg_ring[mbox].wr_count, |
| 1721 | priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); |
| 1722 | ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); |
| 1723 | |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1724 | spin_unlock_irqrestore(&priv->omsg_ring[mbox].lock, flags); |
| 1725 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1726 | return 0; |
| 1727 | } |
| 1728 | |
| 1729 | /** |
| 1730 | * tsi721_omsg_handler - Outbound Message Interrupt Handler |
| 1731 | * @priv: pointer to tsi721 private data |
| 1732 | * @ch: number of OB MSG channel to service |
| 1733 | * |
| 1734 | * Services channel interrupts from outbound messaging engine. |
| 1735 | */ |
| 1736 | static void tsi721_omsg_handler(struct tsi721_device *priv, int ch) |
| 1737 | { |
| 1738 | u32 omsg_int; |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1739 | struct rio_mport *mport = &priv->mport; |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1740 | void *dev_id = NULL; |
| 1741 | u32 tx_slot = 0xffffffff; |
| 1742 | int do_callback = 0; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1743 | |
| 1744 | spin_lock(&priv->omsg_ring[ch].lock); |
| 1745 | |
| 1746 | omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch)); |
| 1747 | |
| 1748 | if (omsg_int & TSI721_OBDMAC_INT_ST_FULL) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1749 | tsi_info(&priv->pdev->dev, |
| 1750 | "OB MBOX%d: Status FIFO is full", ch); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1751 | |
| 1752 | if (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) { |
| 1753 | u32 srd_ptr; |
| 1754 | u64 *sts_ptr, last_ptr = 0, prev_ptr = 0; |
| 1755 | int i, j; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1756 | |
| 1757 | /* |
| 1758 | * Find last successfully processed descriptor |
| 1759 | */ |
| 1760 | |
| 1761 | /* Check and clear descriptor status FIFO entries */ |
| 1762 | srd_ptr = priv->omsg_ring[ch].sts_rdptr; |
| 1763 | sts_ptr = priv->omsg_ring[ch].sts_base; |
| 1764 | j = srd_ptr * 8; |
| 1765 | while (sts_ptr[j]) { |
| 1766 | for (i = 0; i < 8 && sts_ptr[j]; i++, j++) { |
| 1767 | prev_ptr = last_ptr; |
| 1768 | last_ptr = le64_to_cpu(sts_ptr[j]); |
| 1769 | sts_ptr[j] = 0; |
| 1770 | } |
| 1771 | |
| 1772 | ++srd_ptr; |
| 1773 | srd_ptr %= priv->omsg_ring[ch].sts_size; |
| 1774 | j = srd_ptr * 8; |
| 1775 | } |
| 1776 | |
| 1777 | if (last_ptr == 0) |
| 1778 | goto no_sts_update; |
| 1779 | |
| 1780 | priv->omsg_ring[ch].sts_rdptr = srd_ptr; |
| 1781 | iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch)); |
| 1782 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1783 | if (!mport->outb_msg[ch].mcback) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1784 | goto no_sts_update; |
| 1785 | |
| 1786 | /* Inform upper layer about transfer completion */ |
| 1787 | |
| 1788 | tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/ |
| 1789 | sizeof(struct tsi721_omsg_desc); |
| 1790 | |
| 1791 | /* |
| 1792 | * Check if this is a Link Descriptor (LD). |
| 1793 | * If yes, ignore LD and use descriptor processed |
| 1794 | * before LD. |
| 1795 | */ |
| 1796 | if (tx_slot == priv->omsg_ring[ch].size) { |
| 1797 | if (prev_ptr) |
| 1798 | tx_slot = (prev_ptr - |
| 1799 | (u64)priv->omsg_ring[ch].omd_phys)/ |
| 1800 | sizeof(struct tsi721_omsg_desc); |
| 1801 | else |
| 1802 | goto no_sts_update; |
| 1803 | } |
| 1804 | |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1805 | if (tx_slot >= priv->omsg_ring[ch].size) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1806 | tsi_debug(OMSG, &priv->pdev->dev, |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1807 | "OB_MSG tx_slot=%x > size=%x", |
| 1808 | tx_slot, priv->omsg_ring[ch].size); |
| 1809 | WARN_ON(tx_slot >= priv->omsg_ring[ch].size); |
| 1810 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1811 | /* Move slot index to the next message to be sent */ |
| 1812 | ++tx_slot; |
| 1813 | if (tx_slot == priv->omsg_ring[ch].size) |
| 1814 | tx_slot = 0; |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1815 | |
| 1816 | dev_id = priv->omsg_ring[ch].dev_id; |
| 1817 | do_callback = 1; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1818 | } |
| 1819 | |
| 1820 | no_sts_update: |
| 1821 | |
| 1822 | if (omsg_int & TSI721_OBDMAC_INT_ERROR) { |
| 1823 | /* |
| 1824 | * Outbound message operation aborted due to error, |
| 1825 | * reinitialize OB MSG channel |
| 1826 | */ |
| 1827 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1828 | tsi_debug(OMSG, &priv->pdev->dev, "OB MSG ABORT ch_stat=%x", |
| 1829 | ioread32(priv->regs + TSI721_OBDMAC_STS(ch))); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1830 | |
| 1831 | iowrite32(TSI721_OBDMAC_INT_ERROR, |
| 1832 | priv->regs + TSI721_OBDMAC_INT(ch)); |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1833 | iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1834 | priv->regs + TSI721_OBDMAC_CTL(ch)); |
| 1835 | ioread32(priv->regs + TSI721_OBDMAC_CTL(ch)); |
| 1836 | |
| 1837 | /* Inform upper level to clear all pending tx slots */ |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1838 | dev_id = priv->omsg_ring[ch].dev_id; |
| 1839 | tx_slot = priv->omsg_ring[ch].tx_slot; |
| 1840 | do_callback = 1; |
| 1841 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1842 | /* Synch tx_slot tracking */ |
| 1843 | iowrite32(priv->omsg_ring[ch].tx_slot, |
| 1844 | priv->regs + TSI721_OBDMAC_DRDCNT(ch)); |
| 1845 | ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch)); |
| 1846 | priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot; |
| 1847 | priv->omsg_ring[ch].sts_rdptr = 0; |
| 1848 | } |
| 1849 | |
| 1850 | /* Clear channel interrupts */ |
| 1851 | iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch)); |
| 1852 | |
| 1853 | if (!(priv->flags & TSI721_USING_MSIX)) { |
| 1854 | u32 ch_inte; |
| 1855 | |
| 1856 | /* Re-enable channel interrupts */ |
| 1857 | ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 1858 | ch_inte |= TSI721_INT_OMSG_CHAN(ch); |
| 1859 | iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); |
| 1860 | } |
| 1861 | |
| 1862 | spin_unlock(&priv->omsg_ring[ch].lock); |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 1863 | |
| 1864 | if (mport->outb_msg[ch].mcback && do_callback) |
| 1865 | mport->outb_msg[ch].mcback(mport, dev_id, ch, tx_slot); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1866 | } |
| 1867 | |
| 1868 | /** |
| 1869 | * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox |
| 1870 | * @mport: Master port implementing Outbound Messaging Engine |
| 1871 | * @dev_id: Device specific pointer to pass on event |
| 1872 | * @mbox: Mailbox to open |
| 1873 | * @entries: Number of entries in the outbound mailbox ring |
| 1874 | */ |
| 1875 | static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id, |
| 1876 | int mbox, int entries) |
| 1877 | { |
| 1878 | struct tsi721_device *priv = mport->priv; |
| 1879 | struct tsi721_omsg_desc *bd_ptr; |
| 1880 | int i, rc = 0; |
| 1881 | |
| 1882 | if ((entries < TSI721_OMSGD_MIN_RING_SIZE) || |
| 1883 | (entries > (TSI721_OMSGD_RING_SIZE)) || |
| 1884 | (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) { |
| 1885 | rc = -EINVAL; |
| 1886 | goto out; |
| 1887 | } |
| 1888 | |
Alexandre Bounine | e519685 | 2016-08-02 14:06:43 -0700 | [diff] [blame^] | 1889 | if ((mbox_sel & (1 << mbox)) == 0) { |
| 1890 | rc = -ENODEV; |
| 1891 | goto out; |
| 1892 | } |
| 1893 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1894 | priv->omsg_ring[mbox].dev_id = dev_id; |
| 1895 | priv->omsg_ring[mbox].size = entries; |
| 1896 | priv->omsg_ring[mbox].sts_rdptr = 0; |
| 1897 | spin_lock_init(&priv->omsg_ring[mbox].lock); |
| 1898 | |
| 1899 | /* Outbound Msg Buffer allocation based on |
| 1900 | the number of maximum descriptor entries */ |
| 1901 | for (i = 0; i < entries; i++) { |
| 1902 | priv->omsg_ring[mbox].omq_base[i] = |
| 1903 | dma_alloc_coherent( |
| 1904 | &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE, |
| 1905 | &priv->omsg_ring[mbox].omq_phys[i], |
| 1906 | GFP_KERNEL); |
| 1907 | if (priv->omsg_ring[mbox].omq_base[i] == NULL) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1908 | tsi_debug(OMSG, &priv->pdev->dev, |
| 1909 | "ENOMEM for OB_MSG_%d data buffer", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1910 | rc = -ENOMEM; |
| 1911 | goto out_buf; |
| 1912 | } |
| 1913 | } |
| 1914 | |
| 1915 | /* Outbound message descriptor allocation */ |
| 1916 | priv->omsg_ring[mbox].omd_base = dma_alloc_coherent( |
| 1917 | &priv->pdev->dev, |
| 1918 | (entries + 1) * sizeof(struct tsi721_omsg_desc), |
| 1919 | &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL); |
| 1920 | if (priv->omsg_ring[mbox].omd_base == NULL) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1921 | tsi_debug(OMSG, &priv->pdev->dev, |
| 1922 | "ENOMEM for OB_MSG_%d descriptor memory", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1923 | rc = -ENOMEM; |
| 1924 | goto out_buf; |
| 1925 | } |
| 1926 | |
| 1927 | priv->omsg_ring[mbox].tx_slot = 0; |
| 1928 | |
| 1929 | /* Outbound message descriptor status FIFO allocation */ |
| 1930 | priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1); |
Alexandre Bounine | ceb9639 | 2011-12-08 14:34:35 -0800 | [diff] [blame] | 1931 | priv->omsg_ring[mbox].sts_base = dma_zalloc_coherent(&priv->pdev->dev, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1932 | priv->omsg_ring[mbox].sts_size * |
| 1933 | sizeof(struct tsi721_dma_sts), |
| 1934 | &priv->omsg_ring[mbox].sts_phys, GFP_KERNEL); |
| 1935 | if (priv->omsg_ring[mbox].sts_base == NULL) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1936 | tsi_debug(OMSG, &priv->pdev->dev, |
| 1937 | "ENOMEM for OB_MSG_%d status FIFO", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1938 | rc = -ENOMEM; |
| 1939 | goto out_desc; |
| 1940 | } |
| 1941 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1942 | /* |
| 1943 | * Configure Outbound Messaging Engine |
| 1944 | */ |
| 1945 | |
| 1946 | /* Setup Outbound Message descriptor pointer */ |
| 1947 | iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32), |
| 1948 | priv->regs + TSI721_OBDMAC_DPTRH(mbox)); |
| 1949 | iowrite32(((u64)priv->omsg_ring[mbox].omd_phys & |
| 1950 | TSI721_OBDMAC_DPTRL_MASK), |
| 1951 | priv->regs + TSI721_OBDMAC_DPTRL(mbox)); |
| 1952 | |
| 1953 | /* Setup Outbound Message descriptor status FIFO */ |
| 1954 | iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32), |
| 1955 | priv->regs + TSI721_OBDMAC_DSBH(mbox)); |
| 1956 | iowrite32(((u64)priv->omsg_ring[mbox].sts_phys & |
| 1957 | TSI721_OBDMAC_DSBL_MASK), |
| 1958 | priv->regs + TSI721_OBDMAC_DSBL(mbox)); |
| 1959 | iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size), |
| 1960 | priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox)); |
| 1961 | |
| 1962 | /* Enable interrupts */ |
| 1963 | |
| 1964 | #ifdef CONFIG_PCI_MSI |
| 1965 | if (priv->flags & TSI721_USING_MSIX) { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1966 | int idx = TSI721_VECT_OMB0_DONE + mbox; |
| 1967 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1968 | /* Request interrupt service if we are in MSI-X mode */ |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1969 | rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0, |
| 1970 | priv->msix[idx].irq_name, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1971 | |
| 1972 | if (rc) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1973 | tsi_debug(OMSG, &priv->pdev->dev, |
| 1974 | "Unable to get MSI-X IRQ for OBOX%d-DONE", |
| 1975 | mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1976 | goto out_stat; |
| 1977 | } |
| 1978 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1979 | idx = TSI721_VECT_OMB0_INT + mbox; |
| 1980 | rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0, |
| 1981 | priv->msix[idx].irq_name, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1982 | |
| 1983 | if (rc) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 1984 | tsi_debug(OMSG, &priv->pdev->dev, |
| 1985 | "Unable to get MSI-X IRQ for MBOX%d-INT", mbox); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 1986 | idx = TSI721_VECT_OMB0_DONE + mbox; |
| 1987 | free_irq(priv->msix[idx].vector, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 1988 | goto out_stat; |
| 1989 | } |
| 1990 | } |
| 1991 | #endif /* CONFIG_PCI_MSI */ |
| 1992 | |
| 1993 | tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL); |
| 1994 | |
| 1995 | /* Initialize Outbound Message descriptors ring */ |
| 1996 | bd_ptr = priv->omsg_ring[mbox].omd_base; |
| 1997 | bd_ptr[entries].type_id = cpu_to_le32(DTYPE5 << 29); |
| 1998 | bd_ptr[entries].msg_info = 0; |
| 1999 | bd_ptr[entries].next_lo = |
| 2000 | cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys & |
| 2001 | TSI721_OBDMAC_DPTRL_MASK); |
| 2002 | bd_ptr[entries].next_hi = |
| 2003 | cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32); |
| 2004 | priv->omsg_ring[mbox].wr_count = 0; |
| 2005 | mb(); |
| 2006 | |
| 2007 | /* Initialize Outbound Message engine */ |
Alexandre Bounine | 2ece1ca | 2016-03-22 14:26:47 -0700 | [diff] [blame] | 2008 | iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT, |
| 2009 | priv->regs + TSI721_OBDMAC_CTL(mbox)); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2010 | ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); |
| 2011 | udelay(10); |
| 2012 | |
| 2013 | priv->omsg_init[mbox] = 1; |
| 2014 | |
| 2015 | return 0; |
| 2016 | |
| 2017 | #ifdef CONFIG_PCI_MSI |
| 2018 | out_stat: |
| 2019 | dma_free_coherent(&priv->pdev->dev, |
| 2020 | priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), |
| 2021 | priv->omsg_ring[mbox].sts_base, |
| 2022 | priv->omsg_ring[mbox].sts_phys); |
| 2023 | |
| 2024 | priv->omsg_ring[mbox].sts_base = NULL; |
| 2025 | #endif /* CONFIG_PCI_MSI */ |
| 2026 | |
| 2027 | out_desc: |
| 2028 | dma_free_coherent(&priv->pdev->dev, |
| 2029 | (entries + 1) * sizeof(struct tsi721_omsg_desc), |
| 2030 | priv->omsg_ring[mbox].omd_base, |
| 2031 | priv->omsg_ring[mbox].omd_phys); |
| 2032 | |
| 2033 | priv->omsg_ring[mbox].omd_base = NULL; |
| 2034 | |
| 2035 | out_buf: |
| 2036 | for (i = 0; i < priv->omsg_ring[mbox].size; i++) { |
| 2037 | if (priv->omsg_ring[mbox].omq_base[i]) { |
| 2038 | dma_free_coherent(&priv->pdev->dev, |
| 2039 | TSI721_MSG_BUFFER_SIZE, |
| 2040 | priv->omsg_ring[mbox].omq_base[i], |
| 2041 | priv->omsg_ring[mbox].omq_phys[i]); |
| 2042 | |
| 2043 | priv->omsg_ring[mbox].omq_base[i] = NULL; |
| 2044 | } |
| 2045 | } |
| 2046 | |
| 2047 | out: |
| 2048 | return rc; |
| 2049 | } |
| 2050 | |
| 2051 | /** |
| 2052 | * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox |
| 2053 | * @mport: Master port implementing the outbound message unit |
| 2054 | * @mbox: Mailbox to close |
| 2055 | */ |
| 2056 | static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox) |
| 2057 | { |
| 2058 | struct tsi721_device *priv = mport->priv; |
| 2059 | u32 i; |
| 2060 | |
| 2061 | if (!priv->omsg_init[mbox]) |
| 2062 | return; |
| 2063 | priv->omsg_init[mbox] = 0; |
| 2064 | |
| 2065 | /* Disable Interrupts */ |
| 2066 | |
| 2067 | tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL); |
| 2068 | |
| 2069 | #ifdef CONFIG_PCI_MSI |
| 2070 | if (priv->flags & TSI721_USING_MSIX) { |
| 2071 | free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2072 | (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2073 | free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2074 | (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2075 | } |
| 2076 | #endif /* CONFIG_PCI_MSI */ |
| 2077 | |
| 2078 | /* Free OMSG Descriptor Status FIFO */ |
| 2079 | dma_free_coherent(&priv->pdev->dev, |
| 2080 | priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), |
| 2081 | priv->omsg_ring[mbox].sts_base, |
| 2082 | priv->omsg_ring[mbox].sts_phys); |
| 2083 | |
| 2084 | priv->omsg_ring[mbox].sts_base = NULL; |
| 2085 | |
| 2086 | /* Free OMSG descriptors */ |
| 2087 | dma_free_coherent(&priv->pdev->dev, |
| 2088 | (priv->omsg_ring[mbox].size + 1) * |
| 2089 | sizeof(struct tsi721_omsg_desc), |
| 2090 | priv->omsg_ring[mbox].omd_base, |
| 2091 | priv->omsg_ring[mbox].omd_phys); |
| 2092 | |
| 2093 | priv->omsg_ring[mbox].omd_base = NULL; |
| 2094 | |
| 2095 | /* Free message buffers */ |
| 2096 | for (i = 0; i < priv->omsg_ring[mbox].size; i++) { |
| 2097 | if (priv->omsg_ring[mbox].omq_base[i]) { |
| 2098 | dma_free_coherent(&priv->pdev->dev, |
| 2099 | TSI721_MSG_BUFFER_SIZE, |
| 2100 | priv->omsg_ring[mbox].omq_base[i], |
| 2101 | priv->omsg_ring[mbox].omq_phys[i]); |
| 2102 | |
| 2103 | priv->omsg_ring[mbox].omq_base[i] = NULL; |
| 2104 | } |
| 2105 | } |
| 2106 | } |
| 2107 | |
| 2108 | /** |
| 2109 | * tsi721_imsg_handler - Inbound Message Interrupt Handler |
| 2110 | * @priv: pointer to tsi721 private data |
| 2111 | * @ch: inbound message channel number to service |
| 2112 | * |
| 2113 | * Services channel interrupts from inbound messaging engine. |
| 2114 | */ |
| 2115 | static void tsi721_imsg_handler(struct tsi721_device *priv, int ch) |
| 2116 | { |
| 2117 | u32 mbox = ch - 4; |
| 2118 | u32 imsg_int; |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2119 | struct rio_mport *mport = &priv->mport; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2120 | |
| 2121 | spin_lock(&priv->imsg_ring[mbox].lock); |
| 2122 | |
| 2123 | imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch)); |
| 2124 | |
| 2125 | if (imsg_int & TSI721_IBDMAC_INT_SRTO) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2126 | tsi_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2127 | |
| 2128 | if (imsg_int & TSI721_IBDMAC_INT_PC_ERROR) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2129 | tsi_info(&priv->pdev->dev, "IB MBOX%d PCIe error", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2130 | |
| 2131 | if (imsg_int & TSI721_IBDMAC_INT_FQ_LOW) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2132 | tsi_info(&priv->pdev->dev, "IB MBOX%d IB free queue low", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2133 | |
| 2134 | /* Clear IB channel interrupts */ |
| 2135 | iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch)); |
| 2136 | |
| 2137 | /* If an IB Msg is received notify the upper layer */ |
| 2138 | if (imsg_int & TSI721_IBDMAC_INT_DQ_RCV && |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2139 | mport->inb_msg[mbox].mcback) |
| 2140 | mport->inb_msg[mbox].mcback(mport, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2141 | priv->imsg_ring[mbox].dev_id, mbox, -1); |
| 2142 | |
| 2143 | if (!(priv->flags & TSI721_USING_MSIX)) { |
| 2144 | u32 ch_inte; |
| 2145 | |
| 2146 | /* Re-enable channel interrupts */ |
| 2147 | ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); |
| 2148 | ch_inte |= TSI721_INT_IMSG_CHAN(ch); |
| 2149 | iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); |
| 2150 | } |
| 2151 | |
| 2152 | spin_unlock(&priv->imsg_ring[mbox].lock); |
| 2153 | } |
| 2154 | |
| 2155 | /** |
| 2156 | * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox |
| 2157 | * @mport: Master port implementing the Inbound Messaging Engine |
| 2158 | * @dev_id: Device specific pointer to pass on event |
| 2159 | * @mbox: Mailbox to open |
| 2160 | * @entries: Number of entries in the inbound mailbox ring |
| 2161 | */ |
| 2162 | static int tsi721_open_inb_mbox(struct rio_mport *mport, void *dev_id, |
| 2163 | int mbox, int entries) |
| 2164 | { |
| 2165 | struct tsi721_device *priv = mport->priv; |
| 2166 | int ch = mbox + 4; |
| 2167 | int i; |
| 2168 | u64 *free_ptr; |
| 2169 | int rc = 0; |
| 2170 | |
| 2171 | if ((entries < TSI721_IMSGD_MIN_RING_SIZE) || |
| 2172 | (entries > TSI721_IMSGD_RING_SIZE) || |
| 2173 | (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) { |
| 2174 | rc = -EINVAL; |
| 2175 | goto out; |
| 2176 | } |
| 2177 | |
Alexandre Bounine | e519685 | 2016-08-02 14:06:43 -0700 | [diff] [blame^] | 2178 | if ((mbox_sel & (1 << mbox)) == 0) { |
| 2179 | rc = -ENODEV; |
| 2180 | goto out; |
| 2181 | } |
| 2182 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2183 | /* Initialize IB Messaging Ring */ |
| 2184 | priv->imsg_ring[mbox].dev_id = dev_id; |
| 2185 | priv->imsg_ring[mbox].size = entries; |
| 2186 | priv->imsg_ring[mbox].rx_slot = 0; |
| 2187 | priv->imsg_ring[mbox].desc_rdptr = 0; |
| 2188 | priv->imsg_ring[mbox].fq_wrptr = 0; |
| 2189 | for (i = 0; i < priv->imsg_ring[mbox].size; i++) |
| 2190 | priv->imsg_ring[mbox].imq_base[i] = NULL; |
| 2191 | spin_lock_init(&priv->imsg_ring[mbox].lock); |
| 2192 | |
| 2193 | /* Allocate buffers for incoming messages */ |
| 2194 | priv->imsg_ring[mbox].buf_base = |
| 2195 | dma_alloc_coherent(&priv->pdev->dev, |
| 2196 | entries * TSI721_MSG_BUFFER_SIZE, |
| 2197 | &priv->imsg_ring[mbox].buf_phys, |
| 2198 | GFP_KERNEL); |
| 2199 | |
| 2200 | if (priv->imsg_ring[mbox].buf_base == NULL) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2201 | tsi_err(&priv->pdev->dev, |
| 2202 | "Failed to allocate buffers for IB MBOX%d", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2203 | rc = -ENOMEM; |
| 2204 | goto out; |
| 2205 | } |
| 2206 | |
| 2207 | /* Allocate memory for circular free list */ |
| 2208 | priv->imsg_ring[mbox].imfq_base = |
| 2209 | dma_alloc_coherent(&priv->pdev->dev, |
| 2210 | entries * 8, |
| 2211 | &priv->imsg_ring[mbox].imfq_phys, |
| 2212 | GFP_KERNEL); |
| 2213 | |
| 2214 | if (priv->imsg_ring[mbox].imfq_base == NULL) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2215 | tsi_err(&priv->pdev->dev, |
| 2216 | "Failed to allocate free queue for IB MBOX%d", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2217 | rc = -ENOMEM; |
| 2218 | goto out_buf; |
| 2219 | } |
| 2220 | |
| 2221 | /* Allocate memory for Inbound message descriptors */ |
| 2222 | priv->imsg_ring[mbox].imd_base = |
| 2223 | dma_alloc_coherent(&priv->pdev->dev, |
| 2224 | entries * sizeof(struct tsi721_imsg_desc), |
| 2225 | &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL); |
| 2226 | |
| 2227 | if (priv->imsg_ring[mbox].imd_base == NULL) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2228 | tsi_err(&priv->pdev->dev, |
| 2229 | "Failed to allocate descriptor memory for IB MBOX%d", |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2230 | mbox); |
| 2231 | rc = -ENOMEM; |
| 2232 | goto out_dma; |
| 2233 | } |
| 2234 | |
| 2235 | /* Fill free buffer pointer list */ |
| 2236 | free_ptr = priv->imsg_ring[mbox].imfq_base; |
| 2237 | for (i = 0; i < entries; i++) |
| 2238 | free_ptr[i] = cpu_to_le64( |
| 2239 | (u64)(priv->imsg_ring[mbox].buf_phys) + |
| 2240 | i * 0x1000); |
| 2241 | |
| 2242 | mb(); |
| 2243 | |
| 2244 | /* |
| 2245 | * For mapping of inbound SRIO Messages into appropriate queues we need |
| 2246 | * to set Inbound Device ID register in the messaging engine. We do it |
| 2247 | * once when first inbound mailbox is requested. |
| 2248 | */ |
| 2249 | if (!(priv->flags & TSI721_IMSGID_SET)) { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2250 | iowrite32((u32)priv->mport.host_deviceid, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2251 | priv->regs + TSI721_IB_DEVID); |
| 2252 | priv->flags |= TSI721_IMSGID_SET; |
| 2253 | } |
| 2254 | |
| 2255 | /* |
| 2256 | * Configure Inbound Messaging channel (ch = mbox + 4) |
| 2257 | */ |
| 2258 | |
| 2259 | /* Setup Inbound Message free queue */ |
| 2260 | iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32), |
| 2261 | priv->regs + TSI721_IBDMAC_FQBH(ch)); |
| 2262 | iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys & |
| 2263 | TSI721_IBDMAC_FQBL_MASK), |
| 2264 | priv->regs+TSI721_IBDMAC_FQBL(ch)); |
| 2265 | iowrite32(TSI721_DMAC_DSSZ_SIZE(entries), |
| 2266 | priv->regs + TSI721_IBDMAC_FQSZ(ch)); |
| 2267 | |
| 2268 | /* Setup Inbound Message descriptor queue */ |
| 2269 | iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32), |
| 2270 | priv->regs + TSI721_IBDMAC_DQBH(ch)); |
| 2271 | iowrite32(((u32)priv->imsg_ring[mbox].imd_phys & |
| 2272 | (u32)TSI721_IBDMAC_DQBL_MASK), |
| 2273 | priv->regs+TSI721_IBDMAC_DQBL(ch)); |
| 2274 | iowrite32(TSI721_DMAC_DSSZ_SIZE(entries), |
| 2275 | priv->regs + TSI721_IBDMAC_DQSZ(ch)); |
| 2276 | |
| 2277 | /* Enable interrupts */ |
| 2278 | |
| 2279 | #ifdef CONFIG_PCI_MSI |
| 2280 | if (priv->flags & TSI721_USING_MSIX) { |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2281 | int idx = TSI721_VECT_IMB0_RCV + mbox; |
| 2282 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2283 | /* Request interrupt service if we are in MSI-X mode */ |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2284 | rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0, |
| 2285 | priv->msix[idx].irq_name, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2286 | |
| 2287 | if (rc) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2288 | tsi_debug(IMSG, &priv->pdev->dev, |
| 2289 | "Unable to get MSI-X IRQ for IBOX%d-DONE", |
| 2290 | mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2291 | goto out_desc; |
| 2292 | } |
| 2293 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2294 | idx = TSI721_VECT_IMB0_INT + mbox; |
| 2295 | rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0, |
| 2296 | priv->msix[idx].irq_name, (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2297 | |
| 2298 | if (rc) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2299 | tsi_debug(IMSG, &priv->pdev->dev, |
| 2300 | "Unable to get MSI-X IRQ for IBOX%d-INT", mbox); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2301 | free_irq( |
| 2302 | priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2303 | (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2304 | goto out_desc; |
| 2305 | } |
| 2306 | } |
| 2307 | #endif /* CONFIG_PCI_MSI */ |
| 2308 | |
| 2309 | tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL); |
| 2310 | |
| 2311 | /* Initialize Inbound Message Engine */ |
| 2312 | iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch)); |
| 2313 | ioread32(priv->regs + TSI721_IBDMAC_CTL(ch)); |
| 2314 | udelay(10); |
| 2315 | priv->imsg_ring[mbox].fq_wrptr = entries - 1; |
| 2316 | iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch)); |
| 2317 | |
| 2318 | priv->imsg_init[mbox] = 1; |
| 2319 | return 0; |
| 2320 | |
| 2321 | #ifdef CONFIG_PCI_MSI |
| 2322 | out_desc: |
| 2323 | dma_free_coherent(&priv->pdev->dev, |
| 2324 | priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc), |
| 2325 | priv->imsg_ring[mbox].imd_base, |
| 2326 | priv->imsg_ring[mbox].imd_phys); |
| 2327 | |
| 2328 | priv->imsg_ring[mbox].imd_base = NULL; |
| 2329 | #endif /* CONFIG_PCI_MSI */ |
| 2330 | |
| 2331 | out_dma: |
| 2332 | dma_free_coherent(&priv->pdev->dev, |
| 2333 | priv->imsg_ring[mbox].size * 8, |
| 2334 | priv->imsg_ring[mbox].imfq_base, |
| 2335 | priv->imsg_ring[mbox].imfq_phys); |
| 2336 | |
| 2337 | priv->imsg_ring[mbox].imfq_base = NULL; |
| 2338 | |
| 2339 | out_buf: |
| 2340 | dma_free_coherent(&priv->pdev->dev, |
| 2341 | priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE, |
| 2342 | priv->imsg_ring[mbox].buf_base, |
| 2343 | priv->imsg_ring[mbox].buf_phys); |
| 2344 | |
| 2345 | priv->imsg_ring[mbox].buf_base = NULL; |
| 2346 | |
| 2347 | out: |
| 2348 | return rc; |
| 2349 | } |
| 2350 | |
| 2351 | /** |
| 2352 | * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox |
| 2353 | * @mport: Master port implementing the Inbound Messaging Engine |
| 2354 | * @mbox: Mailbox to close |
| 2355 | */ |
| 2356 | static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox) |
| 2357 | { |
| 2358 | struct tsi721_device *priv = mport->priv; |
| 2359 | u32 rx_slot; |
| 2360 | int ch = mbox + 4; |
| 2361 | |
| 2362 | if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */ |
| 2363 | return; |
| 2364 | priv->imsg_init[mbox] = 0; |
| 2365 | |
| 2366 | /* Disable Inbound Messaging Engine */ |
| 2367 | |
| 2368 | /* Disable Interrupts */ |
| 2369 | tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK); |
| 2370 | |
| 2371 | #ifdef CONFIG_PCI_MSI |
| 2372 | if (priv->flags & TSI721_USING_MSIX) { |
| 2373 | free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2374 | (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2375 | free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2376 | (void *)priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2377 | } |
| 2378 | #endif /* CONFIG_PCI_MSI */ |
| 2379 | |
| 2380 | /* Clear Inbound Buffer Queue */ |
| 2381 | for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++) |
| 2382 | priv->imsg_ring[mbox].imq_base[rx_slot] = NULL; |
| 2383 | |
| 2384 | /* Free memory allocated for message buffers */ |
| 2385 | dma_free_coherent(&priv->pdev->dev, |
| 2386 | priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE, |
| 2387 | priv->imsg_ring[mbox].buf_base, |
| 2388 | priv->imsg_ring[mbox].buf_phys); |
| 2389 | |
| 2390 | priv->imsg_ring[mbox].buf_base = NULL; |
| 2391 | |
| 2392 | /* Free memory allocated for free pointr list */ |
| 2393 | dma_free_coherent(&priv->pdev->dev, |
| 2394 | priv->imsg_ring[mbox].size * 8, |
| 2395 | priv->imsg_ring[mbox].imfq_base, |
| 2396 | priv->imsg_ring[mbox].imfq_phys); |
| 2397 | |
| 2398 | priv->imsg_ring[mbox].imfq_base = NULL; |
| 2399 | |
| 2400 | /* Free memory allocated for RX descriptors */ |
| 2401 | dma_free_coherent(&priv->pdev->dev, |
| 2402 | priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc), |
| 2403 | priv->imsg_ring[mbox].imd_base, |
| 2404 | priv->imsg_ring[mbox].imd_phys); |
| 2405 | |
| 2406 | priv->imsg_ring[mbox].imd_base = NULL; |
| 2407 | } |
| 2408 | |
| 2409 | /** |
| 2410 | * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue |
| 2411 | * @mport: Master port implementing the Inbound Messaging Engine |
| 2412 | * @mbox: Inbound mailbox number |
| 2413 | * @buf: Buffer to add to inbound queue |
| 2414 | */ |
| 2415 | static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) |
| 2416 | { |
| 2417 | struct tsi721_device *priv = mport->priv; |
| 2418 | u32 rx_slot; |
| 2419 | int rc = 0; |
| 2420 | |
| 2421 | rx_slot = priv->imsg_ring[mbox].rx_slot; |
| 2422 | if (priv->imsg_ring[mbox].imq_base[rx_slot]) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2423 | tsi_err(&priv->pdev->dev, |
| 2424 | "Error adding inbound buffer %d, buffer exists", |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2425 | rx_slot); |
| 2426 | rc = -EINVAL; |
| 2427 | goto out; |
| 2428 | } |
| 2429 | |
| 2430 | priv->imsg_ring[mbox].imq_base[rx_slot] = buf; |
| 2431 | |
| 2432 | if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size) |
| 2433 | priv->imsg_ring[mbox].rx_slot = 0; |
| 2434 | |
| 2435 | out: |
| 2436 | return rc; |
| 2437 | } |
| 2438 | |
| 2439 | /** |
| 2440 | * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue |
| 2441 | * @mport: Master port implementing the Inbound Messaging Engine |
| 2442 | * @mbox: Inbound mailbox number |
| 2443 | * |
| 2444 | * Returns pointer to the message on success or NULL on failure. |
| 2445 | */ |
| 2446 | static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox) |
| 2447 | { |
| 2448 | struct tsi721_device *priv = mport->priv; |
| 2449 | struct tsi721_imsg_desc *desc; |
| 2450 | u32 rx_slot; |
| 2451 | void *rx_virt = NULL; |
| 2452 | u64 rx_phys; |
| 2453 | void *buf = NULL; |
| 2454 | u64 *free_ptr; |
| 2455 | int ch = mbox + 4; |
| 2456 | int msg_size; |
| 2457 | |
| 2458 | if (!priv->imsg_init[mbox]) |
| 2459 | return NULL; |
| 2460 | |
| 2461 | desc = priv->imsg_ring[mbox].imd_base; |
| 2462 | desc += priv->imsg_ring[mbox].desc_rdptr; |
| 2463 | |
| 2464 | if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO)) |
| 2465 | goto out; |
| 2466 | |
| 2467 | rx_slot = priv->imsg_ring[mbox].rx_slot; |
| 2468 | while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) { |
| 2469 | if (++rx_slot == priv->imsg_ring[mbox].size) |
| 2470 | rx_slot = 0; |
| 2471 | } |
| 2472 | |
| 2473 | rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) | |
| 2474 | le32_to_cpu(desc->bufptr_lo); |
| 2475 | |
| 2476 | rx_virt = priv->imsg_ring[mbox].buf_base + |
| 2477 | (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys); |
| 2478 | |
| 2479 | buf = priv->imsg_ring[mbox].imq_base[rx_slot]; |
| 2480 | msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT; |
| 2481 | if (msg_size == 0) |
| 2482 | msg_size = RIO_MAX_MSG_SIZE; |
| 2483 | |
| 2484 | memcpy(buf, rx_virt, msg_size); |
| 2485 | priv->imsg_ring[mbox].imq_base[rx_slot] = NULL; |
| 2486 | |
| 2487 | desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO); |
| 2488 | if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size) |
| 2489 | priv->imsg_ring[mbox].desc_rdptr = 0; |
| 2490 | |
| 2491 | iowrite32(priv->imsg_ring[mbox].desc_rdptr, |
| 2492 | priv->regs + TSI721_IBDMAC_DQRP(ch)); |
| 2493 | |
| 2494 | /* Return free buffer into the pointer list */ |
| 2495 | free_ptr = priv->imsg_ring[mbox].imfq_base; |
| 2496 | free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys); |
| 2497 | |
| 2498 | if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size) |
| 2499 | priv->imsg_ring[mbox].fq_wrptr = 0; |
| 2500 | |
| 2501 | iowrite32(priv->imsg_ring[mbox].fq_wrptr, |
| 2502 | priv->regs + TSI721_IBDMAC_FQWP(ch)); |
| 2503 | out: |
| 2504 | return buf; |
| 2505 | } |
| 2506 | |
| 2507 | /** |
| 2508 | * tsi721_messages_init - Initialization of Messaging Engine |
| 2509 | * @priv: pointer to tsi721 private data |
| 2510 | * |
| 2511 | * Configures Tsi721 messaging engine. |
| 2512 | */ |
| 2513 | static int tsi721_messages_init(struct tsi721_device *priv) |
| 2514 | { |
| 2515 | int ch; |
| 2516 | |
| 2517 | iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG); |
| 2518 | iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT); |
| 2519 | iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT); |
| 2520 | |
| 2521 | /* Set SRIO Message Request/Response Timeout */ |
| 2522 | iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO); |
| 2523 | |
| 2524 | /* Initialize Inbound Messaging Engine Registers */ |
| 2525 | for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) { |
| 2526 | /* Clear interrupt bits */ |
| 2527 | iowrite32(TSI721_IBDMAC_INT_MASK, |
| 2528 | priv->regs + TSI721_IBDMAC_INT(ch)); |
| 2529 | /* Clear Status */ |
| 2530 | iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch)); |
| 2531 | |
| 2532 | iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK, |
| 2533 | priv->regs + TSI721_SMSG_ECC_COR_LOG(ch)); |
| 2534 | iowrite32(TSI721_SMSG_ECC_NCOR_MASK, |
| 2535 | priv->regs + TSI721_SMSG_ECC_NCOR(ch)); |
| 2536 | } |
| 2537 | |
| 2538 | return 0; |
| 2539 | } |
| 2540 | |
| 2541 | /** |
Alexandre Bounine | dbe74af | 2016-03-22 14:26:02 -0700 | [diff] [blame] | 2542 | * tsi721_query_mport - Fetch inbound message from the Tsi721 MSG Queue |
| 2543 | * @mport: Master port implementing the Inbound Messaging Engine |
| 2544 | * @mbox: Inbound mailbox number |
| 2545 | * |
| 2546 | * Returns pointer to the message on success or NULL on failure. |
| 2547 | */ |
| 2548 | static int tsi721_query_mport(struct rio_mport *mport, |
| 2549 | struct rio_mport_attr *attr) |
| 2550 | { |
| 2551 | struct tsi721_device *priv = mport->priv; |
| 2552 | u32 rval; |
| 2553 | |
| 2554 | rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_ERR_STS_CSR(0))); |
| 2555 | if (rval & RIO_PORT_N_ERR_STS_PORT_OK) { |
| 2556 | rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_CTL2_CSR(0))); |
| 2557 | attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28; |
| 2558 | rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_CTL_CSR(0))); |
| 2559 | attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27; |
| 2560 | } else |
| 2561 | attr->link_speed = RIO_LINK_DOWN; |
| 2562 | |
| 2563 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
| 2564 | attr->flags = RIO_MPORT_DMA | RIO_MPORT_DMA_SG; |
| 2565 | attr->dma_max_sge = 0; |
| 2566 | attr->dma_max_size = TSI721_BDMA_MAX_BCOUNT; |
| 2567 | attr->dma_align = 0; |
| 2568 | #else |
| 2569 | attr->flags = 0; |
| 2570 | #endif |
| 2571 | return 0; |
| 2572 | } |
| 2573 | |
| 2574 | /** |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2575 | * tsi721_disable_ints - disables all device interrupts |
| 2576 | * @priv: pointer to tsi721 private data |
| 2577 | */ |
| 2578 | static void tsi721_disable_ints(struct tsi721_device *priv) |
| 2579 | { |
| 2580 | int ch; |
| 2581 | |
| 2582 | /* Disable all device level interrupts */ |
| 2583 | iowrite32(0, priv->regs + TSI721_DEV_INTE); |
| 2584 | |
| 2585 | /* Disable all Device Channel interrupts */ |
| 2586 | iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE); |
| 2587 | |
| 2588 | /* Disable all Inbound Msg Channel interrupts */ |
| 2589 | for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) |
| 2590 | iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch)); |
| 2591 | |
| 2592 | /* Disable all Outbound Msg Channel interrupts */ |
| 2593 | for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++) |
| 2594 | iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch)); |
| 2595 | |
| 2596 | /* Disable all general messaging interrupts */ |
| 2597 | iowrite32(0, priv->regs + TSI721_SMSG_INTE); |
| 2598 | |
| 2599 | /* Disable all BDMA Channel interrupts */ |
| 2600 | for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2601 | iowrite32(0, |
| 2602 | priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2603 | |
| 2604 | /* Disable all general BDMA interrupts */ |
| 2605 | iowrite32(0, priv->regs + TSI721_BDMA_INTE); |
| 2606 | |
| 2607 | /* Disable all SRIO Channel interrupts */ |
| 2608 | for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++) |
| 2609 | iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch)); |
| 2610 | |
| 2611 | /* Disable all general SR2PC interrupts */ |
| 2612 | iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE); |
| 2613 | |
| 2614 | /* Disable all PC2SR interrupts */ |
| 2615 | iowrite32(0, priv->regs + TSI721_PC2SR_INTE); |
| 2616 | |
| 2617 | /* Disable all I2C interrupts */ |
| 2618 | iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE); |
| 2619 | |
| 2620 | /* Disable SRIO MAC interrupts */ |
| 2621 | iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE); |
| 2622 | iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN); |
| 2623 | } |
| 2624 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2625 | static struct rio_ops tsi721_rio_ops = { |
| 2626 | .lcread = tsi721_lcread, |
| 2627 | .lcwrite = tsi721_lcwrite, |
| 2628 | .cread = tsi721_cread_dma, |
| 2629 | .cwrite = tsi721_cwrite_dma, |
| 2630 | .dsend = tsi721_dsend, |
| 2631 | .open_inb_mbox = tsi721_open_inb_mbox, |
| 2632 | .close_inb_mbox = tsi721_close_inb_mbox, |
| 2633 | .open_outb_mbox = tsi721_open_outb_mbox, |
| 2634 | .close_outb_mbox = tsi721_close_outb_mbox, |
| 2635 | .add_outb_message = tsi721_add_outb_message, |
| 2636 | .add_inb_buffer = tsi721_add_inb_buffer, |
| 2637 | .get_inb_message = tsi721_get_inb_message, |
| 2638 | .map_inb = tsi721_rio_map_inb_mem, |
| 2639 | .unmap_inb = tsi721_rio_unmap_inb_mem, |
| 2640 | .pwenable = tsi721_pw_enable, |
| 2641 | .query_mport = tsi721_query_mport, |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 2642 | .map_outb = tsi721_map_outb_win, |
| 2643 | .unmap_outb = tsi721_unmap_outb_win, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2644 | }; |
| 2645 | |
| 2646 | static void tsi721_mport_release(struct device *dev) |
| 2647 | { |
| 2648 | struct rio_mport *mport = to_rio_mport(dev); |
| 2649 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2650 | tsi_debug(EXIT, dev, "%s id=%d", mport->name, mport->id); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2651 | } |
| 2652 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2653 | /** |
| 2654 | * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port |
| 2655 | * @priv: pointer to tsi721 private data |
| 2656 | * |
| 2657 | * Configures Tsi721 as RapidIO master port. |
| 2658 | */ |
Bill Pemberton | 305c891 | 2012-11-19 13:23:25 -0500 | [diff] [blame] | 2659 | static int tsi721_setup_mport(struct tsi721_device *priv) |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2660 | { |
| 2661 | struct pci_dev *pdev = priv->pdev; |
| 2662 | int err = 0; |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2663 | struct rio_mport *mport = &priv->mport; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2664 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2665 | err = rio_mport_initialize(mport); |
| 2666 | if (err) |
| 2667 | return err; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2668 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2669 | mport->ops = &tsi721_rio_ops; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2670 | mport->index = 0; |
| 2671 | mport->sys_size = 0; /* small system */ |
| 2672 | mport->phy_type = RIO_PHY_SERIAL; |
| 2673 | mport->priv = (void *)priv; |
| 2674 | mport->phys_efptr = 0x100; |
Alexandre Bounine | 2aaf308 | 2014-04-07 15:38:56 -0700 | [diff] [blame] | 2675 | mport->dev.parent = &pdev->dev; |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2676 | mport->dev.release = tsi721_mport_release; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2677 | |
| 2678 | INIT_LIST_HEAD(&mport->dbells); |
| 2679 | |
| 2680 | rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); |
Alexandre Bounine | b439e66 | 2011-12-08 14:34:36 -0800 | [diff] [blame] | 2681 | rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3); |
| 2682 | rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3); |
Alexandre Bounine | ed43f44 | 2012-10-04 17:15:51 -0700 | [diff] [blame] | 2683 | snprintf(mport->name, RIO_MAX_MPORT_NAME, "%s(%s)", |
| 2684 | dev_driver_string(&pdev->dev), dev_name(&pdev->dev)); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2685 | |
| 2686 | /* Hook up interrupt handler */ |
| 2687 | |
| 2688 | #ifdef CONFIG_PCI_MSI |
| 2689 | if (!tsi721_enable_msix(priv)) |
| 2690 | priv->flags |= TSI721_USING_MSIX; |
| 2691 | else if (!pci_enable_msi(pdev)) |
| 2692 | priv->flags |= TSI721_USING_MSI; |
| 2693 | else |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2694 | tsi_debug(MPORT, &pdev->dev, |
| 2695 | "MSI/MSI-X is not available. Using legacy INTx."); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2696 | #endif /* CONFIG_PCI_MSI */ |
| 2697 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2698 | err = tsi721_request_irq(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2699 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2700 | if (err) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2701 | tsi_err(&pdev->dev, "Unable to get PCI IRQ %02X (err=0x%x)", |
| 2702 | pdev->irq, err); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2703 | return err; |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2704 | } |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2705 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2706 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2707 | err = tsi721_register_dma(priv); |
| 2708 | if (err) |
| 2709 | goto err_exit; |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2710 | #endif |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2711 | /* Enable SRIO link */ |
| 2712 | iowrite32(ioread32(priv->regs + TSI721_DEVCTL) | |
| 2713 | TSI721_DEVCTL_SRBOOT_CMPL, |
| 2714 | priv->regs + TSI721_DEVCTL); |
| 2715 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2716 | if (mport->host_deviceid >= 0) |
| 2717 | iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER | |
| 2718 | RIO_PORT_GEN_DISCOVERED, |
| 2719 | priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR)); |
| 2720 | else |
| 2721 | iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR)); |
| 2722 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2723 | err = rio_register_mport(mport); |
| 2724 | if (err) { |
| 2725 | tsi721_unregister_dma(priv); |
| 2726 | goto err_exit; |
| 2727 | } |
| 2728 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2729 | return 0; |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2730 | |
| 2731 | err_exit: |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2732 | tsi721_free_irq(priv); |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2733 | return err; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2734 | } |
| 2735 | |
Bill Pemberton | 305c891 | 2012-11-19 13:23:25 -0500 | [diff] [blame] | 2736 | static int tsi721_probe(struct pci_dev *pdev, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2737 | const struct pci_device_id *id) |
| 2738 | { |
| 2739 | struct tsi721_device *priv; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2740 | int err; |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2741 | |
| 2742 | priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL); |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2743 | if (!priv) { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2744 | err = -ENOMEM; |
| 2745 | goto err_exit; |
| 2746 | } |
| 2747 | |
| 2748 | err = pci_enable_device(pdev); |
| 2749 | if (err) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2750 | tsi_err(&pdev->dev, "Failed to enable PCI device"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2751 | goto err_clean; |
| 2752 | } |
| 2753 | |
| 2754 | priv->pdev = pdev; |
| 2755 | |
| 2756 | #ifdef DEBUG |
Alexandre Bounine | 9a9a9a7 | 2012-08-21 16:16:12 -0700 | [diff] [blame] | 2757 | { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2758 | int i; |
| 2759 | |
| 2760 | for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { |
| 2761 | tsi_debug(INIT, &pdev->dev, "res%d %pR", |
| 2762 | i, &pdev->resource[i]); |
| 2763 | } |
Alexandre Bounine | 9a9a9a7 | 2012-08-21 16:16:12 -0700 | [diff] [blame] | 2764 | } |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2765 | #endif |
| 2766 | /* |
| 2767 | * Verify BAR configuration |
| 2768 | */ |
| 2769 | |
| 2770 | /* BAR_0 (registers) must be 512KB+ in 32-bit address space */ |
| 2771 | if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) || |
| 2772 | pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 || |
| 2773 | pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2774 | tsi_err(&pdev->dev, "Missing or misconfigured CSR BAR0"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2775 | err = -ENODEV; |
| 2776 | goto err_disable_pdev; |
| 2777 | } |
| 2778 | |
| 2779 | /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */ |
| 2780 | if (!(pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM) || |
| 2781 | pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM_64 || |
| 2782 | pci_resource_len(pdev, BAR_1) < TSI721_DB_WIN_SIZE) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2783 | tsi_err(&pdev->dev, "Missing or misconfigured Doorbell BAR1"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2784 | err = -ENODEV; |
| 2785 | goto err_disable_pdev; |
| 2786 | } |
| 2787 | |
| 2788 | /* |
| 2789 | * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address |
| 2790 | * space. |
| 2791 | * NOTE: BAR_2 and BAR_4 are not used by this version of driver. |
| 2792 | * It may be a good idea to keep them disabled using HW configuration |
| 2793 | * to save PCI memory space. |
| 2794 | */ |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 2795 | |
| 2796 | priv->p2r_bar[0].size = priv->p2r_bar[1].size = 0; |
| 2797 | |
| 2798 | if (pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM_64) { |
| 2799 | if (pci_resource_flags(pdev, BAR_2) & IORESOURCE_PREFETCH) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2800 | tsi_debug(INIT, &pdev->dev, |
| 2801 | "Prefetchable OBW BAR2 will not be used"); |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 2802 | else { |
| 2803 | priv->p2r_bar[0].base = pci_resource_start(pdev, BAR_2); |
| 2804 | priv->p2r_bar[0].size = pci_resource_len(pdev, BAR_2); |
| 2805 | } |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2806 | } |
| 2807 | |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 2808 | if (pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM_64) { |
| 2809 | if (pci_resource_flags(pdev, BAR_4) & IORESOURCE_PREFETCH) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2810 | tsi_debug(INIT, &pdev->dev, |
| 2811 | "Prefetchable OBW BAR4 will not be used"); |
Alexandre Bounine | 1679e8d | 2016-03-22 14:26:53 -0700 | [diff] [blame] | 2812 | else { |
| 2813 | priv->p2r_bar[1].base = pci_resource_start(pdev, BAR_4); |
| 2814 | priv->p2r_bar[1].size = pci_resource_len(pdev, BAR_4); |
| 2815 | } |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2816 | } |
| 2817 | |
| 2818 | err = pci_request_regions(pdev, DRV_NAME); |
| 2819 | if (err) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2820 | tsi_err(&pdev->dev, "Unable to obtain PCI resources"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2821 | goto err_disable_pdev; |
| 2822 | } |
| 2823 | |
| 2824 | pci_set_master(pdev); |
| 2825 | |
| 2826 | priv->regs = pci_ioremap_bar(pdev, BAR_0); |
| 2827 | if (!priv->regs) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2828 | tsi_err(&pdev->dev, "Unable to map device registers space"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2829 | err = -ENOMEM; |
| 2830 | goto err_free_res; |
| 2831 | } |
| 2832 | |
| 2833 | priv->odb_base = pci_ioremap_bar(pdev, BAR_1); |
| 2834 | if (!priv->odb_base) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2835 | tsi_err(&pdev->dev, "Unable to map outbound doorbells space"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2836 | err = -ENOMEM; |
| 2837 | goto err_unmap_bars; |
| 2838 | } |
| 2839 | |
| 2840 | /* Configure DMA attributes. */ |
| 2841 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
Peter Senna Tschudin | 18f6287 | 2012-10-04 17:15:55 -0700 | [diff] [blame] | 2842 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 2843 | if (err) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2844 | tsi_err(&pdev->dev, "Unable to set DMA mask"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2845 | goto err_unmap_bars; |
| 2846 | } |
| 2847 | |
| 2848 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2849 | tsi_info(&pdev->dev, "Unable to set consistent DMA mask"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2850 | } else { |
| 2851 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
| 2852 | if (err) |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2853 | tsi_info(&pdev->dev, "Unable to set consistent DMA mask"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2854 | } |
| 2855 | |
Jiang Liu | 5cdaaf8 | 2012-07-24 17:20:31 +0800 | [diff] [blame] | 2856 | BUG_ON(!pci_is_pcie(pdev)); |
Alexandre Bounine | 1cee22b | 2011-12-08 14:34:42 -0800 | [diff] [blame] | 2857 | |
Alexandre Bounine | 174f1a7 | 2016-03-22 14:25:48 -0700 | [diff] [blame] | 2858 | /* Clear "no snoop" and "relaxed ordering" bits. */ |
Jiang Liu | 5cdaaf8 | 2012-07-24 17:20:31 +0800 | [diff] [blame] | 2859 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, |
Alexandre Bounine | 174f1a7 | 2016-03-22 14:25:48 -0700 | [diff] [blame] | 2860 | PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0); |
Alexandre Bounine | 1cee22b | 2011-12-08 14:34:42 -0800 | [diff] [blame] | 2861 | |
Alexandre Bounine | cb782cd | 2016-08-02 14:06:40 -0700 | [diff] [blame] | 2862 | /* Override PCIe Maximum Read Request Size setting if requested */ |
| 2863 | if (pcie_mrrs >= 0) { |
| 2864 | if (pcie_mrrs <= 5) |
| 2865 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, |
| 2866 | PCI_EXP_DEVCTL_READRQ, pcie_mrrs << 12); |
| 2867 | else |
| 2868 | tsi_info(&pdev->dev, |
| 2869 | "Invalid MRRS override value %d", pcie_mrrs); |
| 2870 | } |
| 2871 | |
Alexandre Bounine | 1cee22b | 2011-12-08 14:34:42 -0800 | [diff] [blame] | 2872 | /* Adjust PCIe completion timeout. */ |
Jiang Liu | 5cdaaf8 | 2012-07-24 17:20:31 +0800 | [diff] [blame] | 2873 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2874 | |
| 2875 | /* |
| 2876 | * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block |
| 2877 | */ |
| 2878 | pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0x01); |
| 2879 | pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXTBL, |
| 2880 | TSI721_MSIXTBL_OFFSET); |
| 2881 | pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXPBA, |
| 2882 | TSI721_MSIXPBA_OFFSET); |
| 2883 | pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0); |
| 2884 | /* End of FIXUP */ |
| 2885 | |
| 2886 | tsi721_disable_ints(priv); |
| 2887 | |
| 2888 | tsi721_init_pc2sr_mapping(priv); |
| 2889 | tsi721_init_sr2pc_mapping(priv); |
| 2890 | |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2891 | if (tsi721_bdma_maint_init(priv)) { |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2892 | tsi_err(&pdev->dev, "BDMA initialization failed"); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2893 | err = -ENOMEM; |
| 2894 | goto err_unmap_bars; |
| 2895 | } |
| 2896 | |
| 2897 | err = tsi721_doorbell_init(priv); |
| 2898 | if (err) |
| 2899 | goto err_free_bdma; |
| 2900 | |
| 2901 | tsi721_port_write_init(priv); |
| 2902 | |
| 2903 | err = tsi721_messages_init(priv); |
| 2904 | if (err) |
| 2905 | goto err_free_consistent; |
| 2906 | |
| 2907 | err = tsi721_setup_mport(priv); |
| 2908 | if (err) |
| 2909 | goto err_free_consistent; |
| 2910 | |
Alexandre Bounine | e3dd8cd | 2016-03-22 14:26:08 -0700 | [diff] [blame] | 2911 | pci_set_drvdata(pdev, priv); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2912 | tsi721_interrupts_init(priv); |
Alexandre Bounine | e3dd8cd | 2016-03-22 14:26:08 -0700 | [diff] [blame] | 2913 | |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2914 | return 0; |
| 2915 | |
| 2916 | err_free_consistent: |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2917 | tsi721_port_write_free(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2918 | tsi721_doorbell_free(priv); |
| 2919 | err_free_bdma: |
Alexandre Bounine | 9eaa3d9 | 2012-05-31 16:26:39 -0700 | [diff] [blame] | 2920 | tsi721_bdma_maint_free(priv); |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2921 | err_unmap_bars: |
| 2922 | if (priv->regs) |
| 2923 | iounmap(priv->regs); |
| 2924 | if (priv->odb_base) |
| 2925 | iounmap(priv->odb_base); |
| 2926 | err_free_res: |
| 2927 | pci_release_regions(pdev); |
| 2928 | pci_clear_master(pdev); |
| 2929 | err_disable_pdev: |
| 2930 | pci_disable_device(pdev); |
| 2931 | err_clean: |
| 2932 | kfree(priv); |
| 2933 | err_exit: |
| 2934 | return err; |
| 2935 | } |
| 2936 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2937 | static void tsi721_remove(struct pci_dev *pdev) |
| 2938 | { |
| 2939 | struct tsi721_device *priv = pci_get_drvdata(pdev); |
| 2940 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2941 | tsi_debug(EXIT, &pdev->dev, "enter"); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2942 | |
| 2943 | tsi721_disable_ints(priv); |
| 2944 | tsi721_free_irq(priv); |
Alexandre Bounine | 9a0b062 | 2016-03-22 14:26:44 -0700 | [diff] [blame] | 2945 | flush_scheduled_work(); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2946 | rio_unregister_mport(&priv->mport); |
| 2947 | |
| 2948 | tsi721_unregister_dma(priv); |
| 2949 | tsi721_bdma_maint_free(priv); |
| 2950 | tsi721_doorbell_free(priv); |
| 2951 | tsi721_port_write_free(priv); |
| 2952 | tsi721_close_sr2pc_mapping(priv); |
| 2953 | |
| 2954 | if (priv->regs) |
| 2955 | iounmap(priv->regs); |
| 2956 | if (priv->odb_base) |
| 2957 | iounmap(priv->odb_base); |
| 2958 | #ifdef CONFIG_PCI_MSI |
| 2959 | if (priv->flags & TSI721_USING_MSIX) |
| 2960 | pci_disable_msix(priv->pdev); |
| 2961 | else if (priv->flags & TSI721_USING_MSI) |
| 2962 | pci_disable_msi(priv->pdev); |
| 2963 | #endif |
| 2964 | pci_release_regions(pdev); |
| 2965 | pci_clear_master(pdev); |
| 2966 | pci_disable_device(pdev); |
| 2967 | pci_set_drvdata(pdev, NULL); |
| 2968 | kfree(priv); |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2969 | tsi_debug(EXIT, &pdev->dev, "exit"); |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2970 | } |
| 2971 | |
Alexandre Bounine | e3dd8cd | 2016-03-22 14:26:08 -0700 | [diff] [blame] | 2972 | static void tsi721_shutdown(struct pci_dev *pdev) |
| 2973 | { |
| 2974 | struct tsi721_device *priv = pci_get_drvdata(pdev); |
| 2975 | |
Alexandre Bounine | 72d8a0d | 2016-03-22 14:26:56 -0700 | [diff] [blame] | 2976 | tsi_debug(EXIT, &pdev->dev, "enter"); |
Alexandre Bounine | e3dd8cd | 2016-03-22 14:26:08 -0700 | [diff] [blame] | 2977 | |
| 2978 | tsi721_disable_ints(priv); |
| 2979 | tsi721_dma_stop_all(priv); |
| 2980 | pci_clear_master(pdev); |
| 2981 | pci_disable_device(pdev); |
| 2982 | } |
| 2983 | |
Benoit Taine | 9baa3c3 | 2014-08-08 15:56:03 +0200 | [diff] [blame] | 2984 | static const struct pci_device_id tsi721_pci_tbl[] = { |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2985 | { PCI_DEVICE(PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_TSI721) }, |
| 2986 | { 0, } /* terminate list */ |
| 2987 | }; |
| 2988 | |
| 2989 | MODULE_DEVICE_TABLE(pci, tsi721_pci_tbl); |
| 2990 | |
| 2991 | static struct pci_driver tsi721_driver = { |
| 2992 | .name = "tsi721", |
| 2993 | .id_table = tsi721_pci_tbl, |
| 2994 | .probe = tsi721_probe, |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2995 | .remove = tsi721_remove, |
Alexandre Bounine | e3dd8cd | 2016-03-22 14:26:08 -0700 | [diff] [blame] | 2996 | .shutdown = tsi721_shutdown, |
Alexandre Bounine | 48618fb | 2011-11-02 13:39:09 -0700 | [diff] [blame] | 2997 | }; |
| 2998 | |
Alexandre Bounine | 748353c | 2016-03-22 14:26:23 -0700 | [diff] [blame] | 2999 | module_pci_driver(tsi721_driver); |
Alexandre Bounine | 94d9bd4 | 2013-07-03 15:08:55 -0700 | [diff] [blame] | 3000 | |
| 3001 | MODULE_DESCRIPTION("IDT Tsi721 PCIExpress-to-SRIO bridge driver"); |
| 3002 | MODULE_AUTHOR("Integrated Device Technology, Inc."); |
| 3003 | MODULE_LICENSE("GPL"); |