Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> |
| 3 | * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> |
| 4 | * |
| 5 | * Permission to use, copy, modify, and distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #ifndef _ATH5K_H |
| 19 | #define _ATH5K_H |
| 20 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 21 | /* TODO: Clean up channel debuging -doesn't work anyway- and start |
| 22 | * working on reg. control code using all available eeprom information |
| 23 | * -rev. engineering needed- */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 24 | #define CHAN_DEBUG 0 |
| 25 | |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/types.h> |
Bruno Randolf | eef39be | 2010-11-16 10:58:43 +0900 | [diff] [blame] | 28 | #include <linux/average.h> |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 29 | #include <net/mac80211.h> |
| 30 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 31 | /* RX/TX descriptor hw structs |
| 32 | * TODO: Driver part should only see sw structs */ |
| 33 | #include "desc.h" |
| 34 | |
| 35 | /* EEPROM structs/offsets |
| 36 | * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) |
| 37 | * and clean up common bits, then introduce set/get functions in eeprom.c */ |
| 38 | #include "eeprom.h" |
Luis R. Rodriguez | db71971 | 2009-09-10 11:20:57 -0700 | [diff] [blame] | 39 | #include "../ath.h" |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 40 | |
| 41 | /* PCI IDs */ |
| 42 | #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ |
| 43 | #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ |
| 44 | #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ |
| 45 | #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ |
| 46 | #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ |
| 47 | #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ |
| 48 | #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ |
| 49 | #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ |
| 50 | #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ |
| 51 | #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ |
| 52 | #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ |
| 53 | #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ |
| 54 | #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ |
| 55 | #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ |
| 56 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ |
| 57 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ |
| 58 | #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ |
| 59 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ |
| 60 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ |
| 61 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ |
| 62 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ |
| 63 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ |
| 64 | #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ |
| 65 | #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ |
| 66 | #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ |
| 67 | #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ |
| 68 | #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ |
| 69 | #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ |
| 70 | |
| 71 | /****************************\ |
| 72 | GENERIC DRIVER DEFINITIONS |
| 73 | \****************************/ |
| 74 | |
| 75 | #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) |
| 76 | |
| 77 | #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ |
| 78 | printk(_level "ath5k %s: " _fmt, \ |
| 79 | ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ |
| 80 | ##__VA_ARGS__) |
| 81 | |
| 82 | #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ |
| 83 | if (net_ratelimit()) \ |
| 84 | ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ |
| 85 | } while (0) |
| 86 | |
| 87 | #define ATH5K_INFO(_sc, _fmt, ...) \ |
| 88 | ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) |
| 89 | |
| 90 | #define ATH5K_WARN(_sc, _fmt, ...) \ |
| 91 | ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) |
| 92 | |
| 93 | #define ATH5K_ERR(_sc, _fmt, ...) \ |
| 94 | ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) |
| 95 | |
| 96 | /* |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 97 | * AR5K REGISTER ACCESS |
| 98 | */ |
| 99 | |
| 100 | /* Some macros to read/write fields */ |
| 101 | |
| 102 | /* First shift, then mask */ |
| 103 | #define AR5K_REG_SM(_val, _flags) \ |
| 104 | (((_val) << _flags##_S) & (_flags)) |
| 105 | |
| 106 | /* First mask, then shift */ |
| 107 | #define AR5K_REG_MS(_val, _flags) \ |
| 108 | (((_val) & (_flags)) >> _flags##_S) |
| 109 | |
| 110 | /* Some registers can hold multiple values of interest. For this |
| 111 | * reason when we want to write to these registers we must first |
| 112 | * retrieve the values which we do not want to clear (lets call this |
| 113 | * old_data) and then set the register with this and our new_value: |
| 114 | * ( old_data | new_value) */ |
| 115 | #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ |
| 116 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ |
| 117 | (((_val) << _flags##_S) & (_flags)), _reg) |
| 118 | |
| 119 | #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ |
| 120 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ |
| 121 | (_mask)) | (_flags), _reg) |
| 122 | |
| 123 | #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ |
| 124 | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) |
| 125 | |
| 126 | #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ |
| 127 | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) |
| 128 | |
| 129 | /* Access to PHY registers */ |
| 130 | #define AR5K_PHY_READ(ah, _reg) \ |
| 131 | ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) |
| 132 | |
| 133 | #define AR5K_PHY_WRITE(ah, _reg, _val) \ |
| 134 | ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) |
| 135 | |
| 136 | /* Access QCU registers per queue */ |
| 137 | #define AR5K_REG_READ_Q(ah, _reg, _queue) \ |
| 138 | (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ |
| 139 | |
| 140 | #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ |
| 141 | ath5k_hw_reg_write(ah, (1 << _queue), _reg) |
| 142 | |
| 143 | #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ |
| 144 | _reg |= 1 << _queue; \ |
| 145 | } while (0) |
| 146 | |
| 147 | #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ |
| 148 | _reg &= ~(1 << _queue); \ |
| 149 | } while (0) |
| 150 | |
| 151 | /* Used while writing initvals */ |
| 152 | #define AR5K_REG_WAIT(_i) do { \ |
| 153 | if (_i % 64) \ |
| 154 | udelay(1); \ |
| 155 | } while (0) |
| 156 | |
| 157 | /* Register dumps are done per operation mode */ |
| 158 | #define AR5K_INI_RFGAIN_5GHZ 0 |
| 159 | #define AR5K_INI_RFGAIN_2GHZ 1 |
| 160 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 161 | /* |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 162 | * Some tuneable values (these should be changeable by the user) |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 163 | * TODO: Make use of them and add more options OR use debug/configfs |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 164 | */ |
| 165 | #define AR5K_TUNE_DMA_BEACON_RESP 2 |
| 166 | #define AR5K_TUNE_SW_BEACON_RESP 10 |
| 167 | #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 |
| 168 | #define AR5K_TUNE_RADAR_ALERT false |
| 169 | #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 |
Nick Kossifidis | b612798 | 2010-08-15 13:03:11 -0400 | [diff] [blame] | 170 | #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 171 | #define AR5K_TUNE_REGISTER_TIMEOUT 20000 |
| 172 | /* Register for RSSI threshold has a mask of 0xff, so 255 seems to |
| 173 | * be the max value. */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 174 | #define AR5K_TUNE_RSSI_THRES 129 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 175 | /* This must be set when setting the RSSI threshold otherwise it can |
| 176 | * prevent a reset. If AR5K_RSSI_THR is read after writing to it |
| 177 | * the BMISS_THRES will be seen as 0, seems harware doesn't keep |
| 178 | * track of it. Max value depends on harware. For AR5210 this is just 7. |
| 179 | * For AR5211+ this seems to be up to 255. */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 180 | #define AR5K_TUNE_BMISS_THRES 7 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 181 | #define AR5K_TUNE_REGISTER_DWELL_TIME 20000 |
| 182 | #define AR5K_TUNE_BEACON_INTERVAL 100 |
| 183 | #define AR5K_TUNE_AIFS 2 |
| 184 | #define AR5K_TUNE_AIFS_11B 2 |
| 185 | #define AR5K_TUNE_AIFS_XR 0 |
| 186 | #define AR5K_TUNE_CWMIN 15 |
| 187 | #define AR5K_TUNE_CWMIN_11B 31 |
| 188 | #define AR5K_TUNE_CWMIN_XR 3 |
| 189 | #define AR5K_TUNE_CWMAX 1023 |
| 190 | #define AR5K_TUNE_CWMAX_11B 1023 |
| 191 | #define AR5K_TUNE_CWMAX_XR 7 |
| 192 | #define AR5K_TUNE_NOISE_FLOOR -72 |
Bob Copeland | e5e2647 | 2009-10-14 14:16:30 -0400 | [diff] [blame] | 193 | #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 194 | #define AR5K_TUNE_MAX_TXPOWER 63 |
| 195 | #define AR5K_TUNE_DEFAULT_TXPOWER 25 |
| 196 | #define AR5K_TUNE_TPC_TXPOWER false |
Bruno Randolf | 1063b17 | 2010-03-25 14:49:03 +0900 | [diff] [blame] | 197 | #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ |
Bruno Randolf | 2111ac0 | 2010-04-02 18:44:08 +0900 | [diff] [blame] | 198 | #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ |
Bruno Randolf | afe8628 | 2010-05-19 10:31:10 +0900 | [diff] [blame] | 199 | #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 200 | |
Bruno Randolf | 4edd761 | 2010-09-17 11:36:56 +0900 | [diff] [blame] | 201 | #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ |
| 202 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 203 | #define AR5K_INIT_CARR_SENSE_EN 1 |
| 204 | |
| 205 | /*Swap RX/TX Descriptor for big endian archs*/ |
| 206 | #if defined(__BIG_ENDIAN) |
| 207 | #define AR5K_INIT_CFG ( \ |
| 208 | AR5K_CFG_SWTD | AR5K_CFG_SWRD \ |
| 209 | ) |
| 210 | #else |
| 211 | #define AR5K_INIT_CFG 0x00000000 |
| 212 | #endif |
| 213 | |
| 214 | /* Initial values */ |
Nick Kossifidis | e8f055f | 2009-02-09 06:12:58 +0200 | [diff] [blame] | 215 | #define AR5K_INIT_CYCRSSI_THR1 2 |
Nick Kossifidis | eeb8832 | 2010-11-23 21:19:45 +0200 | [diff] [blame] | 216 | |
| 217 | /* Tx retry limits */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 218 | #define AR5K_INIT_SH_RETRY 10 |
| 219 | #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY |
Nick Kossifidis | eeb8832 | 2010-11-23 21:19:45 +0200 | [diff] [blame] | 220 | /* For station mode */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 221 | #define AR5K_INIT_SSH_RETRY 32 |
| 222 | #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY |
| 223 | #define AR5K_INIT_TX_RETRY 10 |
| 224 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 225 | |
Nick Kossifidis | 3017fca | 2010-11-23 21:09:11 +0200 | [diff] [blame] | 226 | /* Slot time */ |
| 227 | #define AR5K_INIT_SLOT_TIME_TURBO 6 |
| 228 | #define AR5K_INIT_SLOT_TIME_DEFAULT 9 |
| 229 | #define AR5K_INIT_SLOT_TIME_HALF_RATE 13 |
| 230 | #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 |
| 231 | #define AR5K_INIT_SLOT_TIME_B 20 |
| 232 | #define AR5K_SLOT_TIME_MAX 0xffff |
| 233 | |
| 234 | /* SIFS */ |
| 235 | #define AR5K_INIT_SIFS_TURBO 6 |
| 236 | /* XXX: 8 from initvals 10 from standard */ |
| 237 | #define AR5K_INIT_SIFS_DEFAULT_BG 8 |
| 238 | #define AR5K_INIT_SIFS_DEFAULT_A 16 |
| 239 | #define AR5K_INIT_SIFS_HALF_RATE 32 |
| 240 | #define AR5K_INIT_SIFS_QUARTER_RATE 64 |
| 241 | |
Nick Kossifidis | 61cde03 | 2010-11-23 21:12:23 +0200 | [diff] [blame] | 242 | /* Used to calculate tx time for non 5/10/40MHz |
| 243 | * operation */ |
| 244 | /* It's preamble time + signal time (16 + 4) */ |
| 245 | #define AR5K_INIT_OFDM_PREAMPLE_TIME 20 |
| 246 | /* Preamble time for 40MHz (turbo) operation (min ?) */ |
| 247 | #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 |
| 248 | #define AR5K_INIT_OFDM_SYMBOL_TIME 4 |
| 249 | #define AR5K_INIT_OFDM_PLCP_BITS 22 |
| 250 | |
Nick Kossifidis | c297560 | 2010-11-23 21:00:37 +0200 | [diff] [blame] | 251 | /* Rx latency for 5 and 10MHz operation (max ?) */ |
| 252 | #define AR5K_INIT_RX_LAT_MAX 63 |
| 253 | /* Tx latencies from initvals (5212 only but no problem |
| 254 | * because we only tweak them on 5212) */ |
| 255 | #define AR5K_INIT_TX_LAT_A 54 |
| 256 | #define AR5K_INIT_TX_LAT_BG 384 |
| 257 | /* Tx latency for 40MHz (turbo) operation (min ?) */ |
| 258 | #define AR5K_INIT_TX_LAT_MIN 32 |
Nick Kossifidis | b405086 | 2010-11-23 21:04:43 +0200 | [diff] [blame] | 259 | /* Default Tx/Rx latencies (same for 5211)*/ |
| 260 | #define AR5K_INIT_TX_LATENCY_5210 54 |
| 261 | #define AR5K_INIT_RX_LATENCY_5210 29 |
Nick Kossifidis | c297560 | 2010-11-23 21:00:37 +0200 | [diff] [blame] | 262 | |
| 263 | /* Tx frame to Tx data start delay */ |
| 264 | #define AR5K_INIT_TXF2TXD_START_DEFAULT 14 |
| 265 | #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 |
| 266 | #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 |
| 267 | |
Nick Kossifidis | b405086 | 2010-11-23 21:04:43 +0200 | [diff] [blame] | 268 | /* We need to increase PHY switch and agc settling time |
| 269 | * on turbo mode */ |
| 270 | #define AR5K_SWITCH_SETTLING 5760 |
| 271 | #define AR5K_SWITCH_SETTLING_TURBO 7168 |
| 272 | |
| 273 | #define AR5K_AGC_SETTLING 28 |
| 274 | /* 38 on 5210 but shouldn't matter */ |
| 275 | #define AR5K_AGC_SETTLING_TURBO 37 |
Nick Kossifidis | c297560 | 2010-11-23 21:00:37 +0200 | [diff] [blame] | 276 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 277 | |
| 278 | /* GENERIC CHIPSET DEFINITIONS */ |
| 279 | |
| 280 | /* MAC Chips */ |
| 281 | enum ath5k_version { |
| 282 | AR5K_AR5210 = 0, |
| 283 | AR5K_AR5211 = 1, |
| 284 | AR5K_AR5212 = 2, |
| 285 | }; |
| 286 | |
| 287 | /* PHY Chips */ |
| 288 | enum ath5k_radio { |
| 289 | AR5K_RF5110 = 0, |
| 290 | AR5K_RF5111 = 1, |
| 291 | AR5K_RF5112 = 2, |
Nick Kossifidis | 8daeef9 | 2008-02-28 14:40:00 -0500 | [diff] [blame] | 292 | AR5K_RF2413 = 3, |
| 293 | AR5K_RF5413 = 4, |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 294 | AR5K_RF2316 = 5, |
| 295 | AR5K_RF2317 = 6, |
| 296 | AR5K_RF2425 = 7, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 297 | }; |
| 298 | |
| 299 | /* |
| 300 | * Common silicon revision/version values |
| 301 | */ |
| 302 | |
| 303 | enum ath5k_srev_type { |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 304 | AR5K_VERSION_MAC, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 305 | AR5K_VERSION_RAD, |
| 306 | }; |
| 307 | |
| 308 | struct ath5k_srev_name { |
| 309 | const char *sr_name; |
| 310 | enum ath5k_srev_type sr_type; |
| 311 | u_int sr_val; |
| 312 | }; |
| 313 | |
| 314 | #define AR5K_SREV_UNKNOWN 0xffff |
| 315 | |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 316 | #define AR5K_SREV_AR5210 0x00 /* Crete */ |
| 317 | #define AR5K_SREV_AR5311 0x10 /* Maui 1 */ |
| 318 | #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ |
| 319 | #define AR5K_SREV_AR5311B 0x30 /* Spirit */ |
| 320 | #define AR5K_SREV_AR5211 0x40 /* Oahu */ |
| 321 | #define AR5K_SREV_AR5212 0x50 /* Venice */ |
Bob Copeland | ca5efbe | 2009-08-27 15:17:15 -0400 | [diff] [blame] | 322 | #define AR5K_SREV_AR5212_V4 0x54 /* ??? */ |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 323 | #define AR5K_SREV_AR5213 0x55 /* ??? */ |
| 324 | #define AR5K_SREV_AR5213A 0x59 /* Hainan */ |
| 325 | #define AR5K_SREV_AR2413 0x78 /* Griffin lite */ |
| 326 | #define AR5K_SREV_AR2414 0x70 /* Griffin */ |
| 327 | #define AR5K_SREV_AR5424 0x90 /* Condor */ |
| 328 | #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ |
| 329 | #define AR5K_SREV_AR5414 0xa0 /* Eagle */ |
Nick Kossifidis | e8f055f | 2009-02-09 06:12:58 +0200 | [diff] [blame] | 330 | #define AR5K_SREV_AR2415 0xb0 /* Talon */ |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 331 | #define AR5K_SREV_AR5416 0xc0 /* PCI-E */ |
| 332 | #define AR5K_SREV_AR5418 0xca /* PCI-E */ |
| 333 | #define AR5K_SREV_AR2425 0xe0 /* Swan */ |
| 334 | #define AR5K_SREV_AR2417 0xf0 /* Nala */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 335 | |
| 336 | #define AR5K_SREV_RAD_5110 0x00 |
| 337 | #define AR5K_SREV_RAD_5111 0x10 |
| 338 | #define AR5K_SREV_RAD_5111A 0x15 |
| 339 | #define AR5K_SREV_RAD_2111 0x20 |
| 340 | #define AR5K_SREV_RAD_5112 0x30 |
| 341 | #define AR5K_SREV_RAD_5112A 0x35 |
Nick Kossifidis | e5a4ad0 | 2008-07-20 06:34:39 +0300 | [diff] [blame] | 342 | #define AR5K_SREV_RAD_5112B 0x36 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 343 | #define AR5K_SREV_RAD_2112 0x40 |
| 344 | #define AR5K_SREV_RAD_2112A 0x45 |
Nick Kossifidis | e5a4ad0 | 2008-07-20 06:34:39 +0300 | [diff] [blame] | 345 | #define AR5K_SREV_RAD_2112B 0x46 |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 346 | #define AR5K_SREV_RAD_2413 0x50 |
| 347 | #define AR5K_SREV_RAD_5413 0x60 |
Nick Kossifidis | e8f055f | 2009-02-09 06:12:58 +0200 | [diff] [blame] | 348 | #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 349 | #define AR5K_SREV_RAD_2317 0x80 |
| 350 | #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ |
| 351 | #define AR5K_SREV_RAD_2425 0xa2 |
| 352 | #define AR5K_SREV_RAD_5133 0xc0 |
| 353 | |
| 354 | #define AR5K_SREV_PHY_5211 0x30 |
| 355 | #define AR5K_SREV_PHY_5212 0x41 |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 356 | #define AR5K_SREV_PHY_5212A 0x42 |
Nick Kossifidis | e8f055f | 2009-02-09 06:12:58 +0200 | [diff] [blame] | 357 | #define AR5K_SREV_PHY_5212B 0x43 |
Nick Kossifidis | 1bef016 | 2008-09-29 02:09:09 +0300 | [diff] [blame] | 358 | #define AR5K_SREV_PHY_2413 0x45 |
| 359 | #define AR5K_SREV_PHY_5413 0x61 |
| 360 | #define AR5K_SREV_PHY_2425 0x70 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 361 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 362 | /* TODO add support to mac80211 for vendor-specific rates and modes */ |
| 363 | |
| 364 | /* |
| 365 | * Some of this information is based on Documentation from: |
| 366 | * |
Justin P. Mattock | 631dd1a | 2010-10-18 11:03:14 +0200 | [diff] [blame] | 367 | * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 368 | * |
| 369 | * Modulation for Atheros' eXtended Range - range enhancing extension that is |
| 370 | * supposed to double the distance an Atheros client device can keep a |
| 371 | * connection with an Atheros access point. This is achieved by increasing |
| 372 | * the receiver sensitivity up to, -105dBm, which is about 20dB above what |
| 373 | * the 802.11 specifications demand. In addition, new (proprietary) data rates |
| 374 | * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. |
| 375 | * |
| 376 | * Please note that can you either use XR or TURBO but you cannot use both, |
| 377 | * they are exclusive. |
| 378 | * |
| 379 | */ |
| 380 | #define MODULATION_XR 0x00000200 |
| 381 | /* |
| 382 | * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a |
| 383 | * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s |
| 384 | * signaling rate achieved through the bonding of two 54Mbit/s 802.11g |
| 385 | * channels. To use this feature your Access Point must also suport it. |
| 386 | * There is also a distinction between "static" and "dynamic" turbo modes: |
| 387 | * |
| 388 | * - Static: is the dumb version: devices set to this mode stick to it until |
| 389 | * the mode is turned off. |
| 390 | * - Dynamic: is the intelligent version, the network decides itself if it |
| 391 | * is ok to use turbo. As soon as traffic is detected on adjacent channels |
| 392 | * (which would get used in turbo mode), or when a non-turbo station joins |
| 393 | * the network, turbo mode won't be used until the situation changes again. |
| 394 | * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which |
| 395 | * monitors the used radio band in order to decide whether turbo mode may |
| 396 | * be used or not. |
| 397 | * |
| 398 | * This article claims Super G sticks to bonding of channels 5 and 6 for |
| 399 | * USA: |
| 400 | * |
| 401 | * http://www.pcworld.com/article/id,113428-page,1/article.html |
| 402 | * |
| 403 | * The channel bonding seems to be driver specific though. In addition to |
| 404 | * deciding what channels will be used, these "Turbo" modes are accomplished |
| 405 | * by also enabling the following features: |
| 406 | * |
| 407 | * - Bursting: allows multiple frames to be sent at once, rather than pausing |
| 408 | * after each frame. Bursting is a standards-compliant feature that can be |
| 409 | * used with any Access Point. |
| 410 | * - Fast frames: increases the amount of information that can be sent per |
| 411 | * frame, also resulting in a reduction of transmission overhead. It is a |
| 412 | * proprietary feature that needs to be supported by the Access Point. |
| 413 | * - Compression: data frames are compressed in real time using a Lempel Ziv |
| 414 | * algorithm. This is done transparently. Once this feature is enabled, |
| 415 | * compression and decompression takes place inside the chipset, without |
| 416 | * putting additional load on the host CPU. |
| 417 | * |
| 418 | */ |
| 419 | #define MODULATION_TURBO 0x00000080 |
| 420 | |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 421 | enum ath5k_driver_mode { |
| 422 | AR5K_MODE_11A = 0, |
Nick Kossifidis | 8c2b418 | 2010-11-23 21:51:38 +0200 | [diff] [blame] | 423 | AR5K_MODE_11B = 1, |
| 424 | AR5K_MODE_11G = 2, |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 425 | AR5K_MODE_XR = 0, |
Nick Kossifidis | 8c2b418 | 2010-11-23 21:51:38 +0200 | [diff] [blame] | 426 | AR5K_MODE_MAX = 3 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 427 | }; |
| 428 | |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 429 | enum ath5k_ant_mode { |
| 430 | AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ |
| 431 | AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ |
| 432 | AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ |
| 433 | AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ |
| 434 | AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ |
| 435 | AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ |
| 436 | AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ |
| 437 | AR5K_ANTMODE_MAX, |
| 438 | }; |
| 439 | |
Nick Kossifidis | fa3d2fe | 2010-11-23 20:58:34 +0200 | [diff] [blame] | 440 | enum ath5k_bw_mode { |
| 441 | AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ |
| 442 | AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ |
| 443 | AR5K_BWMODE_10MHZ = 2, /* Half rate */ |
| 444 | AR5K_BWMODE_40MHZ = 3 /* Turbo */ |
| 445 | }; |
Bruno Randolf | 19fd6e5 | 2008-03-05 18:35:23 +0900 | [diff] [blame] | 446 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 447 | /****************\ |
| 448 | TX DEFINITIONS |
| 449 | \****************/ |
| 450 | |
| 451 | /* |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 452 | * TX Status descriptor |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 453 | */ |
| 454 | struct ath5k_tx_status { |
| 455 | u16 ts_seqnum; |
| 456 | u16 ts_tstamp; |
| 457 | u8 ts_status; |
Felix Fietkau | 2f7fe87 | 2008-10-05 18:05:48 +0200 | [diff] [blame] | 458 | u8 ts_rate[4]; |
| 459 | u8 ts_retry[4]; |
| 460 | u8 ts_final_idx; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 461 | s8 ts_rssi; |
| 462 | u8 ts_shortretry; |
| 463 | u8 ts_longretry; |
| 464 | u8 ts_virtcol; |
| 465 | u8 ts_antenna; |
| 466 | }; |
| 467 | |
| 468 | #define AR5K_TXSTAT_ALTRATE 0x80 |
| 469 | #define AR5K_TXERR_XRETRY 0x01 |
| 470 | #define AR5K_TXERR_FILT 0x02 |
| 471 | #define AR5K_TXERR_FIFO 0x04 |
| 472 | |
| 473 | /** |
| 474 | * enum ath5k_tx_queue - Queue types used to classify tx queues. |
| 475 | * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue |
| 476 | * @AR5K_TX_QUEUE_DATA: A normal data queue |
| 477 | * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue |
| 478 | * @AR5K_TX_QUEUE_BEACON: The beacon queue |
| 479 | * @AR5K_TX_QUEUE_CAB: The after-beacon queue |
| 480 | * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue |
| 481 | */ |
| 482 | enum ath5k_tx_queue { |
| 483 | AR5K_TX_QUEUE_INACTIVE = 0, |
| 484 | AR5K_TX_QUEUE_DATA, |
| 485 | AR5K_TX_QUEUE_XR_DATA, |
| 486 | AR5K_TX_QUEUE_BEACON, |
| 487 | AR5K_TX_QUEUE_CAB, |
| 488 | AR5K_TX_QUEUE_UAPSD, |
| 489 | }; |
| 490 | |
| 491 | #define AR5K_NUM_TX_QUEUES 10 |
| 492 | #define AR5K_NUM_TX_QUEUES_NOQCU 2 |
| 493 | |
| 494 | /* |
| 495 | * Queue syb-types to classify normal data queues. |
| 496 | * These are the 4 Access Categories as defined in |
| 497 | * WME spec. 0 is the lowest priority and 4 is the |
| 498 | * highest. Normal data that hasn't been classified |
| 499 | * goes to the Best Effort AC. |
| 500 | */ |
| 501 | enum ath5k_tx_queue_subtype { |
| 502 | AR5K_WME_AC_BK = 0, /*Background traffic*/ |
| 503 | AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ |
| 504 | AR5K_WME_AC_VI, /*Video traffic*/ |
| 505 | AR5K_WME_AC_VO, /*Voice traffic*/ |
| 506 | }; |
| 507 | |
| 508 | /* |
| 509 | * Queue ID numbers as returned by the hw functions, each number |
| 510 | * represents a hw queue. If hw does not support hw queues |
| 511 | * (eg 5210) all data goes in one queue. These match |
| 512 | * d80211 definitions (net80211/MadWiFi don't use them). |
| 513 | */ |
| 514 | enum ath5k_tx_queue_id { |
| 515 | AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, |
| 516 | AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, |
| 517 | AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ |
| 518 | AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ |
| 519 | AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ |
| 520 | AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ |
| 521 | AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ |
| 522 | AR5K_TX_QUEUE_ID_UAPSD = 8, |
| 523 | AR5K_TX_QUEUE_ID_XR_DATA = 9, |
| 524 | }; |
| 525 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 526 | /* |
| 527 | * Flags to set hw queue's parameters... |
| 528 | */ |
| 529 | #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ |
| 530 | #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ |
| 531 | #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ |
| 532 | #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ |
| 533 | #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 534 | #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ |
| 535 | #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ |
| 536 | #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ |
| 537 | #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ |
| 538 | #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ |
| 539 | #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ |
| 540 | #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ |
| 541 | #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ |
| 542 | #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 543 | |
| 544 | /* |
| 545 | * A struct to hold tx queue's parameters |
| 546 | */ |
| 547 | struct ath5k_txq_info { |
| 548 | enum ath5k_tx_queue tqi_type; |
| 549 | enum ath5k_tx_queue_subtype tqi_subtype; |
| 550 | u16 tqi_flags; /* Tx queue flags (see above) */ |
Bruno Randolf | de8af45 | 2010-09-17 11:37:12 +0900 | [diff] [blame] | 551 | u8 tqi_aifs; /* Arbitrated Interframe Space */ |
| 552 | u16 tqi_cw_min; /* Minimum Contention Window */ |
| 553 | u16 tqi_cw_max; /* Maximum Contention Window */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 554 | u32 tqi_cbr_period; /* Constant bit rate period */ |
| 555 | u32 tqi_cbr_overflow_limit; |
| 556 | u32 tqi_burst_time; |
Bob Copeland | a951ae2 | 2010-01-20 23:51:04 -0500 | [diff] [blame] | 557 | u32 tqi_ready_time; /* Time queue waits after an event */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 558 | }; |
| 559 | |
| 560 | /* |
| 561 | * Transmit packet types. |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 562 | * used on tx control descriptor |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 563 | */ |
| 564 | enum ath5k_pkt_type { |
| 565 | AR5K_PKT_TYPE_NORMAL = 0, |
| 566 | AR5K_PKT_TYPE_ATIM = 1, |
| 567 | AR5K_PKT_TYPE_PSPOLL = 2, |
| 568 | AR5K_PKT_TYPE_BEACON = 3, |
| 569 | AR5K_PKT_TYPE_PROBE_RESP = 4, |
| 570 | AR5K_PKT_TYPE_PIFS = 5, |
| 571 | }; |
| 572 | |
| 573 | /* |
| 574 | * TX power and TPC settings |
| 575 | */ |
| 576 | #define AR5K_TXPOWER_OFDM(_r, _v) ( \ |
| 577 | ((0 & 1) << ((_v) + 6)) | \ |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 578 | (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 579 | ) |
| 580 | |
| 581 | #define AR5K_TXPOWER_CCK(_r, _v) ( \ |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 582 | (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 583 | ) |
| 584 | |
| 585 | /* |
Bruno Randolf | beade63 | 2010-06-16 19:11:25 +0900 | [diff] [blame] | 586 | * DMA size definitions (2^(n+2)) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 587 | */ |
| 588 | enum ath5k_dmasize { |
| 589 | AR5K_DMASIZE_4B = 0, |
| 590 | AR5K_DMASIZE_8B, |
| 591 | AR5K_DMASIZE_16B, |
| 592 | AR5K_DMASIZE_32B, |
| 593 | AR5K_DMASIZE_64B, |
| 594 | AR5K_DMASIZE_128B, |
| 595 | AR5K_DMASIZE_256B, |
| 596 | AR5K_DMASIZE_512B |
| 597 | }; |
| 598 | |
| 599 | |
| 600 | /****************\ |
| 601 | RX DEFINITIONS |
| 602 | \****************/ |
| 603 | |
| 604 | /* |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 605 | * RX Status descriptor |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 606 | */ |
| 607 | struct ath5k_rx_status { |
| 608 | u16 rs_datalen; |
| 609 | u16 rs_tstamp; |
| 610 | u8 rs_status; |
| 611 | u8 rs_phyerr; |
| 612 | s8 rs_rssi; |
| 613 | u8 rs_keyix; |
| 614 | u8 rs_rate; |
| 615 | u8 rs_antenna; |
| 616 | u8 rs_more; |
| 617 | }; |
| 618 | |
| 619 | #define AR5K_RXERR_CRC 0x01 |
| 620 | #define AR5K_RXERR_PHY 0x02 |
| 621 | #define AR5K_RXERR_FIFO 0x04 |
| 622 | #define AR5K_RXERR_DECRYPT 0x08 |
| 623 | #define AR5K_RXERR_MIC 0x10 |
| 624 | #define AR5K_RXKEYIX_INVALID ((u8) - 1) |
| 625 | #define AR5K_TXKEYIX_INVALID ((u32) - 1) |
| 626 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 627 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 628 | /**************************\ |
| 629 | BEACON TIMERS DEFINITIONS |
| 630 | \**************************/ |
| 631 | |
| 632 | #define AR5K_BEACON_PERIOD 0x0000ffff |
| 633 | #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ |
| 634 | #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ |
| 635 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 636 | |
| 637 | /* |
| 638 | * TSF to TU conversion: |
| 639 | * |
| 640 | * TSF is a 64bit value in usec (microseconds). |
Bruno Randolf | e535c1a | 2008-01-18 21:51:40 +0900 | [diff] [blame] | 641 | * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of |
| 642 | * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 643 | */ |
| 644 | #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) |
| 645 | |
| 646 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 647 | /*******************************\ |
| 648 | GAIN OPTIMIZATION DEFINITIONS |
| 649 | \*******************************/ |
| 650 | |
| 651 | enum ath5k_rfgain { |
| 652 | AR5K_RFGAIN_INACTIVE = 0, |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 653 | AR5K_RFGAIN_ACTIVE, |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 654 | AR5K_RFGAIN_READ_REQUESTED, |
| 655 | AR5K_RFGAIN_NEED_CHANGE, |
| 656 | }; |
| 657 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 658 | struct ath5k_gain { |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 659 | u8 g_step_idx; |
| 660 | u8 g_current; |
| 661 | u8 g_target; |
| 662 | u8 g_low; |
| 663 | u8 g_high; |
| 664 | u8 g_f_corr; |
| 665 | u8 g_state; |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 666 | }; |
| 667 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 668 | /********************\ |
| 669 | COMMON DEFINITIONS |
| 670 | \********************/ |
| 671 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 672 | #define AR5K_SLOT_TIME_9 396 |
| 673 | #define AR5K_SLOT_TIME_20 880 |
| 674 | #define AR5K_SLOT_TIME_MAX 0xffff |
| 675 | |
| 676 | /* channel_flags */ |
| 677 | #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 678 | #define CHANNEL_CCK 0x0020 /* CCK channel */ |
| 679 | #define CHANNEL_OFDM 0x0040 /* OFDM channel */ |
| 680 | #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ |
| 681 | #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ |
| 682 | #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ |
| 683 | #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ |
| 684 | #define CHANNEL_XR 0x0800 /* XR channel */ |
| 685 | |
| 686 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
| 687 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
| 688 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 689 | #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) |
| 690 | |
Nick Kossifidis | acb091d | 2010-11-23 21:49:53 +0200 | [diff] [blame] | 691 | #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 692 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 693 | #define CHANNEL_MODES CHANNEL_ALL |
| 694 | |
| 695 | /* |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 696 | * Used internaly for reset_tx_queue). |
| 697 | * Also see struct struct ieee80211_channel. |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 698 | */ |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 699 | #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) |
| 700 | #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 701 | |
| 702 | /* |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 703 | * The following structure is used to map 2GHz channels to |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 704 | * 5GHz Atheros channels. |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 705 | * TODO: Clean up |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 706 | */ |
| 707 | struct ath5k_athchan_2ghz { |
| 708 | u32 a2_flags; |
| 709 | u16 a2_athchan; |
| 710 | }; |
| 711 | |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 712 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 713 | /******************\ |
| 714 | RATE DEFINITIONS |
| 715 | \******************/ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 716 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 717 | /** |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 718 | * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 719 | * |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 720 | * The rate code is used to get the RX rate or set the TX rate on the |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 721 | * hardware descriptors. It is also used for internal modulation control |
| 722 | * and settings. |
| 723 | * |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 724 | * This is the hardware rate map we are aware of: |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 725 | * |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 726 | * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 727 | * rate_kbps 3000 1000 ? ? ? 2000 500 48000 |
| 728 | * |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 729 | * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 730 | * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? |
| 731 | * |
| 732 | * rate_code 17 18 19 20 21 22 23 24 |
| 733 | * rate_kbps ? ? ? ? ? ? ? 11000 |
| 734 | * |
| 735 | * rate_code 25 26 27 28 29 30 31 32 |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 736 | * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 737 | * |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 738 | * "S" indicates CCK rates with short preamble. |
| 739 | * |
| 740 | * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the |
| 741 | * lowest 4 bits, so they are the same as below with a 0xF mask. |
| 742 | * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). |
| 743 | * We handle this in ath5k_setup_bands(). |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 744 | */ |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 745 | #define AR5K_MAX_RATES 32 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 746 | |
Bruno Randolf | 63266a6 | 2008-07-30 17:12:58 +0200 | [diff] [blame] | 747 | /* B */ |
| 748 | #define ATH5K_RATE_CODE_1M 0x1B |
| 749 | #define ATH5K_RATE_CODE_2M 0x1A |
| 750 | #define ATH5K_RATE_CODE_5_5M 0x19 |
| 751 | #define ATH5K_RATE_CODE_11M 0x18 |
| 752 | /* A and G */ |
| 753 | #define ATH5K_RATE_CODE_6M 0x0B |
| 754 | #define ATH5K_RATE_CODE_9M 0x0F |
| 755 | #define ATH5K_RATE_CODE_12M 0x0A |
| 756 | #define ATH5K_RATE_CODE_18M 0x0E |
| 757 | #define ATH5K_RATE_CODE_24M 0x09 |
| 758 | #define ATH5K_RATE_CODE_36M 0x0D |
| 759 | #define ATH5K_RATE_CODE_48M 0x08 |
| 760 | #define ATH5K_RATE_CODE_54M 0x0C |
| 761 | /* XR */ |
| 762 | #define ATH5K_RATE_CODE_XR_500K 0x07 |
| 763 | #define ATH5K_RATE_CODE_XR_1M 0x02 |
| 764 | #define ATH5K_RATE_CODE_XR_2M 0x06 |
| 765 | #define ATH5K_RATE_CODE_XR_3M 0x01 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 766 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 767 | /* adding this flag to rate_code enables short preamble */ |
| 768 | #define AR5K_SET_SHORT_PREAMBLE 0x04 |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 769 | |
| 770 | /* |
| 771 | * Crypto definitions |
| 772 | */ |
| 773 | |
| 774 | #define AR5K_KEYCACHE_SIZE 8 |
| 775 | |
| 776 | /***********************\ |
| 777 | HW RELATED DEFINITIONS |
| 778 | \***********************/ |
| 779 | |
| 780 | /* |
| 781 | * Misc definitions |
| 782 | */ |
| 783 | #define AR5K_RSSI_EP_MULTIPLIER (1<<7) |
| 784 | |
| 785 | #define AR5K_ASSERT_ENTRY(_e, _s) do { \ |
| 786 | if (_e >= _s) \ |
| 787 | return (false); \ |
| 788 | } while (0) |
| 789 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 790 | /* |
| 791 | * Hardware interrupt abstraction |
| 792 | */ |
| 793 | |
| 794 | /** |
| 795 | * enum ath5k_int - Hardware interrupt masks helpers |
| 796 | * |
| 797 | * @AR5K_INT_RX: mask to identify received frame interrupts, of type |
| 798 | * AR5K_ISR_RXOK or AR5K_ISR_RXERR |
| 799 | * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) |
| 800 | * @AR5K_INT_RXNOFRM: No frame received (?) |
| 801 | * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The |
| 802 | * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's |
| 803 | * LinkPtr is NULL. For more details, refer to: |
| 804 | * http://www.freepatentsonline.com/20030225739.html |
| 805 | * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). |
| 806 | * Note that Rx overrun is not always fatal, on some chips we can continue |
| 807 | * operation without reseting the card, that's why int_fatal is not |
| 808 | * common for all chips. |
| 809 | * @AR5K_INT_TX: mask to identify received frame interrupts, of type |
| 810 | * AR5K_ISR_TXOK or AR5K_ISR_TXERR |
| 811 | * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) |
| 812 | * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold |
| 813 | * We currently do increments on interrupt by |
| 814 | * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 |
Bruno Randolf | 2111ac0 | 2010-04-02 18:44:08 +0900 | [diff] [blame] | 815 | * @AR5K_INT_MIB: Indicates the either Management Information Base counters or |
| 816 | * one of the PHY error counters reached the maximum value and should be |
| 817 | * read and cleared. |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 818 | * @AR5K_INT_RXPHY: RX PHY Error |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 819 | * @AR5K_INT_RXKCM: RX Key cache miss |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 820 | * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a |
| 821 | * beacon that must be handled in software. The alternative is if you |
| 822 | * have VEOL support, in that case you let the hardware deal with things. |
| 823 | * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing |
| 824 | * beacons from the AP have associated with, we should probably try to |
| 825 | * reassociate. When in IBSS mode this might mean we have not received |
| 826 | * any beacons from any local stations. Note that every station in an |
| 827 | * IBSS schedules to send beacons at the Target Beacon Transmission Time |
| 828 | * (TBTT) with a random backoff. |
| 829 | * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? |
| 830 | * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now |
| 831 | * until properly handled |
| 832 | * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA |
| 833 | * errors. These types of errors we can enable seem to be of type |
| 834 | * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 835 | * @AR5K_INT_GLOBAL: Used to clear and set the IER |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 836 | * @AR5K_INT_NOCARD: signals the card has been removed |
| 837 | * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same |
| 838 | * bit value |
| 839 | * |
| 840 | * These are mapped to take advantage of some common bits |
| 841 | * between the MACs, to be able to set intr properties |
| 842 | * easier. Some of them are not used yet inside hw.c. Most map |
| 843 | * to the respective hw interrupt value as they are common amogst different |
| 844 | * MACs. |
| 845 | */ |
| 846 | enum ath5k_int { |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 847 | AR5K_INT_RXOK = 0x00000001, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 848 | AR5K_INT_RXDESC = 0x00000002, |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 849 | AR5K_INT_RXERR = 0x00000004, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 850 | AR5K_INT_RXNOFRM = 0x00000008, |
| 851 | AR5K_INT_RXEOL = 0x00000010, |
| 852 | AR5K_INT_RXORN = 0x00000020, |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 853 | AR5K_INT_TXOK = 0x00000040, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 854 | AR5K_INT_TXDESC = 0x00000080, |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 855 | AR5K_INT_TXERR = 0x00000100, |
| 856 | AR5K_INT_TXNOFRM = 0x00000200, |
| 857 | AR5K_INT_TXEOL = 0x00000400, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 858 | AR5K_INT_TXURN = 0x00000800, |
| 859 | AR5K_INT_MIB = 0x00001000, |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 860 | AR5K_INT_SWI = 0x00002000, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 861 | AR5K_INT_RXPHY = 0x00004000, |
| 862 | AR5K_INT_RXKCM = 0x00008000, |
| 863 | AR5K_INT_SWBA = 0x00010000, |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 864 | AR5K_INT_BRSSI = 0x00020000, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 865 | AR5K_INT_BMISS = 0x00040000, |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 866 | AR5K_INT_FATAL = 0x00080000, /* Non common */ |
| 867 | AR5K_INT_BNR = 0x00100000, /* Non common */ |
| 868 | AR5K_INT_TIM = 0x00200000, /* Non common */ |
| 869 | AR5K_INT_DTIM = 0x00400000, /* Non common */ |
| 870 | AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ |
| 871 | AR5K_INT_GPIO = 0x01000000, |
| 872 | AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ |
| 873 | AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ |
| 874 | AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ |
| 875 | AR5K_INT_QCBRORN = 0x10000000, /* Non common */ |
| 876 | AR5K_INT_QCBRURN = 0x20000000, /* Non common */ |
| 877 | AR5K_INT_QTRIG = 0x40000000, /* Non common */ |
| 878 | AR5K_INT_GLOBAL = 0x80000000, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 879 | |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 880 | AR5K_INT_COMMON = AR5K_INT_RXOK |
| 881 | | AR5K_INT_RXDESC |
| 882 | | AR5K_INT_RXERR |
| 883 | | AR5K_INT_RXNOFRM |
| 884 | | AR5K_INT_RXEOL |
| 885 | | AR5K_INT_RXORN |
| 886 | | AR5K_INT_TXOK |
| 887 | | AR5K_INT_TXDESC |
| 888 | | AR5K_INT_TXERR |
| 889 | | AR5K_INT_TXNOFRM |
| 890 | | AR5K_INT_TXEOL |
| 891 | | AR5K_INT_TXURN |
| 892 | | AR5K_INT_MIB |
| 893 | | AR5K_INT_SWI |
| 894 | | AR5K_INT_RXPHY |
| 895 | | AR5K_INT_RXKCM |
| 896 | | AR5K_INT_SWBA |
| 897 | | AR5K_INT_BRSSI |
| 898 | | AR5K_INT_BMISS |
| 899 | | AR5K_INT_GPIO |
| 900 | | AR5K_INT_GLOBAL, |
| 901 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 902 | AR5K_INT_NOCARD = 0xffffffff |
| 903 | }; |
| 904 | |
Bruno Randolf | e65e1d7 | 2010-03-25 14:49:09 +0900 | [diff] [blame] | 905 | /* mask which calibration is active at the moment */ |
| 906 | enum ath5k_calibration_mask { |
| 907 | AR5K_CALIBRATION_FULL = 0x01, |
| 908 | AR5K_CALIBRATION_SHORT = 0x02, |
Bruno Randolf | 2111ac0 | 2010-04-02 18:44:08 +0900 | [diff] [blame] | 909 | AR5K_CALIBRATION_ANI = 0x04, |
Nick Kossifidis | 6e220662 | 2009-08-10 03:31:31 +0300 | [diff] [blame] | 910 | }; |
| 911 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 912 | /* |
| 913 | * Power management |
| 914 | */ |
| 915 | enum ath5k_power_mode { |
| 916 | AR5K_PM_UNDEFINED = 0, |
| 917 | AR5K_PM_AUTO, |
| 918 | AR5K_PM_AWAKE, |
| 919 | AR5K_PM_FULL_SLEEP, |
| 920 | AR5K_PM_NETWORK_SLEEP, |
| 921 | }; |
| 922 | |
| 923 | /* |
| 924 | * These match net80211 definitions (not used in |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 925 | * mac80211). |
| 926 | * TODO: Clean this up |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 927 | */ |
| 928 | #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ |
| 929 | #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ |
| 930 | #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ |
| 931 | #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ |
| 932 | #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ |
| 933 | |
| 934 | /* GPIO-controlled software LED */ |
| 935 | #define AR5K_SOFTLED_PIN 0 |
| 936 | #define AR5K_SOFTLED_ON 0 |
| 937 | #define AR5K_SOFTLED_OFF 1 |
| 938 | |
| 939 | /* |
| 940 | * Chipset capabilities -see ath5k_hw_get_capability- |
| 941 | * get_capability function is not yet fully implemented |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 942 | * in ath5k so most of these don't work yet... |
| 943 | * TODO: Implement these & merge with _TUNE_ stuff above |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 944 | */ |
| 945 | enum ath5k_capability_type { |
| 946 | AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ |
| 947 | AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ |
| 948 | AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ |
| 949 | AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ |
| 950 | AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ |
| 951 | AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ |
| 952 | AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ |
| 953 | AR5K_CAP_COMPRESSION = 8, /* Supports compression */ |
| 954 | AR5K_CAP_BURST = 9, /* Supports packet bursting */ |
| 955 | AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ |
| 956 | AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ |
| 957 | AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ |
| 958 | AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ |
| 959 | AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ |
| 960 | AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ |
| 961 | AR5K_CAP_XR = 16, /* Supports XR mode */ |
| 962 | AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ |
| 963 | AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ |
| 964 | AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ |
| 965 | AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ |
| 966 | }; |
| 967 | |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 968 | |
| 969 | /* XXX: we *may* move cap_range stuff to struct wiphy */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 970 | struct ath5k_capabilities { |
| 971 | /* |
| 972 | * Supported PHY modes |
| 973 | * (ie. CHANNEL_A, CHANNEL_B, ...) |
| 974 | */ |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 975 | DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 976 | |
| 977 | /* |
| 978 | * Frequency range (without regulation restrictions) |
| 979 | */ |
| 980 | struct { |
| 981 | u16 range_2ghz_min; |
| 982 | u16 range_2ghz_max; |
| 983 | u16 range_5ghz_min; |
| 984 | u16 range_5ghz_max; |
| 985 | } cap_range; |
| 986 | |
| 987 | /* |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 988 | * Values stored in the EEPROM (some of them...) |
| 989 | */ |
| 990 | struct ath5k_eeprom_info cap_eeprom; |
| 991 | |
| 992 | /* |
| 993 | * Queue information |
| 994 | */ |
| 995 | struct { |
| 996 | u8 q_tx_num; |
| 997 | } cap_queues; |
Bruno Randolf | a8c944f | 2010-03-25 14:49:47 +0900 | [diff] [blame] | 998 | |
| 999 | bool cap_has_phyerr_counters; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1000 | }; |
| 1001 | |
Bob Copeland | e5e2647 | 2009-10-14 14:16:30 -0400 | [diff] [blame] | 1002 | /* size of noise floor history (keep it a power of two) */ |
| 1003 | #define ATH5K_NF_CAL_HIST_MAX 8 |
| 1004 | struct ath5k_nfcal_hist |
| 1005 | { |
| 1006 | s16 index; /* current index into nfval */ |
| 1007 | s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ |
| 1008 | }; |
| 1009 | |
Bruno Randolf | b4ea449 | 2010-03-25 14:49:25 +0900 | [diff] [blame] | 1010 | /** |
| 1011 | * struct avg_val - Helper structure for average calculation |
| 1012 | * @avg: contains the actual average value |
| 1013 | * @avg_weight: is used internally during calculation to prevent rounding errors |
| 1014 | */ |
| 1015 | struct ath5k_avg_val { |
| 1016 | int avg; |
| 1017 | int avg_weight; |
| 1018 | }; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1019 | |
| 1020 | /***************************************\ |
| 1021 | HARDWARE ABSTRACTION LAYER STRUCTURE |
| 1022 | \***************************************/ |
| 1023 | |
| 1024 | /* |
| 1025 | * Misc defines |
| 1026 | */ |
| 1027 | |
| 1028 | #define AR5K_MAX_GPIO 10 |
| 1029 | #define AR5K_MAX_RF_BANKS 8 |
| 1030 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1031 | /* TODO: Clean up and merge with ath5k_softc */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1032 | struct ath5k_hw { |
Luis R. Rodriguez | db71971 | 2009-09-10 11:20:57 -0700 | [diff] [blame] | 1033 | struct ath_common common; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1034 | |
| 1035 | struct ath5k_softc *ah_sc; |
| 1036 | void __iomem *ah_iobase; |
| 1037 | |
| 1038 | enum ath5k_int ah_imr; |
| 1039 | |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 1040 | struct ieee80211_channel *ah_current_channel; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1041 | bool ah_calibration; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1042 | bool ah_single_chip; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1043 | |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 1044 | enum ath5k_version ah_version; |
| 1045 | enum ath5k_radio ah_radio; |
| 1046 | u32 ah_phy; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1047 | u32 ah_mac_srev; |
| 1048 | u16 ah_mac_version; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1049 | u16 ah_phy_revision; |
| 1050 | u16 ah_radio_5ghz_revision; |
| 1051 | u16 ah_radio_2ghz_revision; |
| 1052 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1053 | #define ah_modes ah_capabilities.cap_mode |
| 1054 | #define ah_ee_version ah_capabilities.cap_eeprom.ee_version |
| 1055 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1056 | u32 ah_limit_tx_retries; |
Lukáš Turek | 6e08d22 | 2009-12-21 22:50:51 +0100 | [diff] [blame] | 1057 | u8 ah_coverage_class; |
Nick Kossifidis | 61cde03 | 2010-11-23 21:12:23 +0200 | [diff] [blame] | 1058 | bool ah_ack_bitrate_high; |
Nick Kossifidis | fa3d2fe | 2010-11-23 20:58:34 +0200 | [diff] [blame] | 1059 | u8 ah_bwmode; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1060 | |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1061 | /* Antenna Control */ |
| 1062 | u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; |
| 1063 | u8 ah_ant_mode; |
| 1064 | u8 ah_tx_ant; |
| 1065 | u8 ah_def_ant; |
Bob Copeland | 46026e8 | 2009-06-10 22:22:20 -0400 | [diff] [blame] | 1066 | bool ah_software_retry; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1067 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1068 | struct ath5k_capabilities ah_capabilities; |
| 1069 | |
| 1070 | struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; |
| 1071 | u32 ah_txq_status; |
| 1072 | u32 ah_txq_imr_txok; |
| 1073 | u32 ah_txq_imr_txerr; |
| 1074 | u32 ah_txq_imr_txurn; |
| 1075 | u32 ah_txq_imr_txdesc; |
| 1076 | u32 ah_txq_imr_txeol; |
Nick Kossifidis | 4c674c6 | 2008-10-26 20:40:25 +0200 | [diff] [blame] | 1077 | u32 ah_txq_imr_cbrorn; |
| 1078 | u32 ah_txq_imr_cbrurn; |
| 1079 | u32 ah_txq_imr_qtrig; |
| 1080 | u32 ah_txq_imr_nofrm; |
| 1081 | u32 ah_txq_isr; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1082 | u32 *ah_rf_banks; |
| 1083 | size_t ah_rf_banks_size; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 1084 | size_t ah_rf_regs_count; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1085 | struct ath5k_gain ah_gain; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame] | 1086 | u8 ah_offset[AR5K_MAX_RF_BANKS]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1087 | |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1088 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1089 | struct { |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1090 | /* Temporary tables used for interpolation */ |
| 1091 | u8 tmpL[AR5K_EEPROM_N_PD_GAINS] |
| 1092 | [AR5K_EEPROM_POWER_TABLE_SIZE]; |
| 1093 | u8 tmpR[AR5K_EEPROM_N_PD_GAINS] |
| 1094 | [AR5K_EEPROM_POWER_TABLE_SIZE]; |
| 1095 | u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; |
| 1096 | u16 txp_rates_power_table[AR5K_MAX_RATES]; |
| 1097 | u8 txp_min_idx; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1098 | bool txp_tpc; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1099 | /* Values in 0.25dB units */ |
| 1100 | s16 txp_min_pwr; |
| 1101 | s16 txp_max_pwr; |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 1102 | /* Values in 0.5dB units */ |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1103 | s16 txp_offset; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1104 | s16 txp_ofdm; |
Nick Kossifidis | 8f655dd | 2009-03-15 22:20:35 +0200 | [diff] [blame] | 1105 | s16 txp_cck_ofdm_gainf_delta; |
Nick Kossifidis | a082381 | 2009-04-30 15:55:44 -0400 | [diff] [blame] | 1106 | /* Value in dB units */ |
| 1107 | s16 txp_cck_ofdm_pwr_delta; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1108 | } ah_txpower; |
| 1109 | |
| 1110 | struct { |
| 1111 | bool r_enabled; |
| 1112 | int r_last_alert; |
| 1113 | struct ieee80211_channel r_last_channel; |
| 1114 | } ah_radar; |
| 1115 | |
Bob Copeland | e5e2647 | 2009-10-14 14:16:30 -0400 | [diff] [blame] | 1116 | struct ath5k_nfcal_hist ah_nfcal_hist; |
| 1117 | |
Bruno Randolf | b4ea449 | 2010-03-25 14:49:25 +0900 | [diff] [blame] | 1118 | /* average beacon RSSI in our BSS (used by ANI) */ |
Bruno Randolf | eef39be | 2010-11-16 10:58:43 +0900 | [diff] [blame] | 1119 | struct ewma ah_beacon_rssi_avg; |
Bruno Randolf | b4ea449 | 2010-03-25 14:49:25 +0900 | [diff] [blame] | 1120 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1121 | /* noise floor from last periodic calibration */ |
| 1122 | s32 ah_noise_floor; |
| 1123 | |
Nick Kossifidis | 6e220662 | 2009-08-10 03:31:31 +0300 | [diff] [blame] | 1124 | /* Calibration timestamp */ |
Bruno Randolf | a9167f9 | 2010-03-25 14:49:14 +0900 | [diff] [blame] | 1125 | unsigned long ah_cal_next_full; |
Bruno Randolf | 2111ac0 | 2010-04-02 18:44:08 +0900 | [diff] [blame] | 1126 | unsigned long ah_cal_next_ani; |
Bruno Randolf | afe8628 | 2010-05-19 10:31:10 +0900 | [diff] [blame] | 1127 | unsigned long ah_cal_next_nf; |
Nick Kossifidis | 6e220662 | 2009-08-10 03:31:31 +0300 | [diff] [blame] | 1128 | |
Bruno Randolf | e65e1d7 | 2010-03-25 14:49:09 +0900 | [diff] [blame] | 1129 | /* Calibration mask */ |
| 1130 | u8 ah_cal_mask; |
Nick Kossifidis | 6e220662 | 2009-08-10 03:31:31 +0300 | [diff] [blame] | 1131 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1132 | /* |
| 1133 | * Function pointers |
| 1134 | */ |
| 1135 | int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, |
Benoit Papillault | 8127fbd | 2010-02-27 23:05:26 +0100 | [diff] [blame] | 1136 | unsigned int, unsigned int, int, enum ath5k_pkt_type, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1137 | unsigned int, unsigned int, unsigned int, unsigned int, |
Benoit Papillault | 8127fbd | 2010-02-27 23:05:26 +0100 | [diff] [blame] | 1138 | unsigned int, unsigned int, unsigned int, unsigned int); |
Bruno Randolf | b47f407 | 2008-03-05 18:35:45 +0900 | [diff] [blame] | 1139 | int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, |
| 1140 | struct ath5k_tx_status *); |
| 1141 | int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, |
| 1142 | struct ath5k_rx_status *); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1143 | }; |
| 1144 | |
| 1145 | /* |
| 1146 | * Prototypes |
| 1147 | */ |
Felix Fietkau | e5b046d | 2010-12-02 10:27:01 +0100 | [diff] [blame^] | 1148 | extern const struct ieee80211_ops ath5k_hw_ops; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1149 | |
Felix Fietkau | 132b1c3 | 2010-12-02 10:26:56 +0100 | [diff] [blame] | 1150 | /* Initialization and detach functions */ |
| 1151 | int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops); |
| 1152 | void ath5k_deinit_softc(struct ath5k_softc *sc); |
| 1153 | int ath5k_hw_init(struct ath5k_softc *sc); |
| 1154 | void ath5k_hw_deinit(struct ath5k_hw *ah); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1155 | |
Bruno Randolf | 40ca22e | 2010-05-19 10:31:32 +0900 | [diff] [blame] | 1156 | int ath5k_sysfs_register(struct ath5k_softc *sc); |
| 1157 | void ath5k_sysfs_unregister(struct ath5k_softc *sc); |
| 1158 | |
Felix Fietkau | e5b046d | 2010-12-02 10:27:01 +0100 | [diff] [blame^] | 1159 | /*Chip id helper function */ |
| 1160 | const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1161 | |
Bob Copeland | 0ed4548 | 2009-03-08 00:10:20 -0500 | [diff] [blame] | 1162 | /* LED functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1163 | int ath5k_init_leds(struct ath5k_softc *sc); |
| 1164 | void ath5k_led_enable(struct ath5k_softc *sc); |
| 1165 | void ath5k_led_off(struct ath5k_softc *sc); |
| 1166 | void ath5k_unregister_leds(struct ath5k_softc *sc); |
Bob Copeland | 0ed4548 | 2009-03-08 00:10:20 -0500 | [diff] [blame] | 1167 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1168 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1169 | /* Reset Functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1170 | int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); |
| 1171 | int ath5k_hw_on_hold(struct ath5k_hw *ah); |
| 1172 | int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, |
Nick Kossifidis | 8aec7af | 2010-11-23 21:39:28 +0200 | [diff] [blame] | 1173 | struct ieee80211_channel *channel, bool fast, bool skip_pcu); |
Pavel Roskin | ec182d9 | 2010-02-18 20:28:41 -0500 | [diff] [blame] | 1174 | int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, |
| 1175 | bool is_set); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1176 | /* Power management functions */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1177 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1178 | |
| 1179 | /* Clock rate related functions */ |
| 1180 | unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); |
| 1181 | unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); |
| 1182 | void ath5k_hw_set_clockrate(struct ath5k_hw *ah); |
| 1183 | |
| 1184 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1185 | /* DMA Related Functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1186 | void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1187 | u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); |
Nick Kossifidis | e8325ed | 2010-11-23 20:52:24 +0200 | [diff] [blame] | 1188 | int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1189 | int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); |
Nick Kossifidis | 14fae2d | 2010-11-23 20:55:17 +0200 | [diff] [blame] | 1190 | int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1191 | u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); |
| 1192 | int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1193 | u32 phys_addr); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1194 | int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1195 | /* Interrupt handling */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1196 | bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); |
| 1197 | int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); |
| 1198 | enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); |
Bruno Randolf | 495391d | 2010-03-25 14:49:36 +0900 | [diff] [blame] | 1199 | void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); |
Nick Kossifidis | d41174f | 2010-11-23 20:41:15 +0200 | [diff] [blame] | 1200 | /* Init/Stop functions */ |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1201 | void ath5k_hw_dma_init(struct ath5k_hw *ah); |
Nick Kossifidis | d41174f | 2010-11-23 20:41:15 +0200 | [diff] [blame] | 1202 | int ath5k_hw_dma_stop(struct ath5k_hw *ah); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1203 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1204 | /* EEPROM access functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1205 | int ath5k_eeprom_init(struct ath5k_hw *ah); |
| 1206 | void ath5k_eeprom_detach(struct ath5k_hw *ah); |
| 1207 | int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1208 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1209 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1210 | /* Protocol Control Unit Functions */ |
Nick Kossifidis | eeb8832 | 2010-11-23 21:19:45 +0200 | [diff] [blame] | 1211 | /* Helpers */ |
| 1212 | int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, |
| 1213 | int len, struct ieee80211_rate *rate); |
Nick Kossifidis | 71ba1c3 | 2010-11-23 21:24:54 +0200 | [diff] [blame] | 1214 | unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); |
Nick Kossifidis | eeb8832 | 2010-11-23 21:19:45 +0200 | [diff] [blame] | 1215 | unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); |
Bruno Randolf | ccfe555 | 2010-03-09 16:55:38 +0900 | [diff] [blame] | 1216 | extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1217 | void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1218 | /* RX filter control*/ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1219 | int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); |
Nick Kossifidis | 418de6d | 2010-08-15 13:03:10 -0400 | [diff] [blame] | 1220 | void ath5k_hw_set_bssid(struct ath5k_hw *ah); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1221 | void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1222 | void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); |
| 1223 | u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); |
| 1224 | void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1225 | /* Receive (DRU) start/stop functions */ |
| 1226 | void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); |
| 1227 | void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1228 | /* Beacon control functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1229 | u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); |
| 1230 | void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); |
| 1231 | void ath5k_hw_reset_tsf(struct ath5k_hw *ah); |
| 1232 | void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); |
Bruno Randolf | 7f89612 | 2010-09-27 12:22:21 +0900 | [diff] [blame] | 1233 | bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1234 | /* Init function */ |
| 1235 | void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, |
| 1236 | u8 mode); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1237 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1238 | /* Queue Control Unit, DFS Control Unit Functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1239 | int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, |
| 1240 | struct ath5k_txq_info *queue_info); |
| 1241 | int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, |
| 1242 | const struct ath5k_txq_info *queue_info); |
| 1243 | int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, |
| 1244 | enum ath5k_tx_queue queue_type, |
| 1245 | struct ath5k_txq_info *queue_info); |
| 1246 | u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); |
| 1247 | void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); |
| 1248 | int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); |
Nick Kossifidis | eeb8832 | 2010-11-23 21:19:45 +0200 | [diff] [blame] | 1249 | int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1250 | /* Init function */ |
| 1251 | int ath5k_hw_init_queues(struct ath5k_hw *ah); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1252 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1253 | /* Hardware Descriptor Functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1254 | int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); |
Bruno Randolf | a666819 | 2010-06-16 19:12:01 +0900 | [diff] [blame] | 1255 | int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, |
| 1256 | u32 size, unsigned int flags); |
| 1257 | int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, |
| 1258 | unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, |
| 1259 | u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1260 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1261 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1262 | /* GPIO Functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1263 | void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); |
| 1264 | int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); |
| 1265 | int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); |
| 1266 | u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); |
| 1267 | int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); |
| 1268 | void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, |
| 1269 | u32 interrupt_level); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1270 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1271 | |
| 1272 | /* RFkill Functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1273 | void ath5k_rfkill_hw_start(struct ath5k_hw *ah); |
| 1274 | void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); |
Tobias Doerffel | e6a3b61 | 2009-06-09 17:33:27 +0200 | [diff] [blame] | 1275 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1276 | |
| 1277 | /* Misc functions TODO: Cleanup */ |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1278 | int ath5k_hw_set_capabilities(struct ath5k_hw *ah); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1279 | int ath5k_hw_get_capability(struct ath5k_hw *ah, |
| 1280 | enum ath5k_capability_type cap_type, u32 capability, |
| 1281 | u32 *result); |
| 1282 | int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); |
| 1283 | int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1284 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1285 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1286 | /* Initial register settings functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1287 | int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1288 | |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1289 | |
| 1290 | /* PHY functions */ |
| 1291 | /* Misc PHY functions */ |
| 1292 | u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); |
| 1293 | int ath5k_hw_phy_disable(struct ath5k_hw *ah); |
| 1294 | /* Gain_F optimization */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1295 | enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); |
| 1296 | int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1297 | /* PHY/RF channel functions */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1298 | bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1299 | /* PHY calibration */ |
Bob Copeland | e5e2647 | 2009-10-14 14:16:30 -0400 | [diff] [blame] | 1300 | void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1301 | int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, |
| 1302 | struct ieee80211_channel *channel); |
Bruno Randolf | 9e04a7e | 2010-05-19 10:31:00 +0900 | [diff] [blame] | 1303 | void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); |
Nick Kossifidis | 57e6c56 | 2009-04-30 15:55:50 -0400 | [diff] [blame] | 1304 | /* Spur mitigation */ |
| 1305 | bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1306 | struct ieee80211_channel *channel); |
Nick Kossifidis | 2bed03e | 2009-04-30 15:55:49 -0400 | [diff] [blame] | 1307 | /* Antenna control */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1308 | void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); |
Bruno Randolf | 0ca7402 | 2010-06-07 13:11:30 +0900 | [diff] [blame] | 1309 | void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1310 | /* TX power setup */ |
Pavel Roskin | a25d1e4 | 2010-02-18 20:28:23 -0500 | [diff] [blame] | 1311 | int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); |
Nick Kossifidis | 9320b5c4 | 2010-11-23 20:36:45 +0200 | [diff] [blame] | 1312 | /* Init function */ |
| 1313 | int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, |
Nick Kossifidis | 8aec7af | 2010-11-23 21:39:28 +0200 | [diff] [blame] | 1314 | u8 mode, u8 ee_mode, u8 freq, bool fast); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1315 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1316 | /* |
| 1317 | * Functions used internaly |
| 1318 | */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1319 | |
Luis R. Rodriguez | e5aa847 | 2009-09-10 16:55:11 -0700 | [diff] [blame] | 1320 | static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) |
| 1321 | { |
| 1322 | return &ah->common; |
| 1323 | } |
| 1324 | |
| 1325 | static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) |
| 1326 | { |
| 1327 | return &(ath5k_hw_common(ah)->regulatory); |
| 1328 | } |
| 1329 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1330 | static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) |
| 1331 | { |
| 1332 | return ioread32(ah->ah_iobase + reg); |
| 1333 | } |
| 1334 | |
| 1335 | static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) |
| 1336 | { |
| 1337 | iowrite32(val, ah->ah_iobase + reg); |
| 1338 | } |
| 1339 | |
Felix Fietkau | 132b1c3 | 2010-12-02 10:26:56 +0100 | [diff] [blame] | 1340 | static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) |
| 1341 | { |
| 1342 | common->bus_ops->read_cachesize(common, csz); |
| 1343 | } |
| 1344 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1345 | static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) |
| 1346 | { |
| 1347 | u32 retval = 0, bit, i; |
| 1348 | |
| 1349 | for (i = 0; i < bits; i++) { |
| 1350 | bit = (val >> i) & 1; |
| 1351 | retval = (retval << 1) | bit; |
| 1352 | } |
| 1353 | |
| 1354 | return retval; |
| 1355 | } |
| 1356 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1357 | #endif |