Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xor offload engine api |
| 3 | * |
| 4 | * Copyright © 2006, Intel Corporation. |
| 5 | * |
| 6 | * Dan Williams <dan.j.williams@intel.com> |
| 7 | * |
| 8 | * with architecture considerations by: |
| 9 | * Neil Brown <neilb@suse.de> |
| 10 | * Jeff Garzik <jeff@garzik.org> |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms and conditions of the GNU General Public License, |
| 14 | * version 2, as published by the Free Software Foundation. |
| 15 | * |
| 16 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 19 | * more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License along with |
| 22 | * this program; if not, write to the Free Software Foundation, Inc., |
| 23 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 24 | * |
| 25 | */ |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/interrupt.h> |
Paul Gortmaker | 4bb33cc | 2011-05-27 14:41:48 -0400 | [diff] [blame] | 28 | #include <linux/module.h> |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 29 | #include <linux/mm.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/raid/xor.h> |
| 32 | #include <linux/async_tx.h> |
| 33 | |
Dan Williams | 06164f3 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 34 | /* do_async_xor - dma map the pages and perform the xor with an engine */ |
| 35 | static __async_inline struct dma_async_tx_descriptor * |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 36 | do_async_xor(struct dma_chan *chan, struct dmaengine_unmap_data *unmap, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 37 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 38 | { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 39 | struct dma_device *dma = chan->device; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 40 | struct dma_async_tx_descriptor *tx = NULL; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 41 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
| 42 | void *cb_param_orig = submit->cb_param; |
| 43 | enum async_tx_flags flags_orig = submit->flags; |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 44 | enum dma_ctrl_flags dma_flags = 0; |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 45 | int src_cnt = unmap->to_cnt; |
| 46 | int xor_src_cnt; |
| 47 | dma_addr_t dma_dest = unmap->addr[unmap->to_cnt]; |
| 48 | dma_addr_t *src_list = unmap->addr; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 49 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 50 | while (src_cnt) { |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 51 | dma_addr_t tmp; |
| 52 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 53 | submit->flags = flags_orig; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 54 | xor_src_cnt = min(src_cnt, (int)dma->max_xor); |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 55 | /* if we are submitting additional xors, leave the chain open |
| 56 | * and clear the callback parameters |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 57 | */ |
| 58 | if (src_cnt > xor_src_cnt) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 59 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 60 | submit->flags |= ASYNC_TX_FENCE; |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 61 | submit->cb_fn = NULL; |
| 62 | submit->cb_param = NULL; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 63 | } else { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 64 | submit->cb_fn = cb_fn_orig; |
| 65 | submit->cb_param = cb_param_orig; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 66 | } |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 67 | if (submit->cb_fn) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 68 | dma_flags |= DMA_PREP_INTERRUPT; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 69 | if (submit->flags & ASYNC_TX_FENCE) |
| 70 | dma_flags |= DMA_PREP_FENCE; |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 71 | |
| 72 | /* Drivers force forward progress in case they can not provide a |
| 73 | * descriptor |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 74 | */ |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 75 | tmp = src_list[0]; |
| 76 | if (src_list > unmap->addr) |
| 77 | src_list[0] = dma_dest; |
| 78 | tx = dma->device_prep_dma_xor(chan, dma_dest, src_list, |
| 79 | xor_src_cnt, unmap->len, |
| 80 | dma_flags); |
| 81 | src_list[0] = tmp; |
| 82 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 83 | |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 84 | if (unlikely(!tx)) |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 85 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 86 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 87 | /* spin wait for the preceding transactions to complete */ |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 88 | while (unlikely(!tx)) { |
| 89 | dma_async_issue_pending(chan); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 90 | tx = dma->device_prep_dma_xor(chan, dma_dest, |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 91 | src_list, |
| 92 | xor_src_cnt, unmap->len, |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 93 | dma_flags); |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 94 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 95 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 96 | dma_set_unmap(tx, unmap); |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 97 | async_tx_submit(chan, tx, submit); |
| 98 | submit->depend_tx = tx; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 99 | |
| 100 | if (src_cnt > xor_src_cnt) { |
| 101 | /* drop completed sources */ |
| 102 | src_cnt -= xor_src_cnt; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 103 | /* use the intermediate result a source */ |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 104 | src_cnt++; |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 105 | src_list += xor_src_cnt - 1; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 106 | } else |
| 107 | break; |
| 108 | } |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 109 | |
| 110 | return tx; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static void |
| 114 | do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 115 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 116 | { |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 117 | int i; |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 118 | int xor_src_cnt = 0; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 119 | int src_off = 0; |
| 120 | void *dest_buf; |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 121 | void **srcs; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 122 | |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 123 | if (submit->scribble) |
| 124 | srcs = submit->scribble; |
| 125 | else |
| 126 | srcs = (void **) src_list; |
| 127 | |
| 128 | /* convert to buffer pointers */ |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 129 | for (i = 0; i < src_cnt; i++) |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 130 | if (src_list[i]) |
| 131 | srcs[xor_src_cnt++] = page_address(src_list[i]) + offset; |
| 132 | src_cnt = xor_src_cnt; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 133 | /* set destination address */ |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 134 | dest_buf = page_address(dest) + offset; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 135 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 136 | if (submit->flags & ASYNC_TX_XOR_ZERO_DST) |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 137 | memset(dest_buf, 0, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 138 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 139 | while (src_cnt > 0) { |
| 140 | /* process up to 'MAX_XOR_BLOCKS' sources */ |
| 141 | xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS); |
| 142 | xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]); |
| 143 | |
| 144 | /* drop completed sources */ |
| 145 | src_cnt -= xor_src_cnt; |
| 146 | src_off += xor_src_cnt; |
| 147 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 148 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 149 | async_tx_sync_epilog(submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | /** |
| 153 | * async_xor - attempt to xor a set of blocks with a dma engine. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 154 | * @dest: destination page |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 155 | * @src_list: array of source pages |
| 156 | * @offset: common src/dst offset to start transaction |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 157 | * @src_cnt: number of source pages |
| 158 | * @len: length in bytes |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 159 | * @submit: submission / completion modifiers |
| 160 | * |
| 161 | * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST |
| 162 | * |
| 163 | * xor_blocks always uses the dest as a source so the |
| 164 | * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in |
| 165 | * the calculation. The assumption with dma eninges is that they only |
| 166 | * use the destination buffer as a source when it is explicity specified |
| 167 | * in the source list. |
| 168 | * |
| 169 | * src_list note: if the dest is also a source it must be at index zero. |
| 170 | * The contents of this array will be overwritten if a scribble region |
| 171 | * is not specified. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 172 | */ |
| 173 | struct dma_async_tx_descriptor * |
| 174 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 175 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 176 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 177 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 178 | &dest, 1, src_list, |
| 179 | src_cnt, len); |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 180 | struct dma_device *device = chan ? chan->device : NULL; |
| 181 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 182 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 183 | BUG_ON(src_cnt <= 1); |
| 184 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 185 | if (device) |
| 186 | unmap = dmaengine_get_unmap_data(device->dev, src_cnt+1, GFP_NOIO); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 187 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 188 | if (unmap && is_dma_xor_aligned(device, offset, 0, len)) { |
| 189 | struct dma_async_tx_descriptor *tx; |
| 190 | int i, j; |
| 191 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 192 | /* run the xor asynchronously */ |
| 193 | pr_debug("%s (async): len: %zu\n", __func__, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 194 | |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 195 | unmap->len = len; |
| 196 | for (i = 0, j = 0; i < src_cnt; i++) { |
| 197 | if (!src_list[i]) |
| 198 | continue; |
| 199 | unmap->to_cnt++; |
| 200 | unmap->addr[j++] = dma_map_page(device->dev, src_list[i], |
| 201 | offset, len, DMA_TO_DEVICE); |
| 202 | } |
| 203 | |
| 204 | /* map it bidirectional as it may be re-used as a source */ |
| 205 | unmap->addr[j] = dma_map_page(device->dev, dest, offset, len, |
| 206 | DMA_BIDIRECTIONAL); |
| 207 | unmap->bidi_cnt = 1; |
| 208 | |
| 209 | tx = do_async_xor(chan, unmap, submit); |
| 210 | dmaengine_unmap_put(unmap); |
| 211 | return tx; |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 212 | } else { |
Dan Williams | fb36ab1 | 2013-10-18 19:35:26 +0200 | [diff] [blame] | 213 | dmaengine_unmap_put(unmap); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 214 | /* run the xor synchronously */ |
| 215 | pr_debug("%s (sync): len: %zu\n", __func__, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 216 | WARN_ONCE(chan, "%s: no space for dma address conversion\n", |
| 217 | __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 218 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 219 | /* in the sync case the dest is an implied source |
| 220 | * (assumes the dest is the first source) |
| 221 | */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 222 | if (submit->flags & ASYNC_TX_XOR_DROP_DST) { |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 223 | src_cnt--; |
| 224 | src_list++; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 225 | } |
| 226 | |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 227 | /* wait for any prerequisite operations */ |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 228 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 229 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 230 | do_sync_xor(dest, src_list, offset, src_cnt, len, submit); |
Dan Williams | 1e55db2 | 2008-07-16 19:44:56 -0700 | [diff] [blame] | 231 | |
| 232 | return NULL; |
| 233 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 234 | } |
| 235 | EXPORT_SYMBOL_GPL(async_xor); |
| 236 | |
| 237 | static int page_is_zero(struct page *p, unsigned int offset, size_t len) |
| 238 | { |
Akinobu Mita | 2c88ae9 | 2012-10-28 00:49:33 +0900 | [diff] [blame] | 239 | return !memchr_inv(page_address(p) + offset, 0, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 240 | } |
| 241 | |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 242 | static inline struct dma_chan * |
| 243 | xor_val_chan(struct async_submit_ctl *submit, struct page *dest, |
| 244 | struct page **src_list, int src_cnt, size_t len) |
| 245 | { |
| 246 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA |
| 247 | return NULL; |
| 248 | #endif |
| 249 | return async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list, |
| 250 | src_cnt, len); |
| 251 | } |
| 252 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 253 | /** |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 254 | * async_xor_val - attempt a xor parity check with a dma engine. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 255 | * @dest: destination page used if the xor is performed synchronously |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 256 | * @src_list: array of source pages |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 257 | * @offset: offset in pages to start transaction |
| 258 | * @src_cnt: number of source pages |
| 259 | * @len: length in bytes |
| 260 | * @result: 0 if sum == 0 else non-zero |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 261 | * @submit: submission / completion modifiers |
| 262 | * |
| 263 | * honored flags: ASYNC_TX_ACK |
| 264 | * |
| 265 | * src_list note: if the dest is also a source it must be at index zero. |
| 266 | * The contents of this array will be overwritten if a scribble region |
| 267 | * is not specified. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 268 | */ |
| 269 | struct dma_async_tx_descriptor * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 270 | async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 271 | int src_cnt, size_t len, enum sum_check_flags *result, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 272 | struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 273 | { |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 274 | struct dma_chan *chan = xor_val_chan(submit, dest, src_list, src_cnt, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 275 | struct dma_device *device = chan ? chan->device : NULL; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 276 | struct dma_async_tx_descriptor *tx = NULL; |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 277 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 278 | |
| 279 | BUG_ON(src_cnt <= 1); |
| 280 | |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 281 | if (device) |
| 282 | unmap = dmaengine_get_unmap_data(device->dev, src_cnt, GFP_NOIO); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 283 | |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 284 | if (unmap && src_cnt <= device->max_xor && |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 285 | is_dma_xor_aligned(device, offset, 0, len)) { |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 286 | unsigned long dma_prep_flags = 0; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 287 | int i; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 288 | |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 289 | pr_debug("%s: (async) len: %zu\n", __func__, len); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 290 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 291 | if (submit->cb_fn) |
| 292 | dma_prep_flags |= DMA_PREP_INTERRUPT; |
| 293 | if (submit->flags & ASYNC_TX_FENCE) |
| 294 | dma_prep_flags |= DMA_PREP_FENCE; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 295 | |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 296 | for (i = 0; i < src_cnt; i++) { |
| 297 | unmap->addr[i] = dma_map_page(device->dev, src_list[i], |
| 298 | offset, len, DMA_TO_DEVICE); |
| 299 | unmap->to_cnt++; |
| 300 | } |
| 301 | unmap->len = len; |
| 302 | |
| 303 | tx = device->device_prep_dma_xor_val(chan, unmap->addr, src_cnt, |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 304 | len, result, |
| 305 | dma_prep_flags); |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 306 | if (unlikely(!tx)) { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 307 | async_tx_quiesce(&submit->depend_tx); |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 308 | |
Dan Williams | e34a8ae | 2008-08-05 10:22:05 -0700 | [diff] [blame] | 309 | while (!tx) { |
Dan Williams | 669ab0b | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 310 | dma_async_issue_pending(chan); |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 311 | tx = device->device_prep_dma_xor_val(chan, |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 312 | unmap->addr, src_cnt, len, result, |
Dan Williams | d4c56f9 | 2008-02-02 19:49:58 -0700 | [diff] [blame] | 313 | dma_prep_flags); |
Dan Williams | e34a8ae | 2008-08-05 10:22:05 -0700 | [diff] [blame] | 314 | } |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 315 | } |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 316 | dma_set_unmap(tx, unmap); |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 317 | async_tx_submit(chan, tx, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 318 | } else { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 319 | enum async_tx_flags flags_orig = submit->flags; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 320 | |
Dan Williams | 3280ab3e | 2008-03-13 17:45:28 -0700 | [diff] [blame] | 321 | pr_debug("%s: (sync) len: %zu\n", __func__, len); |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 322 | WARN_ONCE(device && src_cnt <= device->max_xor, |
| 323 | "%s: no space for dma address conversion\n", |
| 324 | __func__); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 325 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 326 | submit->flags |= ASYNC_TX_XOR_DROP_DST; |
| 327 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 328 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 329 | tx = async_xor(dest, src_list, offset, src_cnt, len, submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 330 | |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 331 | async_tx_quiesce(&tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 332 | |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 333 | *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 334 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 335 | async_tx_sync_epilog(submit); |
| 336 | submit->flags = flags_orig; |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 337 | } |
Dan Williams | 173e86b | 2013-10-18 19:35:27 +0200 | [diff] [blame] | 338 | dmaengine_unmap_put(unmap); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 339 | |
| 340 | return tx; |
| 341 | } |
Dan Williams | 099f53c | 2009-04-08 14:28:37 -0700 | [diff] [blame] | 342 | EXPORT_SYMBOL_GPL(async_xor_val); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 343 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 344 | MODULE_AUTHOR("Intel Corporation"); |
| 345 | MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api"); |
| 346 | MODULE_LICENSE("GPL"); |