Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef _LINUX_QCOM_GENI_SE |
| 16 | #define _LINUX_QCOM_GENI_SE |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 17 | #include <linux/clk.h> |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 18 | #include <linux/dma-direction.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/list.h> |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 21 | #include <linux/msm-bus.h> |
| 22 | #include <linux/msm-bus-board.h> |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 23 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 24 | /* Transfer mode supported by GENI Serial Engines */ |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 25 | enum se_xfer_mode { |
| 26 | INVALID, |
| 27 | FIFO_MODE, |
| 28 | GSI_DMA, |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 29 | SE_DMA, |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 30 | }; |
| 31 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 32 | /* Protocols supported by GENI Serial Engines */ |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 33 | enum se_protocol_types { |
| 34 | NONE, |
| 35 | SPI, |
| 36 | UART, |
| 37 | I2C, |
| 38 | I3C |
| 39 | }; |
| 40 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 41 | /** |
| 42 | * struct geni_se_rsc - GENI Serial Engine Resource |
| 43 | * @wrapper_dev: Pointer to the parent QUPv3 core. |
| 44 | * @se_clk: Handle to the core serial engine clock. |
| 45 | * @m_ahb_clk: Handle to the primary AHB clock. |
| 46 | * @s_ahb_clk: Handle to the secondary AHB clock. |
| 47 | * @ab_list: List Head of Average bus banwidth list. |
| 48 | * @ab: Average bus bandwidth request value. |
| 49 | * @ib_list: List Head of Instantaneous bus banwidth list. |
| 50 | * @ib: Instantaneous bus bandwidth request value. |
| 51 | * @geni_pinctrl: Handle to the pinctrl configuration. |
| 52 | * @geni_gpio_active: Handle to the default/active pinctrl state. |
| 53 | * @geni_gpi_sleep: Handle to the sleep pinctrl state. |
| 54 | */ |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 55 | struct se_geni_rsc { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 56 | struct device *wrapper_dev; |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 57 | struct clk *se_clk; |
| 58 | struct clk *m_ahb_clk; |
| 59 | struct clk *s_ahb_clk; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 60 | struct list_head ab_list; |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 61 | unsigned long ab; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 62 | struct list_head ib_list; |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 63 | unsigned long ib; |
| 64 | struct pinctrl *geni_pinctrl; |
| 65 | struct pinctrl_state *geni_gpio_active; |
| 66 | struct pinctrl_state *geni_gpio_sleep; |
Shrey Vijay | 6f23120 | 2017-07-11 11:16:16 +0530 | [diff] [blame] | 67 | int clk_freq_out; |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | #define PINCTRL_DEFAULT "default" |
| 71 | #define PINCTRL_SLEEP "sleep" |
| 72 | |
Shrey Vijay | 6f23120 | 2017-07-11 11:16:16 +0530 | [diff] [blame] | 73 | #define KHz(freq) (1000 * (freq)) |
| 74 | |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 75 | /* Common SE registers */ |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 76 | #define GENI_INIT_CFG_REVISION (0x0) |
| 77 | #define GENI_S_INIT_CFG_REVISION (0x4) |
| 78 | #define GENI_FORCE_DEFAULT_REG (0x20) |
| 79 | #define GENI_OUTPUT_CTRL (0x24) |
| 80 | #define GENI_CGC_CTRL (0x28) |
| 81 | #define SE_GENI_STATUS (0x40) |
| 82 | #define GENI_SER_M_CLK_CFG (0x48) |
| 83 | #define GENI_SER_S_CLK_CFG (0x4C) |
| 84 | #define GENI_CLK_CTRL_RO (0x60) |
| 85 | #define GENI_IF_DISABLE_RO (0x64) |
| 86 | #define GENI_FW_REVISION_RO (0x68) |
| 87 | #define GENI_FW_S_REVISION_RO (0x6C) |
| 88 | #define SE_GENI_CLK_SEL (0x7C) |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 89 | #define SE_GENI_BYTE_GRAN (0x254) |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 90 | #define SE_GENI_DMA_MODE_EN (0x258) |
| 91 | #define SE_GENI_TX_PACKING_CFG0 (0x260) |
| 92 | #define SE_GENI_TX_PACKING_CFG1 (0x264) |
| 93 | #define SE_GENI_RX_PACKING_CFG0 (0x284) |
| 94 | #define SE_GENI_RX_PACKING_CFG1 (0x288) |
| 95 | #define SE_GENI_M_CMD0 (0x600) |
| 96 | #define SE_GENI_M_CMD_CTRL_REG (0x604) |
| 97 | #define SE_GENI_M_IRQ_STATUS (0x610) |
| 98 | #define SE_GENI_M_IRQ_EN (0x614) |
| 99 | #define SE_GENI_M_IRQ_CLEAR (0x618) |
| 100 | #define SE_GENI_S_CMD0 (0x630) |
| 101 | #define SE_GENI_S_CMD_CTRL_REG (0x634) |
| 102 | #define SE_GENI_S_IRQ_STATUS (0x640) |
| 103 | #define SE_GENI_S_IRQ_EN (0x644) |
| 104 | #define SE_GENI_S_IRQ_CLEAR (0x648) |
| 105 | #define SE_GENI_TX_FIFOn (0x700) |
| 106 | #define SE_GENI_RX_FIFOn (0x780) |
| 107 | #define SE_GENI_TX_FIFO_STATUS (0x800) |
| 108 | #define SE_GENI_RX_FIFO_STATUS (0x804) |
| 109 | #define SE_GENI_TX_WATERMARK_REG (0x80C) |
| 110 | #define SE_GENI_RX_WATERMARK_REG (0x810) |
| 111 | #define SE_GENI_RX_RFR_WATERMARK_REG (0x814) |
Girish Mahadevan | 7115f4e | 2017-03-15 15:18:34 -0600 | [diff] [blame] | 112 | #define SE_GENI_IOS (0x908) |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 113 | #define SE_GENI_M_GP_LENGTH (0x910) |
| 114 | #define SE_GENI_S_GP_LENGTH (0x914) |
Girish Mahadevan | a95a361 | 2017-04-19 11:49:24 -0600 | [diff] [blame] | 115 | #define SE_GSI_EVENT_EN (0xE18) |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 116 | #define SE_IRQ_EN (0xE1C) |
| 117 | #define SE_HW_PARAM_0 (0xE24) |
| 118 | #define SE_HW_PARAM_1 (0xE28) |
| 119 | #define SE_DMA_GENERAL_CFG (0xE30) |
| 120 | |
| 121 | /* GENI_OUTPUT_CTRL fields */ |
| 122 | #define DEFAULT_IO_OUTPUT_CTRL_MSK (GENMASK(6, 0)) |
| 123 | |
| 124 | /* GENI_FORCE_DEFAULT_REG fields */ |
| 125 | #define FORCE_DEFAULT (BIT(0)) |
| 126 | |
| 127 | /* GENI_CGC_CTRL fields */ |
| 128 | #define CFG_AHB_CLK_CGC_ON (BIT(0)) |
| 129 | #define CFG_AHB_WR_ACLK_CGC_ON (BIT(1)) |
| 130 | #define DATA_AHB_CLK_CGC_ON (BIT(2)) |
| 131 | #define SCLK_CGC_ON (BIT(3)) |
| 132 | #define TX_CLK_CGC_ON (BIT(4)) |
| 133 | #define RX_CLK_CGC_ON (BIT(5)) |
| 134 | #define EXT_CLK_CGC_ON (BIT(6)) |
| 135 | #define PROG_RAM_HCLK_OFF (BIT(8)) |
| 136 | #define PROG_RAM_SCLK_OFF (BIT(9)) |
| 137 | #define DEFAULT_CGC_EN (GENMASK(6, 0)) |
| 138 | |
| 139 | /* GENI_STATUS fields */ |
| 140 | #define M_GENI_CMD_ACTIVE (BIT(0)) |
| 141 | #define S_GENI_CMD_ACTIVE (BIT(12)) |
| 142 | |
| 143 | /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ |
| 144 | #define SER_CLK_EN (BIT(0)) |
| 145 | #define CLK_DIV_MSK (GENMASK(15, 4)) |
| 146 | #define CLK_DIV_SHFT (4) |
| 147 | |
| 148 | /* CLK_CTRL_RO fields */ |
| 149 | |
| 150 | /* IF_DISABLE_RO fields */ |
| 151 | |
| 152 | /* FW_REVISION_RO fields */ |
| 153 | #define FW_REV_PROTOCOL_MSK (GENMASK(15, 8)) |
| 154 | #define FW_REV_PROTOCOL_SHFT (8) |
| 155 | |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 156 | /* GENI_CLK_SEL fields */ |
| 157 | #define CLK_SEL_MSK (GENMASK(2, 0)) |
| 158 | |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 159 | /* SE_GENI_DMA_MODE_EN */ |
| 160 | #define GENI_DMA_MODE_EN (BIT(0)) |
| 161 | |
| 162 | /* GENI_M_CMD0 fields */ |
| 163 | #define M_OPCODE_MSK (GENMASK(31, 27)) |
| 164 | #define M_OPCODE_SHFT (27) |
| 165 | #define M_PARAMS_MSK (GENMASK(26, 0)) |
| 166 | |
| 167 | /* GENI_M_CMD_CTRL_REG */ |
| 168 | #define M_GENI_CMD_CANCEL BIT(2) |
| 169 | #define M_GENI_CMD_ABORT BIT(1) |
| 170 | #define M_GENI_DISABLE BIT(0) |
| 171 | |
| 172 | /* GENI_S_CMD0 fields */ |
| 173 | #define S_OPCODE_MSK (GENMASK(31, 27)) |
| 174 | #define S_OPCODE_SHFT (27) |
| 175 | #define S_PARAMS_MSK (GENMASK(26, 0)) |
| 176 | |
| 177 | /* GENI_S_CMD_CTRL_REG */ |
| 178 | #define S_GENI_CMD_CANCEL (BIT(2)) |
| 179 | #define S_GENI_CMD_ABORT (BIT(1)) |
| 180 | #define S_GENI_DISABLE (BIT(0)) |
| 181 | |
| 182 | /* GENI_M_IRQ_EN fields */ |
| 183 | #define M_CMD_DONE_EN (BIT(0)) |
| 184 | #define M_CMD_OVERRUN_EN (BIT(1)) |
| 185 | #define M_ILLEGAL_CMD_EN (BIT(2)) |
| 186 | #define M_CMD_FAILURE_EN (BIT(3)) |
| 187 | #define M_CMD_CANCEL_EN (BIT(4)) |
| 188 | #define M_CMD_ABORT_EN (BIT(5)) |
| 189 | #define M_TIMESTAMP_EN (BIT(6)) |
| 190 | #define M_RX_IRQ_EN (BIT(7)) |
| 191 | #define M_GP_SYNC_IRQ_0_EN (BIT(8)) |
| 192 | #define M_GP_IRQ_0_EN (BIT(9)) |
| 193 | #define M_GP_IRQ_1_EN (BIT(10)) |
| 194 | #define M_GP_IRQ_2_EN (BIT(11)) |
| 195 | #define M_GP_IRQ_3_EN (BIT(12)) |
| 196 | #define M_GP_IRQ_4_EN (BIT(13)) |
| 197 | #define M_GP_IRQ_5_EN (BIT(14)) |
| 198 | #define M_IO_DATA_DEASSERT_EN (BIT(22)) |
| 199 | #define M_IO_DATA_ASSERT_EN (BIT(23)) |
| 200 | #define M_RX_FIFO_RD_ERR_EN (BIT(24)) |
| 201 | #define M_RX_FIFO_WR_ERR_EN (BIT(25)) |
| 202 | #define M_RX_FIFO_WATERMARK_EN (BIT(26)) |
| 203 | #define M_RX_FIFO_LAST_EN (BIT(27)) |
| 204 | #define M_TX_FIFO_RD_ERR_EN (BIT(28)) |
| 205 | #define M_TX_FIFO_WR_ERR_EN (BIT(29)) |
| 206 | #define M_TX_FIFO_WATERMARK_EN (BIT(30)) |
| 207 | #define M_SEC_IRQ_EN (BIT(31)) |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 208 | #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ |
| 209 | M_IO_DATA_DEASSERT_EN | \ |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 210 | M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ |
| 211 | M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 212 | M_TX_FIFO_WR_ERR_EN) |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 213 | |
| 214 | /* GENI_S_IRQ_EN fields */ |
| 215 | #define S_CMD_DONE_EN (BIT(0)) |
| 216 | #define S_CMD_OVERRUN_EN (BIT(1)) |
| 217 | #define S_ILLEGAL_CMD_EN (BIT(2)) |
| 218 | #define S_CMD_FAILURE_EN (BIT(3)) |
| 219 | #define S_CMD_CANCEL_EN (BIT(4)) |
| 220 | #define S_CMD_ABORT_EN (BIT(5)) |
| 221 | #define S_GP_SYNC_IRQ_0_EN (BIT(8)) |
| 222 | #define S_GP_IRQ_0_EN (BIT(9)) |
| 223 | #define S_GP_IRQ_1_EN (BIT(10)) |
| 224 | #define S_GP_IRQ_2_EN (BIT(11)) |
| 225 | #define S_GP_IRQ_3_EN (BIT(12)) |
| 226 | #define S_GP_IRQ_4_EN (BIT(13)) |
| 227 | #define S_GP_IRQ_5_EN (BIT(14)) |
| 228 | #define S_IO_DATA_DEASSERT_EN (BIT(22)) |
| 229 | #define S_IO_DATA_ASSERT_EN (BIT(23)) |
| 230 | #define S_RX_FIFO_RD_ERR_EN (BIT(24)) |
| 231 | #define S_RX_FIFO_WR_ERR_EN (BIT(25)) |
| 232 | #define S_RX_FIFO_WATERMARK_EN (BIT(26)) |
| 233 | #define S_RX_FIFO_LAST_EN (BIT(27)) |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 234 | #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 235 | S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) |
| 236 | |
| 237 | /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ |
| 238 | #define WATERMARK_MSK (GENMASK(5, 0)) |
| 239 | |
| 240 | /* GENI_TX_FIFO_STATUS fields */ |
| 241 | #define TX_FIFO_WC (GENMASK(27, 0)) |
| 242 | |
| 243 | /* GENI_RX_FIFO_STATUS fields */ |
| 244 | #define RX_LAST (BIT(31)) |
| 245 | #define RX_LAST_BYTE_VALID_MSK (GENMASK(30, 28)) |
| 246 | #define RX_LAST_BYTE_VALID_SHFT (28) |
| 247 | #define RX_FIFO_WC_MSK (GENMASK(24, 0)) |
| 248 | |
Girish Mahadevan | a95a361 | 2017-04-19 11:49:24 -0600 | [diff] [blame] | 249 | /* SE_GSI_EVENT_EN fields */ |
| 250 | #define DMA_RX_EVENT_EN (BIT(0)) |
| 251 | #define DMA_TX_EVENT_EN (BIT(1)) |
| 252 | #define GENI_M_EVENT_EN (BIT(2)) |
| 253 | #define GENI_S_EVENT_EN (BIT(3)) |
| 254 | |
Girish Mahadevan | 7115f4e | 2017-03-15 15:18:34 -0600 | [diff] [blame] | 255 | /* SE_GENI_IOS fields */ |
| 256 | #define IO2_DATA_IN (BIT(1)) |
| 257 | #define RX_DATA_IN (BIT(0)) |
| 258 | |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 259 | /* SE_IRQ_EN fields */ |
| 260 | #define DMA_RX_IRQ_EN (BIT(0)) |
| 261 | #define DMA_TX_IRQ_EN (BIT(1)) |
| 262 | #define GENI_M_IRQ_EN (BIT(2)) |
| 263 | #define GENI_S_IRQ_EN (BIT(3)) |
| 264 | |
| 265 | /* SE_HW_PARAM_0 fields */ |
| 266 | #define TX_FIFO_WIDTH_MSK (GENMASK(29, 24)) |
| 267 | #define TX_FIFO_WIDTH_SHFT (24) |
| 268 | #define TX_FIFO_DEPTH_MSK (GENMASK(21, 16)) |
| 269 | #define TX_FIFO_DEPTH_SHFT (16) |
| 270 | |
| 271 | /* SE_HW_PARAM_1 fields */ |
| 272 | #define RX_FIFO_WIDTH_MSK (GENMASK(29, 24)) |
| 273 | #define RX_FIFO_WIDTH_SHFT (24) |
| 274 | #define RX_FIFO_DEPTH_MSK (GENMASK(21, 16)) |
| 275 | #define RX_FIFO_DEPTH_SHFT (16) |
| 276 | |
| 277 | /* SE_DMA_GENERAL_CFG */ |
| 278 | #define DMA_RX_CLK_CGC_ON (BIT(0)) |
| 279 | #define DMA_TX_CLK_CGC_ON (BIT(1)) |
| 280 | #define DMA_AHB_SLV_CFG_ON (BIT(2)) |
| 281 | #define AHB_SEC_SLV_CLK_CGC_ON (BIT(3)) |
| 282 | #define DUMMY_RX_NON_BUFFERABLE (BIT(4)) |
| 283 | #define RX_DMA_ZERO_PADDING_EN (BIT(5)) |
| 284 | #define RX_DMA_IRQ_DELAY_MSK (GENMASK(8, 6)) |
| 285 | #define RX_DMA_IRQ_DELAY_SHFT (6) |
| 286 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 287 | #define SE_DMA_TX_PTR_L (0xC30) |
| 288 | #define SE_DMA_TX_PTR_H (0xC34) |
| 289 | #define SE_DMA_TX_ATTR (0xC38) |
| 290 | #define SE_DMA_TX_LEN (0xC3C) |
| 291 | #define SE_DMA_TX_IRQ_STAT (0xC40) |
| 292 | #define SE_DMA_TX_IRQ_CLR (0xC44) |
| 293 | #define SE_DMA_TX_IRQ_EN (0xC48) |
| 294 | #define SE_DMA_TX_IRQ_EN_SET (0xC4C) |
| 295 | #define SE_DMA_TX_IRQ_EN_CLR (0xC50) |
| 296 | #define SE_DMA_TX_LEN_IN (0xC54) |
| 297 | #define SE_DMA_TX_FSM_RST (0xC58) |
| 298 | #define SE_DMA_TX_MAX_BURST (0xC5C) |
| 299 | |
| 300 | #define SE_DMA_RX_PTR_L (0xD30) |
| 301 | #define SE_DMA_RX_PTR_H (0xD34) |
| 302 | #define SE_DMA_RX_ATTR (0xD38) |
| 303 | #define SE_DMA_RX_LEN (0xD3C) |
| 304 | #define SE_DMA_RX_IRQ_STAT (0xD40) |
| 305 | #define SE_DMA_RX_IRQ_CLR (0xD44) |
| 306 | #define SE_DMA_RX_IRQ_EN (0xD48) |
| 307 | #define SE_DMA_RX_IRQ_EN_SET (0xD4C) |
| 308 | #define SE_DMA_RX_IRQ_EN_CLR (0xD50) |
| 309 | #define SE_DMA_RX_LEN_IN (0xD54) |
| 310 | #define SE_DMA_RX_FSM_RST (0xD58) |
| 311 | #define SE_DMA_RX_MAX_BURST (0xD5C) |
| 312 | #define SE_DMA_RX_FLUSH (0xD60) |
| 313 | |
Karthikeyan Ramasubramanian | a576657 | 2017-04-19 11:31:42 -0600 | [diff] [blame] | 314 | /* SE_DMA_TX_IRQ_STAT Register fields */ |
| 315 | #define TX_DMA_DONE (BIT(0)) |
| 316 | #define TX_EOT (BIT(1)) |
| 317 | #define TX_SBE (BIT(2)) |
| 318 | #define TX_RESET_DONE (BIT(3)) |
| 319 | |
| 320 | /* SE_DMA_RX_IRQ_STAT Register fields */ |
| 321 | #define RX_DMA_DONE (BIT(0)) |
| 322 | #define RX_EOT (BIT(1)) |
| 323 | #define RX_SBE (BIT(2)) |
| 324 | #define RX_RESET_DONE (BIT(3)) |
| 325 | #define RX_FLUSH_DONE (BIT(4)) |
| 326 | #define RX_GENI_GP_IRQ (GENMASK(10, 5)) |
| 327 | #define RX_GENI_CANCEL_IRQ (BIT(11)) |
| 328 | #define RX_GENI_GP_IRQ_EXT (GENMASK(13, 12)) |
| 329 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 330 | #define DEFAULT_BUS_WIDTH (4) |
| 331 | #define DEFAULT_SE_CLK (19200000) |
| 332 | |
| 333 | #define GENI_SE_ERR(log_ctx, print, dev, x...) do { \ |
| 334 | if (log_ctx) \ |
| 335 | ipc_log_string(log_ctx, x); \ |
| 336 | if (print) { \ |
| 337 | if (dev) \ |
| 338 | dev_err((dev), x); \ |
| 339 | else \ |
| 340 | pr_err(x); \ |
| 341 | } \ |
| 342 | } while (0) |
| 343 | |
| 344 | #define GENI_SE_DBG(log_ctx, print, dev, x...) do { \ |
| 345 | if (log_ctx) \ |
| 346 | ipc_log_string(log_ctx, x); \ |
| 347 | if (print) { \ |
| 348 | if (dev) \ |
| 349 | dev_dbg((dev), x); \ |
| 350 | else \ |
| 351 | pr_debug(x); \ |
| 352 | } \ |
| 353 | } while (0) |
| 354 | |
| 355 | |
| 356 | #ifdef CONFIG_QCOM_GENI_SE |
| 357 | /** |
| 358 | * geni_read_reg_nolog() - Helper function to read from a GENI register |
| 359 | * @base: Base address of the serial engine's register block. |
| 360 | * @offset: Offset within the serial engine's register block. |
| 361 | * |
| 362 | * Return: Return the contents of the register. |
| 363 | */ |
| 364 | unsigned int geni_read_reg_nolog(void __iomem *base, int offset); |
| 365 | |
| 366 | /** |
| 367 | * geni_write_reg_nolog() - Helper function to write into a GENI register |
| 368 | * @value: Value to be written into the register. |
| 369 | * @base: Base address of the serial engine's register block. |
| 370 | * @offset: Offset within the serial engine's register block. |
| 371 | */ |
| 372 | void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset); |
| 373 | |
| 374 | /** |
| 375 | * geni_read_reg() - Helper function to read from a GENI register |
| 376 | * @base: Base address of the serial engine's register block. |
| 377 | * @offset: Offset within the serial engine's register block. |
| 378 | * |
| 379 | * Return: Return the contents of the register. |
| 380 | */ |
| 381 | unsigned int geni_read_reg(void __iomem *base, int offset); |
| 382 | |
| 383 | /** |
| 384 | * geni_write_reg() - Helper function to write into a GENI register |
| 385 | * @value: Value to be written into the register. |
| 386 | * @base: Base address of the serial engine's register block. |
| 387 | * @offset: Offset within the serial engine's register block. |
| 388 | */ |
| 389 | void geni_write_reg(unsigned int value, void __iomem *base, int offset); |
| 390 | |
| 391 | /** |
| 392 | * get_se_proto() - Read the protocol configured for a serial engine |
| 393 | * @base: Base address of the serial engine's register block. |
| 394 | * |
| 395 | * Return: Protocol value as configured in the serial engine. |
| 396 | */ |
| 397 | int get_se_proto(void __iomem *base); |
| 398 | |
| 399 | /** |
| 400 | * geni_se_init() - Initialize the GENI Serial Engine |
| 401 | * @base: Base address of the serial engine's register block. |
| 402 | * @rx_wm: Receive watermark to be configured. |
| 403 | * @rx_rfr_wm: Ready-for-receive watermark to be configured. |
| 404 | * |
| 405 | * This function is used to initialize the GENI serial engine, configure |
| 406 | * the transfer mode, receive watermark and ready-for-receive watermarks. |
| 407 | * |
| 408 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 409 | */ |
| 410 | int geni_se_init(void __iomem *base, unsigned int rx_wm, unsigned int rx_rfr); |
| 411 | |
| 412 | /** |
| 413 | * geni_se_select_mode() - Select the serial engine transfer mode |
| 414 | * @base: Base address of the serial engine's register block. |
| 415 | * @mode: Transfer mode to be selected. |
| 416 | * |
| 417 | * Return: 0 on success, standard Linux error codes on failure. |
| 418 | */ |
| 419 | int geni_se_select_mode(void __iomem *base, int mode); |
| 420 | |
| 421 | /** |
| 422 | * geni_setup_m_cmd() - Setup the primary sequencer |
| 423 | * @base: Base address of the serial engine's register block. |
| 424 | * @cmd: Command/Operation to setup in the primary sequencer. |
| 425 | * @params: Parameter for the sequencer command. |
| 426 | * |
| 427 | * This function is used to configure the primary sequencer with the |
| 428 | * command and its assoicated parameters. |
| 429 | */ |
| 430 | void geni_setup_m_cmd(void __iomem *base, u32 cmd, u32 params); |
| 431 | |
| 432 | /** |
| 433 | * geni_setup_s_cmd() - Setup the secondary sequencer |
| 434 | * @base: Base address of the serial engine's register block. |
| 435 | * @cmd: Command/Operation to setup in the secondary sequencer. |
| 436 | * @params: Parameter for the sequencer command. |
| 437 | * |
| 438 | * This function is used to configure the secondary sequencer with the |
| 439 | * command and its assoicated parameters. |
| 440 | */ |
| 441 | void geni_setup_s_cmd(void __iomem *base, u32 cmd, u32 params); |
| 442 | |
| 443 | /** |
| 444 | * geni_cancel_m_cmd() - Cancel the command configured in the primary sequencer |
| 445 | * @base: Base address of the serial engine's register block. |
| 446 | * |
| 447 | * This function is used to cancel the currently configured command in the |
| 448 | * primary sequencer. |
| 449 | */ |
| 450 | void geni_cancel_m_cmd(void __iomem *base); |
| 451 | |
| 452 | /** |
| 453 | * geni_cancel_s_cmd() - Cancel the command configured in the secondary |
| 454 | * sequencer |
| 455 | * @base: Base address of the serial engine's register block. |
| 456 | * |
| 457 | * This function is used to cancel the currently configured command in the |
| 458 | * secondary sequencer. |
| 459 | */ |
| 460 | void geni_cancel_s_cmd(void __iomem *base); |
| 461 | |
| 462 | /** |
| 463 | * geni_abort_m_cmd() - Abort the command configured in the primary sequencer |
| 464 | * @base: Base address of the serial engine's register block. |
| 465 | * |
| 466 | * This function is used to force abort the currently configured command in the |
| 467 | * primary sequencer. |
| 468 | */ |
| 469 | void geni_abort_m_cmd(void __iomem *base); |
| 470 | |
| 471 | /** |
| 472 | * geni_abort_s_cmd() - Abort the command configured in the secondary |
| 473 | * sequencer |
| 474 | * @base: Base address of the serial engine's register block. |
| 475 | * |
| 476 | * This function is used to force abort the currently configured command in the |
| 477 | * secondary sequencer. |
| 478 | */ |
| 479 | void geni_abort_s_cmd(void __iomem *base); |
| 480 | |
| 481 | /** |
| 482 | * get_tx_fifo_depth() - Get the TX fifo depth of the serial engine |
| 483 | * @base: Base address of the serial engine's register block. |
| 484 | * |
| 485 | * This function is used to get the depth i.e. number of elements in the |
| 486 | * TX fifo of the serial engine. |
| 487 | * |
| 488 | * Return: TX fifo depth in units of FIFO words. |
| 489 | */ |
| 490 | int get_tx_fifo_depth(void __iomem *base); |
| 491 | |
| 492 | /** |
| 493 | * get_tx_fifo_width() - Get the TX fifo width of the serial engine |
| 494 | * @base: Base address of the serial engine's register block. |
| 495 | * |
| 496 | * This function is used to get the width i.e. word size per element in the |
| 497 | * TX fifo of the serial engine. |
| 498 | * |
| 499 | * Return: TX fifo width in bits. |
| 500 | */ |
| 501 | int get_tx_fifo_width(void __iomem *base); |
| 502 | |
| 503 | /** |
| 504 | * get_rx_fifo_depth() - Get the RX fifo depth of the serial engine |
| 505 | * @base: Base address of the serial engine's register block. |
| 506 | * |
| 507 | * This function is used to get the depth i.e. number of elements in the |
| 508 | * RX fifo of the serial engine. |
| 509 | * |
| 510 | * Return: RX fifo depth in units of FIFO words. |
| 511 | */ |
| 512 | int get_rx_fifo_depth(void __iomem *base); |
| 513 | |
| 514 | /** |
| 515 | * se_get_packing_config() - Get the packing configuration based on input |
| 516 | * @bpw: Bits of data per transfer word. |
| 517 | * @pack_words: Number of words per fifo element. |
| 518 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
| 519 | * @cfg0: Output buffer to hold the first half of configuration. |
| 520 | * @cfg1: Output buffer to hold the second half of configuration. |
| 521 | * |
| 522 | * This function is used to calculate the packing configuration based on |
| 523 | * the input packing requirement and the configuration logic. |
| 524 | */ |
| 525 | void se_get_packing_config(int bpw, int pack_words, bool msb_to_lsb, |
| 526 | unsigned long *cfg0, unsigned long *cfg1); |
| 527 | |
| 528 | /** |
| 529 | * se_config_packing() - Packing configuration of the serial engine |
| 530 | * @base: Base address of the serial engine's register block. |
| 531 | * @bpw: Bits of data per transfer word. |
| 532 | * @pack_words: Number of words per fifo element. |
| 533 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
| 534 | * |
| 535 | * This function is used to configure the packing rules for the current |
| 536 | * transfer. |
| 537 | */ |
| 538 | void se_config_packing(void __iomem *base, int bpw, int pack_words, |
| 539 | bool msb_to_lsb); |
| 540 | |
| 541 | /** |
| 542 | * se_geni_resources_off() - Turn off resources associated with the serial |
| 543 | * engine |
| 544 | * @rsc: Handle to resources associated with the serial engine. |
| 545 | * |
| 546 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 547 | */ |
| 548 | int se_geni_resources_off(struct se_geni_rsc *rsc); |
| 549 | |
| 550 | /** |
| 551 | * se_geni_resources_on() - Turn on resources associated with the serial |
| 552 | * engine |
| 553 | * @rsc: Handle to resources associated with the serial engine. |
| 554 | * |
| 555 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 556 | */ |
| 557 | int se_geni_resources_on(struct se_geni_rsc *rsc); |
| 558 | |
| 559 | /** |
| 560 | * geni_se_resources_init() - Init the SE resource structure |
| 561 | * @rsc: SE resource structure to be initialized. |
| 562 | * @ab: Initial Average bus bandwidth request value. |
| 563 | * @ib: Initial Instantaneous bus bandwidth request value. |
| 564 | * |
| 565 | * Return: 0 on success, standard Linux error codes on failure. |
| 566 | */ |
| 567 | int geni_se_resources_init(struct se_geni_rsc *rsc, |
| 568 | unsigned long ab, unsigned long ib); |
| 569 | |
| 570 | /** |
Karthikeyan Ramasubramanian | 8bef5ea | 2017-05-11 17:02:46 -0600 | [diff] [blame] | 571 | * geni_se_clk_tbl_get() - Get the clock table to program DFS |
| 572 | * @rsc: Resource for which the clock table is requested. |
| 573 | * @tbl: Table in which the output is returned. |
| 574 | * |
| 575 | * This function is called by the protocol drivers to determine the different |
| 576 | * clock frequencies supported by Serail Engine Core Clock. The protocol |
| 577 | * drivers use the output to determine the clock frequency index to be |
| 578 | * programmed into DFS. |
| 579 | * |
| 580 | * Return: number of valid performance levels in the table on success, |
| 581 | * standard Linux error codes on failure. |
| 582 | */ |
| 583 | int geni_se_clk_tbl_get(struct se_geni_rsc *rsc, unsigned long **tbl); |
| 584 | |
| 585 | /** |
| 586 | * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency |
| 587 | * @rsc: Resource for which the clock frequency is requested. |
| 588 | * @req_freq: Requested clock frequency. |
| 589 | * @index: Index of the resultant frequency in the table. |
| 590 | * @res_freq: Resultant frequency which matches or is closer to the |
| 591 | * requested frequency. |
| 592 | * @exact: Flag to indicate exact multiple requirement of the requested |
| 593 | * frequency . |
| 594 | * |
| 595 | * This function is called by the protocol drivers to determine the matching |
| 596 | * or closest frequency of the Serial Engine clock to be selected in order |
| 597 | * to meet the performance requirements. |
| 598 | * |
| 599 | * Return: 0 on success, standard Linux error codes on failure. |
| 600 | */ |
| 601 | int geni_se_clk_freq_match(struct se_geni_rsc *rsc, unsigned long req_freq, |
| 602 | unsigned int *index, unsigned long *res_freq, |
| 603 | bool exact); |
| 604 | |
| 605 | /** |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 606 | * geni_se_tx_dma_prep() - Prepare the Serial Engine for TX DMA transfer |
| 607 | * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped. |
| 608 | * @base: Base address of the SE register block. |
| 609 | * @tx_buf: Pointer to the TX buffer. |
| 610 | * @tx_len: Length of the TX buffer. |
| 611 | * @tx_dma: Pointer to store the mapped DMA address. |
| 612 | * |
| 613 | * This function is used to prepare the buffers for DMA TX. |
| 614 | * |
| 615 | * Return: 0 on success, standard Linux error codes on error/failure. |
| 616 | */ |
| 617 | int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base, |
| 618 | void *tx_buf, int tx_len, dma_addr_t *tx_dma); |
| 619 | |
| 620 | /** |
| 621 | * geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer |
| 622 | * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped. |
| 623 | * @base: Base address of the SE register block. |
| 624 | * @rx_buf: Pointer to the RX buffer. |
| 625 | * @rx_len: Length of the RX buffer. |
| 626 | * @rx_dma: Pointer to store the mapped DMA address. |
| 627 | * |
| 628 | * This function is used to prepare the buffers for DMA RX. |
| 629 | * |
| 630 | * Return: 0 on success, standard Linux error codes on error/failure. |
| 631 | */ |
| 632 | int geni_se_rx_dma_prep(struct device *wrapper_dev, void __iomem *base, |
| 633 | void *rx_buf, int rx_len, dma_addr_t *rx_dma); |
| 634 | |
| 635 | /** |
| 636 | * geni_se_tx_dma_unprep() - Unprepare the Serial Engine after TX DMA transfer |
| 637 | * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped. |
| 638 | * @tx_dma: DMA address of the TX buffer. |
| 639 | * @tx_len: Length of the TX buffer. |
| 640 | * |
| 641 | * This function is used to unprepare the DMA buffers after DMA TX. |
| 642 | */ |
| 643 | void geni_se_tx_dma_unprep(struct device *wrapper_dev, |
| 644 | dma_addr_t tx_dma, int tx_len); |
| 645 | |
| 646 | /** |
| 647 | * geni_se_rx_dma_unprep() - Unprepare the Serial Engine after RX DMA transfer |
| 648 | * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped. |
| 649 | * @rx_dma: DMA address of the RX buffer. |
| 650 | * @rx_len: Length of the RX buffer. |
| 651 | * |
| 652 | * This function is used to unprepare the DMA buffers after DMA RX. |
| 653 | */ |
| 654 | void geni_se_rx_dma_unprep(struct device *wrapper_dev, |
| 655 | dma_addr_t rx_dma, int rx_len); |
| 656 | |
| 657 | /** |
| 658 | * geni_se_qupv3_hw_version() - Read the QUPv3 Hardware version |
| 659 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 660 | * @major: Buffer for Major Version field. |
| 661 | * @minor: Buffer for Minor Version field. |
| 662 | * @step: Buffer for Step Version field. |
| 663 | * |
| 664 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 665 | */ |
| 666 | int geni_se_qupv3_hw_version(struct device *wrapper_dev, unsigned int *major, |
| 667 | unsigned int *minor, unsigned int *step); |
| 668 | |
| 669 | /** |
| 670 | * geni_se_iommu_map_buf() - Map a single buffer into QUPv3 context bank |
| 671 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 672 | * @iova: Pointer in which the mapped virtual address is stored. |
| 673 | * @buf: Address of the buffer that needs to be mapped. |
| 674 | * @size: Size of the buffer. |
| 675 | * @dir: Direction of the DMA transfer. |
| 676 | * |
| 677 | * This function is used to map an already allocated buffer into the |
| 678 | * QUPv3 context bank device space. |
| 679 | * |
| 680 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 681 | */ |
| 682 | int geni_se_iommu_map_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 683 | void *buf, size_t size, enum dma_data_direction dir); |
| 684 | |
| 685 | /** |
| 686 | * geni_se_iommu_alloc_buf() - Allocate & map a single buffer into QUPv3 |
| 687 | * context bank |
| 688 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 689 | * @iova: Pointer in which the mapped virtual address is stored. |
| 690 | * @size: Size of the buffer. |
| 691 | * |
| 692 | * This function is used to allocate a buffer and map it into the |
| 693 | * QUPv3 context bank device space. |
| 694 | * |
| 695 | * Return: address of the buffer on success, NULL or ERR_PTR on |
| 696 | * failure/error. |
| 697 | */ |
| 698 | void *geni_se_iommu_alloc_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 699 | size_t size); |
| 700 | |
| 701 | /** |
| 702 | * geni_se_iommu_unmap_buf() - Unmap a single buffer from QUPv3 context bank |
| 703 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 704 | * @iova: Pointer in which the mapped virtual address is stored. |
| 705 | * @size: Size of the buffer. |
| 706 | * @dir: Direction of the DMA transfer. |
| 707 | * |
| 708 | * This function is used to unmap an already mapped buffer from the |
| 709 | * QUPv3 context bank device space. |
| 710 | * |
| 711 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 712 | */ |
| 713 | int geni_se_iommu_unmap_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 714 | size_t size, enum dma_data_direction dir); |
| 715 | |
| 716 | /** |
| 717 | * geni_se_iommu_free_buf() - Unmap & free a single buffer from QUPv3 |
| 718 | * context bank |
| 719 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 720 | * @iova: Pointer in which the mapped virtual address is stored. |
| 721 | * @buf: Address of the buffer. |
| 722 | * @size: Size of the buffer. |
| 723 | * |
| 724 | * This function is used to unmap and free a buffer from the |
| 725 | * QUPv3 context bank device space. |
| 726 | * |
| 727 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 728 | */ |
| 729 | int geni_se_iommu_free_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 730 | void *buf, size_t size); |
| 731 | |
| 732 | #else |
Girish Mahadevan | bd9b44f | 2017-04-11 13:11:10 -0600 | [diff] [blame] | 733 | static inline unsigned int geni_read_reg_nolog(void __iomem *base, int offset) |
| 734 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 735 | return 0; |
Girish Mahadevan | bd9b44f | 2017-04-11 13:11:10 -0600 | [diff] [blame] | 736 | } |
| 737 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 738 | static inline void geni_write_reg_nolog(unsigned int value, |
| 739 | void __iomem *base, int offset) |
Girish Mahadevan | bd9b44f | 2017-04-11 13:11:10 -0600 | [diff] [blame] | 740 | { |
Girish Mahadevan | bd9b44f | 2017-04-11 13:11:10 -0600 | [diff] [blame] | 741 | } |
| 742 | |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 743 | static inline unsigned int geni_read_reg(void __iomem *base, int offset) |
| 744 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 745 | return 0; |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 746 | } |
| 747 | |
| 748 | static inline void geni_write_reg(unsigned int value, void __iomem *base, |
| 749 | int offset) |
| 750 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 751 | } |
| 752 | |
| 753 | static inline int get_se_proto(void __iomem *base) |
| 754 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 755 | return -ENXIO; |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 756 | } |
| 757 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 758 | static inline int geni_se_init(void __iomem *base, |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 759 | unsigned int rx_wm, unsigned int rx_rfr) |
| 760 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 761 | return -ENXIO; |
| 762 | } |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 763 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 764 | static inline int geni_se_select_mode(void __iomem *base, int mode) |
| 765 | { |
| 766 | return -ENXIO; |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | static inline void geni_setup_m_cmd(void __iomem *base, u32 cmd, |
| 770 | u32 params) |
| 771 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static inline void geni_setup_s_cmd(void __iomem *base, u32 cmd, |
| 775 | u32 params) |
| 776 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | static inline void geni_cancel_m_cmd(void __iomem *base) |
| 780 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 781 | } |
| 782 | |
| 783 | static inline void geni_cancel_s_cmd(void __iomem *base) |
| 784 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 785 | } |
| 786 | |
| 787 | static inline void geni_abort_m_cmd(void __iomem *base) |
| 788 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 789 | } |
| 790 | |
Girish Mahadevan | 24f5659 | 2017-04-15 17:35:05 -0600 | [diff] [blame] | 791 | static inline void geni_abort_s_cmd(void __iomem *base) |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 792 | { |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 793 | } |
| 794 | |
| 795 | static inline int get_tx_fifo_depth(void __iomem *base) |
| 796 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 797 | return -ENXIO; |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 798 | } |
| 799 | |
| 800 | static inline int get_tx_fifo_width(void __iomem *base) |
| 801 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 802 | return -ENXIO; |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 803 | } |
| 804 | |
| 805 | static inline int get_rx_fifo_depth(void __iomem *base) |
| 806 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 807 | return -ENXIO; |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 808 | } |
| 809 | |
Girish Mahadevan | b1ab172 | 2017-04-27 16:39:11 -0600 | [diff] [blame] | 810 | static inline void se_get_packing_config(int bpw, int pack_words, |
| 811 | bool msb_to_lsb, unsigned long *cfg0, |
| 812 | unsigned long *cfg1) |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 813 | { |
Girish Mahadevan | b1ab172 | 2017-04-27 16:39:11 -0600 | [diff] [blame] | 814 | } |
| 815 | |
| 816 | static inline void se_config_packing(void __iomem *base, int bpw, |
| 817 | int pack_words, bool msb_to_lsb) |
| 818 | { |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 819 | } |
| 820 | |
| 821 | static inline int se_geni_resources_on(struct se_geni_rsc *rsc) |
| 822 | { |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 823 | return -ENXIO; |
Girish Mahadevan | ebeed35 | 2016-11-23 10:59:29 -0700 | [diff] [blame] | 824 | } |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 825 | |
| 826 | static inline int se_geni_resources_off(struct se_geni_rsc *rsc) |
| 827 | { |
| 828 | return -ENXIO; |
| 829 | } |
| 830 | |
| 831 | static inline int geni_se_resources_init(struct se_geni_rsc *rsc, |
| 832 | unsigned long ab, unsigned long ib) |
| 833 | { |
| 834 | return -ENXIO; |
| 835 | } |
| 836 | |
Karthikeyan Ramasubramanian | 8bef5ea | 2017-05-11 17:02:46 -0600 | [diff] [blame] | 837 | static inline int geni_se_clk_tbl_get(struct se_geni_rsc *rsc, |
| 838 | unsigned long **tbl) |
| 839 | { |
| 840 | return -ENXIO; |
| 841 | } |
| 842 | |
| 843 | static inline int geni_se_clk_freq_match(struct se_geni_rsc *rsc, |
| 844 | unsigned long req_freq, unsigned int *index, |
| 845 | unsigned long *res_freq, bool exact) |
| 846 | { |
| 847 | return -ENXIO; |
| 848 | } |
| 849 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 850 | static inline int geni_se_tx_dma_prep(struct device *wrapper_dev, |
| 851 | void __iomem *base, void *tx_buf, int tx_len, dma_addr_t *tx_dma) |
| 852 | { |
| 853 | return -ENXIO; |
| 854 | } |
| 855 | |
| 856 | static inline int geni_se_rx_dma_prep(struct device *wrapper_dev, |
| 857 | void __iomem *base, void *rx_buf, int rx_len, dma_addr_t *rx_dma) |
| 858 | { |
| 859 | return -ENXIO; |
| 860 | } |
| 861 | |
| 862 | static inline void geni_se_tx_dma_unprep(struct device *wrapper_dev, |
| 863 | dma_addr_t tx_dma, int tx_len) |
| 864 | { |
| 865 | } |
| 866 | |
| 867 | static inline void geni_se_rx_dma_unprep(struct device *wrapper_dev, |
| 868 | dma_addr_t rx_dma, int rx_len) |
| 869 | { |
| 870 | } |
| 871 | |
| 872 | static inline int geni_se_qupv3_hw_version(struct device *wrapper_dev, |
| 873 | unsigned int *major, unsigned int *minor, unsigned int *step) |
| 874 | { |
| 875 | return -ENXIO; |
| 876 | } |
| 877 | |
| 878 | static inline int geni_se_iommu_map_buf(struct device *wrapper_dev, |
| 879 | dma_addr_t *iova, void *buf, size_t size, enum dma_data_direction dir) |
| 880 | { |
| 881 | return -ENXIO; |
| 882 | } |
| 883 | |
| 884 | static inline void *geni_se_iommu_alloc_buf(struct device *wrapper_dev, |
| 885 | dma_addr_t *iova, size_t size) |
| 886 | { |
| 887 | return NULL; |
| 888 | } |
| 889 | |
| 890 | static inline int geni_se_iommu_unmap_buf(struct device *wrapper_dev, |
| 891 | dma_addr_t *iova, size_t size, enum dma_data_direction dir) |
| 892 | { |
| 893 | return -ENXIO; |
| 894 | |
| 895 | } |
| 896 | |
| 897 | static inline int geni_se_iommu_free_buf(struct device *wrapper_dev, |
| 898 | dma_addr_t *iova, void *buf, size_t size) |
| 899 | { |
| 900 | return -ENXIO; |
| 901 | } |
| 902 | |
| 903 | #endif |
Sagar Dharia | 7c927c0 | 2016-11-23 11:51:43 -0700 | [diff] [blame] | 904 | #endif |