Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 1 | * CoreSight Components: |
| 2 | |
| 3 | CoreSight components are compliant with the ARM CoreSight architecture |
Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame] | 4 | specification and can be connected in various topologies to suite a particular |
| 5 | SoCs tracing needs. These trace components can generally be classified as sinks, |
| 6 | links and sources. Trace data produced by one or more sources flows through the |
| 7 | intermediate links connecting the source to the currently selected sink. Each |
| 8 | CoreSight component device should use these properties to describe its hardware |
| 9 | characteristcs. |
| 10 | |
| 11 | Required properties: |
| 12 | |
| 13 | - compatible : name of the component used for driver matching, should be one of |
| 14 | the following: |
| 15 | "arm,coresight-tmc" for coresight tmc-etr or tmc-etf device, |
| 16 | "arm,coresight-tpiu" for coresight tpiu device, |
| 17 | "qcom,coresight-replicator" for coresight replicator device, |
| 18 | "arm,coresight-funnel" for coresight funnel devices, |
| 19 | "qcom,coresight-tpda" for coresight tpda device, |
| 20 | "qcom,coresight-tpdm" for coresight tpdm device, |
| 21 | "qcom,coresight-dbgui" for coresight dbgui device |
| 22 | "arm,coresight-stm" for coresight stm trace device, |
| 23 | "arm,coresight-etm" for coresight etm trace devices, |
| 24 | "arm,coresight-etmv4" for coresight etmv4 trace devices, |
| 25 | "qcom,coresight-csr" for coresight csr device, |
| 26 | "arm,coresight-cti" for coresight cti devices, |
| 27 | "qcom,coresight-hwevent" for coresight hardware event devices |
| 28 | "arm,coresight-fuse" for coresight fuse v1 device, |
| 29 | "arm,coresight-fuse-v2" for coresight fuse v2 device, |
| 30 | "arm,coresight-fuse-v3" for coresight fuse v3 device, |
| 31 | "qcom,coresight-remote-etm" for coresight remote processor etm trace device, |
| 32 | "qcom,coresight-qpdi" for coresight qpdi device |
| 33 | - reg : physical base address and length of the register set(s) of the component. |
| 34 | Not required for the following compatible string: |
| 35 | - "qcom,coresight-remote-etm" |
| 36 | - reg-names : names corresponding to each reg property value. |
| 37 | Not required for the following compatible string: |
| 38 | - "qcom,coresight-remote-etm" |
| 39 | The reg-names that need to be used with corresponding compatible string |
| 40 | for a coresight device are: |
| 41 | - for coresight tmc-etr or tmc-etf device: |
| 42 | compatible : should be "arm,coresight-tmc" |
| 43 | reg-names : should be: |
| 44 | "tmc-base" - physical base address of tmc configuration |
| 45 | registers |
| 46 | "bam-base" - physical base address of tmc-etr bam registers |
| 47 | - for coresight tpiu device: |
| 48 | compatible : should be "arm,coresight-tpiu" |
| 49 | reg-names : should be: |
| 50 | "tpiu-base" - physical base address of tpiu registers |
| 51 | - for coresight replicator device |
| 52 | compatible : should be "qcom,coresight-replicator" |
| 53 | reg-names : should be: |
| 54 | "replicator-base" - physical base address of replicator |
| 55 | registers |
| 56 | - for coresight funnel devices |
| 57 | compatible : should be "arm,coresight-funnel" |
| 58 | reg-names : should be: |
| 59 | "funnel-base" - physical base address of funnel registers |
| 60 | - for coresight tpda trace device |
| 61 | compatible : should be "qcom,coresight-tpda" |
| 62 | reg-names : should be: |
| 63 | "tpda-base" - physical base address of tpda registers |
| 64 | - for coresight tpdm trace device |
| 65 | compatible : should be "qcom,coresight-tpdm" |
| 66 | reg-names : should be: |
| 67 | "tpdm-base" - physical base address of tpdm registers |
| 68 | - for coresight dbgui device: |
| 69 | compatible : should be "qcom,coresight-dbgui" |
| 70 | reg-names : should be: |
| 71 | "dbgui-base" - physical base address of dbgui registers |
| 72 | - for coresight stm trace device |
| 73 | compatible : should be "arm,coresight-stm" |
| 74 | reg-names : should be: |
| 75 | "stm-base" - physical base address of stm configuration |
| 76 | registers |
| 77 | "stm-data-base" - physical base address of stm data registers |
| 78 | - for coresight etm trace devices |
| 79 | compatible : should be "arm,coresight-etm" |
| 80 | reg-names : should be: |
| 81 | "etm-base" - physical base address of etm registers |
| 82 | - for coresight etmv4 trace devices |
| 83 | compatible : should be "arm,coresight-etmv4" |
| 84 | reg-names : should be: |
| 85 | "etm-base" - physical base address of etmv4 registers |
| 86 | - for coresight csr device: |
| 87 | compatible : should be "qcom,coresight-csr" |
| 88 | reg-names : should be: |
| 89 | "csr-base" - physical base address of csr registers |
| 90 | - for coresight cti devices: |
| 91 | compatible : should be "arm,coresight-cti" |
| 92 | reg-names : should be: |
| 93 | "cti<num>-base" - physical base address of cti registers |
| 94 | - for coresight hardware event devices: |
| 95 | compatible : should be "qcom,coresight-hwevent" |
| 96 | reg-names : should be: |
| 97 | "<ss-mux>" - physical base address of hardware event mux |
| 98 | control registers where <ss-mux> is subsystem mux it |
| 99 | represents |
| 100 | - for coresight fuse device: |
| 101 | compatible : should be "arm,coresight-fuse" |
| 102 | reg-names : should be: |
| 103 | "fuse-base" - physical base address of fuse registers |
| 104 | "nidnt-fuse-base" - physical base address of nidnt fuse registers |
| 105 | "qpdi-fuse-base" - physical base address of qpdi fuse registers |
| 106 | - for coresight qpdi device: |
| 107 | compatible : should be "qcom,coresight-qpdi" |
| 108 | reg-names : should be: |
| 109 | "qpdi-base" - physical base address of qpdi registers |
| 110 | - coresight-id : unique integer identifier for the component |
| 111 | - coresight-name : unique descriptive name of the component |
| 112 | - coresight-nr-inports : number of input ports on the component |
| 113 | |
| 114 | Optional properties: |
| 115 | |
| 116 | - coresight-outports : list of output port numbers of this component |
| 117 | - coresight-child-list : list of phandles pointing to the children of this |
| 118 | component |
| 119 | - coresight-child-ports : list of input port numbers of the children |
| 120 | - coresight-default-sink : represents the default compile time CoreSight sink |
| 121 | - coresight-ctis : list of ctis that this component interacts with |
| 122 | - qcom,cti-save : boolean, indicating cti context needs to be saved and restored |
| 123 | - qcom,cti-hwclk : boolean, indicating support of hardware clock to access cti |
| 124 | registers to be saved and restored |
| 125 | - qcom,cti-gpio-trigin : cti trigger input driven by gpio |
| 126 | - qcom,cti-gpio-trigout : cti trigger output sent to gpio |
| 127 | - qcom,pc-save : program counter save implemented |
| 128 | - qcom,blk-size : block size for tmc-etr to usb transfers |
| 129 | - qcom,memory-size : size of coherent memory to be allocated for tmc-etr buffer |
| 130 | - qcom,round-robin : indicates if per core etms are allowed round-robin access |
| 131 | by the funnel |
| 132 | - qcom,write-64bit : only 64bit data writes supported by stm |
| 133 | - qcom,data-barrier : barrier required for every stm data write to channel space |
| 134 | - <supply-name>-supply: phandle to the regulator device tree node. The required |
| 135 | <supply-name> is "vdd" for SD card and "vdd-io" for SD |
| 136 | I/O supply. Used for tpiu component |
| 137 | - qcom,<supply>-voltage-level : specifies voltage level for vdd supply. Should |
| 138 | be specified in pairs (min, max) with units |
| 139 | being uV. Here <supply> can be "vdd" for SD card |
| 140 | vdd supply or "vdd-io" for SD I/O vdd supply. |
| 141 | - qcom,<supply>-current-level : specifies current load levels for vdd supply. |
| 142 | Should be specified in pairs (lpm, hpm) with |
| 143 | units being uA. Here <supply> can be "vdd" for |
| 144 | SD card vdd supply or "vdd-io" for SD I/O vdd |
| 145 | supply. |
| 146 | - qcom,hwevent-clks : list of clocks required by hardware event driver |
| 147 | - qcom,hwevent-regs : list of regulators required by hardware event driver |
| 148 | - qcom,byte-cntr-absent : specifies if the byte counter feature is absent on |
| 149 | the device. Only relevant in case of tmc-etr device. |
| 150 | - interrupts : <a b c> where a is 0 or 1 depending on if the interrupt is |
| 151 | spi/ppi, b is the interrupt number and c is the mask, |
| 152 | - interrupt-names : a list of strings that map in order to the list of |
| 153 | interrupts specified in the 'interrupts' property. |
| 154 | - qcom,sg-enable : indicates whether scatter gather feature is supported for TMC |
| 155 | ETR configuration. |
| 156 | - qcom,force-reg-dump : boolean, indicate whether TMC register need to be dumped. |
| 157 | Used for TMC component |
| 158 | - qcom,nidntsw : boolean, indicating NIDnT software debug or trace support |
| 159 | present. Used for tpiu component |
| 160 | - qcom,nidnthw : boolean, indicating NIDnT hardware sensing support present. |
| 161 | Used for tpiu component |
| 162 | qcom,nidntsw and qcom,nidnthw are mutually exclusive properties, either of |
| 163 | these may specified for tpiu component |
| 164 | - qcom,nidnt-swduart : boolean, indicating NIDnT swd uart support present. Used |
| 165 | for tpiu component |
| 166 | - qcom,nidnt-swdtrc : boolean, indicating NIDnT swd trace support present. Used |
| 167 | for tpiu component |
| 168 | - qcom,nidnt-jtag : boolean, indicating NIDnT jtag debug support present. Used |
| 169 | for tpiu component |
| 170 | - qcom,nidnt-spmi : boolean, indicating NIDnT spmi debug support present. Used |
| 171 | for tpiu component |
| 172 | - nidnt-gpio : specifies gpio for NIDnT hardware detection |
| 173 | - nidnt-gpio-polarity : specifies gpio polarity for NIDnT hardware detection |
| 174 | - pinctrl-names : names corresponding to the numbered pinctrl. The allowed |
| 175 | names are subset of the following: cti-trigin-pctrl, |
| 176 | cti-trigout-pctrl. Used for cti component |
| 177 | - pinctrl-<n>: list of pinctrl phandles for the different pinctrl states. Refer |
| 178 | to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt". |
| 179 | - qcom,funnel-save-restore : boolean, indicating funnel port needs to be disabled |
| 180 | for the ETM whose CPU is being powered down. The port |
| 181 | state is restored when CPU is powered up. Used for |
| 182 | funnel component. |
| 183 | - qcom,tmc-flush-powerdown : boolean, indicating trace data needs to be flushed before |
| 184 | powering down CPU. Used for TMC component. |
| 185 | - qcom,bc-elem-size : specifies the BC element size supported by each monitor |
| 186 | connected to the aggregator on each port. Should be specified |
| 187 | in pairs (port, bc element size). |
| 188 | - qcom,tc-elem-size : specifies the TC element size supported by each monitor |
| 189 | connected to the aggregator on each port. Should be specified |
| 190 | in pairs (port, tc element size). |
| 191 | - qcom,dsb-elem-size : specifies the DSB element size supported by each monitor |
| 192 | connected to the aggregator on each port. Should be specified |
| 193 | in pairs (port, dsb element size). |
| 194 | - qcom,cmb-elem-size : specifies the CMB element size supported by each monitor |
| 195 | connected to the aggregator on each port. Should be specified |
| 196 | in pairs (port, cmb element size). |
| 197 | - qcom,clk-enable: specifies whether additional clock bit needs to be set for |
| 198 | M4M TPDM. |
| 199 | - qcom,tpda-atid : specifies the ATID for TPDA. |
| 200 | - qcom,inst-id : QMI instance id for remote ETMs. |
| 201 | - qcom,noovrflw-enable : boolean, indicating whether no overflow bit needs to be |
| 202 | set in ETM stall control register. |
| 203 | - coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true |
| 204 | - coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device |
| 205 | - qcom,dbgui-addr-offset : indicates the offset of dbgui address registers |
| 206 | - qcom,dbgui-data-offset : indicates the offset of dbgui data registers |
| 207 | - qcom,dbgui-size : indicates the size of dbgui address and data registers |
| 208 | - qcom,pmic-carddetect-gpio : indicates the hotplug capabilities of the qpdi driver |
| 209 | - qcom,cpuss-debug-cgc: debug clock gating phandle for etm |
| 210 | reg : the clock gating register for each cluster |
| 211 | cluster : indicate the cluster number |
| 212 | |
| 213 | coresight-outports, coresight-child-list and coresight-child-ports lists will |
| 214 | be of the same length and will have a one to one correspondence among the |
| 215 | elements at the same list index. |
| 216 | |
| 217 | coresight-default-sink must be specified for one of the sink devices that is |
| 218 | intended to be made the default sink. Other sink devices must not have this |
| 219 | specified. Not specifying this property on any of the sinks is invalid. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 220 | |
| 221 | * Required properties for all components *except* non-configurable replicators: |
| 222 | |
| 223 | * compatible: These have to be supplemented with "arm,primecell" as |
| 224 | drivers are using the AMBA bus interface. Possible values include: |
mathieu.poirier@linaro.org | 4b681ef | 2016-06-22 09:01:03 -0600 | [diff] [blame] | 225 | - Embedded Trace Buffer (version 1.0): |
| 226 | "arm,coresight-etb10", "arm,primecell"; |
| 227 | |
| 228 | - Trace Port Interface Unit: |
| 229 | "arm,coresight-tpiu", "arm,primecell"; |
| 230 | |
| 231 | - Trace Memory Controller, used for Embedded Trace Buffer(ETB), |
| 232 | Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) |
| 233 | configuration. The configuration mode (ETB, ETF, ETR) is |
| 234 | discovered at boot time when the device is probed. |
| 235 | "arm,coresight-tmc", "arm,primecell"; |
| 236 | |
| 237 | - Trace Funnel: |
| 238 | "arm,coresight-funnel", "arm,primecell"; |
| 239 | |
| 240 | - Embedded Trace Macrocell (version 3.x) and |
| 241 | Program Flow Trace Macrocell: |
| 242 | "arm,coresight-etm3x", "arm,primecell"; |
| 243 | |
| 244 | - Embedded Trace Macrocell (version 4.x): |
| 245 | "arm,coresight-etm4x", "arm,primecell"; |
| 246 | |
| 247 | - Qualcomm Configurable Replicator (version 1.x): |
| 248 | "qcom,coresight-replicator1x", "arm,primecell"; |
| 249 | |
| 250 | - System Trace Macrocell: |
| 251 | "arm,coresight-stm", "arm,primecell"; [1] |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 252 | - Trigger Generation Unit: |
| 253 | "arm,primecell"; |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 254 | |
| 255 | * reg: physical base address and length of the register |
| 256 | set(s) of the component. |
| 257 | |
Linus Walleij | 70dd9d2 | 2015-05-19 10:55:19 -0600 | [diff] [blame] | 258 | * clocks: the clocks associated to this component. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 259 | |
Linus Walleij | 70dd9d2 | 2015-05-19 10:55:19 -0600 | [diff] [blame] | 260 | * clock-names: the name of the clocks referenced by the code. |
| 261 | Since we are using the AMBA framework, the name of the clock |
| 262 | providing the interconnect should be "apb_pclk", and some |
| 263 | coresight blocks also have an additional clock "atclk", which |
| 264 | clocks the core of that coresight component. The latter clock |
| 265 | is optional. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 266 | |
| 267 | * port or ports: The representation of the component's port |
| 268 | layout using the generic DT graph presentation found in |
| 269 | "bindings/graph.txt". |
| 270 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 271 | * coresight-name: unique descriptive name of the component. |
| 272 | |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 273 | * Additional required properties for System Trace Macrocells (STM): |
| 274 | * reg: along with the physical base address and length of the register |
| 275 | set as described above, another entry is required to describe the |
| 276 | mapping of the extended stimulus port area. |
| 277 | |
| 278 | * reg-names: the only acceptable values are "stm-base" and |
| 279 | "stm-stimulus-base", each corresponding to the areas defined in "reg". |
| 280 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 281 | * Required properties for devices that don't show up on the AMBA bus, such as |
| 282 | non-configurable replicators: |
| 283 | |
| 284 | * compatible: Currently supported value is (note the absence of the |
| 285 | AMBA markee): |
| 286 | - "arm,coresight-replicator" |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 287 | - "qcom,coresight-csr" |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 288 | - "qcom,coresight-remote-etm" |
| 289 | - "qcom,coresight-hwevent" |
| 290 | - "qcom,coresight-dummy" |
Mukesh Ojha | 4350ecb | 2017-11-30 19:24:55 +0530 | [diff] [blame] | 291 | - "qcom,coresight-dbgui" |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 292 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 293 | * port or ports: same as above. |
| 294 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 295 | * coresight-name: unique descriptive name of the component. |
| 296 | |
Satyajit Desai | 80e47d4 | 2017-03-06 18:23:52 -0800 | [diff] [blame] | 297 | * Additional required property for coresight-dummy devices: |
| 298 | * qcom,dummy-source: Configure the device as source. |
| 299 | |
Satyajit Desai | f4c5ee9 | 2017-01-04 15:31:06 -0800 | [diff] [blame] | 300 | * qcom,dummy-sink: Configure the device as sink. |
| 301 | |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 302 | * Additional required property for coresight-tgu devices: |
| 303 | * tgu-steps: must be present. Indicates number of steps supported |
| 304 | by the TGU. |
| 305 | * tgu-conditions: must be present. Indicates the number of conditions |
| 306 | supported by the TGU. |
| 307 | * tgu-regs: must be present. Indicates the number of regs supported |
| 308 | by the TGU. |
| 309 | * tgu-timer-counters: must be present. Indicates the number of timers and |
| 310 | counters available in the TGU to do a comparision. |
| 311 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 312 | * Optional properties for all components: |
| 313 | * reg-names: names corresponding to each reg property value. |
| 314 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 315 | * Optional properties for ETM/PTMs: |
| 316 | |
| 317 | * arm,cp14: must be present if the system accesses ETM/PTM management |
| 318 | registers via co-processor 14. |
| 319 | |
| 320 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the |
| 321 | source is considered to belong to CPU0. |
| 322 | |
| 323 | * Optional property for TMC: |
| 324 | |
| 325 | * arm,buffer-size: size of contiguous buffer space for TMC ETR |
| 326 | (embedded trace router) |
| 327 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 328 | * arm,default-sink: represents the default compile time CoreSight sink |
| 329 | |
| 330 | * coresight-ctis: represents flush and reset CTIs for TMC buffer |
| 331 | |
| 332 | * qcom,force-reg-dump: enables TMC reg dump support |
| 333 | |
| 334 | * arm,sg-enable : indicates whether scatter gather feature is enabled |
| 335 | by default for TMC ETR configuration. |
| 336 | |
| 337 | * Required property for TPDAs: |
| 338 | |
| 339 | * qcom,tpda-atid: must be present. Specifies the ATID for TPDA. |
| 340 | |
| 341 | * Optional properties for TPDAs: |
| 342 | |
| 343 | * qcom,bc-elem-size: specifies the BC element size supported by each |
| 344 | monitor connected to the aggregator on each port. Should be specified |
| 345 | in pairs (port, bc element size). |
| 346 | |
| 347 | * qcom,tc-elem-size: specifies the TC element size supported by each |
| 348 | monitor connected to the aggregator on each port. Should be specified |
| 349 | in pairs (port, tc element size). |
| 350 | |
| 351 | * qcom,dsb-elem-size: specifies the DSB element size supported by each |
| 352 | monitor connected to the aggregator on each port. Should be specified |
| 353 | in pairs (port, dsb element size). |
| 354 | |
| 355 | * qcom,cmb-elem-size: specifies the CMB element size supported by each |
| 356 | monitor connected to the aggregator on each port. Should be specified |
| 357 | in pairs (port, cmb element size). |
| 358 | |
| 359 | * Optional properties for TPDM: |
| 360 | |
| 361 | * qcom,clk-enable: specifies whether additional clock bit needs to be |
| 362 | set for M4M TPDM. |
| 363 | |
| 364 | * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed |
| 365 | after enabling the subunit. |
| 366 | |
Satyajit Desai | 267d857 | 2017-10-26 15:21:07 -0700 | [diff] [blame] | 367 | * qcom,dump-enable: boolean, specifies to dump MCMB data. |
Satyajit Desai | e450813 | 2017-04-05 17:15:22 -0700 | [diff] [blame] | 368 | * Optional properties for CTI: |
| 369 | |
| 370 | * qcom,cti-gpio-trigin: cti trigger input driven by gpio. |
| 371 | |
| 372 | * qcom,cti-gpio-trigout: cti trigger output sent to gpio. |
| 373 | |
| 374 | * pinctrl-names: names corresponding to the numbered pinctrl. The |
| 375 | allowed names are subset of the following: cti-trigin-pinctrl, |
| 376 | cti-trigout-pctrl. |
| 377 | |
| 378 | * pinctrl-<n>: list of pinctrl phandles for the different pinctrl |
| 379 | states. Refer to |
| 380 | "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" |
| 381 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 382 | * Required property for Remote ETMs: |
| 383 | |
| 384 | * qcom,inst-id: must be present. QMI instance id for remote ETMs. |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 385 | |
Satyajit Desai | caa081f | 2017-06-15 14:54:27 -0700 | [diff] [blame] | 386 | * Optional properties for funnels: |
| 387 | |
| 388 | * qcom,duplicate-funnel: boolean, indicates its a duplicate of an |
| 389 | existing funnel. Funnel devices are now capable of supporting |
| 390 | multiple-input and multiple-output configuration with in built |
| 391 | hardware filtering for TPDM devices. Each set of input-output |
| 392 | combination is treated as independent funnel device. |
| 393 | funnel-base-dummy and funnel-base-real reg-names must be specified |
| 394 | when this property is enabled. |
| 395 | |
| 396 | * reg-names: funnel-base-dummy: dummy register space used by a |
| 397 | duplicate funnel. Should be a valid register address space that |
| 398 | no other device is using. |
| 399 | |
| 400 | * reg-names: funnel-base-real: actual register space for the |
| 401 | duplicate funnel. |
| 402 | |
Mulu He | 1a59c48 | 2017-12-26 19:32:58 +0800 | [diff] [blame] | 403 | * Optional properties for CSRs: |
| 404 | |
| 405 | * qcom,usb-bam-support: boolean, indicates CSR has the ability to operate on |
| 406 | usb bam, include enable,disable and flush. |
| 407 | |
| 408 | * qcom,hwctrl-set-support: boolean, indicates CSR has the ability to operate on |
| 409 | to "HWCTRL" register. |
| 410 | |
| 411 | * qcom,set-byte-cntr-support:boolean, indicates CSR has the ability to operate on |
| 412 | to "BYTECNT" register. |
| 413 | |
| 414 | * qcom,timestamp-support:boolean, indicates CSR support sys interface to read |
| 415 | timestamp value. |
| 416 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 417 | Example: |
| 418 | |
| 419 | 1. Sinks |
| 420 | etb@20010000 { |
| 421 | compatible = "arm,coresight-etb10", "arm,primecell"; |
| 422 | reg = <0 0x20010000 0 0x1000>; |
| 423 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 424 | clocks = <&oscclk6a>; |
| 425 | clock-names = "apb_pclk"; |
| 426 | port { |
| 427 | etb_in_port: endpoint@0 { |
| 428 | slave-mode; |
| 429 | remote-endpoint = <&replicator_out_port0>; |
| 430 | }; |
| 431 | }; |
| 432 | }; |
| 433 | |
| 434 | tpiu@20030000 { |
| 435 | compatible = "arm,coresight-tpiu", "arm,primecell"; |
| 436 | reg = <0 0x20030000 0 0x1000>; |
| 437 | |
| 438 | clocks = <&oscclk6a>; |
| 439 | clock-names = "apb_pclk"; |
| 440 | port { |
| 441 | tpiu_in_port: endpoint@0 { |
| 442 | slave-mode; |
| 443 | remote-endpoint = <&replicator_out_port1>; |
| 444 | }; |
| 445 | }; |
| 446 | }; |
| 447 | |
| 448 | 2. Links |
| 449 | replicator { |
| 450 | /* non-configurable replicators don't show up on the |
| 451 | * AMBA bus. As such no need to add "arm,primecell". |
| 452 | */ |
| 453 | compatible = "arm,coresight-replicator"; |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 454 | |
| 455 | ports { |
| 456 | #address-cells = <1>; |
| 457 | #size-cells = <0>; |
| 458 | |
| 459 | /* replicator output ports */ |
| 460 | port@0 { |
| 461 | reg = <0>; |
| 462 | replicator_out_port0: endpoint { |
| 463 | remote-endpoint = <&etb_in_port>; |
| 464 | }; |
| 465 | }; |
| 466 | |
| 467 | port@1 { |
| 468 | reg = <1>; |
| 469 | replicator_out_port1: endpoint { |
| 470 | remote-endpoint = <&tpiu_in_port>; |
| 471 | }; |
| 472 | }; |
| 473 | |
| 474 | /* replicator input port */ |
| 475 | port@2 { |
| 476 | reg = <0>; |
| 477 | replicator_in_port0: endpoint { |
| 478 | slave-mode; |
| 479 | remote-endpoint = <&funnel_out_port0>; |
| 480 | }; |
| 481 | }; |
| 482 | }; |
| 483 | }; |
| 484 | |
| 485 | funnel@20040000 { |
| 486 | compatible = "arm,coresight-funnel", "arm,primecell"; |
| 487 | reg = <0 0x20040000 0 0x1000>; |
| 488 | |
| 489 | clocks = <&oscclk6a>; |
| 490 | clock-names = "apb_pclk"; |
| 491 | ports { |
| 492 | #address-cells = <1>; |
| 493 | #size-cells = <0>; |
| 494 | |
| 495 | /* funnel output port */ |
| 496 | port@0 { |
| 497 | reg = <0>; |
| 498 | funnel_out_port0: endpoint { |
| 499 | remote-endpoint = |
| 500 | <&replicator_in_port0>; |
| 501 | }; |
| 502 | }; |
| 503 | |
| 504 | /* funnel input ports */ |
| 505 | port@1 { |
| 506 | reg = <0>; |
| 507 | funnel_in_port0: endpoint { |
| 508 | slave-mode; |
| 509 | remote-endpoint = <&ptm0_out_port>; |
| 510 | }; |
| 511 | }; |
| 512 | |
| 513 | port@2 { |
| 514 | reg = <1>; |
| 515 | funnel_in_port1: endpoint { |
| 516 | slave-mode; |
| 517 | remote-endpoint = <&ptm1_out_port>; |
| 518 | }; |
| 519 | }; |
| 520 | |
| 521 | port@3 { |
| 522 | reg = <2>; |
| 523 | funnel_in_port2: endpoint { |
| 524 | slave-mode; |
| 525 | remote-endpoint = <&etm0_out_port>; |
| 526 | }; |
| 527 | }; |
| 528 | |
| 529 | }; |
| 530 | }; |
| 531 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 532 | tpda_mss: tpda@7043000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 533 | compatible = "qcom,coresight-tpda", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 534 | reg = <0x7043000 0x1000>; |
| 535 | reg-names = "tpda-base"; |
| 536 | |
| 537 | coresight-name = "coresight-tpda-mss"; |
| 538 | |
| 539 | qcom,tpda-atid = <67>; |
| 540 | qcom,dsb-elem-size = <0 32>; |
| 541 | qcom,cmb-elem-size = <0 32>; |
| 542 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 543 | clocks = <&clock_aop clk_qdss_clk>; |
| 544 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 545 | |
| 546 | ports { |
| 547 | #address-cells = <1>; |
| 548 | #size-cells = <0>; |
| 549 | port@0 { |
| 550 | reg = <0>; |
| 551 | tpda_mss_out_funnel_in1: endpoint { |
| 552 | remote-endpoint = |
| 553 | <&funnel_in1_in_tpda_mss>; |
| 554 | }; |
| 555 | }; |
| 556 | port@1 { |
| 557 | reg = <0>; |
| 558 | tpda_mss_in_tpdm_mss: endpoint { |
| 559 | slave-mode; |
| 560 | remote-endpoint = |
| 561 | <&tpdm_mss_out_tpda_mss>; |
| 562 | }; |
| 563 | }; |
| 564 | }; |
| 565 | }; |
| 566 | |
Mathieu Poirier | 799656d | 2014-11-12 16:36:59 -0700 | [diff] [blame] | 567 | 3. Sources |
| 568 | ptm@2201c000 { |
| 569 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
| 570 | reg = <0 0x2201c000 0 0x1000>; |
| 571 | |
| 572 | cpu = <&cpu0>; |
| 573 | clocks = <&oscclk6a>; |
| 574 | clock-names = "apb_pclk"; |
| 575 | port { |
| 576 | ptm0_out_port: endpoint { |
| 577 | remote-endpoint = <&funnel_in_port0>; |
| 578 | }; |
| 579 | }; |
| 580 | }; |
| 581 | |
| 582 | ptm@2201d000 { |
| 583 | compatible = "arm,coresight-etm3x", "arm,primecell"; |
| 584 | reg = <0 0x2201d000 0 0x1000>; |
| 585 | |
| 586 | cpu = <&cpu1>; |
| 587 | clocks = <&oscclk6a>; |
| 588 | clock-names = "apb_pclk"; |
| 589 | port { |
| 590 | ptm1_out_port: endpoint { |
| 591 | remote-endpoint = <&funnel_in_port1>; |
| 592 | }; |
| 593 | }; |
| 594 | }; |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 595 | |
| 596 | 4. STM |
| 597 | stm@20100000 { |
| 598 | compatible = "arm,coresight-stm", "arm,primecell"; |
| 599 | reg = <0 0x20100000 0 0x1000>, |
| 600 | <0 0x28000000 0 0x180000>; |
| 601 | reg-names = "stm-base", "stm-stimulus-base"; |
| 602 | |
| 603 | clocks = <&soc_smc50mhz>; |
| 604 | clock-names = "apb_pclk"; |
| 605 | port { |
| 606 | stm_out_port: endpoint { |
| 607 | remote-endpoint = <&main_funnel_in_port2>; |
| 608 | }; |
| 609 | }; |
| 610 | }; |
| 611 | |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 612 | tpdm_mss: tpdm@7042000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 613 | compatible = "qcom,coresight-tpdm", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 614 | reg = <0x7042000 0x1000>; |
| 615 | reg-names = "tpdm-base"; |
| 616 | |
| 617 | coresight-name = "coresight-tpdm-mss"; |
| 618 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 619 | clocks = <&clock_aop qdss_clk>; |
| 620 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 621 | |
| 622 | port{ |
| 623 | tpdm_mss_out_tpda_mss: endpoint { |
| 624 | remote-endpoint = <&tpda_mss_in_tpdm_mss>; |
| 625 | }; |
| 626 | }; |
| 627 | }; |
| 628 | |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 629 | 5. CTIs |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 630 | cti0: cti@6010000 { |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 631 | compatible = "arm,coresight-cti", "arm,primecell"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 632 | reg = <0x6010000 0x1000>; |
| 633 | reg-names = "cti-base"; |
| 634 | |
| 635 | coresight-name = "coresight-cti0"; |
| 636 | |
Satyajit Desai | 045b56b | 2017-04-18 17:47:51 -0700 | [diff] [blame] | 637 | clocks = <&clock_aop qdss_clk>; |
| 638 | clock-names = "apb_pclk"; |
Satyajit Desai | 7bd8804 | 2016-09-15 12:01:50 -0700 | [diff] [blame] | 639 | }; |
| 640 | |
Rama Aparna Mallavarapu | a2a8e3e | 2017-08-16 20:56:00 -0700 | [diff] [blame] | 641 | 6. TGUs |
| 642 | ipcb_tgu: tgu@6b0c000 { |
| 643 | compatible = "arm,primecell"; |
| 644 | arm,primecell-periphid = <0x0003b999>; |
| 645 | reg = <0x06B0C000 0x1000>; |
| 646 | reg-names = "tgu-base"; |
| 647 | tgu-steps = <3>; |
| 648 | tgu-conditions = <4>; |
| 649 | tgu-regs = <4>; |
| 650 | tgu-timer-counters = <8>; |
| 651 | |
| 652 | coresight-name = "coresight-tgu-ipcb"; |
| 653 | |
| 654 | clocks = <&clock_aop QDSS_CLK>; |
| 655 | clock-names = "apb_pclk"; |
| 656 | }; |
Mathieu Poirier | 9eb9331 | 2016-05-03 11:33:39 -0600 | [diff] [blame] | 657 | [1]. There is currently two version of STM: STM32 and STM500. Both |
| 658 | have the same HW interface and as such don't need an explicit binding name. |