Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
Paul Walmsley | 8c34974 | 2010-02-22 22:09:24 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
| 10 | * |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | #undef DEBUG |
| 16 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 17 | #include <linux/kernel.h> |
Paul Walmsley | 1fe9be8 | 2012-09-27 10:33:33 -0600 | [diff] [blame] | 18 | #include <linux/export.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 19 | #include <linux/list.h> |
| 20 | #include <linux/errno.h> |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 21 | #include <linux/err.h> |
| 22 | #include <linux/delay.h> |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 23 | #include <linux/clk-provider.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 24 | #include <linux/io.h> |
Russell King | fbd3bdb | 2008-09-06 12:13:59 +0100 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 26 | #include <linux/regmap.h> |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 27 | #include <linux/of_address.h> |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 28 | #include <linux/bootmem.h> |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 29 | #include <asm/cpu.h> |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 30 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include <trace/events/power.h> |
| 32 | |
| 33 | #include "soc.h" |
| 34 | #include "clockdomain.h" |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 35 | #include "clock.h" |
Paul Walmsley | c4ceedc | 2012-10-29 20:56:29 -0600 | [diff] [blame] | 36 | #include "cm.h" |
Paul Walmsley | ff4ae5d | 2012-10-21 01:01:11 -0600 | [diff] [blame] | 37 | #include "cm2xxx.h" |
| 38 | #include "cm3xxx.h" |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 39 | #include "cm-regbits-24xx.h" |
| 40 | #include "cm-regbits-34xx.h" |
Paul Walmsley | c4ceedc | 2012-10-29 20:56:29 -0600 | [diff] [blame] | 41 | #include "common.h" |
| 42 | |
Afzal Mohammed | 9954119 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 43 | u16 cpu_mask; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 44 | |
Tero Kristo | a24886e | 2014-07-02 11:47:40 +0300 | [diff] [blame] | 45 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ |
| 46 | #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 |
| 47 | #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 |
| 48 | #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 |
| 49 | #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 |
| 50 | |
| 51 | /* |
| 52 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. |
| 53 | * From device data manual section 4.3 "DPLL and DLL Specifications". |
| 54 | */ |
| 55 | #define OMAP3PLUS_DPLL_FINT_MIN 32000 |
| 56 | #define OMAP3PLUS_DPLL_FINT_MAX 52000000 |
| 57 | |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 58 | struct clk_iomap { |
| 59 | struct regmap *regmap; |
| 60 | void __iomem *mem; |
| 61 | }; |
| 62 | |
| 63 | static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 64 | |
| 65 | static void clk_memmap_writel(u32 val, void __iomem *reg) |
| 66 | { |
| 67 | struct clk_omap_reg *r = (struct clk_omap_reg *)® |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 68 | struct clk_iomap *io = clk_memmaps[r->index]; |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 69 | |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 70 | if (io->regmap) |
| 71 | regmap_write(io->regmap, r->offset, val); |
| 72 | else |
| 73 | writel_relaxed(val, io->mem + r->offset); |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | static u32 clk_memmap_readl(void __iomem *reg) |
| 77 | { |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 78 | u32 val; |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 79 | struct clk_omap_reg *r = (struct clk_omap_reg *)® |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 80 | struct clk_iomap *io = clk_memmaps[r->index]; |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 81 | |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 82 | if (io->regmap) |
| 83 | regmap_read(io->regmap, r->offset, &val); |
| 84 | else |
| 85 | val = readl_relaxed(io->mem + r->offset); |
| 86 | |
| 87 | return val; |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 88 | } |
Tero Kristo | 3ada6b10 | 2013-10-22 11:47:08 +0300 | [diff] [blame] | 89 | |
| 90 | void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) |
| 91 | { |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 92 | if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) |
Tero Kristo | 3ada6b10 | 2013-10-22 11:47:08 +0300 | [diff] [blame] | 93 | writel_relaxed(val, reg); |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 94 | else |
| 95 | clk_memmap_writel(val, reg); |
Tero Kristo | 3ada6b10 | 2013-10-22 11:47:08 +0300 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) |
| 99 | { |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 100 | if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) |
| 101 | return readl_relaxed(reg); |
| 102 | else |
| 103 | return clk_memmap_readl(reg); |
| 104 | } |
Tero Kristo | 3ada6b10 | 2013-10-22 11:47:08 +0300 | [diff] [blame] | 105 | |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 106 | static struct ti_clk_ll_ops omap_clk_ll_ops = { |
| 107 | .clk_readl = clk_memmap_readl, |
| 108 | .clk_writel = clk_memmap_writel, |
Tero Kristo | 9a356d6 | 2015-03-03 11:14:31 +0200 | [diff] [blame] | 109 | .clkdm_clk_enable = clkdm_clk_enable, |
| 110 | .clkdm_clk_disable = clkdm_clk_disable, |
Tero Kristo | 192383d | 2015-03-03 13:47:08 +0200 | [diff] [blame] | 111 | .cm_wait_module_ready = omap_cm_wait_module_ready, |
| 112 | .cm_split_idlest_reg = cm_split_idlest_reg, |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 113 | }; |
Tero Kristo | 3ada6b10 | 2013-10-22 11:47:08 +0300 | [diff] [blame] | 114 | |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 115 | /** |
Tero Kristo | e9e6308 | 2015-04-27 21:55:42 +0300 | [diff] [blame^] | 116 | * omap2_clk_setup_ll_ops - setup clock driver low-level ops |
| 117 | * |
| 118 | * Sets up clock driver low-level platform ops. These are needed |
| 119 | * for register accesses and various other misc platform operations. |
| 120 | * Returns 0 on success, -EBUSY if low level ops have been registered |
| 121 | * already. |
| 122 | */ |
| 123 | int __init omap2_clk_setup_ll_ops(void) |
| 124 | { |
| 125 | return ti_clk_setup_ll_ops(&omap_clk_ll_ops); |
| 126 | } |
| 127 | |
| 128 | /** |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 129 | * omap2_clk_provider_init - initialize a clock provider |
| 130 | * @match_table: DT device table to match for devices to init |
| 131 | * @np: device node pointer for the this clock provider |
| 132 | * @index: index for the clock provider |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 133 | + @syscon: syscon regmap pointer |
| 134 | * @mem: iomem pointer for the clock provider memory area, only used if |
| 135 | * syscon is not provided |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 136 | * |
| 137 | * Initializes a clock provider module (CM/PRM etc.), registering |
| 138 | * the memory mapping at specified index and initializing the |
| 139 | * low level driver infrastructure. Returns 0 in success. |
| 140 | */ |
| 141 | int __init omap2_clk_provider_init(struct device_node *np, int index, |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 142 | struct regmap *syscon, void __iomem *mem) |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 143 | { |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 144 | struct clk_iomap *io; |
| 145 | |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 146 | io = kzalloc(sizeof(*io), GFP_KERNEL); |
| 147 | |
| 148 | io->regmap = syscon; |
| 149 | io->mem = mem; |
| 150 | |
| 151 | clk_memmaps[index] = io; |
Tero Kristo | 9f029b1 | 2014-10-22 15:15:36 +0300 | [diff] [blame] | 152 | |
| 153 | ti_dt_clk_init_provider(np, index); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | /** |
| 159 | * omap2_clk_legacy_provider_init - initialize a legacy clock provider |
| 160 | * @index: index for the clock provider |
| 161 | * @mem: iomem pointer for the clock provider memory area |
| 162 | * |
| 163 | * Initializes a legacy clock provider memory mapping. |
| 164 | */ |
| 165 | void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) |
| 166 | { |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 167 | struct clk_iomap *io; |
| 168 | |
Tero Kristo | 80cbb22 | 2015-02-06 16:00:32 +0200 | [diff] [blame] | 169 | io = memblock_virt_alloc(sizeof(*io), 0); |
| 170 | |
| 171 | io->mem = mem; |
| 172 | |
| 173 | clk_memmaps[index] = io; |
Tero Kristo | 3ada6b10 | 2013-10-22 11:47:08 +0300 | [diff] [blame] | 174 | } |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 175 | |
| 176 | /* |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 177 | * OMAP2+ specific clock functions |
| 178 | */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 179 | |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 180 | /* Private functions */ |
| 181 | |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 182 | /* Public functions */ |
| 183 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 184 | /** |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 185 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
| 186 | * @clk: OMAP clock struct ptr to use |
| 187 | * |
| 188 | * Convert a clockdomain name stored in a struct clk 'clk' into a |
| 189 | * clockdomain pointer, and save it into the struct clk. Intended to be |
| 190 | * called during clk_register(). No return value. |
| 191 | */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 192 | void omap2_init_clk_clkdm(struct clk_hw *hw) |
| 193 | { |
| 194 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 195 | struct clockdomain *clkdm; |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 196 | const char *clk_name; |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 197 | |
| 198 | if (!clk->clkdm_name) |
| 199 | return; |
| 200 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 201 | clk_name = __clk_get_name(hw->clk); |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 202 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 203 | clkdm = clkdm_lookup(clk->clkdm_name); |
| 204 | if (clkdm) { |
| 205 | pr_debug("clock: associated clk %s to clkdm %s\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 206 | clk_name, clk->clkdm_name); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 207 | clk->clkdm = clkdm; |
| 208 | } else { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 209 | pr_debug("clock: could not associate clk %s to clkdm %s\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 210 | clk_name, clk->clkdm_name); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 211 | } |
| 212 | } |
| 213 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 214 | static int __initdata mpurate; |
| 215 | |
| 216 | /* |
| 217 | * By default we use the rate set by the bootloader. |
| 218 | * You can override this with mpurate= cmdline option. |
| 219 | */ |
| 220 | static int __init omap_clk_setup(char *str) |
| 221 | { |
| 222 | get_option(&str, &mpurate); |
| 223 | |
| 224 | if (!mpurate) |
| 225 | return 1; |
| 226 | |
| 227 | if (mpurate < 1000) |
| 228 | mpurate *= 1000000; |
| 229 | |
| 230 | return 1; |
| 231 | } |
| 232 | __setup("mpurate=", omap_clk_setup); |
| 233 | |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 234 | /** |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 235 | * omap2_clk_print_new_rates - print summary of current clock tree rates |
| 236 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator |
| 237 | * @core_ck_name: clk name for the on-chip CORE_CLK |
| 238 | * @mpu_ck_name: clk name for the ARM MPU clock |
| 239 | * |
| 240 | * Prints a short message to the console with the HFCLKIN oscillator |
| 241 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. |
| 242 | * Called by the boot-time MPU rate switching code. XXX This is intended |
| 243 | * to be handled by the OPP layer code in the near future and should be |
| 244 | * removed from the clock code. No return value. |
| 245 | */ |
| 246 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, |
| 247 | const char *core_ck_name, |
| 248 | const char *mpu_ck_name) |
| 249 | { |
| 250 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; |
| 251 | unsigned long hfclkin_rate; |
| 252 | |
| 253 | mpu_ck = clk_get(NULL, mpu_ck_name); |
| 254 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) |
| 255 | return; |
| 256 | |
| 257 | core_ck = clk_get(NULL, core_ck_name); |
| 258 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) |
| 259 | return; |
| 260 | |
| 261 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); |
| 262 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) |
| 263 | return; |
| 264 | |
| 265 | hfclkin_rate = clk_get_rate(hfclkin_ck); |
| 266 | |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 267 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 268 | (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 269 | (clk_get_rate(core_ck) / 1000000), |
| 270 | (clk_get_rate(mpu_ck) / 1000000)); |
| 271 | } |
Tero Kristo | 8111e01 | 2014-07-02 11:47:39 +0300 | [diff] [blame] | 272 | |
| 273 | /** |
| 274 | * ti_clk_init_features - init clock features struct for the SoC |
| 275 | * |
| 276 | * Initializes the clock features struct based on the SoC type. |
| 277 | */ |
| 278 | void __init ti_clk_init_features(void) |
| 279 | { |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 280 | struct ti_clk_features features = { 0 }; |
Tero Kristo | a24886e | 2014-07-02 11:47:40 +0300 | [diff] [blame] | 281 | /* Fint setup for DPLLs */ |
| 282 | if (cpu_is_omap3430()) { |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 283 | features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; |
| 284 | features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; |
| 285 | features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; |
| 286 | features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; |
Tero Kristo | a24886e | 2014-07-02 11:47:40 +0300 | [diff] [blame] | 287 | } else { |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 288 | features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; |
| 289 | features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; |
Tero Kristo | a24886e | 2014-07-02 11:47:40 +0300 | [diff] [blame] | 290 | } |
Tero Kristo | 512d91c | 2014-07-02 11:47:42 +0300 | [diff] [blame] | 291 | |
| 292 | /* Bypass value setup for DPLLs */ |
| 293 | if (cpu_is_omap24xx()) { |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 294 | features.dpll_bypass_vals |= |
Tero Kristo | 512d91c | 2014-07-02 11:47:42 +0300 | [diff] [blame] | 295 | (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | |
| 296 | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); |
| 297 | } else if (cpu_is_omap34xx()) { |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 298 | features.dpll_bypass_vals |= |
Tero Kristo | 512d91c | 2014-07-02 11:47:42 +0300 | [diff] [blame] | 299 | (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | |
| 300 | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); |
| 301 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || |
| 302 | soc_is_omap54xx() || soc_is_dra7xx()) { |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 303 | features.dpll_bypass_vals |= |
Tero Kristo | 512d91c | 2014-07-02 11:47:42 +0300 | [diff] [blame] | 304 | (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | |
| 305 | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | |
| 306 | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); |
| 307 | } |
Tero Kristo | 2337c5b | 2014-07-02 11:47:43 +0300 | [diff] [blame] | 308 | |
| 309 | /* Jitter correction only available on OMAP343X */ |
| 310 | if (cpu_is_omap343x()) |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 311 | features.flags |= TI_CLK_DPLL_HAS_FREQSEL; |
Tero Kristo | 066edb2 | 2014-07-02 11:47:44 +0300 | [diff] [blame] | 312 | |
| 313 | /* Idlest value for interface clocks. |
| 314 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 315 | * 34xx reverses this, just to keep us on our toes |
| 316 | * AM35xx uses both, depending on the module. |
| 317 | */ |
| 318 | if (cpu_is_omap24xx()) |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 319 | features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; |
Tero Kristo | 066edb2 | 2014-07-02 11:47:44 +0300 | [diff] [blame] | 320 | else if (cpu_is_omap34xx()) |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 321 | features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; |
Tero Kristo | f0d2f68 | 2014-10-03 16:57:10 +0300 | [diff] [blame] | 322 | |
| 323 | /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ |
| 324 | if (omap_rev() == OMAP3430_REV_ES1_0) |
Tero Kristo | f3b19aa | 2015-02-27 17:54:14 +0200 | [diff] [blame] | 325 | features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; |
| 326 | |
| 327 | ti_clk_setup_features(&features); |
Tero Kristo | 8111e01 | 2014-07-02 11:47:39 +0300 | [diff] [blame] | 328 | } |