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Rafał Miłecki8369ae32011-05-09 18:56:46 +02001/*
2 * Broadcom specific AMBA
3 * ChipCommon core driver
4 *
5 * Copyright 2005, Broadcom Corporation
Michael Büscheb032b92011-07-04 20:50:05 +02006 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
Rafał Miłecki8369ae32011-05-09 18:56:46 +02007 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "bcma_private.h"
Paul Gortmaker44a8e372011-07-27 21:21:04 -040012#include <linux/export.h>
Rafał Miłecki8369ae32011-05-09 18:56:46 +020013#include <linux/bcma/bcma.h>
14
15static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
16 u32 mask, u32 value)
17{
18 value &= mask;
19 value |= bcma_cc_read32(cc, offset) & ~mask;
20 bcma_cc_write32(cc, offset, value);
21
22 return value;
23}
24
25void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
26{
Rafał Miłecki18dfa492011-07-14 21:49:19 +020027 u32 leddc_on = 10;
28 u32 leddc_off = 90;
29
Hauke Mehrtens517f43e2011-07-23 01:20:07 +020030 if (cc->setup_done)
31 return;
32
Hauke Mehrtensef85fb22012-11-20 22:24:27 +000033 spin_lock_init(&cc->gpio_lock);
34
Rafał Miłecki8369ae32011-05-09 18:56:46 +020035 if (cc->core->id.rev >= 11)
36 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
37 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
38 if (cc->core->id.rev >= 35)
39 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
40
Rafał Miłecki1073e4e2011-05-11 02:08:09 +020041 if (cc->core->id.rev >= 20) {
42 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
43 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
44 }
Rafał Miłecki8369ae32011-05-09 18:56:46 +020045
46 if (cc->capabilities & BCMA_CC_CAP_PMU)
47 bcma_pmu_init(cc);
48 if (cc->capabilities & BCMA_CC_CAP_PCTL)
Rafał Miłecki3d9d8af2012-07-05 22:07:32 +020049 bcma_err(cc->core->bus, "Power control not implemented!\n");
Rafał Miłecki18dfa492011-07-14 21:49:19 +020050
51 if (cc->core->id.rev >= 16) {
52 if (cc->core->bus->sprom.leddc_on_time &&
53 cc->core->bus->sprom.leddc_off_time) {
54 leddc_on = cc->core->bus->sprom.leddc_on_time;
55 leddc_off = cc->core->bus->sprom.leddc_off_time;
56 }
57 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
58 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
59 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
60 }
Hauke Mehrtens517f43e2011-07-23 01:20:07 +020061
62 cc->setup_done = true;
Rafał Miłecki8369ae32011-05-09 18:56:46 +020063}
64
65/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
66void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
67{
68 /* instant NMI */
69 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
70}
71
72void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
73{
74 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
75}
76
77u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
78{
79 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
80}
81
82u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
83{
84 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
85}
86
87u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
88{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +000089 unsigned long flags;
90 u32 res;
91
92 spin_lock_irqsave(&cc->gpio_lock, flags);
93 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
94 spin_unlock_irqrestore(&cc->gpio_lock, flags);
95
96 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +020097}
98
99u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
100{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000101 unsigned long flags;
102 u32 res;
103
104 spin_lock_irqsave(&cc->gpio_lock, flags);
105 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
106 spin_unlock_irqrestore(&cc->gpio_lock, flags);
107
108 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200109}
110
111u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
112{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000113 unsigned long flags;
114 u32 res;
115
116 spin_lock_irqsave(&cc->gpio_lock, flags);
117 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
118 spin_unlock_irqrestore(&cc->gpio_lock, flags);
119
120 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200121}
122EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
123
124u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
125{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000126 unsigned long flags;
127 u32 res;
128
129 spin_lock_irqsave(&cc->gpio_lock, flags);
130 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
131 spin_unlock_irqrestore(&cc->gpio_lock, flags);
132
133 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200134}
135
136u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
137{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000138 unsigned long flags;
139 u32 res;
140
141 spin_lock_irqsave(&cc->gpio_lock, flags);
142 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
143 spin_unlock_irqrestore(&cc->gpio_lock, flags);
144
145 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200146}
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200147
Hauke Mehrtensea3488f2012-11-20 22:24:28 +0000148u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
149{
150 unsigned long flags;
151 u32 res;
152
153 if (cc->core->id.rev < 20)
154 return 0;
155
156 spin_lock_irqsave(&cc->gpio_lock, flags);
157 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
158 spin_unlock_irqrestore(&cc->gpio_lock, flags);
159
160 return res;
161}
162
163u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
164{
165 unsigned long flags;
166 u32 res;
167
168 if (cc->core->id.rev < 20)
169 return 0;
170
171 spin_lock_irqsave(&cc->gpio_lock, flags);
172 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
173 spin_unlock_irqrestore(&cc->gpio_lock, flags);
174
175 return res;
176}
177
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200178#ifdef CONFIG_BCMA_DRIVER_MIPS
179void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
180{
181 unsigned int irq;
182 u32 baud_base;
183 u32 i;
184 unsigned int ccrev = cc->core->id.rev;
185 struct bcma_serial_port *ports = cc->serial_ports;
186
187 if (ccrev >= 11 && ccrev != 15) {
188 /* Fixed ALP clock */
189 baud_base = bcma_pmu_alp_clock(cc);
190 if (ccrev >= 21) {
191 /* Turn off UART clock before switching clocksource. */
192 bcma_cc_write32(cc, BCMA_CC_CORECTL,
193 bcma_cc_read32(cc, BCMA_CC_CORECTL)
194 & ~BCMA_CC_CORECTL_UARTCLKEN);
195 }
196 /* Set the override bit so we don't divide it */
197 bcma_cc_write32(cc, BCMA_CC_CORECTL,
198 bcma_cc_read32(cc, BCMA_CC_CORECTL)
199 | BCMA_CC_CORECTL_UARTCLK0);
200 if (ccrev >= 21) {
201 /* Re-enable the UART clock. */
202 bcma_cc_write32(cc, BCMA_CC_CORECTL,
203 bcma_cc_read32(cc, BCMA_CC_CORECTL)
204 | BCMA_CC_CORECTL_UARTCLKEN);
205 }
206 } else {
Rafał Miłecki9a89c3a2012-07-09 19:34:59 +0200207 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200208 return;
209 }
210
211 irq = bcma_core_mips_irq(cc->core);
212
213 /* Determine the registers of the UARTs */
214 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
215 for (i = 0; i < cc->nr_serial_ports; i++) {
216 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
217 (i * 256);
218 ports[i].irq = irq;
219 ports[i].baud_base = baud_base;
220 ports[i].reg_shift = 0;
221 }
222}
223#endif /* CONFIG_BCMA_DRIVER_MIPS */