Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved. |
| 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 5 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 9 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 17 | */ |
| 18 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 19 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 20 | #include <linux/sort.h> |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 21 | #include <linux/debugfs.h> |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 22 | #include <linux/ktime.h> |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 23 | #include <uapi/drm/sde_drm.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 24 | #include <drm/drm_mode.h> |
| 25 | #include <drm/drm_crtc.h> |
| 26 | #include <drm/drm_crtc_helper.h> |
| 27 | #include <drm/drm_flip_work.h> |
| 28 | |
| 29 | #include "sde_kms.h" |
| 30 | #include "sde_hw_lm.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 31 | #include "sde_hw_ctl.h" |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 32 | #include "sde_crtc.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 33 | #include "sde_plane.h" |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 34 | #include "sde_color_processing.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 35 | #include "sde_encoder.h" |
| 36 | #include "sde_connector.h" |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 37 | #include "sde_power_handle.h" |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 38 | #include "sde_core_perf.h" |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 39 | #include "sde_trace.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 40 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 41 | struct sde_crtc_irq_info { |
| 42 | struct sde_irq_callback irq; |
| 43 | u32 event; |
| 44 | int (*func)(struct drm_crtc *crtc, bool en, |
| 45 | struct sde_irq_callback *irq); |
| 46 | struct list_head list; |
| 47 | }; |
| 48 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 49 | struct sde_crtc_custom_events { |
| 50 | u32 event; |
| 51 | int (*func)(struct drm_crtc *crtc, bool en, |
| 52 | struct sde_irq_callback *irq); |
| 53 | }; |
| 54 | |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 55 | static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm, |
| 56 | bool en, struct sde_irq_callback *ad_irq); |
| 57 | |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 58 | static int sde_crtc_pm_event_handler(struct drm_crtc *crtc_drm, |
| 59 | bool en, struct sde_irq_callback *noirq); |
| 60 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 61 | static struct sde_crtc_custom_events custom_events[] = { |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 62 | {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt}, |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 63 | {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler}, |
| 64 | {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler}, |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 65 | }; |
| 66 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 67 | /* default input fence timeout, in ms */ |
| 68 | #define SDE_CRTC_INPUT_FENCE_TIMEOUT 2000 |
| 69 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 70 | /* |
| 71 | * The default input fence timeout is 2 seconds while max allowed |
| 72 | * range is 10 seconds. Any value above 10 seconds adds glitches beyond |
| 73 | * tolerance limit. |
| 74 | */ |
| 75 | #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000 |
| 76 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 77 | /* layer mixer index on sde_crtc */ |
| 78 | #define LEFT_MIXER 0 |
| 79 | #define RIGHT_MIXER 1 |
| 80 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 81 | #define MISR_BUFF_SIZE 256 |
| 82 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 83 | static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 84 | { |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 85 | struct msm_drm_private *priv; |
| 86 | |
| 87 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 88 | SDE_ERROR("invalid crtc\n"); |
| 89 | return NULL; |
| 90 | } |
| 91 | priv = crtc->dev->dev_private; |
| 92 | if (!priv || !priv->kms) { |
| 93 | SDE_ERROR("invalid kms\n"); |
| 94 | return NULL; |
| 95 | } |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 96 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 97 | return to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 98 | } |
| 99 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 100 | static inline int _sde_crtc_power_enable(struct sde_crtc *sde_crtc, bool enable) |
| 101 | { |
| 102 | struct drm_crtc *crtc; |
| 103 | struct msm_drm_private *priv; |
| 104 | struct sde_kms *sde_kms; |
| 105 | |
| 106 | if (!sde_crtc) { |
| 107 | SDE_ERROR("invalid sde crtc\n"); |
| 108 | return -EINVAL; |
| 109 | } |
| 110 | |
| 111 | crtc = &sde_crtc->base; |
| 112 | if (!crtc->dev || !crtc->dev->dev_private) { |
| 113 | SDE_ERROR("invalid drm device\n"); |
| 114 | return -EINVAL; |
| 115 | } |
| 116 | |
| 117 | priv = crtc->dev->dev_private; |
| 118 | if (!priv->kms) { |
| 119 | SDE_ERROR("invalid kms\n"); |
| 120 | return -EINVAL; |
| 121 | } |
| 122 | |
| 123 | sde_kms = to_sde_kms(priv->kms); |
| 124 | |
| 125 | return sde_power_resource_enable(&priv->phandle, sde_kms->core_client, |
| 126 | enable); |
| 127 | } |
| 128 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 129 | /** |
| 130 | * _sde_crtc_rp_to_crtc - get crtc from resource pool object |
| 131 | * @rp: Pointer to resource pool |
| 132 | * return: Pointer to drm crtc if success; null otherwise |
| 133 | */ |
| 134 | static struct drm_crtc *_sde_crtc_rp_to_crtc(struct sde_crtc_respool *rp) |
| 135 | { |
| 136 | if (!rp) |
| 137 | return NULL; |
| 138 | |
| 139 | return container_of(rp, struct sde_crtc_state, rp)->base.crtc; |
| 140 | } |
| 141 | |
| 142 | /** |
| 143 | * _sde_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool |
| 144 | * @rp: Pointer to resource pool |
| 145 | * @force: True to reclaim all resources; otherwise, reclaim only unused ones |
| 146 | * return: None |
| 147 | */ |
| 148 | static void _sde_crtc_rp_reclaim(struct sde_crtc_respool *rp, bool force) |
| 149 | { |
| 150 | struct sde_crtc_res *res, *next; |
| 151 | struct drm_crtc *crtc; |
| 152 | |
| 153 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 154 | if (!crtc) { |
| 155 | SDE_ERROR("invalid crtc\n"); |
| 156 | return; |
| 157 | } |
| 158 | |
| 159 | SDE_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id, |
| 160 | force ? "destroy" : "free_unused"); |
| 161 | |
| 162 | list_for_each_entry_safe(res, next, &rp->res_list, list) { |
| 163 | if (!force && !(res->flags & SDE_CRTC_RES_FLAG_FREE)) |
| 164 | continue; |
| 165 | SDE_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n", |
| 166 | crtc->base.id, rp->sequence_id, |
| 167 | res->type, res->tag, res->val, |
| 168 | atomic_read(&res->refcount)); |
| 169 | list_del(&res->list); |
| 170 | if (res->ops.put) |
| 171 | res->ops.put(res->val); |
| 172 | kfree(res); |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | /** |
| 177 | * _sde_crtc_rp_free_unused - free unused resource in pool |
| 178 | * @rp: Pointer to resource pool |
| 179 | * return: none |
| 180 | */ |
| 181 | static void _sde_crtc_rp_free_unused(struct sde_crtc_respool *rp) |
| 182 | { |
| 183 | _sde_crtc_rp_reclaim(rp, false); |
| 184 | } |
| 185 | |
| 186 | /** |
| 187 | * _sde_crtc_rp_destroy - destroy resource pool |
| 188 | * @rp: Pointer to resource pool |
| 189 | * return: None |
| 190 | */ |
| 191 | static void _sde_crtc_rp_destroy(struct sde_crtc_respool *rp) |
| 192 | { |
| 193 | _sde_crtc_rp_reclaim(rp, true); |
| 194 | } |
| 195 | |
| 196 | /** |
| 197 | * _sde_crtc_hw_blk_get - get callback for hardware block |
| 198 | * @val: Resource handle |
| 199 | * @type: Resource type |
| 200 | * @tag: Search tag for given resource |
| 201 | * return: Resource handle |
| 202 | */ |
| 203 | static void *_sde_crtc_hw_blk_get(void *val, u32 type, u64 tag) |
| 204 | { |
| 205 | SDE_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val); |
| 206 | return sde_hw_blk_get(val, type, tag); |
| 207 | } |
| 208 | |
| 209 | /** |
| 210 | * _sde_crtc_hw_blk_put - put callback for hardware block |
| 211 | * @val: Resource handle |
| 212 | * return: None |
| 213 | */ |
| 214 | static void _sde_crtc_hw_blk_put(void *val) |
| 215 | { |
| 216 | SDE_DEBUG("res://%pK\n", val); |
| 217 | sde_hw_blk_put(val); |
| 218 | } |
| 219 | |
| 220 | /** |
| 221 | * _sde_crtc_rp_duplicate - duplicate resource pool and reset reference count |
| 222 | * @rp: Pointer to original resource pool |
| 223 | * @dup_rp: Pointer to duplicated resource pool |
| 224 | * return: None |
| 225 | */ |
| 226 | static void _sde_crtc_rp_duplicate(struct sde_crtc_respool *rp, |
| 227 | struct sde_crtc_respool *dup_rp) |
| 228 | { |
| 229 | struct sde_crtc_res *res, *dup_res; |
| 230 | struct drm_crtc *crtc; |
| 231 | |
| 232 | if (!rp || !dup_rp) { |
| 233 | SDE_ERROR("invalid resource pool\n"); |
| 234 | return; |
| 235 | } |
| 236 | |
| 237 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 238 | if (!crtc) { |
| 239 | SDE_ERROR("invalid crtc\n"); |
| 240 | return; |
| 241 | } |
| 242 | |
| 243 | SDE_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id); |
| 244 | |
| 245 | dup_rp->sequence_id = rp->sequence_id + 1; |
| 246 | INIT_LIST_HEAD(&dup_rp->res_list); |
| 247 | dup_rp->ops = rp->ops; |
| 248 | list_for_each_entry(res, &rp->res_list, list) { |
| 249 | dup_res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL); |
| 250 | if (!dup_res) |
| 251 | return; |
| 252 | INIT_LIST_HEAD(&dup_res->list); |
| 253 | atomic_set(&dup_res->refcount, 0); |
| 254 | dup_res->type = res->type; |
| 255 | dup_res->tag = res->tag; |
| 256 | dup_res->val = res->val; |
| 257 | dup_res->ops = res->ops; |
| 258 | dup_res->flags = SDE_CRTC_RES_FLAG_FREE; |
| 259 | SDE_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n", |
| 260 | crtc->base.id, dup_rp->sequence_id, |
| 261 | dup_res->type, dup_res->tag, dup_res->val, |
| 262 | atomic_read(&dup_res->refcount)); |
| 263 | list_add_tail(&dup_res->list, &dup_rp->res_list); |
| 264 | if (dup_res->ops.get) |
| 265 | dup_res->ops.get(dup_res->val, 0, -1); |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | /** |
| 270 | * _sde_crtc_rp_reset - reset resource pool after allocation |
| 271 | * @rp: Pointer to original resource pool |
| 272 | * return: None |
| 273 | */ |
| 274 | static void _sde_crtc_rp_reset(struct sde_crtc_respool *rp) |
| 275 | { |
| 276 | if (!rp) { |
| 277 | SDE_ERROR("invalid resource pool\n"); |
| 278 | return; |
| 279 | } |
| 280 | |
| 281 | rp->sequence_id = 0; |
| 282 | INIT_LIST_HEAD(&rp->res_list); |
| 283 | rp->ops.get = _sde_crtc_hw_blk_get; |
| 284 | rp->ops.put = _sde_crtc_hw_blk_put; |
| 285 | } |
| 286 | |
| 287 | /** |
| 288 | * _sde_crtc_rp_add - add given resource to resource pool |
| 289 | * @rp: Pointer to original resource pool |
| 290 | * @type: Resource type |
| 291 | * @tag: Search tag for given resource |
| 292 | * @val: Resource handle |
| 293 | * @ops: Resource callback operations |
| 294 | * return: 0 if success; error code otherwise |
| 295 | */ |
| 296 | static int _sde_crtc_rp_add(struct sde_crtc_respool *rp, u32 type, u64 tag, |
| 297 | void *val, struct sde_crtc_res_ops *ops) |
| 298 | { |
| 299 | struct sde_crtc_res *res; |
| 300 | struct drm_crtc *crtc; |
| 301 | |
| 302 | if (!rp || !ops) { |
| 303 | SDE_ERROR("invalid resource pool/ops\n"); |
| 304 | return -EINVAL; |
| 305 | } |
| 306 | |
| 307 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 308 | if (!crtc) { |
| 309 | SDE_ERROR("invalid crtc\n"); |
| 310 | return -EINVAL; |
| 311 | } |
| 312 | |
| 313 | list_for_each_entry(res, &rp->res_list, list) { |
| 314 | if (res->type != type || res->tag != tag) |
| 315 | continue; |
| 316 | SDE_ERROR("crtc%d.%u already exist res:0x%x/0x%llx/%pK/%d\n", |
| 317 | crtc->base.id, rp->sequence_id, |
| 318 | res->type, res->tag, res->val, |
| 319 | atomic_read(&res->refcount)); |
| 320 | return -EEXIST; |
| 321 | } |
| 322 | res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL); |
| 323 | if (!res) |
| 324 | return -ENOMEM; |
| 325 | INIT_LIST_HEAD(&res->list); |
| 326 | atomic_set(&res->refcount, 1); |
| 327 | res->type = type; |
| 328 | res->tag = tag; |
| 329 | res->val = val; |
| 330 | res->ops = *ops; |
| 331 | list_add_tail(&res->list, &rp->res_list); |
| 332 | SDE_DEBUG("crtc%d.%u added res:0x%x/0x%llx\n", |
| 333 | crtc->base.id, rp->sequence_id, type, tag); |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | /** |
| 338 | * _sde_crtc_rp_get - lookup the resource from given resource pool and obtain |
| 339 | * if available; otherwise, obtain resource from global pool |
| 340 | * @rp: Pointer to original resource pool |
| 341 | * @type: Resource type |
| 342 | * @tag: Search tag for given resource |
| 343 | * return: Resource handle if success; pointer error or null otherwise |
| 344 | */ |
| 345 | static void *_sde_crtc_rp_get(struct sde_crtc_respool *rp, u32 type, u64 tag) |
| 346 | { |
| 347 | struct sde_crtc_res *res; |
| 348 | void *val = NULL; |
| 349 | int rc; |
| 350 | struct drm_crtc *crtc; |
| 351 | |
| 352 | if (!rp) { |
| 353 | SDE_ERROR("invalid resource pool\n"); |
| 354 | return NULL; |
| 355 | } |
| 356 | |
| 357 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 358 | if (!crtc) { |
| 359 | SDE_ERROR("invalid crtc\n"); |
| 360 | return NULL; |
| 361 | } |
| 362 | |
| 363 | list_for_each_entry(res, &rp->res_list, list) { |
| 364 | if (res->type != type || res->tag != tag) |
| 365 | continue; |
| 366 | SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n", |
| 367 | crtc->base.id, rp->sequence_id, |
| 368 | res->type, res->tag, res->val, |
| 369 | atomic_read(&res->refcount)); |
| 370 | atomic_inc(&res->refcount); |
| 371 | res->flags &= ~SDE_CRTC_RES_FLAG_FREE; |
| 372 | return res->val; |
| 373 | } |
| 374 | list_for_each_entry(res, &rp->res_list, list) { |
| 375 | if (res->type != type || !(res->flags & SDE_CRTC_RES_FLAG_FREE)) |
| 376 | continue; |
| 377 | SDE_DEBUG("crtc%d.%u retag res:0x%x/0x%llx/%pK/%d\n", |
| 378 | crtc->base.id, rp->sequence_id, |
| 379 | res->type, res->tag, res->val, |
| 380 | atomic_read(&res->refcount)); |
| 381 | atomic_inc(&res->refcount); |
| 382 | res->tag = tag; |
| 383 | res->flags &= ~SDE_CRTC_RES_FLAG_FREE; |
| 384 | return res->val; |
| 385 | } |
| 386 | if (rp->ops.get) |
| 387 | val = rp->ops.get(NULL, type, -1); |
| 388 | if (IS_ERR_OR_NULL(val)) { |
Alan Kwong | 42e3505 | 2017-05-05 06:52:51 -0700 | [diff] [blame] | 389 | SDE_DEBUG("crtc%d.%u failed to get res:0x%x//\n", |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 390 | crtc->base.id, rp->sequence_id, type); |
| 391 | return NULL; |
| 392 | } |
| 393 | rc = _sde_crtc_rp_add(rp, type, tag, val, &rp->ops); |
| 394 | if (rc) { |
| 395 | SDE_ERROR("crtc%d.%u failed to add res:0x%x/0x%llx\n", |
| 396 | crtc->base.id, rp->sequence_id, type, tag); |
| 397 | if (rp->ops.put) |
| 398 | rp->ops.put(val); |
| 399 | val = NULL; |
| 400 | } |
| 401 | return val; |
| 402 | } |
| 403 | |
| 404 | /** |
| 405 | * _sde_crtc_rp_put - return given resource to resource pool |
| 406 | * @rp: Pointer to original resource pool |
| 407 | * @type: Resource type |
| 408 | * @tag: Search tag for given resource |
| 409 | * return: None |
| 410 | */ |
| 411 | static void _sde_crtc_rp_put(struct sde_crtc_respool *rp, u32 type, u64 tag) |
| 412 | { |
| 413 | struct sde_crtc_res *res, *next; |
| 414 | struct drm_crtc *crtc; |
| 415 | |
| 416 | if (!rp) { |
| 417 | SDE_ERROR("invalid resource pool\n"); |
| 418 | return; |
| 419 | } |
| 420 | |
| 421 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 422 | if (!crtc) { |
| 423 | SDE_ERROR("invalid crtc\n"); |
| 424 | return; |
| 425 | } |
| 426 | |
| 427 | list_for_each_entry_safe(res, next, &rp->res_list, list) { |
| 428 | if (res->type != type || res->tag != tag) |
| 429 | continue; |
| 430 | SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n", |
| 431 | crtc->base.id, rp->sequence_id, |
| 432 | res->type, res->tag, res->val, |
| 433 | atomic_read(&res->refcount)); |
| 434 | if (res->flags & SDE_CRTC_RES_FLAG_FREE) |
| 435 | SDE_ERROR( |
| 436 | "crtc%d.%u already free res:0x%x/0x%llx/%pK/%d\n", |
| 437 | crtc->base.id, rp->sequence_id, |
| 438 | res->type, res->tag, res->val, |
| 439 | atomic_read(&res->refcount)); |
| 440 | else if (atomic_dec_return(&res->refcount) == 0) |
| 441 | res->flags |= SDE_CRTC_RES_FLAG_FREE; |
| 442 | |
| 443 | return; |
| 444 | } |
| 445 | SDE_ERROR("crtc%d.%u not found res:0x%x/0x%llx\n", |
| 446 | crtc->base.id, rp->sequence_id, type, tag); |
| 447 | } |
| 448 | |
| 449 | int sde_crtc_res_add(struct drm_crtc_state *state, u32 type, u64 tag, |
| 450 | void *val, struct sde_crtc_res_ops *ops) |
| 451 | { |
| 452 | struct sde_crtc_respool *rp; |
| 453 | |
| 454 | if (!state) { |
| 455 | SDE_ERROR("invalid parameters\n"); |
| 456 | return -EINVAL; |
| 457 | } |
| 458 | |
| 459 | rp = &to_sde_crtc_state(state)->rp; |
| 460 | return _sde_crtc_rp_add(rp, type, tag, val, ops); |
| 461 | } |
| 462 | |
| 463 | void *sde_crtc_res_get(struct drm_crtc_state *state, u32 type, u64 tag) |
| 464 | { |
| 465 | struct sde_crtc_respool *rp; |
| 466 | void *val; |
| 467 | |
| 468 | if (!state) { |
| 469 | SDE_ERROR("invalid parameters\n"); |
| 470 | return NULL; |
| 471 | } |
| 472 | |
| 473 | rp = &to_sde_crtc_state(state)->rp; |
| 474 | val = _sde_crtc_rp_get(rp, type, tag); |
| 475 | if (IS_ERR(val)) { |
| 476 | SDE_ERROR("failed to get res type:0x%x:0x%llx\n", |
| 477 | type, tag); |
| 478 | return NULL; |
| 479 | } |
| 480 | |
| 481 | return val; |
| 482 | } |
| 483 | |
| 484 | void sde_crtc_res_put(struct drm_crtc_state *state, u32 type, u64 tag) |
| 485 | { |
| 486 | struct sde_crtc_respool *rp; |
| 487 | |
| 488 | if (!state) { |
| 489 | SDE_ERROR("invalid parameters\n"); |
| 490 | return; |
| 491 | } |
| 492 | |
| 493 | rp = &to_sde_crtc_state(state)->rp; |
| 494 | _sde_crtc_rp_put(rp, type, tag); |
| 495 | } |
| 496 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 497 | static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc) |
| 498 | { |
| 499 | if (!sde_crtc) |
| 500 | return; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 501 | } |
| 502 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 503 | static void sde_crtc_destroy(struct drm_crtc *crtc) |
| 504 | { |
| 505 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 506 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 507 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 508 | |
| 509 | if (!crtc) |
| 510 | return; |
| 511 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 512 | if (sde_crtc->blob_info) |
| 513 | drm_property_unreference_blob(sde_crtc->blob_info); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 514 | msm_property_destroy(&sde_crtc->property_info); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 515 | sde_cp_crtc_destroy_properties(crtc); |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 516 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 517 | sde_fence_deinit(&sde_crtc->output_fence); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 518 | _sde_crtc_deinit_events(sde_crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 519 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 520 | drm_crtc_cleanup(crtc); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 521 | mutex_destroy(&sde_crtc->crtc_lock); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 522 | kfree(sde_crtc); |
| 523 | } |
| 524 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 525 | static bool sde_crtc_mode_fixup(struct drm_crtc *crtc, |
| 526 | const struct drm_display_mode *mode, |
| 527 | struct drm_display_mode *adjusted_mode) |
| 528 | { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 529 | SDE_DEBUG("\n"); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 530 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 531 | if (msm_is_mode_seamless(adjusted_mode) && |
| 532 | (!crtc->enabled || crtc->state->active_changed)) { |
| 533 | SDE_ERROR("crtc state prevents seamless transition\n"); |
| 534 | return false; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 535 | } |
| 536 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 537 | return true; |
| 538 | } |
| 539 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 540 | static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer, |
| 541 | struct sde_plane_state *pstate, struct sde_format *format) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 542 | { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 543 | uint32_t blend_op, fg_alpha, bg_alpha; |
| 544 | uint32_t blend_type; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 545 | struct sde_hw_mixer *lm = mixer->hw_lm; |
| 546 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 547 | /* default to opaque blending */ |
| 548 | fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA); |
| 549 | bg_alpha = 0xFF - fg_alpha; |
| 550 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 551 | blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 552 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 553 | SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha); |
| 554 | |
| 555 | switch (blend_type) { |
| 556 | |
| 557 | case SDE_DRM_BLEND_OP_OPAQUE: |
| 558 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 559 | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 560 | break; |
| 561 | |
| 562 | case SDE_DRM_BLEND_OP_PREMULTIPLIED: |
| 563 | if (format->alpha_enable) { |
| 564 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 565 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 566 | if (fg_alpha != 0xff) { |
| 567 | bg_alpha = fg_alpha; |
| 568 | blend_op |= SDE_BLEND_BG_MOD_ALPHA | |
| 569 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 570 | } else { |
| 571 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 572 | } |
| 573 | } |
| 574 | break; |
| 575 | |
| 576 | case SDE_DRM_BLEND_OP_COVERAGE: |
| 577 | if (format->alpha_enable) { |
| 578 | blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL | |
| 579 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 580 | if (fg_alpha != 0xff) { |
| 581 | bg_alpha = fg_alpha; |
| 582 | blend_op |= SDE_BLEND_FG_MOD_ALPHA | |
| 583 | SDE_BLEND_FG_INV_MOD_ALPHA | |
| 584 | SDE_BLEND_BG_MOD_ALPHA | |
| 585 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 586 | } else { |
| 587 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 588 | } |
| 589 | } |
| 590 | break; |
| 591 | default: |
| 592 | /* do nothing */ |
| 593 | break; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 594 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 595 | |
| 596 | lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha, |
| 597 | bg_alpha, blend_op); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 598 | SDE_DEBUG( |
| 599 | "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n", |
| 600 | (char *) &format->base.pixel_format, |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 601 | format->alpha_enable, fg_alpha, bg_alpha, blend_op); |
| 602 | } |
| 603 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 604 | static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc, |
| 605 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer, |
| 606 | struct sde_hw_dim_layer *dim_layer) |
| 607 | { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 608 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 609 | struct sde_hw_mixer *lm; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 610 | struct sde_hw_dim_layer split_dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 611 | int i; |
| 612 | |
| 613 | if (!dim_layer->rect.w || !dim_layer->rect.h) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 614 | SDE_DEBUG("empty dim_layer\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 615 | return; |
| 616 | } |
| 617 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 618 | cstate = to_sde_crtc_state(crtc->state); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 619 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 620 | SDE_DEBUG("dim_layer - flags:%d, stage:%d\n", |
| 621 | dim_layer->flags, dim_layer->stage); |
| 622 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 623 | split_dim_layer.stage = dim_layer->stage; |
| 624 | split_dim_layer.color_fill = dim_layer->color_fill; |
| 625 | |
| 626 | /* |
| 627 | * traverse through the layer mixers attached to crtc and find the |
| 628 | * intersecting dim layer rect in each LM and program accordingly. |
| 629 | */ |
| 630 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 631 | split_dim_layer.flags = dim_layer->flags; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 632 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 633 | sde_kms_rect_intersect(&cstate->lm_bounds[i], &dim_layer->rect, |
Lloyd Atkinson | e0e11e2 | 2017-01-17 12:08:48 -0500 | [diff] [blame] | 634 | &split_dim_layer.rect); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 635 | if (sde_kms_rect_is_null(&split_dim_layer.rect)) { |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 636 | /* |
| 637 | * no extra programming required for non-intersecting |
| 638 | * layer mixers with INCLUSIVE dim layer |
| 639 | */ |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 640 | if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE) |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 641 | continue; |
| 642 | |
| 643 | /* |
| 644 | * program the other non-intersecting layer mixers with |
| 645 | * INCLUSIVE dim layer of full size for uniformity |
| 646 | * with EXCLUSIVE dim layer config. |
| 647 | */ |
| 648 | split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE; |
| 649 | split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 650 | memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i], |
| 651 | sizeof(split_dim_layer.rect)); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 652 | |
| 653 | } else { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 654 | split_dim_layer.rect.x = |
| 655 | split_dim_layer.rect.x - |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 656 | cstate->lm_bounds[i].x; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 657 | } |
| 658 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 659 | SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n", |
| 660 | i, split_dim_layer.rect.x, split_dim_layer.rect.y, |
| 661 | split_dim_layer.rect.w, split_dim_layer.rect.h); |
| 662 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 663 | lm = mixer[i].hw_lm; |
| 664 | mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage; |
| 665 | lm->ops.setup_dim_layer(lm, &split_dim_layer); |
| 666 | } |
| 667 | } |
| 668 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 669 | void sde_crtc_get_crtc_roi(struct drm_crtc_state *state, |
| 670 | const struct sde_rect **crtc_roi) |
| 671 | { |
| 672 | struct sde_crtc_state *crtc_state; |
| 673 | |
| 674 | if (!state || !crtc_roi) |
| 675 | return; |
| 676 | |
| 677 | crtc_state = to_sde_crtc_state(state); |
| 678 | *crtc_roi = &crtc_state->crtc_roi; |
| 679 | } |
| 680 | |
| 681 | static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state, |
| 682 | void *usr_ptr) |
| 683 | { |
| 684 | struct drm_crtc *crtc; |
| 685 | struct sde_crtc_state *cstate; |
| 686 | struct sde_drm_roi_v1 roi_v1; |
| 687 | int i; |
| 688 | |
| 689 | if (!state) { |
| 690 | SDE_ERROR("invalid args\n"); |
| 691 | return -EINVAL; |
| 692 | } |
| 693 | |
| 694 | cstate = to_sde_crtc_state(state); |
| 695 | crtc = cstate->base.crtc; |
| 696 | |
| 697 | memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list)); |
| 698 | |
| 699 | if (!usr_ptr) { |
| 700 | SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc)); |
| 701 | return 0; |
| 702 | } |
| 703 | |
| 704 | if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) { |
| 705 | SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc)); |
| 706 | return -EINVAL; |
| 707 | } |
| 708 | |
| 709 | SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects); |
| 710 | |
| 711 | if (roi_v1.num_rects == 0) { |
| 712 | SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc)); |
| 713 | return 0; |
| 714 | } |
| 715 | |
| 716 | if (roi_v1.num_rects > SDE_MAX_ROI_V1) { |
| 717 | SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc), |
| 718 | roi_v1.num_rects); |
| 719 | return -EINVAL; |
| 720 | } |
| 721 | |
| 722 | cstate->user_roi_list.num_rects = roi_v1.num_rects; |
| 723 | for (i = 0; i < roi_v1.num_rects; ++i) { |
| 724 | cstate->user_roi_list.roi[i] = roi_v1.roi[i]; |
| 725 | SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n", |
| 726 | DRMID(crtc), i, |
| 727 | cstate->user_roi_list.roi[i].x1, |
| 728 | cstate->user_roi_list.roi[i].y1, |
| 729 | cstate->user_roi_list.roi[i].x2, |
| 730 | cstate->user_roi_list.roi[i].y2); |
| 731 | } |
| 732 | |
| 733 | return 0; |
| 734 | } |
| 735 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 736 | static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state) |
| 737 | { |
| 738 | int i; |
| 739 | struct sde_crtc_state *cstate; |
| 740 | bool is_3dmux_dsc = false; |
| 741 | |
| 742 | cstate = to_sde_crtc_state(state); |
| 743 | |
| 744 | for (i = 0; i < cstate->num_connectors; i++) { |
| 745 | struct drm_connector *conn = cstate->connectors[i]; |
| 746 | |
| 747 | if (sde_connector_get_topology_name(conn) == |
| 748 | SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC) |
| 749 | is_3dmux_dsc = true; |
| 750 | } |
| 751 | |
| 752 | return is_3dmux_dsc; |
| 753 | } |
| 754 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 755 | static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc, |
| 756 | struct drm_crtc_state *state) |
| 757 | { |
| 758 | struct drm_connector *conn; |
| 759 | struct drm_connector_state *conn_state; |
| 760 | struct sde_crtc *sde_crtc; |
| 761 | struct sde_crtc_state *crtc_state; |
| 762 | struct sde_rect *crtc_roi; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 763 | int i, num_attached_conns = 0; |
| 764 | |
| 765 | if (!crtc || !state) |
| 766 | return -EINVAL; |
| 767 | |
| 768 | sde_crtc = to_sde_crtc(crtc); |
| 769 | crtc_state = to_sde_crtc_state(state); |
| 770 | crtc_roi = &crtc_state->crtc_roi; |
| 771 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 772 | for_each_connector_in_state(state->state, conn, conn_state, i) { |
| 773 | struct sde_connector_state *sde_conn_state; |
| 774 | |
| 775 | if (!conn_state || conn_state->crtc != crtc) |
| 776 | continue; |
| 777 | |
| 778 | if (num_attached_conns) { |
| 779 | SDE_ERROR( |
| 780 | "crtc%d: unsupported: roi on crtc w/ >1 connectors\n", |
| 781 | DRMID(crtc)); |
| 782 | return -EINVAL; |
| 783 | } |
| 784 | ++num_attached_conns; |
| 785 | |
| 786 | sde_conn_state = to_sde_connector_state(conn_state); |
| 787 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 788 | /* |
| 789 | * current driver only supports same connector and crtc size, |
| 790 | * but if support for different sizes is added, driver needs |
| 791 | * to check the connector roi here to make sure is full screen |
| 792 | * for dsc 3d-mux topology that doesn't support partial update. |
| 793 | */ |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 794 | if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list, |
| 795 | sizeof(crtc_state->user_roi_list))) { |
| 796 | SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n", |
| 797 | sde_crtc->name); |
| 798 | return -EINVAL; |
| 799 | } |
| 800 | } |
| 801 | |
Lloyd Atkinson | c2baf41 | 2017-04-19 17:53:09 -0400 | [diff] [blame] | 802 | sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 803 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 804 | /* |
| 805 | * for 3dmux dsc, make sure is full ROI, since current driver doesn't |
| 806 | * support partial update for this configuration. |
| 807 | */ |
| 808 | if (!sde_kms_rect_is_null(crtc_roi) && |
| 809 | _sde_crtc_setup_is_3dmux_dsc(state)) { |
| 810 | struct drm_display_mode *adj_mode = &state->adjusted_mode; |
| 811 | |
| 812 | if (crtc_roi->w != adj_mode->hdisplay || |
| 813 | crtc_roi->h != adj_mode->vdisplay) { |
| 814 | SDE_ERROR("%s: unsupported top roi[%d %d] wxh[%d %d]\n", |
| 815 | sde_crtc->name, crtc_roi->w, crtc_roi->h, |
| 816 | adj_mode->hdisplay, adj_mode->vdisplay); |
| 817 | return -EINVAL; |
| 818 | } |
| 819 | } |
| 820 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 821 | SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name, |
| 822 | crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h); |
| 823 | |
| 824 | return 0; |
| 825 | } |
| 826 | |
Lloyd Atkinson | 7738220 | 2017-02-01 14:59:43 -0500 | [diff] [blame] | 827 | static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc, |
| 828 | struct drm_crtc_state *state) |
| 829 | { |
| 830 | struct sde_crtc *sde_crtc; |
| 831 | struct sde_crtc_state *crtc_state; |
| 832 | struct drm_connector *conn; |
| 833 | struct drm_connector_state *conn_state; |
| 834 | int i; |
| 835 | |
| 836 | if (!crtc || !state) |
| 837 | return -EINVAL; |
| 838 | |
| 839 | sde_crtc = to_sde_crtc(crtc); |
| 840 | crtc_state = to_sde_crtc_state(state); |
| 841 | |
| 842 | if (sde_kms_rect_is_null(&crtc_state->crtc_roi)) |
| 843 | return 0; |
| 844 | |
| 845 | /* partial update active, check if autorefresh is also requested */ |
| 846 | for_each_connector_in_state(state->state, conn, conn_state, i) { |
| 847 | uint64_t autorefresh; |
| 848 | |
| 849 | if (!conn_state || conn_state->crtc != crtc) |
| 850 | continue; |
| 851 | |
| 852 | autorefresh = sde_connector_get_property(conn_state, |
| 853 | CONNECTOR_PROP_AUTOREFRESH); |
| 854 | if (autorefresh) { |
| 855 | SDE_ERROR( |
| 856 | "%s: autorefresh & partial crtc roi incompatible %llu\n", |
| 857 | sde_crtc->name, autorefresh); |
| 858 | return -EINVAL; |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | return 0; |
| 863 | } |
| 864 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 865 | static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc, |
| 866 | struct drm_crtc_state *state, int lm_idx) |
| 867 | { |
| 868 | struct sde_crtc *sde_crtc; |
| 869 | struct sde_crtc_state *crtc_state; |
| 870 | const struct sde_rect *crtc_roi; |
| 871 | const struct sde_rect *lm_bounds; |
| 872 | struct sde_rect *lm_roi; |
| 873 | |
| 874 | if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds)) |
| 875 | return -EINVAL; |
| 876 | |
| 877 | sde_crtc = to_sde_crtc(crtc); |
| 878 | crtc_state = to_sde_crtc_state(state); |
| 879 | crtc_roi = &crtc_state->crtc_roi; |
| 880 | lm_bounds = &crtc_state->lm_bounds[lm_idx]; |
| 881 | lm_roi = &crtc_state->lm_roi[lm_idx]; |
| 882 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 883 | if (sde_kms_rect_is_null(crtc_roi)) |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 884 | memcpy(lm_roi, lm_bounds, sizeof(*lm_roi)); |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 885 | else |
| 886 | sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 887 | |
| 888 | SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx, |
| 889 | lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h); |
| 890 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 891 | /* if any dimension is zero, clear all dimensions for clarity */ |
| 892 | if (sde_kms_rect_is_null(lm_roi)) |
| 893 | memset(lm_roi, 0, sizeof(*lm_roi)); |
| 894 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 895 | return 0; |
| 896 | } |
| 897 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 898 | static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc, |
| 899 | struct drm_crtc_state *state) |
| 900 | { |
| 901 | struct sde_crtc *sde_crtc; |
| 902 | struct sde_crtc_state *crtc_state; |
| 903 | u32 disp_bitmask = 0; |
| 904 | int i; |
| 905 | |
| 906 | sde_crtc = to_sde_crtc(crtc); |
| 907 | crtc_state = to_sde_crtc_state(state); |
| 908 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 909 | /* pingpong split: one ROI, one LM, two physical displays */ |
| 910 | if (crtc_state->is_ppsplit) { |
| 911 | u32 lm_split_width = crtc_state->lm_bounds[0].w / 2; |
| 912 | struct sde_rect *roi = &crtc_state->lm_roi[0]; |
| 913 | |
| 914 | if (sde_kms_rect_is_null(roi)) |
| 915 | disp_bitmask = 0; |
| 916 | else if ((u32)roi->x + (u32)roi->w <= lm_split_width) |
| 917 | disp_bitmask = BIT(0); /* left only */ |
| 918 | else if (roi->x >= lm_split_width) |
| 919 | disp_bitmask = BIT(1); /* right only */ |
| 920 | else |
| 921 | disp_bitmask = BIT(0) | BIT(1); /* left and right */ |
| 922 | } else { |
| 923 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 924 | if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i])) |
| 925 | disp_bitmask |= BIT(i); |
| 926 | } |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 927 | } |
| 928 | |
| 929 | SDE_DEBUG("affected displays 0x%x\n", disp_bitmask); |
| 930 | |
| 931 | return disp_bitmask; |
| 932 | } |
| 933 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 934 | static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc, |
| 935 | struct drm_crtc_state *state) |
| 936 | { |
| 937 | struct sde_crtc *sde_crtc; |
| 938 | struct sde_crtc_state *crtc_state; |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 939 | const struct sde_rect *roi[CRTC_DUAL_MIXERS]; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 940 | |
| 941 | if (!crtc || !state) |
| 942 | return -EINVAL; |
| 943 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 944 | sde_crtc = to_sde_crtc(crtc); |
| 945 | crtc_state = to_sde_crtc_state(state); |
| 946 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 947 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 948 | SDE_ERROR("%s: unsupported number of mixers: %d\n", |
| 949 | sde_crtc->name, sde_crtc->num_mixers); |
| 950 | return -EINVAL; |
| 951 | } |
| 952 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 953 | /* |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 954 | * If using pingpong split: one ROI, one LM, two physical displays |
| 955 | * then the ROI must be centered on the panel split boundary and |
| 956 | * be of equal width across the split. |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 957 | */ |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 958 | if (crtc_state->is_ppsplit) { |
| 959 | u16 panel_split_width; |
| 960 | u32 display_mask; |
| 961 | |
| 962 | roi[0] = &crtc_state->lm_roi[0]; |
| 963 | |
| 964 | if (sde_kms_rect_is_null(roi[0])) |
| 965 | return 0; |
| 966 | |
| 967 | display_mask = _sde_crtc_get_displays_affected(crtc, state); |
| 968 | if (display_mask != (BIT(0) | BIT(1))) |
| 969 | return 0; |
| 970 | |
| 971 | panel_split_width = crtc_state->lm_bounds[0].w / 2; |
| 972 | if (roi[0]->x + roi[0]->w / 2 != panel_split_width) { |
| 973 | SDE_ERROR("%s: roi x %d w %d split %d\n", |
| 974 | sde_crtc->name, roi[0]->x, roi[0]->w, |
| 975 | panel_split_width); |
| 976 | return -EINVAL; |
| 977 | } |
| 978 | |
| 979 | return 0; |
| 980 | } |
| 981 | |
| 982 | /* |
| 983 | * On certain HW, if using 2 LM, ROIs must be split evenly between the |
| 984 | * LMs and be of equal width. |
| 985 | */ |
Clarence Ip | ffb8742 | 2017-06-30 13:37:48 -0400 | [diff] [blame] | 986 | if (sde_crtc->num_mixers < 2) |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 987 | return 0; |
| 988 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 989 | roi[0] = &crtc_state->lm_roi[0]; |
| 990 | roi[1] = &crtc_state->lm_roi[1]; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 991 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 992 | /* if one of the roi is null it's a left/right-only update */ |
| 993 | if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1])) |
| 994 | return 0; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 995 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 996 | /* check lm rois are equal width & first roi ends at 2nd roi */ |
| 997 | if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) { |
| 998 | SDE_ERROR( |
| 999 | "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n", |
| 1000 | sde_crtc->name, roi[0]->x, roi[0]->w, |
| 1001 | roi[1]->x, roi[1]->w); |
| 1002 | return -EINVAL; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1003 | } |
| 1004 | |
| 1005 | return 0; |
| 1006 | } |
| 1007 | |
| 1008 | static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc, |
| 1009 | struct drm_crtc_state *state) |
| 1010 | { |
| 1011 | struct sde_crtc *sde_crtc; |
| 1012 | struct sde_crtc_state *crtc_state; |
| 1013 | const struct sde_rect *crtc_roi; |
| 1014 | struct drm_plane_state *pstate; |
| 1015 | struct drm_plane *plane; |
| 1016 | |
| 1017 | if (!crtc || !state) |
| 1018 | return -EINVAL; |
| 1019 | |
| 1020 | /* |
| 1021 | * Reject commit if a Plane CRTC destination coordinates fall outside |
| 1022 | * the partial CRTC ROI. LM output is determined via connector ROIs, |
| 1023 | * if they are specified, not Plane CRTC ROIs. |
| 1024 | */ |
| 1025 | |
| 1026 | sde_crtc = to_sde_crtc(crtc); |
| 1027 | crtc_state = to_sde_crtc_state(state); |
| 1028 | crtc_roi = &crtc_state->crtc_roi; |
| 1029 | |
| 1030 | if (sde_kms_rect_is_null(crtc_roi)) |
| 1031 | return 0; |
| 1032 | |
| 1033 | drm_atomic_crtc_state_for_each_plane(plane, state) { |
| 1034 | struct sde_rect plane_roi, intersection; |
| 1035 | |
| 1036 | pstate = drm_atomic_get_plane_state(state->state, plane); |
| 1037 | if (IS_ERR_OR_NULL(pstate)) { |
| 1038 | int rc = PTR_ERR(pstate); |
| 1039 | |
| 1040 | SDE_ERROR("%s: failed to get plane%d state, %d\n", |
| 1041 | sde_crtc->name, plane->base.id, rc); |
| 1042 | return rc; |
| 1043 | } |
| 1044 | |
| 1045 | plane_roi.x = pstate->crtc_x; |
| 1046 | plane_roi.y = pstate->crtc_y; |
| 1047 | plane_roi.w = pstate->crtc_w; |
| 1048 | plane_roi.h = pstate->crtc_h; |
| 1049 | sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection); |
| 1050 | if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) { |
| 1051 | SDE_ERROR( |
| 1052 | "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n", |
| 1053 | sde_crtc->name, plane->base.id, |
| 1054 | plane_roi.x, plane_roi.y, |
| 1055 | plane_roi.w, plane_roi.h, |
| 1056 | crtc_roi->x, crtc_roi->y, |
| 1057 | crtc_roi->w, crtc_roi->h); |
| 1058 | return -E2BIG; |
| 1059 | } |
| 1060 | } |
| 1061 | |
| 1062 | return 0; |
| 1063 | } |
| 1064 | |
| 1065 | static int _sde_crtc_check_rois(struct drm_crtc *crtc, |
| 1066 | struct drm_crtc_state *state) |
| 1067 | { |
| 1068 | struct sde_crtc *sde_crtc; |
| 1069 | int lm_idx; |
| 1070 | int rc; |
| 1071 | |
| 1072 | if (!crtc || !state) |
| 1073 | return -EINVAL; |
| 1074 | |
| 1075 | sde_crtc = to_sde_crtc(crtc); |
| 1076 | |
| 1077 | rc = _sde_crtc_set_crtc_roi(crtc, state); |
| 1078 | if (rc) |
| 1079 | return rc; |
| 1080 | |
Lloyd Atkinson | 7738220 | 2017-02-01 14:59:43 -0500 | [diff] [blame] | 1081 | rc = _sde_crtc_check_autorefresh(crtc, state); |
| 1082 | if (rc) |
| 1083 | return rc; |
| 1084 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1085 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
| 1086 | rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx); |
| 1087 | if (rc) |
| 1088 | return rc; |
| 1089 | } |
| 1090 | |
| 1091 | rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state); |
| 1092 | if (rc) |
| 1093 | return rc; |
| 1094 | |
| 1095 | rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state); |
| 1096 | if (rc) |
| 1097 | return rc; |
| 1098 | |
| 1099 | return 0; |
| 1100 | } |
| 1101 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1102 | static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc) |
| 1103 | { |
| 1104 | struct sde_crtc *sde_crtc; |
| 1105 | struct sde_crtc_state *crtc_state; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1106 | const struct sde_rect *lm_roi; |
| 1107 | struct sde_hw_mixer *hw_lm; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1108 | int lm_idx, lm_horiz_position; |
| 1109 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1110 | if (!crtc) |
| 1111 | return; |
| 1112 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1113 | sde_crtc = to_sde_crtc(crtc); |
| 1114 | crtc_state = to_sde_crtc_state(crtc->state); |
| 1115 | |
| 1116 | lm_horiz_position = 0; |
| 1117 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1118 | struct sde_hw_mixer_cfg cfg; |
| 1119 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1120 | lm_roi = &crtc_state->lm_roi[lm_idx]; |
| 1121 | hw_lm = sde_crtc->mixers[lm_idx].hw_lm; |
| 1122 | |
| 1123 | SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx, |
| 1124 | lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h); |
| 1125 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1126 | if (sde_kms_rect_is_null(lm_roi)) |
| 1127 | continue; |
| 1128 | |
Ping Li | f41c2ef | 2017-05-04 14:40:45 -0700 | [diff] [blame] | 1129 | hw_lm->cfg.out_width = lm_roi->w; |
| 1130 | hw_lm->cfg.out_height = lm_roi->h; |
| 1131 | hw_lm->cfg.right_mixer = lm_horiz_position; |
| 1132 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1133 | cfg.out_width = lm_roi->w; |
| 1134 | cfg.out_height = lm_roi->h; |
| 1135 | cfg.right_mixer = lm_horiz_position++; |
| 1136 | cfg.flags = 0; |
| 1137 | hw_lm->ops.setup_mixer_out(hw_lm, &cfg); |
| 1138 | } |
| 1139 | } |
| 1140 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1141 | static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, |
| 1142 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer) |
| 1143 | { |
| 1144 | struct drm_plane *plane; |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1145 | struct drm_framebuffer *fb; |
| 1146 | struct drm_plane_state *state; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1147 | struct sde_crtc_state *cstate; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1148 | struct sde_plane_state *pstate = NULL; |
| 1149 | struct sde_format *format; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1150 | struct sde_hw_ctl *ctl; |
| 1151 | struct sde_hw_mixer *lm; |
| 1152 | struct sde_hw_stage_cfg *stage_cfg; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1153 | struct sde_rect plane_crtc_roi; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1154 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1155 | u32 flush_mask, flush_sbuf, flush_tmp; |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1156 | uint32_t stage_idx, lm_idx; |
| 1157 | int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 }; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1158 | int i; |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1159 | bool bg_alpha_enable = false; |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1160 | u32 prefill = 0; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1161 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1162 | if (!sde_crtc || !mixer) { |
| 1163 | SDE_ERROR("invalid sde_crtc or mixer\n"); |
| 1164 | return; |
| 1165 | } |
| 1166 | |
| 1167 | ctl = mixer->hw_ctl; |
| 1168 | lm = mixer->hw_lm; |
| 1169 | stage_cfg = &sde_crtc->stage_cfg; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1170 | cstate = to_sde_crtc_state(crtc->state); |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1171 | flush_sbuf = 0x0; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1172 | |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1173 | cstate->sbuf_cfg.rot_op_mode = SDE_CTL_ROT_OP_MODE_OFFLINE; |
| 1174 | cstate->sbuf_prefill_line = 0; |
| 1175 | |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1176 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1177 | state = plane->state; |
| 1178 | if (!state) |
| 1179 | continue; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1180 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1181 | plane_crtc_roi.x = state->crtc_x; |
| 1182 | plane_crtc_roi.y = state->crtc_y; |
| 1183 | plane_crtc_roi.w = state->crtc_w; |
| 1184 | plane_crtc_roi.h = state->crtc_h; |
| 1185 | |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1186 | pstate = to_sde_plane_state(state); |
| 1187 | fb = state->fb; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1188 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1189 | if (sde_plane_is_sbuf_mode(plane, &prefill)) |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1190 | cstate->sbuf_cfg.rot_op_mode = |
| 1191 | SDE_CTL_ROT_OP_MODE_INLINE_SYNC; |
| 1192 | if (prefill > cstate->sbuf_prefill_line) |
| 1193 | cstate->sbuf_prefill_line = prefill; |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1194 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1195 | sde_plane_get_ctl_flush(plane, ctl, &flush_mask, &flush_tmp); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1196 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1197 | /* persist rotator flush bit(s) for one more commit */ |
| 1198 | flush_mask |= cstate->sbuf_flush_mask | flush_tmp; |
| 1199 | flush_sbuf |= flush_tmp; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1200 | |
| 1201 | SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1202 | crtc->base.id, |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1203 | pstate->stage, |
| 1204 | plane->base.id, |
| 1205 | sde_plane_pipe(plane) - SSPP_VIG0, |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1206 | state->fb ? state->fb->base.id : -1); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1207 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1208 | format = to_sde_format(msm_framebuffer_format(pstate->base.fb)); |
Narendra Muppalla | ec11a0a | 2017-06-15 15:35:17 -0700 | [diff] [blame] | 1209 | if (!format) { |
| 1210 | SDE_ERROR("invalid format\n"); |
| 1211 | return; |
| 1212 | } |
| 1213 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1214 | if (pstate->stage == SDE_STAGE_BASE && format->alpha_enable) |
| 1215 | bg_alpha_enable = true; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1216 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1217 | SDE_EVT32(DRMID(crtc), DRMID(plane), |
| 1218 | state->fb ? state->fb->base.id : -1, |
| 1219 | state->src_x >> 16, state->src_y >> 16, |
| 1220 | state->src_w >> 16, state->src_h >> 16, |
| 1221 | state->crtc_x, state->crtc_y, |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1222 | state->crtc_w, state->crtc_h, |
Clarence Ip | eb39cce | 2017-07-19 14:12:43 -0400 | [diff] [blame^] | 1223 | flush_tmp ? cstate->sbuf_cfg.rot_op_mode : |
| 1224 | SDE_CTL_ROT_OP_MODE_OFFLINE); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1225 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1226 | stage_idx = zpos_cnt[pstate->stage]++; |
| 1227 | stage_cfg->stage[pstate->stage][stage_idx] = |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1228 | sde_plane_pipe(plane); |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1229 | stage_cfg->multirect_index[pstate->stage][stage_idx] = |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1230 | pstate->multirect_index; |
| 1231 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1232 | SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx, |
| 1233 | sde_plane_pipe(plane) - SSPP_VIG0, pstate->stage, |
| 1234 | pstate->multirect_index, pstate->multirect_mode, |
| 1235 | format->base.pixel_format, fb ? fb->modifier[0] : 0); |
| 1236 | |
| 1237 | /* blend config update */ |
| 1238 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
| 1239 | _sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate, |
| 1240 | format); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1241 | mixer[lm_idx].flush_mask |= flush_mask; |
| 1242 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1243 | if (bg_alpha_enable && !format->alpha_enable) |
| 1244 | mixer[lm_idx].mixer_op_mode = 0; |
| 1245 | else |
| 1246 | mixer[lm_idx].mixer_op_mode |= |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1247 | 1 << pstate->stage; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1248 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1249 | } |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1250 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1251 | cstate->sbuf_flush_mask = flush_sbuf; |
| 1252 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1253 | if (lm && lm->ops.setup_dim_layer) { |
| 1254 | cstate = to_sde_crtc_state(crtc->state); |
| 1255 | for (i = 0; i < cstate->num_dim_layers; i++) |
| 1256 | _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, |
| 1257 | mixer, &cstate->dim_layer[i]); |
| 1258 | } |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1259 | |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1260 | if (ctl->ops.setup_sbuf_cfg) |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1261 | ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1262 | |
| 1263 | _sde_crtc_program_lm_output_roi(crtc); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1264 | } |
| 1265 | |
Lloyd Atkinson | 094780d | 2017-04-24 17:25:08 -0400 | [diff] [blame] | 1266 | static void _sde_crtc_swap_mixers_for_right_partial_update( |
| 1267 | struct drm_crtc *crtc) |
| 1268 | { |
| 1269 | struct sde_crtc *sde_crtc; |
| 1270 | struct sde_crtc_state *cstate; |
| 1271 | struct drm_encoder *drm_enc; |
| 1272 | bool is_right_only; |
| 1273 | bool encoder_in_dsc_merge = false; |
| 1274 | |
| 1275 | if (!crtc || !crtc->state) |
| 1276 | return; |
| 1277 | |
| 1278 | sde_crtc = to_sde_crtc(crtc); |
| 1279 | cstate = to_sde_crtc_state(crtc->state); |
| 1280 | |
| 1281 | if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS) |
| 1282 | return; |
| 1283 | |
| 1284 | drm_for_each_encoder(drm_enc, crtc->dev) { |
| 1285 | if (drm_enc->crtc == crtc && |
| 1286 | sde_encoder_is_dsc_merge(drm_enc)) { |
| 1287 | encoder_in_dsc_merge = true; |
| 1288 | break; |
| 1289 | } |
| 1290 | } |
| 1291 | |
| 1292 | /** |
| 1293 | * For right-only partial update with DSC merge, we swap LM0 & LM1. |
| 1294 | * This is due to two reasons: |
| 1295 | * - On 8996, there is a DSC HW requirement that in DSC Merge Mode, |
| 1296 | * the left DSC must be used, right DSC cannot be used alone. |
| 1297 | * For right-only partial update, this means swap layer mixers to map |
| 1298 | * Left LM to Right INTF. On later HW this was relaxed. |
| 1299 | * - In DSC Merge mode, the physical encoder has already registered |
| 1300 | * PP0 as the master, to switch to right-only we would have to |
| 1301 | * reprogram to be driven by PP1 instead. |
| 1302 | * To support both cases, we prefer to support the mixer swap solution. |
| 1303 | */ |
| 1304 | if (!encoder_in_dsc_merge) |
| 1305 | return; |
| 1306 | |
| 1307 | is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) && |
| 1308 | !sde_kms_rect_is_null(&cstate->lm_roi[1]); |
| 1309 | |
| 1310 | if (is_right_only && !sde_crtc->mixers_swapped) { |
| 1311 | /* right-only update swap mixers */ |
| 1312 | swap(sde_crtc->mixers[0], sde_crtc->mixers[1]); |
| 1313 | sde_crtc->mixers_swapped = true; |
| 1314 | } else if (!is_right_only && sde_crtc->mixers_swapped) { |
| 1315 | /* left-only or full update, swap back */ |
| 1316 | swap(sde_crtc->mixers[0], sde_crtc->mixers[1]); |
| 1317 | sde_crtc->mixers_swapped = false; |
| 1318 | } |
| 1319 | |
| 1320 | SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n", |
| 1321 | sde_crtc->name, is_right_only, sde_crtc->mixers_swapped, |
| 1322 | sde_crtc->mixers[0].hw_lm->idx - LM_0, |
| 1323 | sde_crtc->mixers[1].hw_lm->idx - LM_0); |
| 1324 | SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped, |
| 1325 | sde_crtc->mixers[0].hw_lm->idx - LM_0, |
| 1326 | sde_crtc->mixers[1].hw_lm->idx - LM_0); |
| 1327 | } |
| 1328 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1329 | /** |
| 1330 | * _sde_crtc_blend_setup - configure crtc mixers |
| 1331 | * @crtc: Pointer to drm crtc structure |
| 1332 | */ |
| 1333 | static void _sde_crtc_blend_setup(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1334 | { |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1335 | struct sde_crtc *sde_crtc; |
| 1336 | struct sde_crtc_state *sde_crtc_state; |
| 1337 | struct sde_crtc_mixer *mixer; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1338 | struct sde_hw_ctl *ctl; |
| 1339 | struct sde_hw_mixer *lm; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1340 | |
| 1341 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1342 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1343 | if (!crtc) |
| 1344 | return; |
| 1345 | |
| 1346 | sde_crtc = to_sde_crtc(crtc); |
| 1347 | sde_crtc_state = to_sde_crtc_state(crtc->state); |
| 1348 | mixer = sde_crtc->mixers; |
| 1349 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1350 | SDE_DEBUG("%s\n", sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1351 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1352 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 1353 | SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers); |
| 1354 | return; |
| 1355 | } |
| 1356 | |
| 1357 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 1358 | if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { |
| 1359 | SDE_ERROR("invalid lm or ctl assigned to mixer\n"); |
| 1360 | return; |
| 1361 | } |
| 1362 | mixer[i].mixer_op_mode = 0; |
| 1363 | mixer[i].flush_mask = 0; |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 1364 | if (mixer[i].hw_ctl->ops.clear_all_blendstages) |
| 1365 | mixer[i].hw_ctl->ops.clear_all_blendstages( |
| 1366 | mixer[i].hw_ctl); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1367 | |
| 1368 | /* clear dim_layer settings */ |
| 1369 | lm = mixer[i].hw_lm; |
| 1370 | if (lm->ops.clear_dim_layer) |
| 1371 | lm->ops.clear_dim_layer(lm); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1372 | } |
| 1373 | |
Lloyd Atkinson | 094780d | 2017-04-24 17:25:08 -0400 | [diff] [blame] | 1374 | _sde_crtc_swap_mixers_for_right_partial_update(crtc); |
| 1375 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1376 | /* initialize stage cfg */ |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1377 | memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1378 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1379 | _sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer); |
| 1380 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1381 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1382 | const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i]; |
| 1383 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1384 | ctl = mixer[i].hw_ctl; |
| 1385 | lm = mixer[i].hw_lm; |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1386 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1387 | if (sde_kms_rect_is_null(lm_roi)) { |
| 1388 | SDE_DEBUG( |
| 1389 | "%s: lm%d leave ctl%d mask 0 since null roi\n", |
| 1390 | sde_crtc->name, lm->idx - LM_0, |
| 1391 | ctl->idx - CTL_0); |
| 1392 | continue; |
| 1393 | } |
| 1394 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1395 | lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1396 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1397 | mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1398 | mixer[i].hw_lm->idx); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1399 | |
| 1400 | /* stage config flush mask */ |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1401 | ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); |
| 1402 | |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1403 | SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", |
| 1404 | mixer[i].hw_lm->idx - LM_0, |
| 1405 | mixer[i].mixer_op_mode, |
| 1406 | ctl->idx - CTL_0, |
| 1407 | mixer[i].flush_mask); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1408 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1409 | ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1410 | &sde_crtc->stage_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1411 | } |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1412 | |
| 1413 | _sde_crtc_program_lm_output_roi(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1414 | } |
| 1415 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1416 | void sde_crtc_prepare_commit(struct drm_crtc *crtc, |
| 1417 | struct drm_crtc_state *old_state) |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1418 | { |
| 1419 | struct sde_crtc *sde_crtc; |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1420 | struct sde_crtc_state *cstate; |
| 1421 | struct drm_connector *conn; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1422 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1423 | if (!crtc || !crtc->state) { |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1424 | SDE_ERROR("invalid crtc\n"); |
| 1425 | return; |
| 1426 | } |
| 1427 | |
| 1428 | sde_crtc = to_sde_crtc(crtc); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1429 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1430 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1431 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1432 | /* identify connectors attached to this crtc */ |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1433 | cstate->num_connectors = 0; |
| 1434 | |
| 1435 | drm_for_each_connector(conn, crtc->dev) |
| 1436 | if (conn->state && conn->state->crtc == crtc && |
| 1437 | cstate->num_connectors < MAX_CONNECTORS) { |
| 1438 | cstate->connectors[cstate->num_connectors++] = conn; |
| 1439 | sde_connector_prepare_fence(conn); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1440 | } |
| 1441 | |
| 1442 | /* prepare main output fence */ |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1443 | sde_fence_prepare(&sde_crtc->output_fence); |
| 1444 | } |
| 1445 | |
Abhinav Kumar | f2e94b5 | 2017-02-09 20:27:24 -0800 | [diff] [blame] | 1446 | /** |
| 1447 | * _sde_crtc_complete_flip - signal pending page_flip events |
| 1448 | * Any pending vblank events are added to the vblank_event_list |
| 1449 | * so that the next vblank interrupt shall signal them. |
| 1450 | * However PAGE_FLIP events are not handled through the vblank_event_list. |
| 1451 | * This API signals any pending PAGE_FLIP events requested through |
| 1452 | * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event. |
| 1453 | * if file!=NULL, this is preclose potential cancel-flip path |
| 1454 | * @crtc: Pointer to drm crtc structure |
| 1455 | * @file: Pointer to drm file |
| 1456 | */ |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1457 | static void _sde_crtc_complete_flip(struct drm_crtc *crtc, |
| 1458 | struct drm_file *file) |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1459 | { |
| 1460 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1461 | struct drm_device *dev = crtc->dev; |
| 1462 | struct drm_pending_vblank_event *event; |
| 1463 | unsigned long flags; |
| 1464 | |
| 1465 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1466 | event = sde_crtc->event; |
| 1467 | if (event) { |
| 1468 | /* if regular vblank case (!file) or if cancel-flip from |
| 1469 | * preclose on file that requested flip, then send the |
| 1470 | * event: |
| 1471 | */ |
| 1472 | if (!file || (event->base.file_priv == file)) { |
| 1473 | sde_crtc->event = NULL; |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1474 | DRM_DEBUG_VBL("%s: send event: %pK\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1475 | sde_crtc->name, event); |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 1476 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 1477 | drm_crtc_send_vblank_event(crtc, event); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1478 | } |
| 1479 | } |
| 1480 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1481 | } |
| 1482 | |
Alan Kwong | 3e985f0 | 2017-02-12 15:08:44 -0800 | [diff] [blame] | 1483 | enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc) |
| 1484 | { |
| 1485 | struct drm_encoder *encoder; |
| 1486 | |
| 1487 | if (!crtc || !crtc->dev) { |
| 1488 | SDE_ERROR("invalid crtc\n"); |
| 1489 | return INTF_MODE_NONE; |
| 1490 | } |
| 1491 | |
| 1492 | drm_for_each_encoder(encoder, crtc->dev) |
| 1493 | if (encoder->crtc == crtc) |
| 1494 | return sde_encoder_get_intf_mode(encoder); |
| 1495 | |
| 1496 | return INTF_MODE_NONE; |
| 1497 | } |
| 1498 | |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1499 | static void sde_crtc_vblank_cb(void *data) |
| 1500 | { |
| 1501 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 1502 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1503 | |
| 1504 | /* keep statistics on vblank callback - with auto reset via debugfs */ |
| 1505 | if (ktime_equal(sde_crtc->vblank_cb_time, ktime_set(0, 0))) |
| 1506 | sde_crtc->vblank_cb_time = ktime_get(); |
| 1507 | else |
| 1508 | sde_crtc->vblank_cb_count++; |
Abhinav Kumar | f2e94b5 | 2017-02-09 20:27:24 -0800 | [diff] [blame] | 1509 | _sde_crtc_complete_flip(crtc, NULL); |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 1510 | drm_crtc_handle_vblank(crtc); |
Lloyd Atkinson | 9eabe7a | 2016-09-14 13:39:15 -0400 | [diff] [blame] | 1511 | DRM_DEBUG_VBL("crtc%d\n", crtc->base.id); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1512 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1513 | } |
| 1514 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1515 | static void sde_crtc_frame_event_work(struct kthread_work *work) |
| 1516 | { |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 1517 | struct msm_drm_private *priv; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1518 | struct sde_crtc_frame_event *fevent; |
| 1519 | struct drm_crtc *crtc; |
| 1520 | struct sde_crtc *sde_crtc; |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1521 | struct sde_crtc_state *cstate; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1522 | struct sde_kms *sde_kms; |
| 1523 | unsigned long flags; |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1524 | bool frame_done = false; |
| 1525 | int i; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1526 | |
| 1527 | if (!work) { |
| 1528 | SDE_ERROR("invalid work handle\n"); |
| 1529 | return; |
| 1530 | } |
| 1531 | |
| 1532 | fevent = container_of(work, struct sde_crtc_frame_event, work); |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1533 | if (!fevent->crtc || !fevent->crtc->state) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1534 | SDE_ERROR("invalid crtc\n"); |
| 1535 | return; |
| 1536 | } |
| 1537 | |
| 1538 | crtc = fevent->crtc; |
| 1539 | sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1540 | cstate = to_sde_crtc_state(crtc->state); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1541 | |
| 1542 | sde_kms = _sde_crtc_get_kms(crtc); |
| 1543 | if (!sde_kms) { |
| 1544 | SDE_ERROR("invalid kms handle\n"); |
| 1545 | return; |
| 1546 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 1547 | priv = sde_kms->dev->dev_private; |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 1548 | SDE_ATRACE_BEGIN("crtc_frame_event"); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1549 | |
| 1550 | SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, |
| 1551 | ktime_to_ns(fevent->ts)); |
| 1552 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1553 | SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY); |
| 1554 | |
| 1555 | if (fevent->event & (SDE_ENCODER_FRAME_EVENT_DONE |
| 1556 | | SDE_ENCODER_FRAME_EVENT_ERROR |
| 1557 | | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1558 | |
| 1559 | if (atomic_read(&sde_crtc->frame_pending) < 1) { |
| 1560 | /* this should not happen */ |
| 1561 | SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n", |
| 1562 | crtc->base.id, |
| 1563 | ktime_to_ns(fevent->ts), |
| 1564 | atomic_read(&sde_crtc->frame_pending)); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1565 | SDE_EVT32(DRMID(crtc), fevent->event, |
| 1566 | SDE_EVTLOG_FUNC_CASE1); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1567 | } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) { |
| 1568 | /* release bandwidth and other resources */ |
| 1569 | SDE_DEBUG("crtc%d ts:%lld last pending\n", |
| 1570 | crtc->base.id, |
| 1571 | ktime_to_ns(fevent->ts)); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1572 | SDE_EVT32(DRMID(crtc), fevent->event, |
| 1573 | SDE_EVTLOG_FUNC_CASE2); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 1574 | sde_core_perf_crtc_release_bw(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1575 | } else { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1576 | SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, |
| 1577 | SDE_EVTLOG_FUNC_CASE3); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1578 | } |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1579 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1580 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_DONE) |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1581 | sde_core_perf_crtc_update(crtc, 0, false); |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1582 | |
| 1583 | if (fevent->event & (SDE_ENCODER_FRAME_EVENT_DONE |
| 1584 | | SDE_ENCODER_FRAME_EVENT_ERROR)) |
| 1585 | frame_done = true; |
| 1586 | } |
| 1587 | |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 1588 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) { |
| 1589 | SDE_ATRACE_BEGIN("signal_release_fence"); |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1590 | sde_fence_signal(&sde_crtc->output_fence, fevent->ts, 0); |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 1591 | SDE_ATRACE_END("signal_release_fence"); |
| 1592 | } |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1593 | |
| 1594 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE) { |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 1595 | SDE_ATRACE_BEGIN("signal_retire_fence"); |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1596 | for (i = 0; i < cstate->num_connectors; ++i) |
| 1597 | sde_connector_complete_commit(cstate->connectors[i], |
| 1598 | fevent->ts); |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 1599 | SDE_ATRACE_END("signal_retire_fence"); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1600 | } |
| 1601 | |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 1602 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) |
| 1603 | SDE_ERROR("crtc%d ts:%lld received panel dead event\n", |
| 1604 | crtc->base.id, ktime_to_ns(fevent->ts)); |
| 1605 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 1606 | if (frame_done) |
| 1607 | complete_all(&sde_crtc->frame_done_comp); |
| 1608 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1609 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 1610 | list_add_tail(&fevent->list, &sde_crtc->frame_event_list); |
| 1611 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 1612 | SDE_ATRACE_END("crtc_frame_event"); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1613 | } |
| 1614 | |
| 1615 | static void sde_crtc_frame_event_cb(void *data, u32 event) |
| 1616 | { |
| 1617 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
| 1618 | struct sde_crtc *sde_crtc; |
| 1619 | struct msm_drm_private *priv; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1620 | struct sde_crtc_frame_event *fevent; |
| 1621 | unsigned long flags; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 1622 | u32 crtc_id; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1623 | |
| 1624 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 1625 | SDE_ERROR("invalid parameters\n"); |
| 1626 | return; |
| 1627 | } |
| 1628 | sde_crtc = to_sde_crtc(crtc); |
| 1629 | priv = crtc->dev->dev_private; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 1630 | crtc_id = drm_crtc_index(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1631 | |
| 1632 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1633 | SDE_EVT32_VERBOSE(DRMID(crtc), event); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1634 | |
| 1635 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
Lloyd Atkinson | 78831f8 | 2016-12-09 11:24:56 -0500 | [diff] [blame] | 1636 | fevent = list_first_entry_or_null(&sde_crtc->frame_event_list, |
| 1637 | struct sde_crtc_frame_event, list); |
| 1638 | if (fevent) |
| 1639 | list_del_init(&fevent->list); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1640 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 1641 | |
Lloyd Atkinson | 78831f8 | 2016-12-09 11:24:56 -0500 | [diff] [blame] | 1642 | if (!fevent) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1643 | SDE_ERROR("crtc%d event %d overflow\n", |
| 1644 | crtc->base.id, event); |
| 1645 | SDE_EVT32(DRMID(crtc), event); |
| 1646 | return; |
| 1647 | } |
| 1648 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1649 | fevent->event = event; |
| 1650 | fevent->crtc = crtc; |
| 1651 | fevent->ts = ktime_get(); |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 1652 | kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1653 | } |
| 1654 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 1655 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1656 | * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout |
| 1657 | * @cstate: Pointer to sde crtc state |
| 1658 | */ |
| 1659 | static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate) |
| 1660 | { |
| 1661 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1662 | SDE_ERROR("invalid cstate\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1663 | return; |
| 1664 | } |
| 1665 | cstate->input_fence_timeout_ns = |
| 1666 | sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 1667 | cstate->input_fence_timeout_ns *= NSEC_PER_MSEC; |
| 1668 | } |
| 1669 | |
| 1670 | /** |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1671 | * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace |
| 1672 | * @cstate: Pointer to sde crtc state |
| 1673 | * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct |
| 1674 | */ |
| 1675 | static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate, |
| 1676 | void *usr_ptr) |
| 1677 | { |
| 1678 | struct sde_drm_dim_layer_v1 dim_layer_v1; |
| 1679 | struct sde_drm_dim_layer_cfg *user_cfg; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1680 | struct sde_hw_dim_layer *dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1681 | u32 count, i; |
| 1682 | |
| 1683 | if (!cstate) { |
| 1684 | SDE_ERROR("invalid cstate\n"); |
| 1685 | return; |
| 1686 | } |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1687 | dim_layer = cstate->dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1688 | |
| 1689 | if (!usr_ptr) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1690 | SDE_DEBUG("dim_layer data removed\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1691 | return; |
| 1692 | } |
| 1693 | |
| 1694 | if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1695 | SDE_ERROR("failed to copy dim_layer data\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1696 | return; |
| 1697 | } |
| 1698 | |
| 1699 | count = dim_layer_v1.num_layers; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1700 | if (count > SDE_MAX_DIM_LAYERS) { |
| 1701 | SDE_ERROR("invalid number of dim_layers:%d", count); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1702 | return; |
| 1703 | } |
| 1704 | |
| 1705 | /* populate from user space */ |
| 1706 | cstate->num_dim_layers = count; |
| 1707 | for (i = 0; i < count; i++) { |
| 1708 | user_cfg = &dim_layer_v1.layer_cfg[i]; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1709 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1710 | dim_layer[i].flags = user_cfg->flags; |
| 1711 | dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1712 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1713 | dim_layer[i].rect.x = user_cfg->rect.x1; |
| 1714 | dim_layer[i].rect.y = user_cfg->rect.y1; |
| 1715 | dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1; |
| 1716 | dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1; |
| 1717 | |
| 1718 | dim_layer[i].color_fill = (struct sde_mdss_color) { |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1719 | user_cfg->color_fill.color_0, |
| 1720 | user_cfg->color_fill.color_1, |
| 1721 | user_cfg->color_fill.color_2, |
| 1722 | user_cfg->color_fill.color_3, |
| 1723 | }; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1724 | |
| 1725 | SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n", |
| 1726 | i, dim_layer[i].flags, dim_layer[i].stage); |
| 1727 | SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n", |
| 1728 | dim_layer[i].rect.x, dim_layer[i].rect.y, |
| 1729 | dim_layer[i].rect.w, dim_layer[i].rect.h, |
| 1730 | dim_layer[i].color_fill.color_0, |
| 1731 | dim_layer[i].color_fill.color_1, |
| 1732 | dim_layer[i].color_fill.color_2, |
| 1733 | dim_layer[i].color_fill.color_3); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1734 | } |
| 1735 | } |
| 1736 | |
| 1737 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1738 | * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences |
| 1739 | * @crtc: Pointer to CRTC object |
| 1740 | */ |
| 1741 | static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc) |
| 1742 | { |
| 1743 | struct drm_plane *plane = NULL; |
| 1744 | uint32_t wait_ms = 1; |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 1745 | ktime_t kt_end, kt_wait; |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1746 | int rc = 0; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1747 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1748 | SDE_DEBUG("\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1749 | |
| 1750 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1751 | SDE_ERROR("invalid crtc/state %pK\n", crtc); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1752 | return; |
| 1753 | } |
| 1754 | |
| 1755 | /* use monotonic timer to limit total fence wait time */ |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 1756 | kt_end = ktime_add_ns(ktime_get(), |
| 1757 | to_sde_crtc_state(crtc->state)->input_fence_timeout_ns); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1758 | |
| 1759 | /* |
| 1760 | * Wait for fences sequentially, as all of them need to be signalled |
| 1761 | * before we can proceed. |
| 1762 | * |
| 1763 | * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call |
| 1764 | * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so |
| 1765 | * that each plane can check its fence status and react appropriately |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1766 | * if its fence has timed out. Call input fence wait multiple times if |
| 1767 | * fence wait is interrupted due to interrupt call. |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1768 | */ |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 1769 | SDE_ATRACE_BEGIN("plane_wait_input_fence"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1770 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1771 | do { |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 1772 | kt_wait = ktime_sub(kt_end, ktime_get()); |
| 1773 | if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0) |
| 1774 | wait_ms = ktime_to_ms(kt_wait); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1775 | else |
| 1776 | wait_ms = 0; |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1777 | |
| 1778 | rc = sde_plane_wait_input_fence(plane, wait_ms); |
| 1779 | } while (wait_ms && rc == -ERESTARTSYS); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1780 | } |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 1781 | SDE_ATRACE_END("plane_wait_input_fence"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1782 | } |
| 1783 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1784 | static void _sde_crtc_setup_mixer_for_encoder( |
| 1785 | struct drm_crtc *crtc, |
| 1786 | struct drm_encoder *enc) |
| 1787 | { |
| 1788 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1789 | struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1790 | struct sde_rm *rm = &sde_kms->rm; |
| 1791 | struct sde_crtc_mixer *mixer; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1792 | struct sde_hw_ctl *last_valid_ctl = NULL; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1793 | int i; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1794 | struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1795 | |
| 1796 | sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM); |
| 1797 | sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1798 | sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1799 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1800 | /* Set up all the mixers and ctls reserved by this encoder */ |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1801 | for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) { |
| 1802 | mixer = &sde_crtc->mixers[i]; |
| 1803 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1804 | if (!sde_rm_get_hw(rm, &lm_iter)) |
| 1805 | break; |
| 1806 | mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw; |
| 1807 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1808 | /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ |
| 1809 | if (!sde_rm_get_hw(rm, &ctl_iter)) { |
| 1810 | SDE_DEBUG("no ctl assigned to lm %d, using previous\n", |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1811 | mixer->hw_lm->idx - LM_0); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1812 | mixer->hw_ctl = last_valid_ctl; |
| 1813 | } else { |
| 1814 | mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw; |
| 1815 | last_valid_ctl = mixer->hw_ctl; |
| 1816 | } |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1817 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1818 | /* Shouldn't happen, mixers are always >= ctls */ |
| 1819 | if (!mixer->hw_ctl) { |
| 1820 | SDE_ERROR("no valid ctls found for lm %d\n", |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1821 | mixer->hw_lm->idx - LM_0); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1822 | return; |
| 1823 | } |
| 1824 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1825 | /* Dspp may be null */ |
| 1826 | (void) sde_rm_get_hw(rm, &dspp_iter); |
| 1827 | mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw; |
| 1828 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1829 | mixer->encoder = enc; |
| 1830 | |
| 1831 | sde_crtc->num_mixers++; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1832 | SDE_DEBUG("setup mixer %d: lm %d\n", |
| 1833 | i, mixer->hw_lm->idx - LM_0); |
| 1834 | SDE_DEBUG("setup mixer %d: ctl %d\n", |
| 1835 | i, mixer->hw_ctl->idx - CTL_0); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1836 | } |
| 1837 | } |
| 1838 | |
| 1839 | static void _sde_crtc_setup_mixers(struct drm_crtc *crtc) |
| 1840 | { |
| 1841 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1842 | struct drm_encoder *enc; |
| 1843 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1844 | sde_crtc->num_mixers = 0; |
| 1845 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 1846 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 1847 | mutex_lock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1848 | /* Check for mixers on all encoders attached to this crtc */ |
| 1849 | list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { |
| 1850 | if (enc->crtc != crtc) |
| 1851 | continue; |
| 1852 | |
| 1853 | _sde_crtc_setup_mixer_for_encoder(crtc, enc); |
| 1854 | } |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1855 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 1856 | mutex_unlock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1857 | } |
| 1858 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1859 | static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state) |
| 1860 | { |
| 1861 | int i; |
| 1862 | struct sde_crtc_state *cstate; |
| 1863 | |
| 1864 | cstate = to_sde_crtc_state(state); |
| 1865 | |
| 1866 | cstate->is_ppsplit = false; |
| 1867 | for (i = 0; i < cstate->num_connectors; i++) { |
| 1868 | struct drm_connector *conn = cstate->connectors[i]; |
| 1869 | |
| 1870 | if (sde_connector_get_topology_name(conn) == |
| 1871 | SDE_RM_TOPOLOGY_PPSPLIT) |
| 1872 | cstate->is_ppsplit = true; |
| 1873 | } |
| 1874 | } |
| 1875 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1876 | static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc, |
| 1877 | struct drm_crtc_state *state) |
| 1878 | { |
| 1879 | struct sde_crtc *sde_crtc; |
| 1880 | struct sde_crtc_state *cstate; |
| 1881 | struct drm_display_mode *adj_mode; |
| 1882 | u32 crtc_split_width; |
| 1883 | int i; |
| 1884 | |
| 1885 | if (!crtc || !state) { |
| 1886 | SDE_ERROR("invalid args\n"); |
| 1887 | return; |
| 1888 | } |
| 1889 | |
| 1890 | sde_crtc = to_sde_crtc(crtc); |
| 1891 | cstate = to_sde_crtc_state(state); |
| 1892 | |
| 1893 | adj_mode = &state->adjusted_mode; |
| 1894 | crtc_split_width = sde_crtc_mixer_width(sde_crtc, adj_mode); |
| 1895 | |
| 1896 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1897 | cstate->lm_bounds[i].x = crtc_split_width * i; |
| 1898 | cstate->lm_bounds[i].y = 0; |
| 1899 | cstate->lm_bounds[i].w = crtc_split_width; |
| 1900 | cstate->lm_bounds[i].h = adj_mode->vdisplay; |
| 1901 | memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i], |
| 1902 | sizeof(cstate->lm_roi[i])); |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 1903 | SDE_EVT32_VERBOSE(DRMID(crtc), i, |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1904 | cstate->lm_bounds[i].x, cstate->lm_bounds[i].y, |
| 1905 | cstate->lm_bounds[i].w, cstate->lm_bounds[i].h); |
| 1906 | SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i, |
| 1907 | cstate->lm_roi[i].x, cstate->lm_roi[i].y, |
| 1908 | cstate->lm_roi[i].w, cstate->lm_roi[i].h); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1909 | } |
| 1910 | |
| 1911 | drm_mode_debug_printmodeline(adj_mode); |
| 1912 | } |
| 1913 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1914 | static void sde_crtc_atomic_begin(struct drm_crtc *crtc, |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1915 | struct drm_crtc_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1916 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1917 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 1918 | struct drm_encoder *encoder; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1919 | struct drm_device *dev; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1920 | unsigned long flags; |
| 1921 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1922 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1923 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1924 | return; |
| 1925 | } |
| 1926 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 1927 | if (!crtc->state->enable) { |
| 1928 | SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", |
| 1929 | crtc->base.id, crtc->state->enable); |
| 1930 | return; |
| 1931 | } |
| 1932 | |
| 1933 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
| 1934 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1935 | sde_crtc = to_sde_crtc(crtc); |
| 1936 | dev = crtc->dev; |
| 1937 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1938 | if (!sde_crtc->num_mixers) { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1939 | _sde_crtc_setup_mixers(crtc); |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1940 | _sde_crtc_setup_is_ppsplit(crtc->state); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1941 | _sde_crtc_setup_lm_bounds(crtc, crtc->state); |
| 1942 | } |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1943 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 1944 | if (sde_crtc->event) { |
| 1945 | WARN_ON(sde_crtc->event); |
| 1946 | } else { |
| 1947 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1948 | sde_crtc->event = crtc->state->event; |
| 1949 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1950 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1951 | |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 1952 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1953 | if (encoder->crtc != crtc) |
| 1954 | continue; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 1955 | |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 1956 | /* encoder will trigger pending mask now */ |
| 1957 | sde_encoder_trigger_kickoff_pending(encoder); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 1958 | } |
| 1959 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1960 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1961 | * If no mixers have been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1962 | * it means we are trying to flush a CRTC whose state is disabled: |
| 1963 | * nothing else needs to be done. |
| 1964 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1965 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1966 | return; |
| 1967 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1968 | _sde_crtc_blend_setup(crtc); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1969 | sde_cp_crtc_apply_properties(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1970 | |
| 1971 | /* |
| 1972 | * PP_DONE irq is only used by command mode for now. |
| 1973 | * It is better to request pending before FLUSH and START trigger |
| 1974 | * to make sure no pp_done irq missed. |
| 1975 | * This is safe because no pp_done will happen before SW trigger |
| 1976 | * in command mode. |
| 1977 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1978 | } |
| 1979 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1980 | static void sde_crtc_atomic_flush(struct drm_crtc *crtc, |
| 1981 | struct drm_crtc_state *old_crtc_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1982 | { |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 1983 | struct drm_encoder *encoder; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1984 | struct sde_crtc *sde_crtc; |
| 1985 | struct drm_device *dev; |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 1986 | struct drm_plane *plane; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1987 | unsigned long flags; |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 1988 | struct sde_crtc_state *cstate; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1989 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1990 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1991 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1992 | return; |
| 1993 | } |
| 1994 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 1995 | if (!crtc->state->enable) { |
| 1996 | SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", |
| 1997 | crtc->base.id, crtc->state->enable); |
| 1998 | return; |
| 1999 | } |
| 2000 | |
| 2001 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2002 | |
| 2003 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2004 | cstate = to_sde_crtc_state(crtc->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2005 | dev = crtc->dev; |
| 2006 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2007 | if (sde_crtc->event) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2008 | SDE_DEBUG("already received sde_crtc->event\n"); |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2009 | } else { |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2010 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2011 | sde_crtc->event = crtc->state->event; |
| 2012 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2013 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2014 | |
| 2015 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2016 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2017 | * it means we are trying to flush a CRTC whose state is disabled: |
| 2018 | * nothing else needs to be done. |
| 2019 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2020 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2021 | return; |
| 2022 | |
Alan Kwong | 346223e | 2017-06-30 15:29:22 -0400 | [diff] [blame] | 2023 | /* |
| 2024 | * For planes without commit update, drm framework will not add |
| 2025 | * those planes to current state since hardware update is not |
| 2026 | * required. However, if those planes were power collapsed since |
| 2027 | * last commit cycle, driver has to restore the hardware state |
| 2028 | * of those planes explicitly here prior to plane flush. |
| 2029 | */ |
| 2030 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2031 | sde_plane_restore(plane); |
| 2032 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2033 | /* wait for acquire fences before anything else is done */ |
| 2034 | _sde_crtc_wait_for_fences(crtc); |
| 2035 | |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2036 | if (!cstate->rsc_update) { |
| 2037 | drm_for_each_encoder(encoder, dev) { |
| 2038 | if (encoder->crtc != crtc) |
| 2039 | continue; |
| 2040 | |
| 2041 | cstate->rsc_client = |
Dhaval Patel | 30fae8a | 2017-04-21 18:42:41 -0700 | [diff] [blame] | 2042 | sde_encoder_get_rsc_client(encoder); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2043 | } |
| 2044 | cstate->rsc_update = true; |
| 2045 | } |
| 2046 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2047 | /* update performance setting before crtc kickoff */ |
| 2048 | sde_core_perf_crtc_update(crtc, 1, false); |
| 2049 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2050 | /* |
| 2051 | * Final plane updates: Give each plane a chance to complete all |
| 2052 | * required writes/flushing before crtc's "flush |
| 2053 | * everything" call below. |
| 2054 | */ |
| 2055 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2056 | sde_plane_flush(plane); |
| 2057 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2058 | /* Kickoff will be scheduled by outer layer */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2059 | } |
| 2060 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2061 | /** |
| 2062 | * sde_crtc_destroy_state - state destroy hook |
| 2063 | * @crtc: drm CRTC |
| 2064 | * @state: CRTC state object to release |
| 2065 | */ |
| 2066 | static void sde_crtc_destroy_state(struct drm_crtc *crtc, |
| 2067 | struct drm_crtc_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2068 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2069 | struct sde_crtc *sde_crtc; |
| 2070 | struct sde_crtc_state *cstate; |
| 2071 | |
| 2072 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2073 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2074 | return; |
| 2075 | } |
| 2076 | |
| 2077 | sde_crtc = to_sde_crtc(crtc); |
| 2078 | cstate = to_sde_crtc_state(state); |
| 2079 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2080 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2081 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2082 | _sde_crtc_rp_destroy(&cstate->rp); |
| 2083 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2084 | __drm_atomic_helper_crtc_destroy_state(state); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2085 | |
| 2086 | /* destroy value helper */ |
| 2087 | msm_property_destroy_state(&sde_crtc->property_info, cstate, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 2088 | &cstate->property_state); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2089 | } |
| 2090 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2091 | static int _sde_crtc_wait_for_frame_done(struct drm_crtc *crtc) |
| 2092 | { |
| 2093 | struct sde_crtc *sde_crtc; |
| 2094 | int ret, rc = 0; |
| 2095 | |
| 2096 | if (!crtc) { |
| 2097 | SDE_ERROR("invalid argument\n"); |
| 2098 | return -EINVAL; |
| 2099 | } |
| 2100 | sde_crtc = to_sde_crtc(crtc); |
| 2101 | |
| 2102 | if (!atomic_read(&sde_crtc->frame_pending)) { |
| 2103 | SDE_DEBUG("no frames pending\n"); |
| 2104 | return 0; |
| 2105 | } |
| 2106 | |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 2107 | SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2108 | ret = wait_for_completion_timeout(&sde_crtc->frame_done_comp, |
| 2109 | msecs_to_jiffies(SDE_FRAME_DONE_TIMEOUT)); |
| 2110 | if (!ret) { |
| 2111 | SDE_ERROR("frame done completion wait timed out, ret:%d\n", |
| 2112 | ret); |
| 2113 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FATAL); |
| 2114 | rc = -ETIMEDOUT; |
| 2115 | } |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 2116 | SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2117 | |
| 2118 | return rc; |
| 2119 | } |
| 2120 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2121 | void sde_crtc_commit_kickoff(struct drm_crtc *crtc) |
| 2122 | { |
Clarence Ip | eb39cce | 2017-07-19 14:12:43 -0400 | [diff] [blame^] | 2123 | struct drm_plane *plane; |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2124 | struct drm_encoder *encoder; |
| 2125 | struct drm_device *dev; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2126 | struct sde_crtc *sde_crtc; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2127 | struct msm_drm_private *priv; |
| 2128 | struct sde_kms *sde_kms; |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2129 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2130 | int ret; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2131 | |
| 2132 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2133 | SDE_ERROR("invalid argument\n"); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2134 | return; |
| 2135 | } |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2136 | dev = crtc->dev; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2137 | sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2138 | sde_kms = _sde_crtc_get_kms(crtc); |
Narendra Muppalla | ec11a0a | 2017-06-15 15:35:17 -0700 | [diff] [blame] | 2139 | |
| 2140 | if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) { |
| 2141 | SDE_ERROR("invalid argument\n"); |
| 2142 | return; |
| 2143 | } |
| 2144 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2145 | priv = sde_kms->dev->dev_private; |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2146 | cstate = to_sde_crtc_state(crtc->state); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2147 | |
Clarence Ip | 90b282d | 2017-05-04 10:00:32 -0700 | [diff] [blame] | 2148 | /* |
| 2149 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
| 2150 | * it means we are trying to start a CRTC whose state is disabled: |
| 2151 | * nothing else needs to be done. |
| 2152 | */ |
| 2153 | if (unlikely(!sde_crtc->num_mixers)) |
| 2154 | return; |
| 2155 | |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2156 | SDE_ATRACE_BEGIN("crtc_commit"); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2157 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2158 | struct sde_encoder_kickoff_params params = { 0 }; |
| 2159 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2160 | if (encoder->crtc != crtc) |
| 2161 | continue; |
| 2162 | |
| 2163 | /* |
| 2164 | * Encoder will flush/start now, unless it has a tx pending. |
| 2165 | * If so, it may delay and flush at an irq event (e.g. ppdone) |
| 2166 | */ |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2167 | params.inline_rotate_prefill = cstate->sbuf_prefill_line; |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 2168 | params.affected_displays = _sde_crtc_get_displays_affected(crtc, |
| 2169 | crtc->state); |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2170 | sde_encoder_prepare_for_kickoff(encoder, ¶ms); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2171 | } |
| 2172 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2173 | /* wait for frame_event_done completion */ |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2174 | SDE_ATRACE_BEGIN("wait_for_frame_done_event"); |
| 2175 | ret = _sde_crtc_wait_for_frame_done(crtc); |
| 2176 | SDE_ATRACE_END("wait_for_frame_done_event"); |
| 2177 | if (ret) { |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2178 | SDE_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", |
| 2179 | crtc->base.id, |
| 2180 | atomic_read(&sde_crtc->frame_pending)); |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2181 | goto end; |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2182 | } |
| 2183 | |
| 2184 | if (atomic_inc_return(&sde_crtc->frame_pending) == 1) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2185 | /* acquire bandwidth and other resources */ |
| 2186 | SDE_DEBUG("crtc%d first commit\n", crtc->base.id); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2187 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2188 | } else { |
| 2189 | SDE_DEBUG("crtc%d commit\n", crtc->base.id); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2190 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2191 | } |
Dhaval Patel | d67cf4a | 2017-06-14 18:08:32 -0700 | [diff] [blame] | 2192 | sde_crtc->play_count++; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2193 | |
Clarence Ip | eb39cce | 2017-07-19 14:12:43 -0400 | [diff] [blame^] | 2194 | if (cstate->sbuf_cfg.rot_op_mode != SDE_CTL_ROT_OP_MODE_OFFLINE) |
| 2195 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2196 | sde_plane_kickoff(plane); |
| 2197 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2198 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2199 | if (encoder->crtc != crtc) |
| 2200 | continue; |
| 2201 | |
| 2202 | sde_encoder_kickoff(encoder); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2203 | } |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2204 | |
| 2205 | reinit_completion(&sde_crtc->frame_done_comp); |
| 2206 | |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2207 | end: |
| 2208 | SDE_ATRACE_END("crtc_commit"); |
| 2209 | return; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2210 | } |
| 2211 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2212 | /** |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2213 | * _sde_crtc_vblank_enable_nolock - update power resource and vblank request |
| 2214 | * @sde_crtc: Pointer to sde crtc structure |
| 2215 | * @enable: Whether to enable/disable vblanks |
| 2216 | */ |
| 2217 | static void _sde_crtc_vblank_enable_nolock( |
| 2218 | struct sde_crtc *sde_crtc, bool enable) |
| 2219 | { |
| 2220 | struct drm_device *dev; |
| 2221 | struct drm_crtc *crtc; |
| 2222 | struct drm_encoder *enc; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2223 | |
| 2224 | if (!sde_crtc) { |
| 2225 | SDE_ERROR("invalid crtc\n"); |
| 2226 | return; |
| 2227 | } |
| 2228 | |
| 2229 | crtc = &sde_crtc->base; |
| 2230 | dev = crtc->dev; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2231 | |
| 2232 | if (enable) { |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2233 | int ret; |
| 2234 | |
| 2235 | /* drop lock since power crtc cb may try to re-acquire lock */ |
| 2236 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2237 | ret = _sde_crtc_power_enable(sde_crtc, true); |
| 2238 | mutex_lock(&sde_crtc->crtc_lock); |
| 2239 | if (ret) |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 2240 | return; |
| 2241 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2242 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 2243 | if (enc->crtc != crtc) |
| 2244 | continue; |
| 2245 | |
| 2246 | SDE_EVT32(DRMID(crtc), DRMID(enc), enable); |
| 2247 | |
| 2248 | sde_encoder_register_vblank_callback(enc, |
| 2249 | sde_crtc_vblank_cb, (void *)crtc); |
| 2250 | } |
| 2251 | } else { |
| 2252 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 2253 | if (enc->crtc != crtc) |
| 2254 | continue; |
| 2255 | |
| 2256 | SDE_EVT32(DRMID(crtc), DRMID(enc), enable); |
| 2257 | |
| 2258 | sde_encoder_register_vblank_callback(enc, NULL, NULL); |
| 2259 | } |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2260 | |
| 2261 | /* drop lock since power crtc cb may try to re-acquire lock */ |
| 2262 | mutex_unlock(&sde_crtc->crtc_lock); |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 2263 | _sde_crtc_power_enable(sde_crtc, false); |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2264 | mutex_lock(&sde_crtc->crtc_lock); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2265 | } |
| 2266 | } |
| 2267 | |
| 2268 | /** |
| 2269 | * _sde_crtc_set_suspend - notify crtc of suspend enable/disable |
| 2270 | * @crtc: Pointer to drm crtc object |
| 2271 | * @enable: true to enable suspend, false to indicate resume |
| 2272 | */ |
| 2273 | static void _sde_crtc_set_suspend(struct drm_crtc *crtc, bool enable) |
| 2274 | { |
| 2275 | struct sde_crtc *sde_crtc; |
| 2276 | struct msm_drm_private *priv; |
| 2277 | struct sde_kms *sde_kms; |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2278 | struct drm_event event; |
| 2279 | u32 power_on; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2280 | |
| 2281 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 2282 | SDE_ERROR("invalid crtc\n"); |
| 2283 | return; |
| 2284 | } |
| 2285 | sde_crtc = to_sde_crtc(crtc); |
| 2286 | priv = crtc->dev->dev_private; |
| 2287 | |
| 2288 | if (!priv->kms) { |
| 2289 | SDE_ERROR("invalid crtc kms\n"); |
| 2290 | return; |
| 2291 | } |
| 2292 | sde_kms = to_sde_kms(priv->kms); |
| 2293 | |
| 2294 | SDE_DEBUG("crtc%d suspend = %d\n", crtc->base.id, enable); |
| 2295 | |
| 2296 | mutex_lock(&sde_crtc->crtc_lock); |
| 2297 | |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2298 | event.type = DRM_EVENT_CRTC_POWER; |
| 2299 | event.length = sizeof(u32); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2300 | /* |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2301 | * Update CP on suspend/resume transitions |
| 2302 | */ |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2303 | if (enable && !sde_crtc->suspend) { |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2304 | sde_cp_crtc_suspend(crtc); |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2305 | power_on = 0; |
| 2306 | } else if (!enable && sde_crtc->suspend) { |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2307 | sde_cp_crtc_resume(crtc); |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2308 | power_on = 1; |
| 2309 | } |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2310 | |
| 2311 | /* |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2312 | * If the vblank is enabled, release a power reference on suspend |
| 2313 | * and take it back during resume (if it is still enabled). |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2314 | */ |
| 2315 | if (sde_crtc->suspend == enable) |
| 2316 | SDE_DEBUG("crtc%d suspend already set to %d, ignoring update\n", |
| 2317 | crtc->base.id, enable); |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2318 | else if (sde_crtc->vblank_enable) |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2319 | _sde_crtc_vblank_enable_nolock(sde_crtc, !enable); |
| 2320 | |
| 2321 | sde_crtc->suspend = enable; |
Benjamin Chan | 34a92c7 | 2017-06-28 11:01:18 -0400 | [diff] [blame] | 2322 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2323 | (u8 *)&power_on); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2324 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2325 | } |
| 2326 | |
| 2327 | /** |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2328 | * sde_crtc_duplicate_state - state duplicate hook |
| 2329 | * @crtc: Pointer to drm crtc structure |
| 2330 | * @Returns: Pointer to new drm_crtc_state structure |
| 2331 | */ |
| 2332 | static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc) |
| 2333 | { |
| 2334 | struct sde_crtc *sde_crtc; |
| 2335 | struct sde_crtc_state *cstate, *old_cstate; |
| 2336 | |
| 2337 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2338 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2339 | return NULL; |
| 2340 | } |
| 2341 | |
| 2342 | sde_crtc = to_sde_crtc(crtc); |
| 2343 | old_cstate = to_sde_crtc_state(crtc->state); |
| 2344 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 2345 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2346 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2347 | return NULL; |
| 2348 | } |
| 2349 | |
| 2350 | /* duplicate value helper */ |
| 2351 | msm_property_duplicate_state(&sde_crtc->property_info, |
| 2352 | old_cstate, cstate, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 2353 | &cstate->property_state, cstate->property_values); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2354 | |
| 2355 | /* duplicate base helper */ |
| 2356 | __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); |
| 2357 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2358 | _sde_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp); |
| 2359 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2360 | return &cstate->base; |
| 2361 | } |
| 2362 | |
| 2363 | /** |
| 2364 | * sde_crtc_reset - reset hook for CRTCs |
| 2365 | * Resets the atomic state for @crtc by freeing the state pointer (which might |
| 2366 | * be NULL, e.g. at driver load time) and allocating a new empty state object. |
| 2367 | * @crtc: Pointer to drm crtc structure |
| 2368 | */ |
| 2369 | static void sde_crtc_reset(struct drm_crtc *crtc) |
| 2370 | { |
| 2371 | struct sde_crtc *sde_crtc; |
| 2372 | struct sde_crtc_state *cstate; |
| 2373 | |
| 2374 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2375 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2376 | return; |
| 2377 | } |
| 2378 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2379 | /* revert suspend actions, if necessary */ |
| 2380 | if (msm_is_suspend_state(crtc->dev)) |
| 2381 | _sde_crtc_set_suspend(crtc, false); |
| 2382 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2383 | /* remove previous state, if present */ |
| 2384 | if (crtc->state) { |
| 2385 | sde_crtc_destroy_state(crtc, crtc->state); |
| 2386 | crtc->state = 0; |
| 2387 | } |
| 2388 | |
| 2389 | sde_crtc = to_sde_crtc(crtc); |
| 2390 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 2391 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2392 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2393 | return; |
| 2394 | } |
| 2395 | |
| 2396 | /* reset value helper */ |
| 2397 | msm_property_reset_state(&sde_crtc->property_info, cstate, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 2398 | &cstate->property_state, |
| 2399 | cstate->property_values); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2400 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2401 | _sde_crtc_set_input_fence_timeout(cstate); |
| 2402 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2403 | _sde_crtc_rp_reset(&cstate->rp); |
| 2404 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2405 | cstate->base.crtc = crtc; |
| 2406 | crtc->state = &cstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2407 | } |
| 2408 | |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2409 | static int _sde_crtc_vblank_no_lock(struct sde_crtc *sde_crtc, bool en) |
| 2410 | { |
| 2411 | if (!sde_crtc) { |
| 2412 | SDE_ERROR("invalid crtc\n"); |
| 2413 | return -EINVAL; |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2414 | } |
| 2415 | |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2416 | if (!sde_crtc->base.enabled || sde_crtc->suspend) |
| 2417 | SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->base.enabled, en, |
| 2418 | sde_crtc->vblank_enable, sde_crtc->suspend); |
| 2419 | else if (sde_crtc->vblank_enable != en) |
| 2420 | _sde_crtc_vblank_enable_nolock(sde_crtc, en); |
| 2421 | sde_crtc->vblank_enable = en; |
| 2422 | |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2423 | return 0; |
| 2424 | } |
| 2425 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2426 | static void sde_crtc_handle_power_event(u32 event_type, void *arg) |
| 2427 | { |
| 2428 | struct drm_crtc *crtc = arg; |
| 2429 | struct sde_crtc *sde_crtc; |
| 2430 | struct drm_encoder *encoder; |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 2431 | struct drm_event event; |
| 2432 | u32 power_on = 0; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2433 | |
| 2434 | if (!crtc) { |
| 2435 | SDE_ERROR("invalid crtc\n"); |
| 2436 | return; |
| 2437 | } |
| 2438 | sde_crtc = to_sde_crtc(crtc); |
| 2439 | |
| 2440 | mutex_lock(&sde_crtc->crtc_lock); |
| 2441 | |
| 2442 | SDE_EVT32(DRMID(crtc), event_type); |
| 2443 | |
| 2444 | if (event_type == SDE_POWER_EVENT_POST_ENABLE) { |
| 2445 | /* restore encoder; crtc will be programmed during commit */ |
| 2446 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2447 | if (encoder->crtc != crtc) |
| 2448 | continue; |
| 2449 | |
| 2450 | sde_encoder_virt_restore(encoder); |
| 2451 | } |
Ping Li | e505f3b | 2017-06-19 14:19:08 -0700 | [diff] [blame] | 2452 | sde_cp_crtc_post_ipc(crtc); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2453 | |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 2454 | event.type = DRM_EVENT_SDE_POWER; |
| 2455 | event.length = sizeof(power_on); |
| 2456 | power_on = 1; |
| 2457 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
| 2458 | (u8 *)&power_on); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2459 | } else if (event_type == SDE_POWER_EVENT_POST_DISABLE) { |
| 2460 | struct drm_plane *plane; |
| 2461 | |
| 2462 | /* |
| 2463 | * set revalidate flag in planes, so it will be re-programmed |
| 2464 | * in the next frame update |
| 2465 | */ |
| 2466 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2467 | sde_plane_set_revalidate(plane, true); |
Alan Kwong | 8a9b38a | 2017-06-22 11:30:52 -0400 | [diff] [blame] | 2468 | |
Gopikrishnaiah Anandan | db90fa1 | 2017-05-09 17:56:08 -0700 | [diff] [blame] | 2469 | sde_cp_crtc_suspend(crtc); |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 2470 | |
| 2471 | event.type = DRM_EVENT_SDE_POWER; |
| 2472 | event.length = sizeof(power_on); |
| 2473 | power_on = 0; |
| 2474 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
| 2475 | (u8 *)&power_on); |
Ping Li | e505f3b | 2017-06-19 14:19:08 -0700 | [diff] [blame] | 2476 | } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) { |
| 2477 | sde_cp_crtc_pre_ipc(crtc); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2478 | } |
| 2479 | |
| 2480 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2481 | } |
| 2482 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2483 | static void sde_crtc_disable(struct drm_crtc *crtc) |
| 2484 | { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2485 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2486 | struct sde_crtc_state *cstate; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 2487 | struct drm_encoder *encoder; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2488 | struct msm_drm_private *priv; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2489 | unsigned long flags; |
| 2490 | struct sde_crtc_irq_info *node = NULL; |
| 2491 | int ret; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2492 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2493 | if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 2494 | SDE_ERROR("invalid crtc\n"); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2495 | return; |
| 2496 | } |
| 2497 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2498 | cstate = to_sde_crtc_state(crtc->state); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2499 | priv = crtc->dev->dev_private; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2500 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2501 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2502 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2503 | if (msm_is_suspend_state(crtc->dev)) |
| 2504 | _sde_crtc_set_suspend(crtc, true); |
| 2505 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 2506 | mutex_lock(&sde_crtc->crtc_lock); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2507 | SDE_EVT32(DRMID(crtc)); |
| 2508 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2509 | /* wait for frame_event_done completion */ |
| 2510 | if (_sde_crtc_wait_for_frame_done(crtc)) |
| 2511 | SDE_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", |
| 2512 | crtc->base.id, |
| 2513 | atomic_read(&sde_crtc->frame_pending)); |
| 2514 | |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2515 | if (sde_crtc->vblank_enable && !sde_crtc->suspend) { |
| 2516 | SDE_DEBUG("crtc%d vblank left enabled at disable time\n", |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2517 | crtc->base.id); |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2518 | SDE_EVT32(DRMID(crtc), sde_crtc->vblank_enable, |
| 2519 | SDE_EVTLOG_FUNC_CASE1); |
| 2520 | _sde_crtc_vblank_enable_nolock(sde_crtc, false); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 2521 | } |
| 2522 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2523 | if (atomic_read(&sde_crtc->frame_pending)) { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 2524 | SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending), |
| 2525 | SDE_EVTLOG_FUNC_CASE2); |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2526 | sde_core_perf_crtc_release_bw(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2527 | atomic_set(&sde_crtc->frame_pending, 0); |
| 2528 | } |
| 2529 | |
Ping Li | 6d5bf54 | 2017-06-27 11:40:28 -0700 | [diff] [blame] | 2530 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 2531 | list_for_each_entry(node, &sde_crtc->user_event_list, list) { |
| 2532 | ret = 0; |
| 2533 | if (node->func) |
| 2534 | ret = node->func(crtc, false, &node->irq); |
| 2535 | if (ret) |
| 2536 | SDE_ERROR("%s failed to disable event %x\n", |
| 2537 | sde_crtc->name, node->event); |
| 2538 | } |
| 2539 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 2540 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2541 | sde_core_perf_crtc_update(crtc, 0, true); |
| 2542 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2543 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2544 | if (encoder->crtc != crtc) |
| 2545 | continue; |
| 2546 | sde_encoder_register_frame_event_callback(encoder, NULL, NULL); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2547 | cstate->rsc_client = NULL; |
| 2548 | cstate->rsc_update = false; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2549 | } |
| 2550 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2551 | if (sde_crtc->power_event) |
| 2552 | sde_power_handle_unregister_event(&priv->phandle, |
| 2553 | sde_crtc->power_event); |
| 2554 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2555 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 2556 | sde_crtc->num_mixers = 0; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2557 | |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 2558 | /* disable clk & bw control until clk & bw properties are set */ |
| 2559 | cstate->bw_control = false; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 2560 | cstate->bw_split_vote = false; |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 2561 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 2562 | mutex_unlock(&sde_crtc->crtc_lock); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2563 | } |
| 2564 | |
| 2565 | static void sde_crtc_enable(struct drm_crtc *crtc) |
| 2566 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2567 | struct sde_crtc *sde_crtc; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2568 | struct drm_encoder *encoder; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2569 | struct msm_drm_private *priv; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2570 | unsigned long flags; |
| 2571 | struct sde_crtc_irq_info *node = NULL; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2572 | int ret; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 2573 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2574 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2575 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2576 | return; |
| 2577 | } |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2578 | priv = crtc->dev->dev_private; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2579 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2580 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2581 | SDE_EVT32(DRMID(crtc)); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2582 | sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 2583 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2584 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2585 | if (encoder->crtc != crtc) |
| 2586 | continue; |
| 2587 | sde_encoder_register_frame_event_callback(encoder, |
| 2588 | sde_crtc_frame_event_cb, (void *)crtc); |
| 2589 | } |
| 2590 | |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2591 | mutex_lock(&sde_crtc->crtc_lock); |
| 2592 | if (sde_crtc->vblank_enable) { |
| 2593 | /* honor user vblank request on crtc while it was disabled */ |
| 2594 | SDE_DEBUG("%s vblank found enabled at crtc enable time\n", |
| 2595 | sde_crtc->name); |
| 2596 | SDE_EVT32(DRMID(crtc), sde_crtc->vblank_enable); |
| 2597 | _sde_crtc_vblank_enable_nolock(sde_crtc, true); |
| 2598 | } |
| 2599 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2600 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2601 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 2602 | list_for_each_entry(node, &sde_crtc->user_event_list, list) { |
| 2603 | ret = 0; |
| 2604 | if (node->func) |
| 2605 | ret = node->func(crtc, true, &node->irq); |
| 2606 | if (ret) |
| 2607 | SDE_ERROR("%s failed to enable event %x\n", |
| 2608 | sde_crtc->name, node->event); |
| 2609 | } |
| 2610 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2611 | |
| 2612 | sde_crtc->power_event = sde_power_handle_register_event( |
| 2613 | &priv->phandle, |
Ping Li | e505f3b | 2017-06-19 14:19:08 -0700 | [diff] [blame] | 2614 | SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE | |
| 2615 | SDE_POWER_EVENT_PRE_DISABLE, |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2616 | sde_crtc_handle_power_event, crtc, sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2617 | } |
| 2618 | |
| 2619 | struct plane_state { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2620 | struct sde_plane_state *sde_pstate; |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2621 | const struct drm_plane_state *drm_pstate; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2622 | int stage; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2623 | u32 pipe_id; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2624 | }; |
| 2625 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2626 | static int pstate_cmp(const void *a, const void *b) |
| 2627 | { |
| 2628 | struct plane_state *pa = (struct plane_state *)a; |
| 2629 | struct plane_state *pb = (struct plane_state *)b; |
| 2630 | int rc = 0; |
| 2631 | int pa_zpos, pb_zpos; |
| 2632 | |
| 2633 | pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS); |
| 2634 | pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS); |
| 2635 | |
| 2636 | if (pa_zpos != pb_zpos) |
| 2637 | rc = pa_zpos - pb_zpos; |
| 2638 | else |
| 2639 | rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; |
| 2640 | |
| 2641 | return rc; |
| 2642 | } |
| 2643 | |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 2644 | static int _sde_crtc_excl_rect_overlap_check(struct plane_state pstates[], |
| 2645 | int cnt, int curr_cnt, struct sde_rect *excl_rect, int z_pos) |
| 2646 | { |
| 2647 | struct sde_rect dst_rect, intersect; |
| 2648 | int i, rc = -EINVAL; |
| 2649 | const struct drm_plane_state *pstate; |
| 2650 | |
| 2651 | /* start checking from next plane */ |
| 2652 | for (i = curr_cnt; i < cnt; i++) { |
| 2653 | pstate = pstates[i].drm_pstate; |
| 2654 | POPULATE_RECT(&dst_rect, pstate->crtc_x, pstate->crtc_y, |
Veera Sundaram Sankaran | 9d9ff91 | 2017-06-20 10:41:21 -0700 | [diff] [blame] | 2655 | pstate->crtc_w, pstate->crtc_h, false); |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 2656 | sde_kms_rect_intersect(&dst_rect, excl_rect, &intersect); |
| 2657 | |
| 2658 | if (intersect.w == excl_rect->w && intersect.h == excl_rect->h |
| 2659 | /* next plane may be on same z-order */ |
| 2660 | && z_pos != pstates[i].stage) { |
| 2661 | rc = 0; |
| 2662 | goto end; |
| 2663 | } |
| 2664 | } |
| 2665 | |
| 2666 | SDE_ERROR("excl rect does not find top overlapping rect\n"); |
| 2667 | end: |
| 2668 | return rc; |
| 2669 | } |
| 2670 | |
| 2671 | /* no input validation - caller API has all the checks */ |
| 2672 | static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state, |
| 2673 | struct plane_state pstates[], int cnt) |
| 2674 | { |
| 2675 | struct sde_crtc_state *cstate = to_sde_crtc_state(state); |
| 2676 | struct drm_display_mode *mode = &state->adjusted_mode; |
| 2677 | const struct drm_plane_state *pstate; |
| 2678 | struct sde_plane_state *sde_pstate; |
| 2679 | int rc = 0, i; |
| 2680 | |
| 2681 | /* Check dim layer rect bounds and stage */ |
| 2682 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 2683 | if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y, |
| 2684 | cstate->dim_layer[i].rect.h, mode->vdisplay)) || |
| 2685 | (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x, |
| 2686 | cstate->dim_layer[i].rect.w, mode->hdisplay)) || |
| 2687 | (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) || |
| 2688 | (!cstate->dim_layer[i].rect.w) || |
| 2689 | (!cstate->dim_layer[i].rect.h)) { |
| 2690 | SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n", |
| 2691 | cstate->dim_layer[i].rect.x, |
| 2692 | cstate->dim_layer[i].rect.y, |
| 2693 | cstate->dim_layer[i].rect.w, |
| 2694 | cstate->dim_layer[i].rect.h, |
| 2695 | cstate->dim_layer[i].stage); |
| 2696 | SDE_ERROR("display: %dx%d\n", mode->hdisplay, |
| 2697 | mode->vdisplay); |
| 2698 | rc = -E2BIG; |
| 2699 | goto end; |
| 2700 | } |
| 2701 | } |
| 2702 | |
| 2703 | /* this is traversing on sorted z-order pstates */ |
| 2704 | for (i = 0; i < cnt; i++) { |
| 2705 | pstate = pstates[i].drm_pstate; |
| 2706 | sde_pstate = to_sde_plane_state(pstate); |
| 2707 | if (sde_pstate->excl_rect.w && sde_pstate->excl_rect.h) { |
| 2708 | /* check overlap on all top z-order */ |
| 2709 | rc = _sde_crtc_excl_rect_overlap_check(pstates, cnt, |
| 2710 | i + 1, &sde_pstate->excl_rect, pstates[i].stage); |
| 2711 | if (rc) |
| 2712 | goto end; |
| 2713 | } |
| 2714 | } |
| 2715 | |
| 2716 | end: |
| 2717 | return rc; |
| 2718 | } |
| 2719 | |
Abhijit Kulkarni | 7444a7d | 2017-06-21 18:53:36 -0700 | [diff] [blame] | 2720 | static int _sde_crtc_find_plane_fb_modes(struct drm_crtc_state *state, |
| 2721 | uint32_t *fb_ns, |
| 2722 | uint32_t *fb_sec, |
| 2723 | uint32_t *fb_ns_dir, |
| 2724 | uint32_t *fb_sec_dir) |
| 2725 | { |
| 2726 | struct drm_plane *plane; |
| 2727 | const struct drm_plane_state *pstate; |
| 2728 | struct sde_plane_state *sde_pstate; |
| 2729 | uint32_t mode = 0; |
| 2730 | int rc; |
| 2731 | |
| 2732 | if (!state) { |
| 2733 | SDE_ERROR("invalid state\n"); |
| 2734 | return -EINVAL; |
| 2735 | } |
| 2736 | |
| 2737 | *fb_ns = 0; |
| 2738 | *fb_sec = 0; |
| 2739 | *fb_ns_dir = 0; |
| 2740 | *fb_sec_dir = 0; |
| 2741 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
| 2742 | if (IS_ERR_OR_NULL(pstate)) { |
| 2743 | rc = PTR_ERR(pstate); |
| 2744 | SDE_ERROR("crtc%d failed to get plane%d state%d\n", |
| 2745 | state->crtc->base.id, |
| 2746 | plane->base.id, rc); |
| 2747 | return rc; |
| 2748 | } |
| 2749 | sde_pstate = to_sde_plane_state(pstate); |
| 2750 | mode = sde_plane_get_property(sde_pstate, |
| 2751 | PLANE_PROP_FB_TRANSLATION_MODE); |
| 2752 | switch (mode) { |
| 2753 | case SDE_DRM_FB_NON_SEC: |
| 2754 | (*fb_ns)++; |
| 2755 | break; |
| 2756 | case SDE_DRM_FB_SEC: |
| 2757 | (*fb_sec)++; |
| 2758 | break; |
| 2759 | case SDE_DRM_FB_NON_SEC_DIR_TRANS: |
| 2760 | (*fb_ns_dir)++; |
| 2761 | break; |
| 2762 | case SDE_DRM_FB_SEC_DIR_TRANS: |
| 2763 | (*fb_sec_dir)++; |
| 2764 | break; |
| 2765 | default: |
| 2766 | SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d", |
| 2767 | plane->base.id, |
| 2768 | mode); |
| 2769 | return -EINVAL; |
| 2770 | } |
| 2771 | } |
| 2772 | return 0; |
| 2773 | } |
| 2774 | |
| 2775 | static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, |
| 2776 | struct drm_crtc_state *state) |
| 2777 | { |
| 2778 | struct drm_encoder *encoder; |
| 2779 | struct sde_crtc_state *cstate; |
| 2780 | uint32_t secure; |
| 2781 | uint32_t fb_ns = 0, fb_sec = 0, fb_ns_dir = 0, fb_sec_dir = 0; |
| 2782 | int encoder_cnt = 0; |
| 2783 | int rc; |
| 2784 | |
| 2785 | if (!crtc || !state) { |
| 2786 | SDE_ERROR("invalid arguments\n"); |
| 2787 | return -EINVAL; |
| 2788 | } |
| 2789 | |
| 2790 | cstate = to_sde_crtc_state(state); |
| 2791 | |
| 2792 | secure = sde_crtc_get_property(cstate, |
| 2793 | CRTC_PROP_SECURITY_LEVEL); |
| 2794 | |
| 2795 | rc = _sde_crtc_find_plane_fb_modes(state, |
| 2796 | &fb_ns, |
| 2797 | &fb_sec, |
| 2798 | &fb_ns_dir, |
| 2799 | &fb_sec_dir); |
| 2800 | if (rc) |
| 2801 | return rc; |
| 2802 | |
| 2803 | /** |
| 2804 | * validate planes |
| 2805 | * fb_ns_dir is for secure display use case, |
| 2806 | * fb_sec_dir is for secure camera preview use case, |
| 2807 | * fb_sec is for secure video playback, |
| 2808 | * fb_ns is for normal non secure use cases. |
| 2809 | */ |
| 2810 | if (((secure == SDE_DRM_SEC_ONLY) && |
| 2811 | (fb_ns || fb_sec || fb_sec_dir)) || |
| 2812 | (fb_sec || fb_sec_dir)) { |
| 2813 | SDE_ERROR( |
| 2814 | "crtc%d: invalid planes fb_modes Sec:%d, NS:%d, Sec_Dir:%d, NS_Dir%d\n", |
| 2815 | crtc->base.id, |
| 2816 | fb_sec, fb_ns, fb_sec_dir, |
| 2817 | fb_ns_dir); |
| 2818 | return -EINVAL; |
| 2819 | } |
| 2820 | |
| 2821 | /** |
| 2822 | * secure_crtc is not allowed in a shared toppolgy |
| 2823 | * across different encoders. |
| 2824 | */ |
| 2825 | if (fb_ns_dir || fb_sec_dir) { |
| 2826 | drm_for_each_encoder(encoder, crtc->dev) |
| 2827 | if (encoder->crtc == crtc) |
| 2828 | encoder_cnt++; |
| 2829 | |
| 2830 | if (encoder_cnt > |
| 2831 | MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) { |
| 2832 | SDE_ERROR( |
| 2833 | "crtc%d, invalid virtual encoder crtc%d\n", |
| 2834 | crtc->base.id, |
| 2835 | encoder_cnt); |
| 2836 | return -EINVAL; |
| 2837 | |
| 2838 | } |
| 2839 | } |
| 2840 | SDE_DEBUG("crtc:%d Secure validation successful\n", crtc->base.id); |
| 2841 | return 0; |
| 2842 | } |
| 2843 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2844 | static int sde_crtc_atomic_check(struct drm_crtc *crtc, |
| 2845 | struct drm_crtc_state *state) |
| 2846 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2847 | struct sde_crtc *sde_crtc; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2848 | struct plane_state pstates[SDE_STAGE_MAX * 4]; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2849 | struct sde_crtc_state *cstate; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2850 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2851 | const struct drm_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2852 | struct drm_plane *plane; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2853 | struct drm_display_mode *mode; |
| 2854 | |
| 2855 | int cnt = 0, rc = 0, mixer_width, i, z_pos; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2856 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2857 | struct sde_multirect_plane_states multirect_plane[SDE_STAGE_MAX * 2]; |
| 2858 | int multirect_count = 0; |
| 2859 | const struct drm_plane_state *pipe_staged[SSPP_MAX]; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2860 | int left_zpos_cnt = 0, right_zpos_cnt = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2861 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2862 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2863 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2864 | return -EINVAL; |
| 2865 | } |
| 2866 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2867 | sde_crtc = to_sde_crtc(crtc); |
| 2868 | cstate = to_sde_crtc_state(state); |
| 2869 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 2870 | if (!state->enable || !state->active) { |
| 2871 | SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", |
| 2872 | crtc->base.id, state->enable, state->active); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2873 | goto end; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 2874 | } |
| 2875 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2876 | mode = &state->adjusted_mode; |
| 2877 | SDE_DEBUG("%s: check", sde_crtc->name); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2878 | |
Clarence Ip | 90b282d | 2017-05-04 10:00:32 -0700 | [diff] [blame] | 2879 | /* force a full mode set if active state changed */ |
| 2880 | if (state->active_changed) |
| 2881 | state->mode_changed = true; |
| 2882 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2883 | memset(pipe_staged, 0, sizeof(pipe_staged)); |
| 2884 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2885 | mixer_width = sde_crtc_mixer_width(sde_crtc, mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2886 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 2887 | _sde_crtc_setup_is_ppsplit(state); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2888 | _sde_crtc_setup_lm_bounds(crtc, state); |
| 2889 | |
Abhijit Kulkarni | 7444a7d | 2017-06-21 18:53:36 -0700 | [diff] [blame] | 2890 | rc = _sde_crtc_check_secure_state(crtc, state); |
| 2891 | if (rc) |
| 2892 | return rc; |
| 2893 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2894 | /* get plane state for all drm planes associated with crtc state */ |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2895 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2896 | if (IS_ERR_OR_NULL(pstate)) { |
| 2897 | rc = PTR_ERR(pstate); |
| 2898 | SDE_ERROR("%s: failed to get plane%d state, %d\n", |
| 2899 | sde_crtc->name, plane->base.id, rc); |
Alan Kwong | 8576728 | 2016-10-03 18:03:37 -0400 | [diff] [blame] | 2900 | goto end; |
| 2901 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2902 | if (cnt >= ARRAY_SIZE(pstates)) |
| 2903 | continue; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2904 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2905 | pstates[cnt].sde_pstate = to_sde_plane_state(pstate); |
| 2906 | pstates[cnt].drm_pstate = pstate; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2907 | pstates[cnt].stage = sde_plane_get_property( |
| 2908 | pstates[cnt].sde_pstate, PLANE_PROP_ZPOS); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2909 | pstates[cnt].pipe_id = sde_plane_pipe(plane); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2910 | |
| 2911 | /* check dim layer stage with every plane */ |
| 2912 | for (i = 0; i < cstate->num_dim_layers; i++) { |
Veera Sundaram Sankaran | b9ed6bd | 2017-07-11 19:18:03 -0700 | [diff] [blame] | 2913 | if (cstate->dim_layer[i].stage |
| 2914 | == (pstates[cnt].stage + SDE_STAGE_0)) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2915 | SDE_ERROR( |
| 2916 | "plane:%d/dim_layer:%i-same stage:%d\n", |
| 2917 | plane->base.id, i, |
| 2918 | cstate->dim_layer[i].stage); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2919 | rc = -EINVAL; |
| 2920 | goto end; |
| 2921 | } |
| 2922 | } |
| 2923 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2924 | if (pipe_staged[pstates[cnt].pipe_id]) { |
| 2925 | multirect_plane[multirect_count].r0 = |
| 2926 | pipe_staged[pstates[cnt].pipe_id]; |
| 2927 | multirect_plane[multirect_count].r1 = pstate; |
| 2928 | multirect_count++; |
| 2929 | |
| 2930 | pipe_staged[pstates[cnt].pipe_id] = NULL; |
| 2931 | } else { |
| 2932 | pipe_staged[pstates[cnt].pipe_id] = pstate; |
| 2933 | } |
| 2934 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2935 | cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2936 | |
| 2937 | if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h, |
| 2938 | mode->vdisplay) || |
| 2939 | CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w, |
| 2940 | mode->hdisplay)) { |
| 2941 | SDE_ERROR("invalid vertical/horizontal destination\n"); |
| 2942 | SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n", |
| 2943 | pstate->crtc_y, pstate->crtc_h, mode->vdisplay, |
| 2944 | pstate->crtc_x, pstate->crtc_w, mode->hdisplay); |
| 2945 | rc = -E2BIG; |
| 2946 | goto end; |
| 2947 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2948 | } |
| 2949 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2950 | for (i = 1; i < SSPP_MAX; i++) { |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 2951 | if (pipe_staged[i]) { |
| 2952 | sde_plane_clear_multirect(pipe_staged[i]); |
| 2953 | |
| 2954 | if (is_sde_plane_virtual(pipe_staged[i]->plane)) { |
Veera Sundaram Sankaran | 372596d | 2017-06-21 17:57:25 -0700 | [diff] [blame] | 2955 | SDE_ERROR( |
| 2956 | "r1 only virt plane:%d not supported\n", |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2957 | pipe_staged[i]->plane->base.id); |
Veera Sundaram Sankaran | 372596d | 2017-06-21 17:57:25 -0700 | [diff] [blame] | 2958 | rc = -EINVAL; |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 2959 | goto end; |
| 2960 | } |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2961 | } |
| 2962 | } |
| 2963 | |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2964 | /* assign mixer stages based on sorted zpos property */ |
| 2965 | sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); |
| 2966 | |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 2967 | rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt); |
| 2968 | if (rc) |
| 2969 | goto end; |
| 2970 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2971 | if (!sde_is_custom_client()) { |
| 2972 | int stage_old = pstates[0].stage; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2973 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2974 | z_pos = 0; |
| 2975 | for (i = 0; i < cnt; i++) { |
| 2976 | if (stage_old != pstates[i].stage) |
| 2977 | ++z_pos; |
| 2978 | stage_old = pstates[i].stage; |
| 2979 | pstates[i].stage = z_pos; |
| 2980 | } |
| 2981 | } |
| 2982 | |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2983 | z_pos = -1; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2984 | for (i = 0; i < cnt; i++) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2985 | /* reset counts at every new blend stage */ |
| 2986 | if (pstates[i].stage != z_pos) { |
| 2987 | left_zpos_cnt = 0; |
| 2988 | right_zpos_cnt = 0; |
| 2989 | z_pos = pstates[i].stage; |
| 2990 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2991 | |
| 2992 | /* verify z_pos setting before using it */ |
Clarence Ip | 649989a | 2016-10-21 14:28:34 -0400 | [diff] [blame] | 2993 | if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2994 | SDE_ERROR("> %d plane stages assigned\n", |
| 2995 | SDE_STAGE_MAX - SDE_STAGE_0); |
| 2996 | rc = -EINVAL; |
| 2997 | goto end; |
| 2998 | } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2999 | if (left_zpos_cnt == 2) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3000 | SDE_ERROR("> 2 planes @ stage %d on left\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3001 | z_pos); |
| 3002 | rc = -EINVAL; |
| 3003 | goto end; |
| 3004 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3005 | left_zpos_cnt++; |
| 3006 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3007 | } else { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3008 | if (right_zpos_cnt == 2) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3009 | SDE_ERROR("> 2 planes @ stage %d on right\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3010 | z_pos); |
| 3011 | rc = -EINVAL; |
| 3012 | goto end; |
| 3013 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3014 | right_zpos_cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3015 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3016 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3017 | pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3018 | SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3019 | } |
| 3020 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3021 | for (i = 0; i < multirect_count; i++) { |
| 3022 | if (sde_plane_validate_multirect_v2(&multirect_plane[i])) { |
| 3023 | SDE_ERROR( |
| 3024 | "multirect validation failed for planes (%d - %d)\n", |
| 3025 | multirect_plane[i].r0->plane->base.id, |
| 3026 | multirect_plane[i].r1->plane->base.id); |
| 3027 | rc = -EINVAL; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3028 | goto end; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3029 | } |
| 3030 | } |
| 3031 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3032 | rc = sde_core_perf_crtc_check(crtc, state); |
| 3033 | if (rc) { |
| 3034 | SDE_ERROR("crtc%d failed performance check %d\n", |
| 3035 | crtc->base.id, rc); |
| 3036 | goto end; |
| 3037 | } |
| 3038 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3039 | /* validate source split: |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3040 | * use pstates sorted by stage to check planes on same stage |
| 3041 | * we assume that all pipes are in source split so its valid to compare |
| 3042 | * without taking into account left/right mixer placement |
| 3043 | */ |
| 3044 | for (i = 1; i < cnt; i++) { |
| 3045 | struct plane_state *prv_pstate, *cur_pstate; |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3046 | struct sde_rect left_rect, right_rect; |
| 3047 | int32_t left_pid, right_pid; |
| 3048 | int32_t stage; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3049 | |
| 3050 | prv_pstate = &pstates[i - 1]; |
| 3051 | cur_pstate = &pstates[i]; |
| 3052 | if (prv_pstate->stage != cur_pstate->stage) |
| 3053 | continue; |
| 3054 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3055 | stage = cur_pstate->stage; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3056 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3057 | left_pid = prv_pstate->sde_pstate->base.plane->base.id; |
| 3058 | POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x, |
| 3059 | prv_pstate->drm_pstate->crtc_y, |
| 3060 | prv_pstate->drm_pstate->crtc_w, |
| 3061 | prv_pstate->drm_pstate->crtc_h, false); |
| 3062 | |
| 3063 | right_pid = cur_pstate->sde_pstate->base.plane->base.id; |
| 3064 | POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x, |
| 3065 | cur_pstate->drm_pstate->crtc_y, |
| 3066 | cur_pstate->drm_pstate->crtc_w, |
| 3067 | cur_pstate->drm_pstate->crtc_h, false); |
| 3068 | |
| 3069 | if (right_rect.x < left_rect.x) { |
| 3070 | swap(left_pid, right_pid); |
| 3071 | swap(left_rect, right_rect); |
| 3072 | } |
| 3073 | |
| 3074 | /** |
| 3075 | * - planes are enumerated in pipe-priority order such that |
| 3076 | * planes with lower drm_id must be left-most in a shared |
| 3077 | * blend-stage when using source split. |
| 3078 | * - planes in source split must be contiguous in width |
| 3079 | * - planes in source split must have same dest yoff and height |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3080 | */ |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3081 | if (right_pid < left_pid) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3082 | SDE_ERROR( |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3083 | "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", |
| 3084 | stage, left_pid, right_pid); |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3085 | rc = -EINVAL; |
| 3086 | goto end; |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3087 | } else if (right_rect.x != (left_rect.x + left_rect.w)) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3088 | SDE_ERROR( |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3089 | "non-contiguous coordinates for src split. stage: %d left: %d - %d right: %d - %d\n", |
| 3090 | stage, left_rect.x, left_rect.w, |
| 3091 | right_rect.x, right_rect.w); |
| 3092 | rc = -EINVAL; |
| 3093 | goto end; |
| 3094 | } else if ((left_rect.y != right_rect.y) || |
| 3095 | (left_rect.h != right_rect.h)) { |
| 3096 | SDE_ERROR( |
| 3097 | "source split at stage: %d. invalid yoff/height: l_y: %d r_y: %d l_h: %d r_h: %d\n", |
| 3098 | stage, left_rect.y, right_rect.y, |
| 3099 | left_rect.h, right_rect.h); |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3100 | rc = -EINVAL; |
| 3101 | goto end; |
| 3102 | } |
| 3103 | } |
| 3104 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3105 | rc = _sde_crtc_check_rois(crtc, state); |
| 3106 | if (rc) { |
| 3107 | SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc); |
| 3108 | goto end; |
| 3109 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3110 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3111 | end: |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3112 | _sde_crtc_rp_free_unused(&cstate->rp); |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3113 | return rc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3114 | } |
| 3115 | |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 3116 | int sde_crtc_vblank(struct drm_crtc *crtc, bool en) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3117 | { |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3118 | struct sde_crtc *sde_crtc; |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 3119 | int rc; |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 3120 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3121 | if (!crtc) { |
| 3122 | SDE_ERROR("invalid crtc\n"); |
| 3123 | return -EINVAL; |
| 3124 | } |
| 3125 | sde_crtc = to_sde_crtc(crtc); |
| 3126 | |
| 3127 | mutex_lock(&sde_crtc->crtc_lock); |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 3128 | rc = _sde_crtc_vblank_no_lock(sde_crtc, en); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3129 | mutex_unlock(&sde_crtc->crtc_lock); |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 3130 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3131 | return rc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3132 | } |
| 3133 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 3134 | void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 3135 | { |
| 3136 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 3137 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 3138 | SDE_DEBUG("%s: cancel: %p\n", sde_crtc->name, file); |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3139 | _sde_crtc_complete_flip(crtc, file); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 3140 | } |
| 3141 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3142 | /** |
| 3143 | * sde_crtc_install_properties - install all drm properties for crtc |
| 3144 | * @crtc: Pointer to drm crtc structure |
| 3145 | */ |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3146 | static void sde_crtc_install_properties(struct drm_crtc *crtc, |
| 3147 | struct sde_mdss_cfg *catalog) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3148 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3149 | struct sde_crtc *sde_crtc; |
| 3150 | struct drm_device *dev; |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3151 | struct sde_kms_info *info; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3152 | struct sde_kms *sde_kms; |
Abhijit Kulkarni | 50d6944 | 2017-04-11 19:50:47 -0700 | [diff] [blame] | 3153 | static const struct drm_prop_enum_list e_secure_level[] = { |
| 3154 | {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"}, |
| 3155 | {SDE_DRM_SEC_ONLY, "sec_only"}, |
| 3156 | }; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3157 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3158 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3159 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3160 | if (!crtc || !catalog) { |
| 3161 | SDE_ERROR("invalid crtc or catalog\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3162 | return; |
| 3163 | } |
| 3164 | |
| 3165 | sde_crtc = to_sde_crtc(crtc); |
| 3166 | dev = crtc->dev; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3167 | sde_kms = _sde_crtc_get_kms(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3168 | |
Narendra Muppalla | ec11a0a | 2017-06-15 15:35:17 -0700 | [diff] [blame] | 3169 | if (!sde_kms) { |
| 3170 | SDE_ERROR("invalid argument\n"); |
| 3171 | return; |
| 3172 | } |
| 3173 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3174 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
| 3175 | if (!info) { |
| 3176 | SDE_ERROR("failed to allocate info memory\n"); |
| 3177 | return; |
| 3178 | } |
| 3179 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3180 | /* range properties */ |
| 3181 | msm_property_install_range(&sde_crtc->property_info, |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 3182 | "input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, |
| 3183 | SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 3184 | |
| 3185 | msm_property_install_range(&sde_crtc->property_info, "output_fence", |
| 3186 | 0x0, 0, INR_OPEN_MAX, 0x0, CRTC_PROP_OUTPUT_FENCE); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3187 | |
| 3188 | msm_property_install_range(&sde_crtc->property_info, |
| 3189 | "output_fence_offset", 0x0, 0, 1, 0, |
| 3190 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3191 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3192 | msm_property_install_range(&sde_crtc->property_info, |
| 3193 | "core_clk", 0x0, 0, U64_MAX, |
| 3194 | sde_kms->perf.max_core_clk_rate, |
| 3195 | CRTC_PROP_CORE_CLK); |
| 3196 | msm_property_install_range(&sde_crtc->property_info, |
| 3197 | "core_ab", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3198 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3199 | CRTC_PROP_CORE_AB); |
| 3200 | msm_property_install_range(&sde_crtc->property_info, |
| 3201 | "core_ib", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3202 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3203 | CRTC_PROP_CORE_IB); |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 3204 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3205 | "llcc_ab", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3206 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3207 | CRTC_PROP_LLCC_AB); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3208 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3209 | "llcc_ib", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3210 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3211 | CRTC_PROP_LLCC_IB); |
| 3212 | msm_property_install_range(&sde_crtc->property_info, |
| 3213 | "dram_ab", 0x0, 0, U64_MAX, |
| 3214 | catalog->perf.max_bw_high * 1000ULL, |
| 3215 | CRTC_PROP_DRAM_AB); |
| 3216 | msm_property_install_range(&sde_crtc->property_info, |
| 3217 | "dram_ib", 0x0, 0, U64_MAX, |
| 3218 | catalog->perf.max_bw_high * 1000ULL, |
| 3219 | CRTC_PROP_DRAM_IB); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3220 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 3221 | "rot_prefill_bw", 0, 0, U64_MAX, |
| 3222 | catalog->perf.max_bw_high * 1000ULL, |
| 3223 | CRTC_PROP_ROT_PREFILL_BW); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3224 | msm_property_install_range(&sde_crtc->property_info, |
| 3225 | "rot_clk", 0, 0, U64_MAX, |
| 3226 | sde_kms->perf.max_core_clk_rate, |
| 3227 | CRTC_PROP_ROT_CLK); |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3228 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3229 | msm_property_install_blob(&sde_crtc->property_info, "capabilities", |
| 3230 | DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3231 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3232 | msm_property_install_volatile_range(&sde_crtc->property_info, |
| 3233 | "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1); |
| 3234 | |
Abhijit Kulkarni | 50d6944 | 2017-04-11 19:50:47 -0700 | [diff] [blame] | 3235 | msm_property_install_enum(&sde_crtc->property_info, "security_level", |
| 3236 | 0x0, 0, e_secure_level, |
| 3237 | ARRAY_SIZE(e_secure_level), |
| 3238 | CRTC_PROP_SECURITY_LEVEL); |
| 3239 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3240 | sde_kms_info_reset(info); |
| 3241 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3242 | if (catalog->has_dim_layer) { |
| 3243 | msm_property_install_volatile_range(&sde_crtc->property_info, |
| 3244 | "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1); |
| 3245 | sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers", |
| 3246 | SDE_MAX_DIM_LAYERS); |
| 3247 | } |
| 3248 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3249 | sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion); |
| 3250 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 3251 | catalog->max_mixer_width); |
| 3252 | sde_kms_info_add_keyint(info, "max_blendstages", |
| 3253 | catalog->max_mixer_blendstages); |
| 3254 | if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2) |
| 3255 | sde_kms_info_add_keystr(info, "qseed_type", "qseed2"); |
| 3256 | if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3) |
| 3257 | sde_kms_info_add_keystr(info, "qseed_type", "qseed3"); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3258 | |
| 3259 | if (sde_is_custom_client()) { |
| 3260 | if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V1) |
| 3261 | sde_kms_info_add_keystr(info, |
| 3262 | "smart_dma_rev", "smart_dma_v1"); |
| 3263 | if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2) |
| 3264 | sde_kms_info_add_keystr(info, |
| 3265 | "smart_dma_rev", "smart_dma_v2"); |
| 3266 | } |
| 3267 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3268 | sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3269 | if (catalog->perf.max_bw_low) |
| 3270 | sde_kms_info_add_keyint(info, "max_bandwidth_low", |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3271 | catalog->perf.max_bw_low * 1000LL); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3272 | if (catalog->perf.max_bw_high) |
| 3273 | sde_kms_info_add_keyint(info, "max_bandwidth_high", |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3274 | catalog->perf.max_bw_high * 1000LL); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3275 | if (sde_kms->perf.max_core_clk_rate) |
| 3276 | sde_kms_info_add_keyint(info, "max_mdp_clk", |
| 3277 | sde_kms->perf.max_core_clk_rate); |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3278 | sde_kms_info_add_keystr(info, "core_ib_ff", |
| 3279 | catalog->perf.core_ib_ff); |
| 3280 | sde_kms_info_add_keystr(info, "core_clk_ff", |
| 3281 | catalog->perf.core_clk_ff); |
| 3282 | sde_kms_info_add_keystr(info, "comp_ratio_rt", |
| 3283 | catalog->perf.comp_ratio_rt); |
| 3284 | sde_kms_info_add_keystr(info, "comp_ratio_nrt", |
| 3285 | catalog->perf.comp_ratio_nrt); |
| 3286 | sde_kms_info_add_keyint(info, "dest_scale_prefill_lines", |
| 3287 | catalog->perf.dest_scale_prefill_lines); |
| 3288 | sde_kms_info_add_keyint(info, "undersized_prefill_lines", |
| 3289 | catalog->perf.undersized_prefill_lines); |
| 3290 | sde_kms_info_add_keyint(info, "macrotile_prefill_lines", |
| 3291 | catalog->perf.macrotile_prefill_lines); |
| 3292 | sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines", |
| 3293 | catalog->perf.yuv_nv12_prefill_lines); |
| 3294 | sde_kms_info_add_keyint(info, "linear_prefill_lines", |
| 3295 | catalog->perf.linear_prefill_lines); |
| 3296 | sde_kms_info_add_keyint(info, "downscaling_prefill_lines", |
| 3297 | catalog->perf.downscaling_prefill_lines); |
| 3298 | sde_kms_info_add_keyint(info, "xtra_prefill_lines", |
| 3299 | catalog->perf.xtra_prefill_lines); |
| 3300 | sde_kms_info_add_keyint(info, "amortizable_threshold", |
| 3301 | catalog->perf.amortizable_threshold); |
| 3302 | sde_kms_info_add_keyint(info, "min_prefill_lines", |
| 3303 | catalog->perf.min_prefill_lines); |
| 3304 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3305 | msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info, |
Narendra Muppalla | 22d1725 | 2017-05-31 15:13:39 -0700 | [diff] [blame] | 3306 | info->data, SDE_KMS_INFO_DATALEN(info), CRTC_PROP_INFO); |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3307 | |
| 3308 | kfree(info); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3309 | } |
| 3310 | |
| 3311 | /** |
| 3312 | * sde_crtc_atomic_set_property - atomically set a crtc drm property |
| 3313 | * @crtc: Pointer to drm crtc structure |
| 3314 | * @state: Pointer to drm crtc state structure |
| 3315 | * @property: Pointer to targeted drm property |
| 3316 | * @val: Updated property value |
| 3317 | * @Returns: Zero on success |
| 3318 | */ |
| 3319 | static int sde_crtc_atomic_set_property(struct drm_crtc *crtc, |
| 3320 | struct drm_crtc_state *state, |
| 3321 | struct drm_property *property, |
| 3322 | uint64_t val) |
| 3323 | { |
| 3324 | struct sde_crtc *sde_crtc; |
| 3325 | struct sde_crtc_state *cstate; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3326 | int idx, ret = -EINVAL; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3327 | |
| 3328 | if (!crtc || !state || !property) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3329 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3330 | } else { |
| 3331 | sde_crtc = to_sde_crtc(crtc); |
| 3332 | cstate = to_sde_crtc_state(state); |
| 3333 | ret = msm_property_atomic_set(&sde_crtc->property_info, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 3334 | &cstate->property_state, property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3335 | if (!ret) { |
| 3336 | idx = msm_property_index(&sde_crtc->property_info, |
| 3337 | property); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3338 | switch (idx) { |
| 3339 | case CRTC_PROP_INPUT_FENCE_TIMEOUT: |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3340 | _sde_crtc_set_input_fence_timeout(cstate); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3341 | break; |
| 3342 | case CRTC_PROP_DIM_LAYER_V1: |
| 3343 | _sde_crtc_set_dim_layer_v1(cstate, (void *)val); |
| 3344 | break; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3345 | case CRTC_PROP_ROI_V1: |
| 3346 | ret = _sde_crtc_set_roi_v1(state, (void *)val); |
| 3347 | break; |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 3348 | case CRTC_PROP_CORE_CLK: |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3349 | case CRTC_PROP_CORE_AB: |
| 3350 | case CRTC_PROP_CORE_IB: |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3351 | cstate->bw_control = true; |
| 3352 | break; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3353 | case CRTC_PROP_LLCC_AB: |
| 3354 | case CRTC_PROP_LLCC_IB: |
| 3355 | case CRTC_PROP_DRAM_AB: |
| 3356 | case CRTC_PROP_DRAM_IB: |
| 3357 | cstate->bw_control = true; |
| 3358 | cstate->bw_split_vote = true; |
| 3359 | break; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3360 | default: |
| 3361 | /* nothing to do */ |
| 3362 | break; |
| 3363 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3364 | } else { |
| 3365 | ret = sde_cp_crtc_set_property(crtc, |
| 3366 | property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3367 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3368 | if (ret) |
| 3369 | DRM_ERROR("failed to set the property\n"); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3370 | |
| 3371 | SDE_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id, |
| 3372 | property->name, property->base.id, val, ret); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3373 | } |
| 3374 | |
| 3375 | return ret; |
| 3376 | } |
| 3377 | |
| 3378 | /** |
| 3379 | * sde_crtc_set_property - set a crtc drm property |
| 3380 | * @crtc: Pointer to drm crtc structure |
| 3381 | * @property: Pointer to targeted drm property |
| 3382 | * @val: Updated property value |
| 3383 | * @Returns: Zero on success |
| 3384 | */ |
| 3385 | static int sde_crtc_set_property(struct drm_crtc *crtc, |
| 3386 | struct drm_property *property, uint64_t val) |
| 3387 | { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3388 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3389 | |
| 3390 | return sde_crtc_atomic_set_property(crtc, crtc->state, property, val); |
| 3391 | } |
| 3392 | |
| 3393 | /** |
| 3394 | * sde_crtc_atomic_get_property - retrieve a crtc drm property |
| 3395 | * @crtc: Pointer to drm crtc structure |
| 3396 | * @state: Pointer to drm crtc state structure |
| 3397 | * @property: Pointer to targeted drm property |
| 3398 | * @val: Pointer to variable for receiving property value |
| 3399 | * @Returns: Zero on success |
| 3400 | */ |
| 3401 | static int sde_crtc_atomic_get_property(struct drm_crtc *crtc, |
| 3402 | const struct drm_crtc_state *state, |
| 3403 | struct drm_property *property, |
| 3404 | uint64_t *val) |
| 3405 | { |
| 3406 | struct sde_crtc *sde_crtc; |
| 3407 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3408 | struct drm_encoder *encoder; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3409 | int i, ret = -EINVAL; |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3410 | bool conn_offset = 0; |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3411 | bool is_cmd = true; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3412 | |
| 3413 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3414 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3415 | } else { |
| 3416 | sde_crtc = to_sde_crtc(crtc); |
| 3417 | cstate = to_sde_crtc_state(state); |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3418 | |
| 3419 | for (i = 0; i < cstate->num_connectors; ++i) { |
| 3420 | conn_offset = sde_connector_needs_offset( |
| 3421 | cstate->connectors[i]); |
| 3422 | if (conn_offset) |
| 3423 | break; |
| 3424 | } |
| 3425 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3426 | /** |
| 3427 | * set the cmd flag only when all the encoders attached |
| 3428 | * to the crtc are in cmd mode. Consider all other cases |
| 3429 | * as video mode. |
| 3430 | */ |
| 3431 | drm_for_each_encoder(encoder, crtc->dev) { |
| 3432 | if (encoder->crtc == crtc) |
| 3433 | is_cmd &= sde_encoder_is_cmd_mode(encoder); |
| 3434 | } |
| 3435 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3436 | i = msm_property_index(&sde_crtc->property_info, property); |
| 3437 | if (i == CRTC_PROP_OUTPUT_FENCE) { |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 3438 | uint32_t offset = sde_crtc_get_property(cstate, |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3439 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
| 3440 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3441 | /** |
| 3442 | * set the offset to 0 only for cmd mode panels, so |
| 3443 | * the release fence for the current frame can be |
| 3444 | * triggered right after PP_DONE interrupt. |
| 3445 | */ |
| 3446 | offset = is_cmd ? 0 : (offset + conn_offset); |
| 3447 | |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3448 | ret = sde_fence_create(&sde_crtc->output_fence, val, |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3449 | offset); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3450 | if (ret) |
| 3451 | SDE_ERROR("fence create failed\n"); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3452 | } else { |
| 3453 | ret = msm_property_atomic_get(&sde_crtc->property_info, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 3454 | &cstate->property_state, |
| 3455 | property, val); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3456 | if (ret) |
| 3457 | ret = sde_cp_crtc_get_property(crtc, |
| 3458 | property, val); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3459 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3460 | if (ret) |
| 3461 | DRM_ERROR("get property failed\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3462 | } |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3463 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3464 | } |
| 3465 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3466 | #ifdef CONFIG_DEBUG_FS |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3467 | static int _sde_debugfs_status_show(struct seq_file *s, void *data) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3468 | { |
| 3469 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3470 | struct sde_plane_state *pstate = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3471 | struct sde_crtc_mixer *m; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3472 | |
| 3473 | struct drm_crtc *crtc; |
| 3474 | struct drm_plane *plane; |
| 3475 | struct drm_display_mode *mode; |
| 3476 | struct drm_framebuffer *fb; |
| 3477 | struct drm_plane_state *state; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3478 | struct sde_crtc_state *cstate; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3479 | |
| 3480 | int i, out_width; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3481 | |
| 3482 | if (!s || !s->private) |
| 3483 | return -EINVAL; |
| 3484 | |
| 3485 | sde_crtc = s->private; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3486 | crtc = &sde_crtc->base; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3487 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3488 | |
| 3489 | mutex_lock(&sde_crtc->crtc_lock); |
| 3490 | mode = &crtc->state->adjusted_mode; |
| 3491 | out_width = sde_crtc_mixer_width(sde_crtc, mode); |
| 3492 | |
| 3493 | seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, |
| 3494 | mode->hdisplay, mode->vdisplay); |
| 3495 | |
| 3496 | seq_puts(s, "\n"); |
| 3497 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3498 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 3499 | m = &sde_crtc->mixers[i]; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3500 | if (!m->hw_lm) |
| 3501 | seq_printf(s, "\tmixer[%d] has no lm\n", i); |
| 3502 | else if (!m->hw_ctl) |
| 3503 | seq_printf(s, "\tmixer[%d] has no ctl\n", i); |
| 3504 | else |
| 3505 | seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", |
| 3506 | m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0, |
| 3507 | out_width, mode->vdisplay); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3508 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 3509 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3510 | seq_puts(s, "\n"); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 3511 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3512 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 3513 | struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i]; |
| 3514 | |
| 3515 | seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n", |
| 3516 | i, dim_layer->stage, dim_layer->flags); |
| 3517 | seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n", |
| 3518 | dim_layer->rect.x, dim_layer->rect.y, |
| 3519 | dim_layer->rect.w, dim_layer->rect.h); |
| 3520 | seq_printf(s, |
| 3521 | "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n", |
| 3522 | dim_layer->color_fill.color_0, |
| 3523 | dim_layer->color_fill.color_1, |
| 3524 | dim_layer->color_fill.color_2, |
| 3525 | dim_layer->color_fill.color_3); |
| 3526 | seq_puts(s, "\n"); |
| 3527 | } |
| 3528 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3529 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
| 3530 | pstate = to_sde_plane_state(plane->state); |
| 3531 | state = plane->state; |
| 3532 | |
| 3533 | if (!pstate || !state) |
| 3534 | continue; |
| 3535 | |
| 3536 | seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, |
| 3537 | pstate->stage); |
| 3538 | |
| 3539 | if (plane->state->fb) { |
| 3540 | fb = plane->state->fb; |
| 3541 | |
| 3542 | seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u bpp:%d\n", |
| 3543 | fb->base.id, (char *) &fb->pixel_format, |
| 3544 | fb->width, fb->height, fb->bits_per_pixel); |
| 3545 | |
| 3546 | seq_puts(s, "\t"); |
| 3547 | for (i = 0; i < ARRAY_SIZE(fb->modifier); i++) |
| 3548 | seq_printf(s, "modifier[%d]:%8llu ", i, |
| 3549 | fb->modifier[i]); |
| 3550 | seq_puts(s, "\n"); |
| 3551 | |
| 3552 | seq_puts(s, "\t"); |
| 3553 | for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) |
| 3554 | seq_printf(s, "pitches[%d]:%8u ", i, |
| 3555 | fb->pitches[i]); |
| 3556 | seq_puts(s, "\n"); |
| 3557 | |
| 3558 | seq_puts(s, "\t"); |
| 3559 | for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) |
| 3560 | seq_printf(s, "offsets[%d]:%8u ", i, |
| 3561 | fb->offsets[i]); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 3562 | seq_puts(s, "\n"); |
| 3563 | } |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3564 | |
| 3565 | seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", |
| 3566 | state->src_x, state->src_y, state->src_w, state->src_h); |
| 3567 | |
| 3568 | seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", |
| 3569 | state->crtc_x, state->crtc_y, state->crtc_w, |
| 3570 | state->crtc_h); |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 3571 | seq_printf(s, "\tmultirect: mode: %d index: %d\n", |
| 3572 | pstate->multirect_mode, pstate->multirect_index); |
Veera Sundaram Sankaran | 58e1281 | 2017-05-05 11:51:09 -0700 | [diff] [blame] | 3573 | |
| 3574 | seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n", |
| 3575 | pstate->excl_rect.x, pstate->excl_rect.y, |
| 3576 | pstate->excl_rect.w, pstate->excl_rect.h); |
| 3577 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3578 | seq_puts(s, "\n"); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3579 | } |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3580 | |
| 3581 | if (sde_crtc->vblank_cb_count) { |
| 3582 | ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time); |
| 3583 | s64 diff_ms = ktime_to_ms(diff); |
| 3584 | s64 fps = diff_ms ? DIV_ROUND_CLOSEST( |
| 3585 | sde_crtc->vblank_cb_count * 1000, diff_ms) : 0; |
| 3586 | |
| 3587 | seq_printf(s, |
Dhaval Patel | d67cf4a | 2017-06-14 18:08:32 -0700 | [diff] [blame] | 3588 | "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", |
| 3589 | fps, sde_crtc->vblank_cb_count, |
| 3590 | ktime_to_ms(diff), sde_crtc->play_count); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3591 | |
| 3592 | /* reset time & count for next measurement */ |
| 3593 | sde_crtc->vblank_cb_count = 0; |
| 3594 | sde_crtc->vblank_cb_time = ktime_set(0, 0); |
| 3595 | } |
| 3596 | |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 3597 | seq_printf(s, "vblank_enable:%d\n", sde_crtc->vblank_enable); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3598 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3599 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3600 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3601 | return 0; |
| 3602 | } |
| 3603 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3604 | static int _sde_debugfs_status_open(struct inode *inode, struct file *file) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3605 | { |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3606 | return single_open(file, _sde_debugfs_status_show, inode->i_private); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3607 | } |
| 3608 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 3609 | static ssize_t _sde_crtc_misr_setup(struct file *file, |
| 3610 | const char __user *user_buf, size_t count, loff_t *ppos) |
| 3611 | { |
| 3612 | struct sde_crtc *sde_crtc; |
| 3613 | struct sde_crtc_mixer *m; |
| 3614 | int i = 0, rc; |
| 3615 | char buf[MISR_BUFF_SIZE + 1]; |
| 3616 | u32 frame_count, enable; |
| 3617 | size_t buff_copy; |
| 3618 | |
| 3619 | if (!file || !file->private_data) |
| 3620 | return -EINVAL; |
| 3621 | |
| 3622 | sde_crtc = file->private_data; |
| 3623 | buff_copy = min_t(size_t, count, MISR_BUFF_SIZE); |
| 3624 | if (copy_from_user(buf, user_buf, buff_copy)) { |
| 3625 | SDE_ERROR("buffer copy failed\n"); |
| 3626 | return -EINVAL; |
| 3627 | } |
| 3628 | |
| 3629 | buf[buff_copy] = 0; /* end of string */ |
| 3630 | |
| 3631 | if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) |
| 3632 | return -EINVAL; |
| 3633 | |
| 3634 | rc = _sde_crtc_power_enable(sde_crtc, true); |
| 3635 | if (rc) |
| 3636 | return rc; |
| 3637 | |
| 3638 | mutex_lock(&sde_crtc->crtc_lock); |
| 3639 | sde_crtc->misr_enable = enable; |
| 3640 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 3641 | m = &sde_crtc->mixers[i]; |
| 3642 | if (!m->hw_lm) |
| 3643 | continue; |
| 3644 | |
| 3645 | m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count); |
| 3646 | } |
| 3647 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3648 | _sde_crtc_power_enable(sde_crtc, false); |
| 3649 | |
| 3650 | return count; |
| 3651 | } |
| 3652 | |
| 3653 | static ssize_t _sde_crtc_misr_read(struct file *file, |
| 3654 | char __user *user_buff, size_t count, loff_t *ppos) |
| 3655 | { |
| 3656 | struct sde_crtc *sde_crtc; |
| 3657 | struct sde_crtc_mixer *m; |
| 3658 | int i = 0, rc; |
| 3659 | ssize_t len = 0; |
| 3660 | char buf[MISR_BUFF_SIZE + 1] = {'\0'}; |
| 3661 | |
| 3662 | if (*ppos) |
| 3663 | return 0; |
| 3664 | |
| 3665 | if (!file || !file->private_data) |
| 3666 | return -EINVAL; |
| 3667 | |
| 3668 | sde_crtc = file->private_data; |
| 3669 | rc = _sde_crtc_power_enable(sde_crtc, true); |
| 3670 | if (rc) |
| 3671 | return rc; |
| 3672 | |
| 3673 | mutex_lock(&sde_crtc->crtc_lock); |
| 3674 | if (!sde_crtc->misr_enable) { |
| 3675 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, |
| 3676 | "disabled\n"); |
| 3677 | goto buff_check; |
| 3678 | } |
| 3679 | |
| 3680 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 3681 | m = &sde_crtc->mixers[i]; |
| 3682 | if (!m->hw_lm) |
| 3683 | continue; |
| 3684 | |
| 3685 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n", |
| 3686 | m->hw_lm->idx - LM_0); |
| 3687 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n", |
| 3688 | m->hw_lm->ops.collect_misr(m->hw_lm)); |
| 3689 | } |
| 3690 | |
| 3691 | buff_check: |
| 3692 | if (count <= len) { |
| 3693 | len = 0; |
| 3694 | goto end; |
| 3695 | } |
| 3696 | |
| 3697 | if (copy_to_user(user_buff, buf, len)) { |
| 3698 | len = -EFAULT; |
| 3699 | goto end; |
| 3700 | } |
| 3701 | |
| 3702 | *ppos += len; /* increase offset */ |
| 3703 | |
| 3704 | end: |
| 3705 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3706 | _sde_crtc_power_enable(sde_crtc, false); |
| 3707 | return len; |
| 3708 | } |
| 3709 | |
| 3710 | #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \ |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3711 | static int __prefix ## _open(struct inode *inode, struct file *file) \ |
| 3712 | { \ |
| 3713 | return single_open(file, __prefix ## _show, inode->i_private); \ |
| 3714 | } \ |
| 3715 | static const struct file_operations __prefix ## _fops = { \ |
| 3716 | .owner = THIS_MODULE, \ |
| 3717 | .open = __prefix ## _open, \ |
| 3718 | .release = single_release, \ |
| 3719 | .read = seq_read, \ |
| 3720 | .llseek = seq_lseek, \ |
| 3721 | } |
| 3722 | |
| 3723 | static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v) |
| 3724 | { |
| 3725 | struct drm_crtc *crtc = (struct drm_crtc *) s->private; |
Alan Kwong | 751cf46 | 2017-06-08 10:26:46 -0400 | [diff] [blame] | 3726 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3727 | struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3728 | struct sde_crtc_res *res; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3729 | int i; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3730 | |
| 3731 | seq_printf(s, "num_connectors: %d\n", cstate->num_connectors); |
Dhaval Patel | 4d42460 | 2017-02-18 19:40:14 -0800 | [diff] [blame] | 3732 | seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc)); |
Alan Kwong | 3e985f0 | 2017-02-12 15:08:44 -0800 | [diff] [blame] | 3733 | seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc)); |
Alan Kwong | 751cf46 | 2017-06-08 10:26:46 -0400 | [diff] [blame] | 3734 | seq_printf(s, "core_clk_rate: %llu\n", |
| 3735 | sde_crtc->cur_perf.core_clk_rate); |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3736 | for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC; |
| 3737 | i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) { |
| 3738 | seq_printf(s, "bw_ctl[%s]: %llu\n", |
| 3739 | sde_power_handle_get_dbus_name(i), |
| 3740 | sde_crtc->cur_perf.bw_ctl[i]); |
| 3741 | seq_printf(s, "max_per_pipe_ib[%s]: %llu\n", |
| 3742 | sde_power_handle_get_dbus_name(i), |
| 3743 | sde_crtc->cur_perf.max_per_pipe_ib[i]); |
| 3744 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3745 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3746 | seq_printf(s, "rp.%d: ", cstate->rp.sequence_id); |
| 3747 | list_for_each_entry(res, &cstate->rp.res_list, list) |
| 3748 | seq_printf(s, "0x%x/0x%llx/%pK/%d ", |
| 3749 | res->type, res->tag, res->val, |
| 3750 | atomic_read(&res->refcount)); |
| 3751 | seq_puts(s, "\n"); |
| 3752 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3753 | return 0; |
| 3754 | } |
| 3755 | DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state); |
| 3756 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3757 | static int _sde_crtc_init_debugfs(struct drm_crtc *crtc) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3758 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3759 | struct sde_crtc *sde_crtc; |
| 3760 | struct sde_kms *sde_kms; |
| 3761 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3762 | static const struct file_operations debugfs_status_fops = { |
| 3763 | .open = _sde_debugfs_status_open, |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3764 | .read = seq_read, |
| 3765 | .llseek = seq_lseek, |
| 3766 | .release = single_release, |
| 3767 | }; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 3768 | static const struct file_operations debugfs_misr_fops = { |
| 3769 | .open = simple_open, |
| 3770 | .read = _sde_crtc_misr_read, |
| 3771 | .write = _sde_crtc_misr_setup, |
| 3772 | }; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3773 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3774 | if (!crtc) |
| 3775 | return -EINVAL; |
| 3776 | sde_crtc = to_sde_crtc(crtc); |
| 3777 | |
| 3778 | sde_kms = _sde_crtc_get_kms(crtc); |
| 3779 | if (!sde_kms) |
| 3780 | return -EINVAL; |
| 3781 | |
| 3782 | sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name, |
Lloyd Atkinson | 09e64bf | 2017-04-13 14:09:59 -0700 | [diff] [blame] | 3783 | crtc->dev->primary->debugfs_root); |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3784 | if (!sde_crtc->debugfs_root) |
| 3785 | return -ENOMEM; |
| 3786 | |
| 3787 | /* don't error check these */ |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 3788 | debugfs_create_file("status", 0400, |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3789 | sde_crtc->debugfs_root, |
| 3790 | sde_crtc, &debugfs_status_fops); |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 3791 | debugfs_create_file("state", 0600, |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3792 | sde_crtc->debugfs_root, |
| 3793 | &sde_crtc->base, |
| 3794 | &sde_crtc_debugfs_state_fops); |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 3795 | debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root, |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 3796 | sde_crtc, &debugfs_misr_fops); |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3797 | |
| 3798 | return 0; |
| 3799 | } |
| 3800 | |
| 3801 | static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc) |
| 3802 | { |
| 3803 | struct sde_crtc *sde_crtc; |
| 3804 | |
| 3805 | if (!crtc) |
| 3806 | return; |
| 3807 | sde_crtc = to_sde_crtc(crtc); |
| 3808 | debugfs_remove_recursive(sde_crtc->debugfs_root); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3809 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3810 | #else |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3811 | static int _sde_crtc_init_debugfs(struct drm_crtc *crtc) |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3812 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3813 | return 0; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3814 | } |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3815 | |
| 3816 | static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc) |
| 3817 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3818 | } |
| 3819 | #endif /* CONFIG_DEBUG_FS */ |
| 3820 | |
| 3821 | static int sde_crtc_late_register(struct drm_crtc *crtc) |
| 3822 | { |
| 3823 | return _sde_crtc_init_debugfs(crtc); |
| 3824 | } |
| 3825 | |
| 3826 | static void sde_crtc_early_unregister(struct drm_crtc *crtc) |
| 3827 | { |
| 3828 | _sde_crtc_destroy_debugfs(crtc); |
| 3829 | } |
| 3830 | |
| 3831 | static const struct drm_crtc_funcs sde_crtc_funcs = { |
| 3832 | .set_config = drm_atomic_helper_set_config, |
| 3833 | .destroy = sde_crtc_destroy, |
| 3834 | .page_flip = drm_atomic_helper_page_flip, |
| 3835 | .set_property = sde_crtc_set_property, |
| 3836 | .atomic_set_property = sde_crtc_atomic_set_property, |
| 3837 | .atomic_get_property = sde_crtc_atomic_get_property, |
| 3838 | .reset = sde_crtc_reset, |
| 3839 | .atomic_duplicate_state = sde_crtc_duplicate_state, |
| 3840 | .atomic_destroy_state = sde_crtc_destroy_state, |
| 3841 | .late_register = sde_crtc_late_register, |
| 3842 | .early_unregister = sde_crtc_early_unregister, |
| 3843 | }; |
| 3844 | |
| 3845 | static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = { |
| 3846 | .mode_fixup = sde_crtc_mode_fixup, |
| 3847 | .disable = sde_crtc_disable, |
| 3848 | .enable = sde_crtc_enable, |
| 3849 | .atomic_check = sde_crtc_atomic_check, |
| 3850 | .atomic_begin = sde_crtc_atomic_begin, |
| 3851 | .atomic_flush = sde_crtc_atomic_flush, |
| 3852 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3853 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3854 | static void _sde_crtc_event_cb(struct kthread_work *work) |
| 3855 | { |
| 3856 | struct sde_crtc_event *event; |
| 3857 | struct sde_crtc *sde_crtc; |
| 3858 | unsigned long irq_flags; |
| 3859 | |
| 3860 | if (!work) { |
| 3861 | SDE_ERROR("invalid work item\n"); |
| 3862 | return; |
| 3863 | } |
| 3864 | |
| 3865 | event = container_of(work, struct sde_crtc_event, kt_work); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3866 | |
| 3867 | /* set sde_crtc to NULL for static work structures */ |
| 3868 | sde_crtc = event->sde_crtc; |
| 3869 | if (!sde_crtc) |
| 3870 | return; |
| 3871 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3872 | if (event->cb_func) |
| 3873 | event->cb_func(&sde_crtc->base, event->usr); |
| 3874 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3875 | spin_lock_irqsave(&sde_crtc->event_lock, irq_flags); |
| 3876 | list_add_tail(&event->list, &sde_crtc->event_free_list); |
| 3877 | spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags); |
| 3878 | } |
| 3879 | |
| 3880 | int sde_crtc_event_queue(struct drm_crtc *crtc, |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3881 | void (*func)(struct drm_crtc *crtc, void *usr), void *usr) |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3882 | { |
| 3883 | unsigned long irq_flags; |
| 3884 | struct sde_crtc *sde_crtc; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 3885 | struct msm_drm_private *priv; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3886 | struct sde_crtc_event *event = NULL; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 3887 | u32 crtc_id; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3888 | |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 3889 | if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) { |
| 3890 | SDE_ERROR("invalid parameters\n"); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3891 | return -EINVAL; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 3892 | } |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3893 | sde_crtc = to_sde_crtc(crtc); |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 3894 | priv = crtc->dev->dev_private; |
| 3895 | crtc_id = drm_crtc_index(crtc); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3896 | |
| 3897 | /* |
| 3898 | * Obtain an event struct from the private cache. This event |
| 3899 | * queue may be called from ISR contexts, so use a private |
| 3900 | * cache to avoid calling any memory allocation functions. |
| 3901 | */ |
| 3902 | spin_lock_irqsave(&sde_crtc->event_lock, irq_flags); |
| 3903 | if (!list_empty(&sde_crtc->event_free_list)) { |
| 3904 | event = list_first_entry(&sde_crtc->event_free_list, |
| 3905 | struct sde_crtc_event, list); |
| 3906 | list_del_init(&event->list); |
| 3907 | } |
| 3908 | spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags); |
| 3909 | |
| 3910 | if (!event) |
| 3911 | return -ENOMEM; |
| 3912 | |
| 3913 | /* populate event node */ |
| 3914 | event->sde_crtc = sde_crtc; |
| 3915 | event->cb_func = func; |
| 3916 | event->usr = usr; |
| 3917 | |
| 3918 | /* queue new event request */ |
| 3919 | kthread_init_work(&event->kt_work, _sde_crtc_event_cb); |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 3920 | kthread_queue_work(&priv->event_thread[crtc_id].worker, |
| 3921 | &event->kt_work); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3922 | |
| 3923 | return 0; |
| 3924 | } |
| 3925 | |
| 3926 | static int _sde_crtc_init_events(struct sde_crtc *sde_crtc) |
| 3927 | { |
| 3928 | int i, rc = 0; |
| 3929 | |
| 3930 | if (!sde_crtc) { |
| 3931 | SDE_ERROR("invalid crtc\n"); |
| 3932 | return -EINVAL; |
| 3933 | } |
| 3934 | |
| 3935 | spin_lock_init(&sde_crtc->event_lock); |
| 3936 | |
| 3937 | INIT_LIST_HEAD(&sde_crtc->event_free_list); |
| 3938 | for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i) |
| 3939 | list_add_tail(&sde_crtc->event_cache[i].list, |
| 3940 | &sde_crtc->event_free_list); |
| 3941 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3942 | return rc; |
| 3943 | } |
| 3944 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3945 | /* initialize crtc */ |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 3946 | struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3947 | { |
| 3948 | struct drm_crtc *crtc = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3949 | struct sde_crtc *sde_crtc = NULL; |
| 3950 | struct msm_drm_private *priv = NULL; |
| 3951 | struct sde_kms *kms = NULL; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3952 | int i, rc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3953 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3954 | priv = dev->dev_private; |
| 3955 | kms = to_sde_kms(priv->kms); |
| 3956 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3957 | sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL); |
| 3958 | if (!sde_crtc) |
| 3959 | return ERR_PTR(-ENOMEM); |
| 3960 | |
| 3961 | crtc = &sde_crtc->base; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3962 | crtc->dev = dev; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3963 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3964 | mutex_init(&sde_crtc->crtc_lock); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3965 | spin_lock_init(&sde_crtc->spin_lock); |
| 3966 | atomic_set(&sde_crtc->frame_pending, 0); |
| 3967 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 3968 | init_completion(&sde_crtc->frame_done_comp); |
| 3969 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3970 | INIT_LIST_HEAD(&sde_crtc->frame_event_list); |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3971 | INIT_LIST_HEAD(&sde_crtc->user_event_list); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3972 | for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) { |
| 3973 | INIT_LIST_HEAD(&sde_crtc->frame_events[i].list); |
| 3974 | list_add(&sde_crtc->frame_events[i].list, |
| 3975 | &sde_crtc->frame_event_list); |
| 3976 | kthread_init_work(&sde_crtc->frame_events[i].work, |
| 3977 | sde_crtc_frame_event_work); |
| 3978 | } |
| 3979 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 3980 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs, |
| 3981 | NULL); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3982 | |
| 3983 | drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3984 | plane->crtc = crtc; |
| 3985 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3986 | /* save user friendly CRTC name for later */ |
| 3987 | snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); |
| 3988 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3989 | /* initialize event handling */ |
| 3990 | rc = _sde_crtc_init_events(sde_crtc); |
| 3991 | if (rc) { |
| 3992 | drm_crtc_cleanup(crtc); |
| 3993 | kfree(sde_crtc); |
| 3994 | return ERR_PTR(rc); |
| 3995 | } |
| 3996 | |
Clarence Ip | 9a74a44 | 2016-08-25 18:29:03 -0400 | [diff] [blame] | 3997 | /* initialize output fence support */ |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 3998 | sde_fence_init(&sde_crtc->output_fence, sde_crtc->name, crtc->base.id); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3999 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 4000 | /* create CRTC properties */ |
| 4001 | msm_property_init(&sde_crtc->property_info, &crtc->base, dev, |
| 4002 | priv->crtc_property, sde_crtc->property_data, |
| 4003 | CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT, |
| 4004 | sizeof(struct sde_crtc_state)); |
| 4005 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 4006 | sde_crtc_install_properties(crtc, kms->catalog); |
Gopikrishnaiah Anandan | 703eb90 | 2016-10-06 18:43:57 -0700 | [diff] [blame] | 4007 | |
| 4008 | /* Install color processing properties */ |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 4009 | sde_cp_crtc_init(crtc); |
Gopikrishnaiah Anandan | 703eb90 | 2016-10-06 18:43:57 -0700 | [diff] [blame] | 4010 | sde_cp_crtc_install_properties(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 4011 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 4012 | SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4013 | return crtc; |
| 4014 | } |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4015 | |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4016 | static int _sde_crtc_event_enable(struct sde_kms *kms, |
| 4017 | struct drm_crtc *crtc_drm, u32 event) |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4018 | { |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4019 | struct sde_crtc *crtc = NULL; |
| 4020 | struct sde_crtc_irq_info *node; |
| 4021 | struct msm_drm_private *priv; |
| 4022 | unsigned long flags; |
| 4023 | bool found = false; |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4024 | int ret, i = 0; |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4025 | |
| 4026 | crtc = to_sde_crtc(crtc_drm); |
| 4027 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 4028 | list_for_each_entry(node, &crtc->user_event_list, list) { |
| 4029 | if (node->event == event) { |
| 4030 | found = true; |
| 4031 | break; |
| 4032 | } |
| 4033 | } |
| 4034 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 4035 | |
| 4036 | /* event already enabled */ |
| 4037 | if (found) |
| 4038 | return 0; |
| 4039 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4040 | node = NULL; |
| 4041 | for (i = 0; i < ARRAY_SIZE(custom_events); i++) { |
| 4042 | if (custom_events[i].event == event && |
| 4043 | custom_events[i].func) { |
| 4044 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
| 4045 | if (!node) |
| 4046 | return -ENOMEM; |
| 4047 | node->event = event; |
| 4048 | INIT_LIST_HEAD(&node->list); |
| 4049 | node->func = custom_events[i].func; |
| 4050 | node->event = event; |
| 4051 | break; |
| 4052 | } |
| 4053 | } |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4054 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4055 | if (!node) { |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4056 | SDE_ERROR("unsupported event %x\n", event); |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4057 | return -EINVAL; |
| 4058 | } |
| 4059 | |
| 4060 | priv = kms->dev->dev_private; |
| 4061 | ret = 0; |
| 4062 | if (crtc_drm->enabled) { |
| 4063 | sde_power_resource_enable(&priv->phandle, kms->core_client, |
| 4064 | true); |
| 4065 | ret = node->func(crtc_drm, true, &node->irq); |
| 4066 | sde_power_resource_enable(&priv->phandle, kms->core_client, |
| 4067 | false); |
| 4068 | } |
| 4069 | |
| 4070 | if (!ret) { |
| 4071 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 4072 | list_add_tail(&node->list, &crtc->user_event_list); |
| 4073 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 4074 | } else { |
| 4075 | kfree(node); |
| 4076 | } |
| 4077 | |
| 4078 | return ret; |
| 4079 | } |
| 4080 | |
| 4081 | static int _sde_crtc_event_disable(struct sde_kms *kms, |
| 4082 | struct drm_crtc *crtc_drm, u32 event) |
| 4083 | { |
| 4084 | struct sde_crtc *crtc = NULL; |
| 4085 | struct sde_crtc_irq_info *node = NULL; |
| 4086 | struct msm_drm_private *priv; |
| 4087 | unsigned long flags; |
| 4088 | bool found = false; |
| 4089 | int ret; |
| 4090 | |
| 4091 | crtc = to_sde_crtc(crtc_drm); |
| 4092 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 4093 | list_for_each_entry(node, &crtc->user_event_list, list) { |
| 4094 | if (node->event == event) { |
| 4095 | list_del(&node->list); |
| 4096 | found = true; |
| 4097 | break; |
| 4098 | } |
| 4099 | } |
| 4100 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 4101 | |
| 4102 | /* event already disabled */ |
| 4103 | if (!found) |
| 4104 | return 0; |
| 4105 | |
| 4106 | /** |
| 4107 | * crtc is disabled interrupts are cleared remove from the list, |
| 4108 | * no need to disable/de-register. |
| 4109 | */ |
| 4110 | if (!crtc_drm->enabled) { |
| 4111 | kfree(node); |
| 4112 | return 0; |
| 4113 | } |
| 4114 | priv = kms->dev->dev_private; |
| 4115 | sde_power_resource_enable(&priv->phandle, kms->core_client, true); |
| 4116 | ret = node->func(crtc_drm, false, &node->irq); |
| 4117 | sde_power_resource_enable(&priv->phandle, kms->core_client, false); |
| 4118 | return ret; |
| 4119 | } |
| 4120 | |
| 4121 | int sde_crtc_register_custom_event(struct sde_kms *kms, |
| 4122 | struct drm_crtc *crtc_drm, u32 event, bool en) |
| 4123 | { |
| 4124 | struct sde_crtc *crtc = NULL; |
| 4125 | int ret; |
| 4126 | |
| 4127 | crtc = to_sde_crtc(crtc_drm); |
| 4128 | if (!crtc || !kms || !kms->dev) { |
| 4129 | DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc, |
| 4130 | kms, ((kms) ? (kms->dev) : NULL)); |
| 4131 | return -EINVAL; |
| 4132 | } |
| 4133 | |
| 4134 | if (en) |
| 4135 | ret = _sde_crtc_event_enable(kms, crtc_drm, event); |
| 4136 | else |
| 4137 | ret = _sde_crtc_event_disable(kms, crtc_drm, event); |
| 4138 | |
| 4139 | return ret; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4140 | } |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 4141 | |
| 4142 | static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm, |
| 4143 | bool en, struct sde_irq_callback *irq) |
| 4144 | { |
| 4145 | return 0; |
| 4146 | } |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 4147 | |
| 4148 | static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en, |
| 4149 | struct sde_irq_callback *noirq) |
| 4150 | { |
| 4151 | /* |
| 4152 | * IRQ object noirq is not being used here since there is |
| 4153 | * no crtc irq from pm event. |
| 4154 | */ |
| 4155 | return 0; |
| 4156 | } |