Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file contains work-arounds for many known PCI hardware |
| 3 | * bugs. Devices present only on certain architectures (host |
| 4 | * bridges et cetera) should be handled in arch-specific code. |
| 5 | * |
| 6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
| 7 | * |
| 8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
| 9 | * |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 10 | * Init/reset quirks for USB host controllers should be in the |
| 11 | * USB quirks file, where their drivers can access reuse it. |
| 12 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * The bridge optimization stuff has been removed. If you really |
| 14 | * have a silly BIOS which is unable to set your host bridge right, |
| 15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). |
| 16 | */ |
| 17 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/types.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/delay.h> |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 23 | #include <linux/acpi.h> |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 24 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
Doug Thompson | bd8481e | 2006-05-08 17:06:09 -0700 | [diff] [blame] | 26 | /* The Mellanox Tavor device gives false positive parity errors |
| 27 | * Mark this device with a broken_parity_status, to allow |
| 28 | * PCI scanning code to "skip" this now blacklisted device. |
| 29 | */ |
| 30 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) |
| 31 | { |
| 32 | dev->broken_parity_status = 1; /* This device gives false positives */ |
| 33 | } |
| 34 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); |
| 35 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | /* Deal with broken BIOS'es that neglect to enable passive release, |
| 38 | which can cause problems in combination with the 82441FX/PPro MTRRs */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 39 | static void quirk_passive_release(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | { |
| 41 | struct pci_dev *d = NULL; |
| 42 | unsigned char dlc; |
| 43 | |
| 44 | /* We have to make sure a particular bit is set in the PIIX3 |
| 45 | ISA bridge, so we have to go out and find it. */ |
| 46 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { |
| 47 | pci_read_config_byte(d, 0x82, &dlc); |
| 48 | if (!(dlc & 1<<1)) { |
| 49 | printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); |
| 50 | dlc |= 1<<1; |
| 51 | pci_write_config_byte(d, 0x82, dlc); |
| 52 | } |
| 53 | } |
| 54 | } |
| 55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 56 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | |
| 58 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround |
| 59 | but VIA don't answer queries. If you happen to have good contacts at VIA |
| 60 | ask them for me please -- Alan |
| 61 | |
| 62 | This appears to be BIOS not version dependent. So presumably there is a |
| 63 | chipset level fix */ |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 64 | int isa_dma_bridge_buggy; |
| 65 | EXPORT_SYMBOL(isa_dma_bridge_buggy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | |
| 67 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) |
| 68 | { |
| 69 | if (!isa_dma_bridge_buggy) { |
| 70 | isa_dma_bridge_buggy=1; |
| 71 | printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); |
| 72 | } |
| 73 | } |
| 74 | /* |
| 75 | * Its not totally clear which chipsets are the problematic ones |
| 76 | * We know 82C586 and 82C596 variants are affected. |
| 77 | */ |
| 78 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); |
| 79 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); |
| 80 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); |
| 81 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); |
| 82 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); |
| 83 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); |
| 84 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); |
| 85 | |
| 86 | int pci_pci_problems; |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 87 | EXPORT_SYMBOL(pci_pci_problems); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * Chipsets where PCI->PCI transfers vanish or hang |
| 91 | */ |
| 92 | static void __devinit quirk_nopcipci(struct pci_dev *dev) |
| 93 | { |
| 94 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { |
| 95 | printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); |
| 96 | pci_pci_problems |= PCIPCI_FAIL; |
| 97 | } |
| 98 | } |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 99 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); |
| 100 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 101 | |
| 102 | static void __devinit quirk_nopciamd(struct pci_dev *dev) |
| 103 | { |
| 104 | u8 rev; |
| 105 | pci_read_config_byte(dev, 0x08, &rev); |
| 106 | if (rev == 0x13) { |
| 107 | /* Erratum 24 */ |
| 108 | printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); |
| 109 | pci_pci_problems |= PCIAGP_FAIL; |
| 110 | } |
| 111 | } |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | * Triton requires workarounds to be used by the drivers |
| 116 | */ |
| 117 | static void __devinit quirk_triton(struct pci_dev *dev) |
| 118 | { |
| 119 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { |
| 120 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 121 | pci_pci_problems |= PCIPCI_TRITON; |
| 122 | } |
| 123 | } |
| 124 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); |
| 125 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); |
| 126 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); |
| 127 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); |
| 128 | |
| 129 | /* |
| 130 | * VIA Apollo KT133 needs PCI latency patch |
| 131 | * Made according to a windows driver based patch by George E. Breese |
| 132 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm |
| 133 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for |
| 134 | * the info on which Mr Breese based his work. |
| 135 | * |
| 136 | * Updated based on further information from the site and also on |
| 137 | * information provided by VIA |
| 138 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 139 | static void quirk_vialatency(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | { |
| 141 | struct pci_dev *p; |
| 142 | u8 rev; |
| 143 | u8 busarb; |
| 144 | /* Ok we have a potential problem chipset here. Now see if we have |
| 145 | a buggy southbridge */ |
| 146 | |
| 147 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
| 148 | if (p!=NULL) { |
| 149 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); |
| 150 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
| 151 | /* Check for buggy part revisions */ |
| 152 | if (rev < 0x40 || rev > 0x42) |
| 153 | goto exit; |
| 154 | } else { |
| 155 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); |
| 156 | if (p==NULL) /* No problem parts */ |
| 157 | goto exit; |
| 158 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); |
| 159 | /* Check for buggy part revisions */ |
| 160 | if (rev < 0x10 || rev > 0x12) |
| 161 | goto exit; |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * Ok we have the problem. Now set the PCI master grant to |
| 166 | * occur every master grant. The apparent bug is that under high |
| 167 | * PCI load (quite common in Linux of course) you can get data |
| 168 | * loss when the CPU is held off the bus for 3 bus master requests |
| 169 | * This happens to include the IDE controllers.... |
| 170 | * |
| 171 | * VIA only apply this fix when an SB Live! is present but under |
| 172 | * both Linux and Windows this isnt enough, and we have seen |
| 173 | * corruption without SB Live! but with things like 3 UDMA IDE |
| 174 | * controllers. So we ignore that bit of the VIA recommendation.. |
| 175 | */ |
| 176 | |
| 177 | pci_read_config_byte(dev, 0x76, &busarb); |
| 178 | /* Set bit 4 and bi 5 of byte 76 to 0x01 |
| 179 | "Master priority rotation on every PCI master grant */ |
| 180 | busarb &= ~(1<<5); |
| 181 | busarb |= (1<<4); |
| 182 | pci_write_config_byte(dev, 0x76, busarb); |
| 183 | printk(KERN_INFO "Applying VIA southbridge workaround.\n"); |
| 184 | exit: |
| 185 | pci_dev_put(p); |
| 186 | } |
| 187 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); |
| 188 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); |
| 189 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 190 | /* Must restore this on a resume from RAM */ |
| 191 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); |
| 192 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); |
| 193 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | |
| 195 | /* |
| 196 | * VIA Apollo VP3 needs ETBF on BT848/878 |
| 197 | */ |
| 198 | static void __devinit quirk_viaetbf(struct pci_dev *dev) |
| 199 | { |
| 200 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { |
| 201 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 202 | pci_pci_problems |= PCIPCI_VIAETBF; |
| 203 | } |
| 204 | } |
| 205 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); |
| 206 | |
| 207 | static void __devinit quirk_vsfx(struct pci_dev *dev) |
| 208 | { |
| 209 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { |
| 210 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 211 | pci_pci_problems |= PCIPCI_VSFX; |
| 212 | } |
| 213 | } |
| 214 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); |
| 215 | |
| 216 | /* |
| 217 | * Ali Magik requires workarounds to be used by the drivers |
| 218 | * that DMA to AGP space. Latency must be set to 0xA and triton |
| 219 | * workaround applied too |
| 220 | * [Info kindly provided by ALi] |
| 221 | */ |
| 222 | static void __init quirk_alimagik(struct pci_dev *dev) |
| 223 | { |
| 224 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { |
| 225 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 226 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
| 227 | } |
| 228 | } |
| 229 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); |
| 230 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); |
| 231 | |
| 232 | /* |
| 233 | * Natoma has some interesting boundary conditions with Zoran stuff |
| 234 | * at least |
| 235 | */ |
| 236 | static void __devinit quirk_natoma(struct pci_dev *dev) |
| 237 | { |
| 238 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { |
| 239 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 240 | pci_pci_problems |= PCIPCI_NATOMA; |
| 241 | } |
| 242 | } |
| 243 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); |
| 244 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); |
| 245 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); |
| 246 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); |
| 247 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); |
| 248 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); |
| 249 | |
| 250 | /* |
| 251 | * This chip can cause PCI parity errors if config register 0xA0 is read |
| 252 | * while DMAs are occurring. |
| 253 | */ |
| 254 | static void __devinit quirk_citrine(struct pci_dev *dev) |
| 255 | { |
| 256 | dev->cfg_size = 0xA0; |
| 257 | } |
| 258 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); |
| 259 | |
| 260 | /* |
| 261 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
| 262 | * If it's needed, re-allocate the region. |
| 263 | */ |
| 264 | static void __devinit quirk_s3_64M(struct pci_dev *dev) |
| 265 | { |
| 266 | struct resource *r = &dev->resource[0]; |
| 267 | |
| 268 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { |
| 269 | r->start = 0; |
| 270 | r->end = 0x3ffffff; |
| 271 | } |
| 272 | } |
| 273 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); |
| 274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); |
| 275 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 276 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
| 277 | unsigned size, int nr, const char *name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | { |
| 279 | region &= ~(size-1); |
| 280 | if (region) { |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 281 | struct pci_bus_region bus_region; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | struct resource *res = dev->resource + nr; |
| 283 | |
| 284 | res->name = pci_name(dev); |
| 285 | res->start = region; |
| 286 | res->end = region + size - 1; |
| 287 | res->flags = IORESOURCE_IO; |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 288 | |
| 289 | /* Convert from PCI bus to resource space. */ |
| 290 | bus_region.start = res->start; |
| 291 | bus_region.end = res->end; |
| 292 | pcibios_bus_to_resource(dev, res, &bus_region); |
| 293 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | pci_claim_resource(dev, nr); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 295 | printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | } |
| 297 | } |
| 298 | |
| 299 | /* |
| 300 | * ATI Northbridge setups MCE the processor if you even |
| 301 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 |
| 302 | */ |
| 303 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) |
| 304 | { |
| 305 | printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); |
| 306 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
| 307 | request_region(0x3b0, 0x0C, "RadeonIGP"); |
| 308 | request_region(0x3d3, 0x01, "RadeonIGP"); |
| 309 | } |
| 310 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); |
| 311 | |
| 312 | /* |
| 313 | * Let's make the southbridge information explicit instead |
| 314 | * of having to worry about people probing the ACPI areas, |
| 315 | * for example.. (Yes, it happens, and if you read the wrong |
| 316 | * ACPI register it will put the machine to sleep with no |
| 317 | * way of waking it up again. Bummer). |
| 318 | * |
| 319 | * ALI M7101: Two IO regions pointed to by words at |
| 320 | * 0xE0 (64 bytes of ACPI registers) |
| 321 | * 0xE2 (32 bytes of SMB registers) |
| 322 | */ |
| 323 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) |
| 324 | { |
| 325 | u16 region; |
| 326 | |
| 327 | pci_read_config_word(dev, 0xE0, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 328 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | pci_read_config_word(dev, 0xE2, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 330 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | } |
| 332 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); |
| 333 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 334 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 335 | { |
| 336 | u32 devres; |
| 337 | u32 mask, size, base; |
| 338 | |
| 339 | pci_read_config_dword(dev, port, &devres); |
| 340 | if ((devres & enable) != enable) |
| 341 | return; |
| 342 | mask = (devres >> 16) & 15; |
| 343 | base = devres & 0xffff; |
| 344 | size = 16; |
| 345 | for (;;) { |
| 346 | unsigned bit = size >> 1; |
| 347 | if ((bit & mask) == bit) |
| 348 | break; |
| 349 | size = bit; |
| 350 | } |
| 351 | /* |
| 352 | * For now we only print it out. Eventually we'll want to |
| 353 | * reserve it (at least if it's in the 0x1000+ range), but |
| 354 | * let's get enough confirmation reports first. |
| 355 | */ |
| 356 | base &= -size; |
| 357 | printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); |
| 358 | } |
| 359 | |
| 360 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 361 | { |
| 362 | u32 devres; |
| 363 | u32 mask, size, base; |
| 364 | |
| 365 | pci_read_config_dword(dev, port, &devres); |
| 366 | if ((devres & enable) != enable) |
| 367 | return; |
| 368 | base = devres & 0xffff0000; |
| 369 | mask = (devres & 0x3f) << 16; |
| 370 | size = 128 << 16; |
| 371 | for (;;) { |
| 372 | unsigned bit = size >> 1; |
| 373 | if ((bit & mask) == bit) |
| 374 | break; |
| 375 | size = bit; |
| 376 | } |
| 377 | /* |
| 378 | * For now we only print it out. Eventually we'll want to |
| 379 | * reserve it, but let's get enough confirmation reports first. |
| 380 | */ |
| 381 | base &= -size; |
| 382 | printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
| 383 | } |
| 384 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | /* |
| 386 | * PIIX4 ACPI: Two IO regions pointed to by longwords at |
| 387 | * 0x40 (64 bytes of ACPI registers) |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 388 | * 0x90 (16 bytes of SMB registers) |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 389 | * and a few strange programmable PIIX4 device resources. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | */ |
| 391 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) |
| 392 | { |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 393 | u32 region, res_a; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | |
| 395 | pci_read_config_dword(dev, 0x40, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 396 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | pci_read_config_dword(dev, 0x90, ®ion); |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 398 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 399 | |
| 400 | /* Device resource A has enables for some of the other ones */ |
| 401 | pci_read_config_dword(dev, 0x5c, &res_a); |
| 402 | |
| 403 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); |
| 404 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); |
| 405 | |
| 406 | /* Device resource D is just bitfields for static resources */ |
| 407 | |
| 408 | /* Device 12 enabled? */ |
| 409 | if (res_a & (1 << 29)) { |
| 410 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); |
| 411 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); |
| 412 | } |
| 413 | /* Device 13 enabled? */ |
| 414 | if (res_a & (1 << 30)) { |
| 415 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); |
| 416 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); |
| 417 | } |
| 418 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); |
| 419 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | } |
| 421 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); |
Linus Torvalds | c676466 | 2006-07-12 08:29:46 -0700 | [diff] [blame] | 422 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | |
| 424 | /* |
| 425 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at |
| 426 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) |
| 427 | * 0x58 (64 bytes of GPIO I/O space) |
| 428 | */ |
| 429 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) |
| 430 | { |
| 431 | u32 region; |
| 432 | |
| 433 | pci_read_config_dword(dev, 0x40, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 434 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | |
| 436 | pci_read_config_dword(dev, 0x58, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 437 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | } |
| 439 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); |
| 440 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); |
| 441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); |
| 442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); |
| 443 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); |
| 444 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); |
| 445 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); |
| 446 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); |
| 447 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); |
R.Marek@sh.cvut.cz | 3aa8c4f | 2005-04-21 10:49:06 +0000 | [diff] [blame] | 448 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 450 | static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) |
| 451 | { |
| 452 | u32 region; |
| 453 | |
| 454 | pci_read_config_dword(dev, 0x40, ®ion); |
| 455 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); |
| 456 | |
| 457 | pci_read_config_dword(dev, 0x48, ®ion); |
| 458 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); |
| 459 | } |
Daniel Ritz | 65ae4dd | 2006-08-22 07:29:10 -0700 | [diff] [blame] | 460 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); |
Daniel Ritz | bacedce | 2006-09-25 16:52:21 -0700 | [diff] [blame] | 462 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi ); |
| 463 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi ); |
| 464 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi ); |
| 465 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi ); |
| 466 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi ); |
| 467 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi ); |
Zhao Yakui | d1ec729 | 2008-01-11 00:24:55 -0500 | [diff] [blame] | 468 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi ); |
| 469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi ); |
| 470 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi ); |
| 471 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi ); |
| 472 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi ); |
| 473 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi ); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 474 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | /* |
| 476 | * VIA ACPI: One IO region pointed to by longword at |
| 477 | * 0x48 or 0x20 (256 bytes of ACPI registers) |
| 478 | */ |
| 479 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) |
| 480 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | u32 region; |
| 482 | |
Auke Kok | 651472f | 2007-08-27 16:18:10 -0700 | [diff] [blame] | 483 | if (dev->revision & 0x10) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | pci_read_config_dword(dev, 0x48, ®ion); |
| 485 | region &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 486 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | } |
| 488 | } |
| 489 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); |
| 490 | |
| 491 | /* |
| 492 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at |
| 493 | * 0x48 (256 bytes of ACPI registers) |
| 494 | * 0x70 (128 bytes of hardware monitoring register) |
| 495 | * 0x90 (16 bytes of SMB registers) |
| 496 | */ |
| 497 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) |
| 498 | { |
| 499 | u16 hm; |
| 500 | u32 smb; |
| 501 | |
| 502 | quirk_vt82c586_acpi(dev); |
| 503 | |
| 504 | pci_read_config_word(dev, 0x70, &hm); |
| 505 | hm &= PCI_BASE_ADDRESS_IO_MASK; |
Meelis Roos | 02f313b | 2005-10-29 13:31:49 +0300 | [diff] [blame] | 506 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | |
| 508 | pci_read_config_dword(dev, 0x90, &smb); |
| 509 | smb &= PCI_BASE_ADDRESS_IO_MASK; |
Meelis Roos | 02f313b | 2005-10-29 13:31:49 +0300 | [diff] [blame] | 510 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | } |
| 512 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); |
| 513 | |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 514 | /* |
| 515 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at |
| 516 | * 0x88 (128 bytes of power management registers) |
| 517 | * 0xd0 (16 bytes of SMB registers) |
| 518 | */ |
| 519 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) |
| 520 | { |
| 521 | u16 pm, smb; |
| 522 | |
| 523 | pci_read_config_word(dev, 0x88, &pm); |
| 524 | pm &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 525 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 526 | |
| 527 | pci_read_config_word(dev, 0xd0, &smb); |
| 528 | smb &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 529 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 530 | } |
| 531 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); |
| 532 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 533 | |
| 534 | #ifdef CONFIG_X86_IO_APIC |
| 535 | |
| 536 | #include <asm/io_apic.h> |
| 537 | |
| 538 | /* |
| 539 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip |
| 540 | * devices to the external APIC. |
| 541 | * |
| 542 | * TODO: When we have device-specific interrupt routers, |
| 543 | * this code will go away from quirks. |
| 544 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 545 | static void quirk_via_ioapic(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | { |
| 547 | u8 tmp; |
| 548 | |
| 549 | if (nr_ioapics < 1) |
| 550 | tmp = 0; /* nothing routed to external APIC */ |
| 551 | else |
| 552 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ |
| 553 | |
| 554 | printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", |
| 555 | tmp == 0 ? "Disa" : "Ena"); |
| 556 | |
| 557 | /* Offset 0x58: External APIC IRQ output control */ |
| 558 | pci_write_config_byte (dev, 0x58, tmp); |
| 559 | } |
| 560 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 561 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | |
| 563 | /* |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 564 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. |
| 565 | * This leads to doubled level interrupt rates. |
| 566 | * Set this bit to get rid of cycle wastage. |
| 567 | * Otherwise uncritical. |
| 568 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 569 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 570 | { |
| 571 | u8 misc_control2; |
| 572 | #define BYPASS_APIC_DEASSERT 8 |
| 573 | |
| 574 | pci_read_config_byte(dev, 0x5B, &misc_control2); |
| 575 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { |
| 576 | printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); |
| 577 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
| 578 | } |
| 579 | } |
| 580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 581 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 582 | |
| 583 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 584 | * The AMD io apic can hang the box when an apic irq is masked. |
| 585 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
| 586 | * is currently marked NoFix |
| 587 | * |
| 588 | * We have multiple reports of hangs with this chipset that went away with |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 589 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | * of course. However the advice is demonstrably good even if so.. |
| 591 | */ |
| 592 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) |
| 593 | { |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 594 | if (dev->revision >= 0x02) { |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 595 | printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); |
| 597 | } |
| 598 | } |
| 599 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); |
| 600 | |
| 601 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) |
| 602 | { |
| 603 | if (dev->devfn == 0 && dev->bus->number == 0) |
| 604 | sis_apic_bug = 1; |
| 605 | } |
| 606 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); |
| 607 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | #define AMD8131_revA0 0x01 |
| 609 | #define AMD8131_revB0 0x11 |
| 610 | #define AMD8131_MISC 0x40 |
| 611 | #define AMD8131_NIOAMODE_BIT 0 |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 612 | static void quirk_amd_8131_ioapic(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | { |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 614 | unsigned char tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 616 | if (nr_ioapics == 0) |
| 617 | return; |
| 618 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 619 | if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); |
| 621 | pci_read_config_byte( dev, AMD8131_MISC, &tmp); |
| 622 | tmp &= ~(1 << AMD8131_NIOAMODE_BIT); |
| 623 | pci_write_config_byte( dev, AMD8131_MISC, tmp); |
| 624 | } |
| 625 | } |
John W. Linville | 5da594b | 2006-03-20 14:33:56 -0500 | [diff] [blame] | 626 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 627 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | #endif /* CONFIG_X86_IO_APIC */ |
| 629 | |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 630 | /* |
| 631 | * Some settings of MMRBC can lead to data corruption so block changes. |
| 632 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide |
| 633 | */ |
| 634 | static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) |
| 635 | { |
Auke Kok | aa288d4 | 2007-08-27 16:17:47 -0700 | [diff] [blame] | 636 | if (dev->subordinate && dev->revision <= 0x12) { |
Andrew Morton | b7b095c | 2007-07-09 11:55:50 -0700 | [diff] [blame] | 637 | printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X " |
Auke Kok | aa288d4 | 2007-08-27 16:17:47 -0700 | [diff] [blame] | 638 | "MMRBC\n", dev->revision); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 639 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
| 640 | } |
| 641 | } |
| 642 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 643 | |
| 644 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | * FIXME: it is questionable that quirk_via_acpi |
| 646 | * is needed. It shows up as an ISA bridge, and does not |
| 647 | * support the PCI_INTERRUPT_LINE register at all. Therefore |
| 648 | * it seems like setting the pci_dev's 'irq' to the |
| 649 | * value of the ACPI SCI interrupt is only done for convenience. |
| 650 | * -jgarzik |
| 651 | */ |
| 652 | static void __devinit quirk_via_acpi(struct pci_dev *d) |
| 653 | { |
| 654 | /* |
| 655 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 |
| 656 | */ |
| 657 | u8 irq; |
| 658 | pci_read_config_byte(d, 0x42, &irq); |
| 659 | irq &= 0xf; |
| 660 | if (irq && (irq != 2)) |
| 661 | d->irq = irq; |
| 662 | } |
| 663 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); |
| 664 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); |
| 665 | |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 666 | |
| 667 | /* |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 668 | * VIA bridges which have VLink |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 669 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 670 | |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 671 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
| 672 | |
| 673 | static void quirk_via_bridge(struct pci_dev *dev) |
| 674 | { |
| 675 | /* See what bridge we have and find the device ranges */ |
| 676 | switch (dev->device) { |
| 677 | case PCI_DEVICE_ID_VIA_82C686: |
Jean Delvare | cb7468e | 2007-01-31 23:48:12 -0800 | [diff] [blame] | 678 | /* The VT82C686 is special, it attaches to PCI and can have |
| 679 | any device number. All its subdevices are functions of |
| 680 | that single device. */ |
| 681 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); |
| 682 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 683 | break; |
| 684 | case PCI_DEVICE_ID_VIA_8237: |
| 685 | case PCI_DEVICE_ID_VIA_8237A: |
| 686 | via_vlink_dev_lo = 15; |
| 687 | break; |
| 688 | case PCI_DEVICE_ID_VIA_8235: |
| 689 | via_vlink_dev_lo = 16; |
| 690 | break; |
| 691 | case PCI_DEVICE_ID_VIA_8231: |
| 692 | case PCI_DEVICE_ID_VIA_8233_0: |
| 693 | case PCI_DEVICE_ID_VIA_8233A: |
| 694 | case PCI_DEVICE_ID_VIA_8233C_0: |
| 695 | via_vlink_dev_lo = 17; |
| 696 | break; |
| 697 | } |
| 698 | } |
| 699 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); |
| 700 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); |
| 701 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); |
| 702 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); |
| 703 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); |
| 704 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); |
| 705 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); |
| 706 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 707 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 708 | /** |
| 709 | * quirk_via_vlink - VIA VLink IRQ number update |
| 710 | * @dev: PCI device |
| 711 | * |
| 712 | * If the device we are dealing with is on a PIC IRQ we need to |
| 713 | * ensure that the IRQ line register which usually is not relevant |
| 714 | * for PCI cards, is actually written so that interrupts get sent |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 715 | * to the right place. |
| 716 | * We only do this on systems where a VIA south bridge was detected, |
| 717 | * and only for VIA devices on the motherboard (see quirk_via_bridge |
| 718 | * above). |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 719 | */ |
| 720 | |
| 721 | static void quirk_via_vlink(struct pci_dev *dev) |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 722 | { |
| 723 | u8 irq, new_irq; |
| 724 | |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 725 | /* Check if we have VLink at all */ |
| 726 | if (via_vlink_dev_lo == -1) |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 727 | return; |
| 728 | |
| 729 | new_irq = dev->irq; |
| 730 | |
| 731 | /* Don't quirk interrupts outside the legacy IRQ range */ |
| 732 | if (!new_irq || new_irq > 15) |
| 733 | return; |
| 734 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 735 | /* Internal device ? */ |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 736 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
| 737 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 738 | return; |
| 739 | |
| 740 | /* This is an internal VLink device on a PIC interrupt. The BIOS |
| 741 | ought to have set this but may not have, so we redo it */ |
| 742 | |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 743 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
| 744 | if (new_irq != irq) { |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 745 | printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n", |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 746 | pci_name(dev), irq, new_irq); |
| 747 | udelay(15); /* unknown if delay really needed */ |
| 748 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); |
| 749 | } |
| 750 | } |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 751 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 752 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | * VIA VT82C598 has its device ID settable and many BIOSes |
| 755 | * set it to the ID of VT82C597 for backward compatibility. |
| 756 | * We need to switch it off to be able to recognize the real |
| 757 | * type of the chip. |
| 758 | */ |
| 759 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) |
| 760 | { |
| 761 | pci_write_config_byte(dev, 0xfc, 0); |
| 762 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); |
| 763 | } |
| 764 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); |
| 765 | |
| 766 | /* |
| 767 | * CardBus controllers have a legacy base address that enables them |
| 768 | * to respond as i82365 pcmcia controllers. We don't want them to |
| 769 | * do this even if the Linux CardBus driver is not loaded, because |
| 770 | * the Linux i82365 driver does not (and should not) handle CardBus. |
| 771 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 772 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | { |
| 774 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) |
| 775 | return; |
| 776 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
| 777 | } |
| 778 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 779 | DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | |
| 781 | /* |
| 782 | * Following the PCI ordering rules is optional on the AMD762. I'm not |
| 783 | * sure what the designers were smoking but let's not inhale... |
| 784 | * |
| 785 | * To be fair to AMD, it follows the spec by default, its BIOS people |
| 786 | * who turn it off! |
| 787 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 788 | static void quirk_amd_ordering(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | { |
| 790 | u32 pcic; |
| 791 | pci_read_config_dword(dev, 0x4C, &pcic); |
| 792 | if ((pcic&6)!=6) { |
| 793 | pcic |= 6; |
| 794 | printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); |
| 795 | pci_write_config_dword(dev, 0x4C, pcic); |
| 796 | pci_read_config_dword(dev, 0x84, &pcic); |
| 797 | pcic |= (1<<23); /* Required in this mode */ |
| 798 | pci_write_config_dword(dev, 0x84, pcic); |
| 799 | } |
| 800 | } |
| 801 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 802 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 803 | |
| 804 | /* |
| 805 | * DreamWorks provided workaround for Dunord I-3000 problem |
| 806 | * |
| 807 | * This card decodes and responds to addresses not apparently |
| 808 | * assigned to it. We force a larger allocation to ensure that |
| 809 | * nothing gets put too close to it. |
| 810 | */ |
| 811 | static void __devinit quirk_dunord ( struct pci_dev * dev ) |
| 812 | { |
| 813 | struct resource *r = &dev->resource [1]; |
| 814 | r->start = 0; |
| 815 | r->end = 0xffffff; |
| 816 | } |
| 817 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); |
| 818 | |
| 819 | /* |
| 820 | * i82380FB mobile docking controller: its PCI-to-PCI bridge |
| 821 | * is subtractive decoding (transparent), and does indicate this |
| 822 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 |
| 823 | * instead of 0x01. |
| 824 | */ |
| 825 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) |
| 826 | { |
| 827 | dev->transparent = 1; |
| 828 | } |
| 829 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); |
| 830 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); |
| 831 | |
| 832 | /* |
| 833 | * Common misconfiguration of the MediaGX/Geode PCI master that will |
| 834 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 |
| 835 | * datasheets found at http://www.national.com/ds/GX for info on what |
| 836 | * these bits do. <christer@weinigel.se> |
| 837 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 838 | static void quirk_mediagx_master(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | { |
| 840 | u8 reg; |
| 841 | pci_read_config_byte(dev, 0x41, ®); |
| 842 | if (reg & 2) { |
| 843 | reg &= ~2; |
| 844 | printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
| 845 | pci_write_config_byte(dev, 0x41, reg); |
| 846 | } |
| 847 | } |
| 848 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 849 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 850 | |
| 851 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | * Ensure C0 rev restreaming is off. This is normally done by |
| 853 | * the BIOS but in the odd case it is not the results are corruption |
| 854 | * hence the presence of a Linux check |
| 855 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 856 | static void quirk_disable_pxb(struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | { |
| 858 | u16 config; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 859 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 860 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | return; |
| 862 | pci_read_config_word(pdev, 0x40, &config); |
| 863 | if (config & (1<<6)) { |
| 864 | config &= ~(1<<6); |
| 865 | pci_write_config_word(pdev, 0x40, config); |
| 866 | printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); |
| 867 | } |
| 868 | } |
| 869 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 870 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 872 | |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 873 | static void __devinit quirk_sb600_sata(struct pci_dev *pdev) |
| 874 | { |
| 875 | /* set sb600 sata to ahci mode */ |
| 876 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { |
| 877 | u8 tmp; |
| 878 | |
| 879 | pci_read_config_byte(pdev, 0x40, &tmp); |
| 880 | pci_write_config_byte(pdev, 0x40, tmp|1); |
| 881 | pci_write_config_byte(pdev, 0x9, 1); |
| 882 | pci_write_config_byte(pdev, 0xa, 6); |
| 883 | pci_write_config_byte(pdev, 0x40, tmp); |
| 884 | |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 885 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 886 | } |
| 887 | } |
| 888 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata); |
Henry Su | 8237771 | 2007-05-10 22:48:50 -0700 | [diff] [blame] | 889 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata); |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 890 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | /* |
| 892 | * Serverworks CSB5 IDE does not fully support native mode |
| 893 | */ |
| 894 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) |
| 895 | { |
| 896 | u8 prog; |
| 897 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 898 | if (prog & 5) { |
| 899 | prog &= ~5; |
| 900 | pdev->class &= ~5; |
| 901 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 902 | /* PCI layer will sort out resources */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | } |
| 904 | } |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 905 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | |
| 907 | /* |
| 908 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same |
| 909 | */ |
| 910 | static void __init quirk_ide_samemode(struct pci_dev *pdev) |
| 911 | { |
| 912 | u8 prog; |
| 913 | |
| 914 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 915 | |
| 916 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { |
| 917 | printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); |
| 918 | prog &= ~5; |
| 919 | pdev->class &= ~5; |
| 920 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | } |
| 922 | } |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 923 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | |
| 925 | /* This was originally an Alpha specific thing, but it really fits here. |
| 926 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
| 927 | */ |
| 928 | static void __init quirk_eisa_bridge(struct pci_dev *dev) |
| 929 | { |
| 930 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; |
| 931 | } |
| 932 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); |
| 933 | |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 934 | |
| 935 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 936 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge |
| 937 | * is not activated. The myth is that Asus said that they do not want the |
| 938 | * users to be irritated by just another PCI Device in the Win98 device |
| 939 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
| 940 | * package 2.7.0 for details) |
| 941 | * |
| 942 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
| 943 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 944 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
| 945 | * is either the Host bridge (preferred) or on-board VGA controller. |
Jean Delvare | 9208ee8 | 2007-03-24 16:56:44 +0100 | [diff] [blame] | 946 | * |
| 947 | * Note that we used to unhide the SMBus that way on Toshiba laptops |
| 948 | * (Satellite A40 and Tecra M2) but then found that the thermal management |
| 949 | * was done by SMM code, which could cause unsynchronized concurrent |
| 950 | * accesses to the SMBus registers, with potentially bad effects. Thus you |
| 951 | * should be very careful when adding new entries: if SMM is accessing the |
| 952 | * Intel SMBus, this is a very good reason to leave it hidden. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | */ |
Vivek Goyal | 9d24a81 | 2007-01-11 01:52:44 +0100 | [diff] [blame] | 954 | static int asus_hides_smbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | |
| 956 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) |
| 957 | { |
| 958 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 959 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) |
| 960 | switch(dev->subsystem_device) { |
Jean Delvare | a00db37 | 2005-06-29 17:04:06 +0200 | [diff] [blame] | 961 | case 0x8025: /* P4B-LX */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | case 0x8070: /* P4B */ |
| 963 | case 0x8088: /* P4B533 */ |
| 964 | case 0x1626: /* L3C notebook */ |
| 965 | asus_hides_smbus = 1; |
| 966 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 967 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | switch(dev->subsystem_device) { |
| 969 | case 0x80b1: /* P4GE-V */ |
| 970 | case 0x80b2: /* P4PE */ |
| 971 | case 0x8093: /* P4B533-V */ |
| 972 | asus_hides_smbus = 1; |
| 973 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 974 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | switch(dev->subsystem_device) { |
| 976 | case 0x8030: /* P4T533 */ |
| 977 | asus_hides_smbus = 1; |
| 978 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 979 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | switch (dev->subsystem_device) { |
| 981 | case 0x8070: /* P4G8X Deluxe */ |
| 982 | asus_hides_smbus = 1; |
| 983 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 984 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 985 | switch (dev->subsystem_device) { |
| 986 | case 0x80c9: /* PU-DLS */ |
| 987 | asus_hides_smbus = 1; |
| 988 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 989 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 990 | switch (dev->subsystem_device) { |
| 991 | case 0x1751: /* M2N notebook */ |
| 992 | case 0x1821: /* M5N notebook */ |
| 993 | asus_hides_smbus = 1; |
| 994 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 995 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | switch (dev->subsystem_device) { |
| 997 | case 0x184b: /* W1N notebook */ |
| 998 | case 0x186a: /* M6Ne notebook */ |
| 999 | asus_hides_smbus = 1; |
| 1000 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1001 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
Jean Delvare | 2e45785 | 2007-01-05 09:17:56 +0100 | [diff] [blame] | 1002 | switch (dev->subsystem_device) { |
| 1003 | case 0x80f2: /* P4P800-X */ |
| 1004 | asus_hides_smbus = 1; |
| 1005 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1006 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1007 | switch (dev->subsystem_device) { |
| 1008 | case 0x1882: /* M6V notebook */ |
Jean Delvare | 2d1e1c7 | 2006-04-01 16:46:35 +0200 | [diff] [blame] | 1009 | case 0x1977: /* A6VA notebook */ |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1010 | asus_hides_smbus = 1; |
| 1011 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
| 1013 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1014 | switch(dev->subsystem_device) { |
| 1015 | case 0x088C: /* HP Compaq nc8000 */ |
| 1016 | case 0x0890: /* HP Compaq nc6000 */ |
| 1017 | asus_hides_smbus = 1; |
| 1018 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1019 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1020 | switch (dev->subsystem_device) { |
| 1021 | case 0x12bc: /* HP D330L */ |
Jean Delvare | e3b1bd5 | 2005-09-21 22:26:31 +0200 | [diff] [blame] | 1022 | case 0x12bd: /* HP D530 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1023 | asus_hides_smbus = 1; |
| 1024 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1025 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
tomek@koprowski.org | 3c0a654 | 2006-02-19 18:03:24 +0100 | [diff] [blame] | 1026 | switch (dev->subsystem_device) { |
| 1027 | case 0x099c: /* HP Compaq nx6110 */ |
| 1028 | asus_hides_smbus = 1; |
| 1029 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1030 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
| 1031 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1032 | switch(dev->subsystem_device) { |
| 1033 | case 0xC00C: /* Samsung P35 notebook */ |
| 1034 | asus_hides_smbus = 1; |
| 1035 | } |
Rumen Ivanov Zarev | c87f883 | 2005-09-06 13:39:32 -0700 | [diff] [blame] | 1036 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
| 1037 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1038 | switch(dev->subsystem_device) { |
| 1039 | case 0x0058: /* Compaq Evo N620c */ |
| 1040 | asus_hides_smbus = 1; |
| 1041 | } |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1042 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
| 1043 | switch(dev->subsystem_device) { |
| 1044 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ |
| 1045 | /* Motherboard doesn't have Host bridge |
| 1046 | * subvendor/subdevice IDs, therefore checking |
| 1047 | * its on-board VGA controller */ |
| 1048 | asus_hides_smbus = 1; |
| 1049 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1050 | } |
| 1051 | } |
| 1052 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); |
| 1053 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); |
| 1054 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); |
| 1055 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); |
| 1056 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 1057 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); |
| 1059 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1060 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1061 | |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1062 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge ); |
| 1063 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1064 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1065 | { |
| 1066 | u16 val; |
| 1067 | |
| 1068 | if (likely(!asus_hides_smbus)) |
| 1069 | return; |
| 1070 | |
| 1071 | pci_read_config_word(dev, 0xF2, &val); |
| 1072 | if (val & 0x8) { |
| 1073 | pci_write_config_word(dev, 0xF2, val & (~0x8)); |
| 1074 | pci_read_config_word(dev, 0xF2, &val); |
| 1075 | if (val & 0x8) |
| 1076 | printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
| 1077 | else |
| 1078 | printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); |
| 1079 | } |
| 1080 | } |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1081 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1082 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); |
| 1083 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 1084 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1085 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); |
| 1086 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); |
| 1087 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1088 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1089 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); |
| 1090 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); |
| 1091 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); |
| 1092 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); |
| 1093 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); |
| 1094 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1095 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1096 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1097 | { |
| 1098 | u32 val, rcba; |
| 1099 | void __iomem *base; |
| 1100 | |
| 1101 | if (likely(!asus_hides_smbus)) |
| 1102 | return; |
| 1103 | pci_read_config_dword(dev, 0xF0, &rcba); |
| 1104 | base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ |
| 1105 | if (base == NULL) return; |
| 1106 | val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ |
| 1107 | writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ |
| 1108 | iounmap(base); |
| 1109 | printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); |
| 1110 | } |
| 1111 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1112 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 1113 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1114 | /* |
| 1115 | * SiS 96x south bridge: BIOS typically hides SMBus device... |
| 1116 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1117 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | { |
| 1119 | u8 val = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1120 | pci_read_config_byte(dev, 0x77, &val); |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1121 | if (val & 0x10) { |
| 1122 | printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); |
| 1123 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
| 1124 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1125 | } |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 1126 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); |
| 1127 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); |
| 1128 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); |
| 1129 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); |
| 1130 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); |
| 1131 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); |
| 1132 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); |
| 1133 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1135 | /* |
| 1136 | * ... This is further complicated by the fact that some SiS96x south |
| 1137 | * bridges pretend to be 85C503/5513 instead. In that case see if we |
| 1138 | * spotted a compatible north bridge to make sure. |
| 1139 | * (pci_find_device doesn't work yet) |
| 1140 | * |
| 1141 | * We can also enable the sis96x bit in the discovery register.. |
| 1142 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | #define SIS_DETECT_REGISTER 0x40 |
| 1144 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1145 | static void quirk_sis_503(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | { |
| 1147 | u8 reg; |
| 1148 | u16 devid; |
| 1149 | |
| 1150 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); |
| 1151 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); |
| 1152 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); |
| 1153 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { |
| 1154 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); |
| 1155 | return; |
| 1156 | } |
| 1157 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1158 | /* |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1159 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
| 1160 | * hand in case it has already been processed. |
| 1161 | * (depends on link order, which is apparently not guaranteed) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | */ |
| 1163 | dev->device = devid; |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1164 | quirk_sis_96x_smbus(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1165 | } |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 1166 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); |
| 1167 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1170 | /* |
| 1171 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller |
| 1172 | * and MC97 modem controller are disabled when a second PCI soundcard is |
| 1173 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. |
| 1174 | * -- bjd |
| 1175 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1176 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1177 | { |
| 1178 | u8 val; |
| 1179 | int asus_hides_ac97 = 0; |
| 1180 | |
| 1181 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 1182 | if (dev->device == PCI_DEVICE_ID_VIA_8237) |
| 1183 | asus_hides_ac97 = 1; |
| 1184 | } |
| 1185 | |
| 1186 | if (!asus_hides_ac97) |
| 1187 | return; |
| 1188 | |
| 1189 | pci_read_config_byte(dev, 0x50, &val); |
| 1190 | if (val & 0xc0) { |
| 1191 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); |
| 1192 | pci_read_config_byte(dev, 0x50, &val); |
| 1193 | if (val & 0xc0) |
| 1194 | printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
| 1195 | else |
| 1196 | printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); |
| 1197 | } |
| 1198 | } |
| 1199 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1200 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); |
| 1201 | |
Tejun Heo | 7796705 | 2006-08-19 03:54:39 +0900 | [diff] [blame] | 1202 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1203 | |
| 1204 | /* |
| 1205 | * If we are using libata we can drive this chip properly but must |
| 1206 | * do this early on to make the additional device appear during |
| 1207 | * the PCI scanning. |
| 1208 | */ |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1209 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1210 | { |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 1211 | u32 conf1, conf5, class; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1212 | u8 hdr; |
| 1213 | |
| 1214 | /* Only poke fn 0 */ |
| 1215 | if (PCI_FUNC(pdev->devfn)) |
| 1216 | return; |
| 1217 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1218 | pci_read_config_dword(pdev, 0x40, &conf1); |
| 1219 | pci_read_config_dword(pdev, 0x80, &conf5); |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1220 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1221 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
| 1222 | conf5 &= ~(1 << 24); /* Clear bit 24 */ |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1223 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1224 | switch (pdev->device) { |
| 1225 | case PCI_DEVICE_ID_JMICRON_JMB360: |
| 1226 | /* The controller should be in single function ahci mode */ |
| 1227 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ |
| 1228 | break; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1229 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1230 | case PCI_DEVICE_ID_JMICRON_JMB365: |
| 1231 | case PCI_DEVICE_ID_JMICRON_JMB366: |
| 1232 | /* Redirect IDE second PATA port to the right spot */ |
| 1233 | conf5 |= (1 << 24); |
| 1234 | /* Fall through */ |
| 1235 | case PCI_DEVICE_ID_JMICRON_JMB361: |
| 1236 | case PCI_DEVICE_ID_JMICRON_JMB363: |
| 1237 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
| 1238 | /* Set the class codes correctly and then direct IDE 0 */ |
Tejun Heo | 3a9e3a5 | 2007-10-23 15:27:31 +0900 | [diff] [blame] | 1239 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1240 | break; |
| 1241 | |
| 1242 | case PCI_DEVICE_ID_JMICRON_JMB368: |
| 1243 | /* The controller should be in single function IDE mode */ |
| 1244 | conf1 |= 0x00C00000; /* Set 22, 23 */ |
| 1245 | break; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1246 | } |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1247 | |
| 1248 | pci_write_config_dword(pdev, 0x40, conf1); |
| 1249 | pci_write_config_dword(pdev, 0x80, conf5); |
| 1250 | |
| 1251 | /* Update pdev accordingly */ |
| 1252 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); |
| 1253 | pdev->hdr_type = hdr & 0x7f; |
| 1254 | pdev->multifunction = !!(hdr & 0x80); |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 1255 | |
| 1256 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); |
| 1257 | pdev->class = class >> 8; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1258 | } |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1259 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
| 1260 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
| 1261 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
| 1262 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
| 1263 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); |
| 1264 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
| 1265 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
| 1266 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
| 1267 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
| 1268 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
| 1269 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); |
| 1270 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1271 | |
| 1272 | #endif |
| 1273 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | #ifdef CONFIG_X86_IO_APIC |
| 1275 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) |
| 1276 | { |
| 1277 | int i; |
| 1278 | |
| 1279 | if ((pdev->class >> 8) != 0xff00) |
| 1280 | return; |
| 1281 | |
| 1282 | /* the first BAR is the location of the IO APIC...we must |
| 1283 | * not touch this (and it's already covered by the fixmap), so |
| 1284 | * forcibly insert it into the resource tree */ |
| 1285 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
| 1286 | insert_resource(&iomem_resource, &pdev->resource[0]); |
| 1287 | |
| 1288 | /* The next five BARs all seem to be rubbish, so just clean |
| 1289 | * them out */ |
| 1290 | for (i=1; i < 6; i++) { |
| 1291 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
| 1292 | } |
| 1293 | |
| 1294 | } |
| 1295 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); |
| 1296 | #endif |
| 1297 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | int pcie_mch_quirk; |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 1299 | EXPORT_SYMBOL(pcie_mch_quirk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1300 | |
| 1301 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) |
| 1302 | { |
| 1303 | pcie_mch_quirk = 1; |
| 1304 | } |
| 1305 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); |
| 1306 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); |
| 1307 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); |
| 1308 | |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1309 | |
| 1310 | /* |
| 1311 | * It's possible for the MSI to get corrupted if shpc and acpi |
| 1312 | * are used together on certain PXH-based systems. |
| 1313 | */ |
| 1314 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) |
| 1315 | { |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 1316 | pci_msi_off(dev); |
| 1317 | |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1318 | dev->no_msi = 1; |
| 1319 | |
| 1320 | printk(KERN_WARNING "PCI: PXH quirk detected, " |
| 1321 | "disabling MSI for SHPC device\n"); |
| 1322 | } |
| 1323 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); |
| 1324 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); |
| 1325 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); |
| 1326 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); |
| 1327 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); |
| 1328 | |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 1329 | /* |
| 1330 | * Some Intel PCI Express chipsets have trouble with downstream |
| 1331 | * device power management. |
| 1332 | */ |
| 1333 | static void quirk_intel_pcie_pm(struct pci_dev * dev) |
| 1334 | { |
| 1335 | pci_pm_d3_delay = 120; |
| 1336 | dev->no_d1d2 = 1; |
| 1337 | } |
| 1338 | |
| 1339 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
| 1340 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); |
| 1341 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); |
| 1342 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); |
| 1343 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); |
| 1344 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); |
| 1345 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); |
| 1346 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); |
| 1347 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); |
| 1348 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); |
| 1349 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); |
| 1350 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); |
| 1351 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); |
| 1352 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); |
| 1353 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); |
| 1354 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); |
| 1355 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); |
| 1356 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); |
| 1357 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); |
| 1358 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); |
| 1359 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1360 | |
Sergei Shtylyov | 33dced2 | 2007-02-07 18:18:45 +0100 | [diff] [blame] | 1361 | /* |
| 1362 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size |
| 1363 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. |
| 1364 | * Re-allocate the region if needed... |
| 1365 | */ |
| 1366 | static void __init quirk_tc86c001_ide(struct pci_dev *dev) |
| 1367 | { |
| 1368 | struct resource *r = &dev->resource[0]; |
| 1369 | |
| 1370 | if (r->start & 0x8) { |
| 1371 | r->start = 0; |
| 1372 | r->end = 0xf; |
| 1373 | } |
| 1374 | } |
| 1375 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, |
| 1376 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, |
| 1377 | quirk_tc86c001_ide); |
| 1378 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1379 | static void __devinit quirk_netmos(struct pci_dev *dev) |
| 1380 | { |
| 1381 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; |
| 1382 | unsigned int num_serial = dev->subsystem_device & 0xf; |
| 1383 | |
| 1384 | /* |
| 1385 | * These Netmos parts are multiport serial devices with optional |
| 1386 | * parallel ports. Even when parallel ports are present, they |
| 1387 | * are identified as class SERIAL, which means the serial driver |
| 1388 | * will claim them. To prevent this, mark them as class OTHER. |
| 1389 | * These combo devices should be claimed by parport_serial. |
| 1390 | * |
| 1391 | * The subdevice ID is of the form 0x00PS, where <P> is the number |
| 1392 | * of parallel ports and <S> is the number of serial ports. |
| 1393 | */ |
| 1394 | switch (dev->device) { |
| 1395 | case PCI_DEVICE_ID_NETMOS_9735: |
| 1396 | case PCI_DEVICE_ID_NETMOS_9745: |
| 1397 | case PCI_DEVICE_ID_NETMOS_9835: |
| 1398 | case PCI_DEVICE_ID_NETMOS_9845: |
| 1399 | case PCI_DEVICE_ID_NETMOS_9855: |
| 1400 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && |
| 1401 | num_parallel) { |
| 1402 | printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " |
| 1403 | "%u serial); changing class SERIAL to OTHER " |
| 1404 | "(use parport_serial)\n", |
| 1405 | dev->device, num_parallel, num_serial); |
| 1406 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | |
| 1407 | (dev->class & 0xff); |
| 1408 | } |
| 1409 | } |
| 1410 | } |
| 1411 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); |
| 1412 | |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1413 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
| 1414 | { |
| 1415 | u16 command; |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1416 | u8 __iomem *csr; |
| 1417 | u8 cmd_hi; |
| 1418 | |
| 1419 | switch (dev->device) { |
| 1420 | /* PCI IDs taken from drivers/net/e100.c */ |
| 1421 | case 0x1029: |
| 1422 | case 0x1030 ... 0x1034: |
| 1423 | case 0x1038 ... 0x103E: |
| 1424 | case 0x1050 ... 0x1057: |
| 1425 | case 0x1059: |
| 1426 | case 0x1064 ... 0x106B: |
| 1427 | case 0x1091 ... 0x1095: |
| 1428 | case 0x1209: |
| 1429 | case 0x1229: |
| 1430 | case 0x2449: |
| 1431 | case 0x2459: |
| 1432 | case 0x245D: |
| 1433 | case 0x27DC: |
| 1434 | break; |
| 1435 | default: |
| 1436 | return; |
| 1437 | } |
| 1438 | |
| 1439 | /* |
| 1440 | * Some firmware hands off the e100 with interrupts enabled, |
| 1441 | * which can cause a flood of interrupts if packets are |
| 1442 | * received before the driver attaches to the device. So |
| 1443 | * disable all e100 interrupts here. The driver will |
| 1444 | * re-enable them when it's ready. |
| 1445 | */ |
| 1446 | pci_read_config_word(dev, PCI_COMMAND, &command); |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1447 | |
Benjamin Herrenschmidt | 1bef7dc | 2007-09-29 09:06:21 +1000 | [diff] [blame] | 1448 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1449 | return; |
| 1450 | |
Benjamin Herrenschmidt | 1bef7dc | 2007-09-29 09:06:21 +1000 | [diff] [blame] | 1451 | /* Convert from PCI bus to resource space. */ |
| 1452 | csr = ioremap(pci_resource_start(dev, 0), 8); |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1453 | if (!csr) { |
| 1454 | printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", |
| 1455 | pci_name(dev)); |
| 1456 | return; |
| 1457 | } |
| 1458 | |
| 1459 | cmd_hi = readb(csr + 3); |
| 1460 | if (cmd_hi == 0) { |
| 1461 | printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " |
| 1462 | "enabled, disabling\n", pci_name(dev)); |
| 1463 | writeb(1, csr + 3); |
| 1464 | } |
| 1465 | |
| 1466 | iounmap(csr); |
| 1467 | } |
Marian Balakowicz | 4e68fc9 | 2007-07-03 11:03:18 +0200 | [diff] [blame] | 1468 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
Ivan Kokshaysky | a5312e2 | 2005-11-01 01:43:56 +0300 | [diff] [blame] | 1469 | |
| 1470 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
| 1471 | { |
| 1472 | /* rev 1 ncr53c810 chips don't set the class at all which means |
| 1473 | * they don't get their resources remapped. Fix that here. |
| 1474 | */ |
| 1475 | |
| 1476 | if (dev->class == PCI_CLASS_NOT_DEFINED) { |
| 1477 | printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); |
| 1478 | dev->class = PCI_CLASS_STORAGE_SCSI; |
| 1479 | } |
| 1480 | } |
| 1481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); |
| 1482 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) |
| 1484 | { |
| 1485 | while (f < end) { |
| 1486 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && |
| 1487 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
| 1488 | pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); |
| 1489 | f->hook(dev); |
| 1490 | } |
| 1491 | f++; |
| 1492 | } |
| 1493 | } |
| 1494 | |
| 1495 | extern struct pci_fixup __start_pci_fixups_early[]; |
| 1496 | extern struct pci_fixup __end_pci_fixups_early[]; |
| 1497 | extern struct pci_fixup __start_pci_fixups_header[]; |
| 1498 | extern struct pci_fixup __end_pci_fixups_header[]; |
| 1499 | extern struct pci_fixup __start_pci_fixups_final[]; |
| 1500 | extern struct pci_fixup __end_pci_fixups_final[]; |
| 1501 | extern struct pci_fixup __start_pci_fixups_enable[]; |
| 1502 | extern struct pci_fixup __end_pci_fixups_enable[]; |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1503 | extern struct pci_fixup __start_pci_fixups_resume[]; |
| 1504 | extern struct pci_fixup __end_pci_fixups_resume[]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1505 | |
| 1506 | |
| 1507 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) |
| 1508 | { |
| 1509 | struct pci_fixup *start, *end; |
| 1510 | |
| 1511 | switch(pass) { |
| 1512 | case pci_fixup_early: |
| 1513 | start = __start_pci_fixups_early; |
| 1514 | end = __end_pci_fixups_early; |
| 1515 | break; |
| 1516 | |
| 1517 | case pci_fixup_header: |
| 1518 | start = __start_pci_fixups_header; |
| 1519 | end = __end_pci_fixups_header; |
| 1520 | break; |
| 1521 | |
| 1522 | case pci_fixup_final: |
| 1523 | start = __start_pci_fixups_final; |
| 1524 | end = __end_pci_fixups_final; |
| 1525 | break; |
| 1526 | |
| 1527 | case pci_fixup_enable: |
| 1528 | start = __start_pci_fixups_enable; |
| 1529 | end = __end_pci_fixups_enable; |
| 1530 | break; |
| 1531 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1532 | case pci_fixup_resume: |
| 1533 | start = __start_pci_fixups_resume; |
| 1534 | end = __end_pci_fixups_resume; |
| 1535 | break; |
| 1536 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1537 | default: |
| 1538 | /* stupid compiler warning, you would think with an enum... */ |
| 1539 | return; |
| 1540 | } |
| 1541 | pci_do_fixups(dev, start, end); |
| 1542 | } |
Adrian Bunk | c30ca1d | 2006-12-19 05:13:15 +0100 | [diff] [blame] | 1543 | EXPORT_SYMBOL(pci_fixup_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1544 | |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1545 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
| 1546 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) |
| 1547 | { |
| 1548 | u16 en1k; |
| 1549 | u8 io_base_lo, io_limit_lo; |
| 1550 | unsigned long base, limit; |
| 1551 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; |
| 1552 | |
| 1553 | pci_read_config_word(dev, 0x40, &en1k); |
| 1554 | |
| 1555 | if (en1k & 0x200) { |
| 1556 | printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); |
| 1557 | |
| 1558 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
| 1559 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
| 1560 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; |
| 1561 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; |
| 1562 | |
| 1563 | if (base <= limit) { |
| 1564 | res->start = base; |
| 1565 | res->end = limit + 0x3ff; |
| 1566 | } |
| 1567 | } |
| 1568 | } |
| 1569 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
| 1570 | |
Daniel Yeisley | 15a260d | 2006-12-21 14:34:57 -0500 | [diff] [blame] | 1571 | /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 |
| 1572 | * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() |
| 1573 | * in drivers/pci/setup-bus.c |
| 1574 | */ |
| 1575 | static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) |
| 1576 | { |
| 1577 | u16 en1k, iobl_adr, iobl_adr_1k; |
| 1578 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; |
| 1579 | |
| 1580 | pci_read_config_word(dev, 0x40, &en1k); |
| 1581 | |
| 1582 | if (en1k & 0x200) { |
| 1583 | pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); |
| 1584 | |
| 1585 | iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); |
| 1586 | |
| 1587 | if (iobl_adr != iobl_adr_1k) { |
| 1588 | printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n", |
| 1589 | iobl_adr,iobl_adr_1k); |
| 1590 | pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); |
| 1591 | } |
| 1592 | } |
| 1593 | } |
| 1594 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); |
| 1595 | |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1596 | /* Under some circumstances, AER is not linked with extended capabilities. |
| 1597 | * Force it to be linked by setting the corresponding control bit in the |
| 1598 | * config space. |
| 1599 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1600 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1601 | { |
| 1602 | uint8_t b; |
| 1603 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { |
| 1604 | if (!(b & 0x20)) { |
| 1605 | pci_write_config_byte(dev, 0xf41, b | 0x20); |
| 1606 | printk(KERN_INFO |
| 1607 | "PCI: Linking AER extended capability on %s\n", |
| 1608 | pci_name(dev)); |
| 1609 | } |
| 1610 | } |
| 1611 | } |
| 1612 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1613 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1614 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1615 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1616 | |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1617 | #ifdef CONFIG_PCI_MSI |
Tejun Heo | ebdf7d3 | 2007-05-31 00:40:48 -0700 | [diff] [blame] | 1618 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
| 1619 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually |
| 1620 | * some other busses controlled by the chipset even if Linux is not |
| 1621 | * aware of it. Instead of setting the flag on all busses in the |
| 1622 | * machine, simply disable MSI globally. |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1623 | */ |
Tejun Heo | ebdf7d3 | 2007-05-31 00:40:48 -0700 | [diff] [blame] | 1624 | static void __init quirk_disable_all_msi(struct pci_dev *dev) |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1625 | { |
Michael Ellerman | 88187df | 2007-01-25 19:34:07 +1100 | [diff] [blame] | 1626 | pci_no_msi(); |
| 1627 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n"); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1628 | } |
Tejun Heo | ebdf7d3 | 2007-05-31 00:40:48 -0700 | [diff] [blame] | 1629 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
| 1630 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); |
| 1631 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); |
Jay Cliburn | 184b812 | 2007-05-26 17:01:04 -0500 | [diff] [blame] | 1632 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1633 | |
| 1634 | /* Disable MSI on chipsets that are known to not support it */ |
| 1635 | static void __devinit quirk_disable_msi(struct pci_dev *dev) |
| 1636 | { |
| 1637 | if (dev->subordinate) { |
| 1638 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 1639 | "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", |
| 1640 | pci_name(dev)); |
| 1641 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 1642 | } |
| 1643 | } |
| 1644 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1645 | |
| 1646 | /* Go through the list of Hypertransport capabilities and |
| 1647 | * return 1 if a HT MSI capability is found and enabled */ |
| 1648 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) |
| 1649 | { |
Michael Ellerman | 7a38050 | 2006-11-22 18:26:21 +1100 | [diff] [blame] | 1650 | int pos, ttl = 48; |
| 1651 | |
| 1652 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
| 1653 | while (pos && ttl--) { |
| 1654 | u8 flags; |
| 1655 | |
| 1656 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, |
| 1657 | &flags) == 0) |
| 1658 | { |
| 1659 | printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n", |
| 1660 | flags & HT_MSI_FLAGS_ENABLE ? |
| 1661 | "enabled" : "disabled", pci_name(dev)); |
| 1662 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1663 | } |
Michael Ellerman | 7a38050 | 2006-11-22 18:26:21 +1100 | [diff] [blame] | 1664 | |
| 1665 | pos = pci_find_next_ht_capability(dev, pos, |
| 1666 | HT_CAPTYPE_MSI_MAPPING); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1667 | } |
| 1668 | return 0; |
| 1669 | } |
| 1670 | |
| 1671 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ |
| 1672 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) |
| 1673 | { |
| 1674 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { |
| 1675 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 1676 | "MSI disabled on chipset %s.\n", |
| 1677 | pci_name(dev)); |
| 1678 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 1679 | } |
| 1680 | } |
| 1681 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, |
| 1682 | quirk_msi_ht_cap); |
David Miller | 1d84b54 | 2007-10-25 01:15:53 -0700 | [diff] [blame] | 1683 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, |
| 1684 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, |
| 1685 | quirk_msi_ht_cap); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1686 | |
| 1687 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
| 1688 | * MSI are supported if the MSI capability set in any of these mappings. |
| 1689 | */ |
| 1690 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
| 1691 | { |
| 1692 | struct pci_dev *pdev; |
| 1693 | |
| 1694 | if (!dev->subordinate) |
| 1695 | return; |
| 1696 | |
| 1697 | /* check HT MSI cap on this chipset and the root one. |
| 1698 | * a single one having MSI is enough to be sure that MSI are supported. |
| 1699 | */ |
Alan Cox | 11f242f | 2006-10-10 14:39:00 -0700 | [diff] [blame] | 1700 | pdev = pci_get_slot(dev->bus, 0); |
Jesper Juhl | 9ac0ce8 | 2006-12-04 15:14:48 -0800 | [diff] [blame] | 1701 | if (!pdev) |
| 1702 | return; |
David Rientjes | 0c875c2 | 2006-12-03 11:55:34 -0800 | [diff] [blame] | 1703 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1704 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 1705 | "MSI disabled on chipset %s.\n", |
| 1706 | pci_name(dev)); |
| 1707 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 1708 | } |
Alan Cox | 11f242f | 2006-10-10 14:39:00 -0700 | [diff] [blame] | 1709 | pci_dev_put(pdev); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 1710 | } |
| 1711 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1712 | quirk_nvidia_ck804_msi_ht_cap); |
David Miller | ba698ad | 2007-10-25 01:16:30 -0700 | [diff] [blame] | 1713 | |
| 1714 | static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) |
| 1715 | { |
| 1716 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
| 1717 | } |
| 1718 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 1719 | PCI_DEVICE_ID_TIGON3_5780, |
| 1720 | quirk_msi_intx_disable_bug); |
| 1721 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 1722 | PCI_DEVICE_ID_TIGON3_5780S, |
| 1723 | quirk_msi_intx_disable_bug); |
| 1724 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 1725 | PCI_DEVICE_ID_TIGON3_5714, |
| 1726 | quirk_msi_intx_disable_bug); |
| 1727 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 1728 | PCI_DEVICE_ID_TIGON3_5714S, |
| 1729 | quirk_msi_intx_disable_bug); |
| 1730 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 1731 | PCI_DEVICE_ID_TIGON3_5715, |
| 1732 | quirk_msi_intx_disable_bug); |
| 1733 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 1734 | PCI_DEVICE_ID_TIGON3_5715S, |
| 1735 | quirk_msi_intx_disable_bug); |
| 1736 | |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 1737 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
| 1738 | quirk_msi_intx_disable_bug); |
| 1739 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
| 1740 | quirk_msi_intx_disable_bug); |
| 1741 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
| 1742 | quirk_msi_intx_disable_bug); |
| 1743 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
| 1744 | quirk_msi_intx_disable_bug); |
| 1745 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
| 1746 | quirk_msi_intx_disable_bug); |
| 1747 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4395, |
| 1748 | quirk_msi_intx_disable_bug); |
| 1749 | |
| 1750 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, |
| 1751 | quirk_msi_intx_disable_bug); |
| 1752 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, |
| 1753 | quirk_msi_intx_disable_bug); |
| 1754 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, |
| 1755 | quirk_msi_intx_disable_bug); |
| 1756 | |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 1757 | #endif /* CONFIG_PCI_MSI */ |