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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparde294aedc2010-02-19 13:54:58 +00002 * Copyright (C) 2005 - 2010 ServerEngines
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/version.h>
24#include <linux/delay.h>
25#include <net/tcp.h>
26#include <net/ip.h>
27#include <net/ipv6.h>
28#include <linux/if_vlan.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h>
Ajit Khaparde84517482009-09-04 03:12:16 +000031#include <linux/firmware.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Sathya Perla6b7c5b92009-03-11 23:32:03 -070033
34#include "be_hw.h"
35
Ajit Khapardee2619842010-07-23 02:05:36 +000036#define DRV_VER "2.103.175u"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070037#define DRV_NAME "be2net"
38#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070039#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
Ajit Khapardec4ca2372009-05-18 15:38:55 -070040#define OC_NAME "Emulex OneConnect 10Gbps NIC"
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070041#define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
Ajit Khaparde35ecf032010-02-09 01:38:06 +000042#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070043
Ajit Khapardec4ca2372009-05-18 15:38:55 -070044#define BE_VENDOR_ID 0x19a2
45#define BE_DEVICE_ID1 0x211
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070046#define BE_DEVICE_ID2 0x221
Ajit Khapardec4ca2372009-05-18 15:38:55 -070047#define OC_DEVICE_ID1 0x700
Ajit Khapardee254f6e2010-02-09 01:28:35 +000048#define OC_DEVICE_ID2 0x710
Ajit Khapardec4ca2372009-05-18 15:38:55 -070049
50static inline char *nic_name(struct pci_dev *pdev)
51{
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070052 switch (pdev->device) {
53 case OC_DEVICE_ID1:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070054 return OC_NAME;
Ajit Khapardee254f6e2010-02-09 01:28:35 +000055 case OC_DEVICE_ID2:
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070056 return OC_NAME1;
57 case BE_DEVICE_ID2:
58 return BE3_NAME;
59 default:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070060 return BE_NAME;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070061 }
Ajit Khapardec4ca2372009-05-18 15:38:55 -070062}
63
Sathya Perla6b7c5b92009-03-11 23:32:03 -070064/* Number of bytes of an RX frame that are copied to skb->data */
65#define BE_HDR_LEN 64
66#define BE_MAX_JUMBO_FRAME_SIZE 9018
67#define BE_MIN_MTU 256
68
69#define BE_NUM_VLANS_SUPPORTED 64
70#define BE_MAX_EQD 96
71#define BE_MAX_TX_FRAG_COUNT 30
72
73#define EVNT_Q_LEN 1024
74#define TX_Q_LEN 2048
75#define TX_CQ_LEN 1024
76#define RX_Q_LEN 1024 /* Does not support any other value */
77#define RX_CQ_LEN 1024
Sathya Perla5fb379e2009-06-18 00:02:59 +000078#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070079#define MCC_CQ_LEN 256
80
81#define BE_NAPI_WEIGHT 64
82#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
83#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
84
Sathya Perla8788fdc2009-07-27 22:52:03 +000085#define FW_VER_LEN 32
86
Sarveshwar Bandiba343c72010-03-31 02:56:12 +000087#define BE_MAX_VF 32
88
Sathya Perla6b7c5b92009-03-11 23:32:03 -070089struct be_dma_mem {
90 void *va;
91 dma_addr_t dma;
92 u32 size;
93};
94
95struct be_queue_info {
96 struct be_dma_mem dma_mem;
97 u16 len;
98 u16 entry_size; /* Size of an element in the queue */
99 u16 id;
100 u16 tail, head;
101 bool created;
102 atomic_t used; /* Number of valid elements in the queue */
103};
104
Sathya Perla5fb379e2009-06-18 00:02:59 +0000105static inline u32 MODULO(u16 val, u16 limit)
106{
107 BUG_ON(limit & (limit - 1));
108 return val & (limit - 1);
109}
110
111static inline void index_adv(u16 *index, u16 val, u16 limit)
112{
113 *index = MODULO((*index + val), limit);
114}
115
116static inline void index_inc(u16 *index, u16 limit)
117{
118 *index = MODULO((*index + 1), limit);
119}
120
121static inline void *queue_head_node(struct be_queue_info *q)
122{
123 return q->dma_mem.va + q->head * q->entry_size;
124}
125
126static inline void *queue_tail_node(struct be_queue_info *q)
127{
128 return q->dma_mem.va + q->tail * q->entry_size;
129}
130
131static inline void queue_head_inc(struct be_queue_info *q)
132{
133 index_inc(&q->head, q->len);
134}
135
136static inline void queue_tail_inc(struct be_queue_info *q)
137{
138 index_inc(&q->tail, q->len);
139}
140
Sathya Perla5fb379e2009-06-18 00:02:59 +0000141struct be_eq_obj {
142 struct be_queue_info q;
143 char desc[32];
144
145 /* Adaptive interrupt coalescing (AIC) info */
146 bool enable_aic;
147 u16 min_eqd; /* in usecs */
148 u16 max_eqd; /* in usecs */
149 u16 cur_eqd; /* in usecs */
150
151 struct napi_struct napi;
152};
153
154struct be_mcc_obj {
155 struct be_queue_info q;
156 struct be_queue_info cq;
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000157 bool rearm_cq;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000158};
159
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700160struct be_drvr_stats {
161 u32 be_tx_reqs; /* number of TX requests initiated */
162 u32 be_tx_stops; /* number of times TX Q was stopped */
163 u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
164 u32 be_tx_wrbs; /* number of tx WRBs used */
165 u32 be_tx_events; /* number of tx completion events */
166 u32 be_tx_compl; /* number of tx completion entries processed */
Sathya Perla4097f662009-03-24 16:40:13 -0700167 ulong be_tx_jiffies;
168 u64 be_tx_bytes;
169 u64 be_tx_bytes_prev;
Ajit Khaparde91992e42010-02-19 13:57:12 +0000170 u64 be_tx_pkts;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700171 u32 be_tx_rate;
172
173 u32 cache_barrier[16];
174
175 u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
Ajit Khapardeb7b83ac2009-11-29 17:57:22 +0000176 u32 be_rx_polls; /* number of times NAPI called poll function */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700177 u32 be_rx_events; /* number of ucast rx completion events */
178 u32 be_rx_compl; /* number of rx completion entries processed */
Sathya Perla4097f662009-03-24 16:40:13 -0700179 ulong be_rx_jiffies;
180 u64 be_rx_bytes;
181 u64 be_rx_bytes_prev;
Ajit Khaparde91992e42010-02-19 13:57:12 +0000182 u64 be_rx_pkts;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700183 u32 be_rx_rate;
Ajit Khaparde1ef78ab2010-09-03 06:17:10 +0000184 u32 be_rx_mcast_pkt;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700185 /* number of non ether type II frames dropped where
186 * frame len > length field of Mac Hdr */
187 u32 be_802_3_dropped_frames;
188 /* number of non ether type II frames malformed where
189 * in frame len < length field of Mac Hdr */
190 u32 be_802_3_malformed_frames;
191 u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
192 ulong rx_fps_jiffies; /* jiffies at last FPS calc */
193 u32 be_rx_frags;
194 u32 be_prev_rx_frags;
195 u32 be_rx_fps; /* Rx frags per second */
196};
197
198struct be_stats_obj {
199 struct be_drvr_stats drvr_stats;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700200 struct be_dma_mem cmd;
201};
202
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700203struct be_tx_obj {
204 struct be_queue_info q;
205 struct be_queue_info cq;
206 /* Remember the skbs that were transmitted */
207 struct sk_buff *sent_skb_list[TX_Q_LEN];
208};
209
210/* Struct to remember the pages posted for rx frags */
211struct be_rx_page_info {
212 struct page *page;
FUJITA Tomonorifac6da52010-04-01 16:53:22 +0000213 DEFINE_DMA_UNMAP_ADDR(bus);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700214 u16 page_offset;
215 bool last_page_user;
216};
217
218struct be_rx_obj {
219 struct be_queue_info q;
220 struct be_queue_info cq;
221 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700222};
223
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000224struct be_vf_cfg {
225 unsigned char vf_mac_addr[ETH_ALEN];
226 u32 vf_if_handle;
227 u32 vf_pmac_id;
Ajit Khaparde1da87b72010-07-23 01:51:22 +0000228 u16 vf_vlan_tag;
Ajit Khapardee1d18732010-07-23 01:52:13 +0000229 u32 vf_tx_rate;
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000230};
231
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700232#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
Ajit Khaparde9cd90002010-07-23 01:49:04 +0000233#define BE_INVALID_PMAC_ID 0xffffffff
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700234struct be_adapter {
235 struct pci_dev *pdev;
236 struct net_device *netdev;
237
Sathya Perla8788fdc2009-07-27 22:52:03 +0000238 u8 __iomem *csr;
239 u8 __iomem *db; /* Door Bell */
240 u8 __iomem *pcicfg; /* PCI config space */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000241
242 spinlock_t mbox_lock; /* For serializing mbox cmds to BE card */
243 struct be_dma_mem mbox_mem;
244 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
245 * is stored for freeing purpose */
246 struct be_dma_mem mbox_mem_alloced;
247
248 struct be_mcc_obj mcc_obj;
249 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
250 spinlock_t mcc_cq_lock;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700251
252 struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
253 bool msix_enabled;
254 bool isr_registered;
255
256 /* TX Rings */
257 struct be_eq_obj tx_eq;
258 struct be_tx_obj tx_obj;
259
260 u32 cache_line_break[8];
261
262 /* Rx rings */
263 struct be_eq_obj rx_eq;
264 struct be_rx_obj rx_obj;
265 u32 big_page_size; /* Compounded page size shared by rx wrbs */
Sathya Perlaea1dae12009-03-19 23:56:20 -0700266 bool rx_post_starved; /* Zero rx frags have been posted to BE */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700267
268 struct vlan_group *vlan_grp;
Ajit Khaparde82903e42010-02-09 01:34:57 +0000269 u16 vlans_added;
270 u16 max_vlans; /* Number of vlans supported */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700271 u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
Sathya Perlae7b909a2009-11-22 22:01:10 +0000272 struct be_dma_mem mc_cmd_mem;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700273
274 struct be_stats_obj stats;
275 /* Work queue used to perform periodic tasks like getting statistics */
276 struct delayed_work work;
277
278 /* Ethtool knobs and info */
279 bool rx_csum; /* BE card must perform rx-checksumming */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700280 char fw_ver[FW_VER_LEN];
281 u32 if_handle; /* Used to configure filtering */
282 u32 pmac_id; /* MAC addr handle used by BE card */
283
Sathya Perlacf588472010-02-14 21:22:01 +0000284 bool eeh_err;
Sathya Perlaa8f447bd2009-06-18 00:10:27 +0000285 bool link_up;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700286 u32 port_num;
Sathya Perla24307ee2009-06-18 00:09:25 +0000287 bool promiscuous;
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000288 bool wol;
Ajit Khaparde3486be22010-07-23 02:04:54 +0000289 u32 function_mode;
Ajit Khaparde9e90c962009-11-06 02:06:59 +0000290 u32 rx_fc; /* Rx flow control */
291 u32 tx_fc; /* Tx flow control */
Ajit Khaparde7c185272010-07-29 06:16:33 +0000292 bool ue_detected;
Ajit Khaparde0fc48c32010-07-29 06:18:58 +0000293 bool stats_ioctl_sent;
Ajit Khaparde0dffc832009-11-29 17:57:46 +0000294 int link_speed;
295 u8 port_type;
Sarveshwar Bandi16c02142009-12-23 04:42:51 +0000296 u8 transceiver;
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000297 u8 autoneg;
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000298 u8 generation; /* BladeEngine ASIC generation */
Sarveshwar Bandidd131e72010-05-25 16:16:32 -0700299 u32 flash_status;
300 struct completion flash_compl;
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000301
302 bool sriov_enabled;
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000303 struct be_vf_cfg vf_cfg[BE_MAX_VF];
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000304 u8 base_eq_id;
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000305 u8 is_virtfn;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700306};
307
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000308#define be_physfn(adapter) (!adapter->is_virtfn)
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000309
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000310/* BladeEngine Generation numbers */
311#define BE_GEN2 2
312#define BE_GEN3 3
313
Stephen Hemminger0fc0b732009-09-02 01:03:33 -0700314extern const struct ethtool_ops be_ethtool_ops;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700315
316#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
317
318#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
319
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700320#define PAGE_SHIFT_4K 12
321#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
322
323/* Returns number of pages spanned by the data starting at the given addr */
324#define PAGES_4K_SPANNED(_address, size) \
325 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
326 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
327
328/* Byte offset into the page corresponding to given address */
329#define OFFSET_IN_PAGE(addr) \
330 ((size_t)(addr) & (PAGE_SIZE_4K-1))
331
332/* Returns bit offset within a DWORD of a bitfield */
333#define AMAP_BIT_OFFSET(_struct, field) \
334 (((size_t)&(((_struct *)0)->field))%32)
335
336/* Returns the bit mask of the field that is NOT shifted into location. */
337static inline u32 amap_mask(u32 bitsize)
338{
339 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
340}
341
342static inline void
343amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
344{
345 u32 *dw = (u32 *) ptr + dw_offset;
346 *dw &= ~(mask << offset);
347 *dw |= (mask & value) << offset;
348}
349
350#define AMAP_SET_BITS(_struct, field, ptr, val) \
351 amap_set(ptr, \
352 offsetof(_struct, field)/32, \
353 amap_mask(sizeof(((_struct *)0)->field)), \
354 AMAP_BIT_OFFSET(_struct, field), \
355 val)
356
357static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
358{
359 u32 *dw = (u32 *) ptr;
360 return mask & (*(dw + dw_offset) >> offset);
361}
362
363#define AMAP_GET_BITS(_struct, field, ptr) \
364 amap_get(ptr, \
365 offsetof(_struct, field)/32, \
366 amap_mask(sizeof(((_struct *)0)->field)), \
367 AMAP_BIT_OFFSET(_struct, field))
368
369#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
370#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
371static inline void swap_dws(void *wrb, int len)
372{
373#ifdef __BIG_ENDIAN
374 u32 *dw = wrb;
375 BUG_ON(len % 4);
376 do {
377 *dw = cpu_to_le32(*dw);
378 dw++;
379 len -= 4;
380 } while (len);
381#endif /* __BIG_ENDIAN */
382}
383
384static inline u8 is_tcp_pkt(struct sk_buff *skb)
385{
386 u8 val = 0;
387
388 if (ip_hdr(skb)->version == 4)
389 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
390 else if (ip_hdr(skb)->version == 6)
391 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
392
393 return val;
394}
395
396static inline u8 is_udp_pkt(struct sk_buff *skb)
397{
398 u8 val = 0;
399
400 if (ip_hdr(skb)->version == 4)
401 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
402 else if (ip_hdr(skb)->version == 6)
403 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
404
405 return val;
406}
407
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000408static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
409{
410 u8 data;
411
412 pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
413 pci_read_config_byte(adapter->pdev, 0xFE, &data);
414 adapter->is_virtfn = (data != 0xAA);
415}
416
Sathya Perla8788fdc2009-07-27 22:52:03 +0000417extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000418 u16 num_popped);
Sathya Perla8788fdc2009-07-27 22:52:03 +0000419extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700420extern void netdev_stats_update(struct be_adapter *adapter);
Ajit Khaparde84517482009-09-04 03:12:16 +0000421extern int be_load_fw(struct be_adapter *adapter, u8 *func);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700422#endif /* BE_H */