Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
Ralf Baechle | 36ccf1c | 2006-02-14 21:04:54 +0000 | [diff] [blame] | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
| 8 | * Copyright (C) 1998 Ulf Carlsson |
| 9 | * Copyright (C) 1999 Silicon Graphics, Inc. |
| 10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
| 11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | */ |
Ralf Baechle | 8e8a52e | 2007-05-31 14:00:19 +0100 | [diff] [blame] | 14 | #include <linux/bug.h> |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 15 | #include <linux/compiler.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <linux/init.h> |
| 17 | #include <linux/mm.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/spinlock.h> |
| 22 | #include <linux/kallsyms.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 23 | #include <linux/bootmem.h> |
Maxime Bizon | d4fd198 | 2006-07-20 18:52:02 +0200 | [diff] [blame] | 24 | #include <linux/interrupt.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 25 | #include <linux/ptrace.h> |
Jason Wessel | 8854700 | 2008-07-29 15:58:53 -0500 | [diff] [blame] | 26 | #include <linux/kgdb.h> |
| 27 | #include <linux/kdebug.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
| 29 | #include <asm/bootinfo.h> |
| 30 | #include <asm/branch.h> |
| 31 | #include <asm/break.h> |
| 32 | #include <asm/cpu.h> |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 33 | #include <asm/dsp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <asm/fpu.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 35 | #include <asm/mipsregs.h> |
| 36 | #include <asm/mipsmtregs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #include <asm/module.h> |
| 38 | #include <asm/pgtable.h> |
| 39 | #include <asm/ptrace.h> |
| 40 | #include <asm/sections.h> |
| 41 | #include <asm/system.h> |
| 42 | #include <asm/tlbdebug.h> |
| 43 | #include <asm/traps.h> |
| 44 | #include <asm/uaccess.h> |
| 45 | #include <asm/mmu_context.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #include <asm/types.h> |
Atsushi Nemoto | 1df0f0f | 2006-09-26 23:44:01 +0900 | [diff] [blame] | 47 | #include <asm/stacktrace.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 49 | extern asmlinkage void handle_int(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | extern asmlinkage void handle_tlbm(void); |
| 51 | extern asmlinkage void handle_tlbl(void); |
| 52 | extern asmlinkage void handle_tlbs(void); |
| 53 | extern asmlinkage void handle_adel(void); |
| 54 | extern asmlinkage void handle_ades(void); |
| 55 | extern asmlinkage void handle_ibe(void); |
| 56 | extern asmlinkage void handle_dbe(void); |
| 57 | extern asmlinkage void handle_sys(void); |
| 58 | extern asmlinkage void handle_bp(void); |
| 59 | extern asmlinkage void handle_ri(void); |
Atsushi Nemoto | 5b10496 | 2006-09-11 17:50:29 +0900 | [diff] [blame] | 60 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
| 61 | extern asmlinkage void handle_ri_rdhwr(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | extern asmlinkage void handle_cpu(void); |
| 63 | extern asmlinkage void handle_ov(void); |
| 64 | extern asmlinkage void handle_tr(void); |
| 65 | extern asmlinkage void handle_fpe(void); |
| 66 | extern asmlinkage void handle_mdmx(void); |
| 67 | extern asmlinkage void handle_watch(void); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 68 | extern asmlinkage void handle_mt(void); |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 69 | extern asmlinkage void handle_dsp(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | extern asmlinkage void handle_mcheck(void); |
| 71 | extern asmlinkage void handle_reserved(void); |
| 72 | |
Ralf Baechle | 12616ed | 2005-10-18 10:26:46 +0100 | [diff] [blame] | 73 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 74 | struct mips_fpu_struct *ctx, int has_fpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | |
| 76 | void (*board_be_init)(void); |
| 77 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 78 | void (*board_nmi_handler_setup)(void); |
| 79 | void (*board_ejtag_handler_setup)(void); |
| 80 | void (*board_bind_eic_interrupt)(int irq, int regset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | |
Franck Bui-Huu | 4d157d5 | 2006-08-03 09:29:21 +0200 | [diff] [blame] | 83 | static void show_raw_backtrace(unsigned long reg29) |
Atsushi Nemoto | e889d78 | 2006-07-25 23:51:36 +0900 | [diff] [blame] | 84 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 85 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
Atsushi Nemoto | e889d78 | 2006-07-25 23:51:36 +0900 | [diff] [blame] | 86 | unsigned long addr; |
| 87 | |
| 88 | printk("Call Trace:"); |
| 89 | #ifdef CONFIG_KALLSYMS |
| 90 | printk("\n"); |
| 91 | #endif |
Thomas Bogendoerfer | 10220c8 | 2008-05-12 17:58:48 +0200 | [diff] [blame] | 92 | while (!kstack_end(sp)) { |
| 93 | unsigned long __user *p = |
| 94 | (unsigned long __user *)(unsigned long)sp++; |
| 95 | if (__get_user(addr, p)) { |
| 96 | printk(" (Bad stack address)"); |
| 97 | break; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 98 | } |
Thomas Bogendoerfer | 10220c8 | 2008-05-12 17:58:48 +0200 | [diff] [blame] | 99 | if (__kernel_text_address(addr)) |
| 100 | print_ip_sym(addr); |
Atsushi Nemoto | e889d78 | 2006-07-25 23:51:36 +0900 | [diff] [blame] | 101 | } |
Thomas Bogendoerfer | 10220c8 | 2008-05-12 17:58:48 +0200 | [diff] [blame] | 102 | printk("\n"); |
Atsushi Nemoto | e889d78 | 2006-07-25 23:51:36 +0900 | [diff] [blame] | 103 | } |
| 104 | |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 105 | #ifdef CONFIG_KALLSYMS |
Atsushi Nemoto | 1df0f0f | 2006-09-26 23:44:01 +0900 | [diff] [blame] | 106 | int raw_show_trace; |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 107 | static int __init set_raw_show_trace(char *str) |
| 108 | { |
| 109 | raw_show_trace = 1; |
| 110 | return 1; |
| 111 | } |
| 112 | __setup("raw_show_trace", set_raw_show_trace); |
Atsushi Nemoto | 1df0f0f | 2006-09-26 23:44:01 +0900 | [diff] [blame] | 113 | #endif |
Franck Bui-Huu | 4d157d5 | 2006-08-03 09:29:21 +0200 | [diff] [blame] | 114 | |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 115 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 116 | { |
Franck Bui-Huu | 4d157d5 | 2006-08-03 09:29:21 +0200 | [diff] [blame] | 117 | unsigned long sp = regs->regs[29]; |
| 118 | unsigned long ra = regs->regs[31]; |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 119 | unsigned long pc = regs->cp0_epc; |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 120 | |
| 121 | if (raw_show_trace || !__kernel_text_address(pc)) { |
Franck Bui-Huu | 87151ae | 2006-08-03 09:29:17 +0200 | [diff] [blame] | 122 | show_raw_backtrace(sp); |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 123 | return; |
| 124 | } |
| 125 | printk("Call Trace:\n"); |
Franck Bui-Huu | 4d157d5 | 2006-08-03 09:29:21 +0200 | [diff] [blame] | 126 | do { |
Franck Bui-Huu | 87151ae | 2006-08-03 09:29:17 +0200 | [diff] [blame] | 127 | print_ip_sym(pc); |
Atsushi Nemoto | 1924600 | 2006-09-29 18:02:51 +0900 | [diff] [blame] | 128 | pc = unwind_stack(task, &sp, pc, &ra); |
Franck Bui-Huu | 4d157d5 | 2006-08-03 09:29:21 +0200 | [diff] [blame] | 129 | } while (pc); |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 130 | printk("\n"); |
| 131 | } |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 132 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | /* |
| 134 | * This routine abuses get_user()/put_user() to reference pointers |
| 135 | * with at least a bit of error checking ... |
| 136 | */ |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 137 | static void show_stacktrace(struct task_struct *task, |
| 138 | const struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | { |
| 140 | const int field = 2 * sizeof(unsigned long); |
| 141 | long stackdata; |
| 142 | int i; |
Atsushi Nemoto | 5e0373b | 2007-07-13 23:02:42 +0900 | [diff] [blame] | 143 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | |
| 145 | printk("Stack :"); |
| 146 | i = 0; |
| 147 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { |
| 148 | if (i && ((i % (64 / field)) == 0)) |
| 149 | printk("\n "); |
| 150 | if (i > 39) { |
| 151 | printk(" ..."); |
| 152 | break; |
| 153 | } |
| 154 | |
| 155 | if (__get_user(stackdata, sp++)) { |
| 156 | printk(" (Bad stack address)"); |
| 157 | break; |
| 158 | } |
| 159 | |
| 160 | printk(" %0*lx", field, stackdata); |
| 161 | i++; |
| 162 | } |
| 163 | printk("\n"); |
Franck Bui-Huu | 87151ae | 2006-08-03 09:29:17 +0200 | [diff] [blame] | 164 | show_backtrace(task, regs); |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 165 | } |
| 166 | |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 167 | void show_stack(struct task_struct *task, unsigned long *sp) |
| 168 | { |
| 169 | struct pt_regs regs; |
| 170 | if (sp) { |
| 171 | regs.regs[29] = (unsigned long)sp; |
| 172 | regs.regs[31] = 0; |
| 173 | regs.cp0_epc = 0; |
| 174 | } else { |
| 175 | if (task && task != current) { |
| 176 | regs.regs[29] = task->thread.reg29; |
| 177 | regs.regs[31] = 0; |
| 178 | regs.cp0_epc = task->thread.reg31; |
| 179 | } else { |
| 180 | prepare_frametrace(®s); |
| 181 | } |
| 182 | } |
| 183 | show_stacktrace(task, ®s); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | /* |
| 187 | * The architecture-independent dump_stack generator |
| 188 | */ |
| 189 | void dump_stack(void) |
| 190 | { |
Franck Bui-Huu | 1666a6f | 2006-08-03 09:29:19 +0200 | [diff] [blame] | 191 | struct pt_regs regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | |
Franck Bui-Huu | 1666a6f | 2006-08-03 09:29:19 +0200 | [diff] [blame] | 193 | prepare_frametrace(®s); |
| 194 | show_backtrace(current, ®s); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | } |
| 196 | |
| 197 | EXPORT_SYMBOL(dump_stack); |
| 198 | |
Atsushi Nemoto | e1bb8289 | 2007-07-13 23:51:46 +0900 | [diff] [blame] | 199 | static void show_code(unsigned int __user *pc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | { |
| 201 | long i; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 202 | unsigned short __user *pc16 = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | |
| 204 | printk("\nCode:"); |
| 205 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 206 | if ((unsigned long)pc & 1) |
| 207 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | for(i = -3 ; i < 6 ; i++) { |
| 209 | unsigned int insn; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 210 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | printk(" (Bad address in epc)\n"); |
| 212 | break; |
| 213 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 214 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | } |
| 216 | } |
| 217 | |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 218 | static void __show_regs(const struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | { |
| 220 | const int field = 2 * sizeof(unsigned long); |
| 221 | unsigned int cause = regs->cp0_cause; |
| 222 | int i; |
| 223 | |
| 224 | printk("Cpu %d\n", smp_processor_id()); |
| 225 | |
| 226 | /* |
| 227 | * Saved main processor registers |
| 228 | */ |
| 229 | for (i = 0; i < 32; ) { |
| 230 | if ((i % 4) == 0) |
| 231 | printk("$%2d :", i); |
| 232 | if (i == 0) |
| 233 | printk(" %0*lx", field, 0UL); |
| 234 | else if (i == 26 || i == 27) |
| 235 | printk(" %*s", field, ""); |
| 236 | else |
| 237 | printk(" %0*lx", field, regs->regs[i]); |
| 238 | |
| 239 | i++; |
| 240 | if ((i % 4) == 0) |
| 241 | printk("\n"); |
| 242 | } |
| 243 | |
Franck Bui-Huu | 9693a85 | 2007-02-02 17:41:47 +0100 | [diff] [blame] | 244 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
| 245 | printk("Acx : %0*lx\n", field, regs->acx); |
| 246 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | printk("Hi : %0*lx\n", field, regs->hi); |
| 248 | printk("Lo : %0*lx\n", field, regs->lo); |
| 249 | |
| 250 | /* |
| 251 | * Saved cp0 registers |
| 252 | */ |
Ralf Baechle | b012cff | 2008-07-15 18:44:33 +0100 | [diff] [blame] | 253 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
| 254 | (void *) regs->cp0_epc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 255 | printk(" %s\n", print_tainted()); |
Ralf Baechle | b012cff | 2008-07-15 18:44:33 +0100 | [diff] [blame] | 256 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
| 257 | (void *) regs->regs[31]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | |
| 259 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
| 260 | |
Maciej W. Rozycki | 3b2396d | 2005-06-22 20:43:29 +0000 | [diff] [blame] | 261 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
| 262 | if (regs->cp0_status & ST0_KUO) |
| 263 | printk("KUo "); |
| 264 | if (regs->cp0_status & ST0_IEO) |
| 265 | printk("IEo "); |
| 266 | if (regs->cp0_status & ST0_KUP) |
| 267 | printk("KUp "); |
| 268 | if (regs->cp0_status & ST0_IEP) |
| 269 | printk("IEp "); |
| 270 | if (regs->cp0_status & ST0_KUC) |
| 271 | printk("KUc "); |
| 272 | if (regs->cp0_status & ST0_IEC) |
| 273 | printk("IEc "); |
| 274 | } else { |
| 275 | if (regs->cp0_status & ST0_KX) |
| 276 | printk("KX "); |
| 277 | if (regs->cp0_status & ST0_SX) |
| 278 | printk("SX "); |
| 279 | if (regs->cp0_status & ST0_UX) |
| 280 | printk("UX "); |
| 281 | switch (regs->cp0_status & ST0_KSU) { |
| 282 | case KSU_USER: |
| 283 | printk("USER "); |
| 284 | break; |
| 285 | case KSU_SUPERVISOR: |
| 286 | printk("SUPERVISOR "); |
| 287 | break; |
| 288 | case KSU_KERNEL: |
| 289 | printk("KERNEL "); |
| 290 | break; |
| 291 | default: |
| 292 | printk("BAD_MODE "); |
| 293 | break; |
| 294 | } |
| 295 | if (regs->cp0_status & ST0_ERL) |
| 296 | printk("ERL "); |
| 297 | if (regs->cp0_status & ST0_EXL) |
| 298 | printk("EXL "); |
| 299 | if (regs->cp0_status & ST0_IE) |
| 300 | printk("IE "); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | printk("\n"); |
| 303 | |
| 304 | printk("Cause : %08x\n", cause); |
| 305 | |
| 306 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; |
| 307 | if (1 <= cause && cause <= 5) |
| 308 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); |
| 309 | |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 310 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
| 311 | cpu_name_string()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | } |
| 313 | |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 314 | /* |
| 315 | * FIXME: really the generic show_regs should take a const pointer argument. |
| 316 | */ |
| 317 | void show_regs(struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | { |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 319 | __show_regs((struct pt_regs *)regs); |
| 320 | } |
| 321 | |
| 322 | void show_registers(const struct pt_regs *regs) |
| 323 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 324 | const int field = 2 * sizeof(unsigned long); |
| 325 | |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 326 | __show_regs(regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | print_modules(); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 328 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
| 329 | current->comm, current->pid, current_thread_info(), current, |
| 330 | field, current_thread_info()->tp_value); |
| 331 | if (cpu_has_userlocal) { |
| 332 | unsigned long tls; |
| 333 | |
| 334 | tls = read_c0_userlocal(); |
| 335 | if (tls != current_thread_info()->tp_value) |
| 336 | printk("*HwTLS: %0*lx\n", field, tls); |
| 337 | } |
| 338 | |
Atsushi Nemoto | f66686f | 2006-07-29 23:27:20 +0900 | [diff] [blame] | 339 | show_stacktrace(current, regs); |
Atsushi Nemoto | e1bb8289 | 2007-07-13 23:51:46 +0900 | [diff] [blame] | 340 | show_code((unsigned int __user *) regs->cp0_epc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | printk("\n"); |
| 342 | } |
| 343 | |
| 344 | static DEFINE_SPINLOCK(die_lock); |
| 345 | |
Ralf Baechle | eae23f2 | 2007-10-14 23:27:21 +0100 | [diff] [blame] | 346 | void __noreturn die(const char * str, const struct pt_regs * regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | { |
| 348 | static int die_counter; |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 349 | #ifdef CONFIG_MIPS_MT_SMTC |
| 350 | unsigned long dvpret = dvpe(); |
| 351 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 352 | |
| 353 | console_verbose(); |
| 354 | spin_lock_irq(&die_lock); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 355 | bust_spinlocks(1); |
| 356 | #ifdef CONFIG_MIPS_MT_SMTC |
| 357 | mips_mt_regdump(dvpret); |
| 358 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | 178086c | 2005-10-13 17:07:54 +0100 | [diff] [blame] | 359 | printk("%s[#%d]:\n", str, ++die_counter); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 360 | show_registers(regs); |
Pavel Emelianov | bcdcd8e | 2007-07-17 04:03:42 -0700 | [diff] [blame] | 361 | add_taint(TAINT_DIE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | spin_unlock_irq(&die_lock); |
Maxime Bizon | d4fd198 | 2006-07-20 18:52:02 +0200 | [diff] [blame] | 363 | |
| 364 | if (in_interrupt()) |
| 365 | panic("Fatal exception in interrupt"); |
| 366 | |
| 367 | if (panic_on_oops) { |
| 368 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); |
| 369 | ssleep(5); |
| 370 | panic("Fatal exception"); |
| 371 | } |
| 372 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | do_exit(SIGSEGV); |
| 374 | } |
| 375 | |
Thomas Bogendoerfer | 0510617 | 2008-08-04 19:44:34 +0200 | [diff] [blame] | 376 | extern struct exception_table_entry __start___dbe_table[]; |
| 377 | extern struct exception_table_entry __stop___dbe_table[]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | |
Ralf Baechle | b6dcec9 | 2007-02-18 15:57:09 +0000 | [diff] [blame] | 379 | __asm__( |
| 380 | " .section __dbe_table, \"a\"\n" |
| 381 | " .previous \n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | |
| 383 | /* Given an address, look for it in the exception tables. */ |
| 384 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) |
| 385 | { |
| 386 | const struct exception_table_entry *e; |
| 387 | |
| 388 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); |
| 389 | if (!e) |
| 390 | e = search_module_dbetables(addr); |
| 391 | return e; |
| 392 | } |
| 393 | |
| 394 | asmlinkage void do_be(struct pt_regs *regs) |
| 395 | { |
| 396 | const int field = 2 * sizeof(unsigned long); |
| 397 | const struct exception_table_entry *fixup = NULL; |
| 398 | int data = regs->cp0_cause & 4; |
| 399 | int action = MIPS_BE_FATAL; |
| 400 | |
| 401 | /* XXX For now. Fixme, this searches the wrong table ... */ |
| 402 | if (data && !user_mode(regs)) |
| 403 | fixup = search_dbe_tables(exception_epc(regs)); |
| 404 | |
| 405 | if (fixup) |
| 406 | action = MIPS_BE_FIXUP; |
| 407 | |
| 408 | if (board_be_handler) |
Atsushi Nemoto | 28fc582 | 2007-07-13 01:49:49 +0900 | [diff] [blame] | 409 | action = board_be_handler(regs, fixup != NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | |
| 411 | switch (action) { |
| 412 | case MIPS_BE_DISCARD: |
| 413 | return; |
| 414 | case MIPS_BE_FIXUP: |
| 415 | if (fixup) { |
| 416 | regs->cp0_epc = fixup->nextinsn; |
| 417 | return; |
| 418 | } |
| 419 | break; |
| 420 | default: |
| 421 | break; |
| 422 | } |
| 423 | |
| 424 | /* |
| 425 | * Assume it would be too dangerous to continue ... |
| 426 | */ |
| 427 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", |
| 428 | data ? "Data" : "Instruction", |
| 429 | field, regs->cp0_epc, field, regs->regs[31]); |
Jason Wessel | 8854700 | 2008-07-29 15:58:53 -0500 | [diff] [blame] | 430 | if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) |
| 431 | == NOTIFY_STOP) |
| 432 | return; |
| 433 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | die_if_kernel("Oops", regs); |
| 435 | force_sig(SIGBUS, current); |
| 436 | } |
| 437 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | /* |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 439 | * ll/sc, rdhwr, sync emulation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | */ |
| 441 | |
| 442 | #define OPCODE 0xfc000000 |
| 443 | #define BASE 0x03e00000 |
| 444 | #define RT 0x001f0000 |
| 445 | #define OFFSET 0x0000ffff |
| 446 | #define LL 0xc0000000 |
| 447 | #define SC 0xe0000000 |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 448 | #define SPEC0 0x00000000 |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 449 | #define SPEC3 0x7c000000 |
| 450 | #define RD 0x0000f800 |
| 451 | #define FUNC 0x0000003f |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 452 | #define SYNC 0x0000000f |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 453 | #define RDHWR 0x0000003b |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | |
| 455 | /* |
| 456 | * The ll_bit is cleared by r*_switch.S |
| 457 | */ |
| 458 | |
| 459 | unsigned long ll_bit; |
| 460 | |
| 461 | static struct task_struct *ll_task = NULL; |
| 462 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 463 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | { |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 465 | unsigned long value, __user *vaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | long offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | |
| 468 | /* |
| 469 | * analyse the ll instruction that just caused a ri exception |
| 470 | * and put the referenced address to addr. |
| 471 | */ |
| 472 | |
| 473 | /* sign extend offset */ |
| 474 | offset = opcode & OFFSET; |
| 475 | offset <<= 16; |
| 476 | offset >>= 16; |
| 477 | |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 478 | vaddr = (unsigned long __user *) |
| 479 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 481 | if ((unsigned long)vaddr & 3) |
| 482 | return SIGBUS; |
| 483 | if (get_user(value, vaddr)) |
| 484 | return SIGSEGV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | |
| 486 | preempt_disable(); |
| 487 | |
| 488 | if (ll_task == NULL || ll_task == current) { |
| 489 | ll_bit = 1; |
| 490 | } else { |
| 491 | ll_bit = 0; |
| 492 | } |
| 493 | ll_task = current; |
| 494 | |
| 495 | preempt_enable(); |
| 496 | |
| 497 | regs->regs[(opcode & RT) >> 16] = value; |
| 498 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 499 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | } |
| 501 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 502 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | { |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 504 | unsigned long __user *vaddr; |
| 505 | unsigned long reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | long offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | |
| 508 | /* |
| 509 | * analyse the sc instruction that just caused a ri exception |
| 510 | * and put the referenced address to addr. |
| 511 | */ |
| 512 | |
| 513 | /* sign extend offset */ |
| 514 | offset = opcode & OFFSET; |
| 515 | offset <<= 16; |
| 516 | offset >>= 16; |
| 517 | |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 518 | vaddr = (unsigned long __user *) |
| 519 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | reg = (opcode & RT) >> 16; |
| 521 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 522 | if ((unsigned long)vaddr & 3) |
| 523 | return SIGBUS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 524 | |
| 525 | preempt_disable(); |
| 526 | |
| 527 | if (ll_bit == 0 || ll_task != current) { |
| 528 | regs->regs[reg] = 0; |
| 529 | preempt_enable(); |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 530 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | } |
| 532 | |
| 533 | preempt_enable(); |
| 534 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 535 | if (put_user(regs->regs[reg], vaddr)) |
| 536 | return SIGSEGV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | |
| 538 | regs->regs[reg] = 1; |
| 539 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 540 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | } |
| 542 | |
| 543 | /* |
| 544 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both |
| 545 | * opcodes are supposed to result in coprocessor unusable exceptions if |
| 546 | * executed on ll/sc-less processors. That's the theory. In practice a |
| 547 | * few processors such as NEC's VR4100 throw reserved instruction exceptions |
| 548 | * instead, so we're doing the emulation thing in both exception handlers. |
| 549 | */ |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 550 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 551 | { |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 552 | if ((opcode & OPCODE) == LL) |
| 553 | return simulate_ll(regs, opcode); |
| 554 | if ((opcode & OPCODE) == SC) |
| 555 | return simulate_sc(regs, opcode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 556 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 557 | return -1; /* Must be something else ... */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | } |
| 559 | |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 560 | /* |
| 561 | * Simulate trapping 'rdhwr' instructions to provide user accessible |
Chris Dearman | 1f5826b | 2006-05-08 18:02:16 +0100 | [diff] [blame] | 562 | * registers not implemented in hardware. |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 563 | */ |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 564 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 565 | { |
Al Viro | dc8f602 | 2006-01-12 01:06:07 -0800 | [diff] [blame] | 566 | struct thread_info *ti = task_thread_info(current); |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 567 | |
| 568 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
| 569 | int rd = (opcode & RD) >> 11; |
| 570 | int rt = (opcode & RT) >> 16; |
| 571 | switch (rd) { |
Chris Dearman | 1f5826b | 2006-05-08 18:02:16 +0100 | [diff] [blame] | 572 | case 0: /* CPU number */ |
| 573 | regs->regs[rt] = smp_processor_id(); |
| 574 | return 0; |
| 575 | case 1: /* SYNCI length */ |
| 576 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, |
| 577 | current_cpu_data.icache.linesz); |
| 578 | return 0; |
| 579 | case 2: /* Read count register */ |
| 580 | regs->regs[rt] = read_c0_count(); |
| 581 | return 0; |
| 582 | case 3: /* Count register resolution */ |
| 583 | switch (current_cpu_data.cputype) { |
| 584 | case CPU_20KC: |
| 585 | case CPU_25KF: |
| 586 | regs->regs[rt] = 1; |
| 587 | break; |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 588 | default: |
Chris Dearman | 1f5826b | 2006-05-08 18:02:16 +0100 | [diff] [blame] | 589 | regs->regs[rt] = 2; |
| 590 | } |
| 591 | return 0; |
| 592 | case 29: |
| 593 | regs->regs[rt] = ti->tp_value; |
| 594 | return 0; |
| 595 | default: |
| 596 | return -1; |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 597 | } |
| 598 | } |
| 599 | |
Daniel Jacobowitz | 56ebd51 | 2005-11-26 22:34:41 -0500 | [diff] [blame] | 600 | /* Not ours. */ |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 601 | return -1; |
| 602 | } |
Ralf Baechle | e567988 | 2006-11-30 01:14:47 +0000 | [diff] [blame] | 603 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 604 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
| 605 | { |
| 606 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) |
| 607 | return 0; |
| 608 | |
| 609 | return -1; /* Must be something else ... */ |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 610 | } |
| 611 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | asmlinkage void do_ov(struct pt_regs *regs) |
| 613 | { |
| 614 | siginfo_t info; |
| 615 | |
Ralf Baechle | 36ccf1c | 2006-02-14 21:04:54 +0000 | [diff] [blame] | 616 | die_if_kernel("Integer overflow", regs); |
| 617 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | info.si_code = FPE_INTOVF; |
| 619 | info.si_signo = SIGFPE; |
| 620 | info.si_errno = 0; |
Ralf Baechle | fe00f94 | 2005-03-01 19:22:29 +0000 | [diff] [blame] | 621 | info.si_addr = (void __user *) regs->cp0_epc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | force_sig_info(SIGFPE, &info, current); |
| 623 | } |
| 624 | |
| 625 | /* |
| 626 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX |
| 627 | */ |
| 628 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) |
| 629 | { |
Thiemo Seufer | 948a34c | 2007-08-22 01:42:04 +0100 | [diff] [blame] | 630 | siginfo_t info; |
| 631 | |
Jason Wessel | 8854700 | 2008-07-29 15:58:53 -0500 | [diff] [blame] | 632 | if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) |
| 633 | == NOTIFY_STOP) |
| 634 | return; |
Chris Dearman | 57725f9 | 2006-06-30 23:35:28 +0100 | [diff] [blame] | 635 | die_if_kernel("FP exception in kernel code", regs); |
| 636 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | if (fcr31 & FPU_CSR_UNI_X) { |
| 638 | int sig; |
| 639 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | /* |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 641 | * Unimplemented operation exception. If we've got the full |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | * software emulator on-board, let's use it... |
| 643 | * |
| 644 | * Force FPU to dump state into task/thread context. We're |
| 645 | * moving a lot of data here for what is probably a single |
| 646 | * instruction, but the alternative is to pre-decode the FP |
| 647 | * register operands before invoking the emulator, which seems |
| 648 | * a bit extreme for what should be an infrequent event. |
| 649 | */ |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 650 | /* Ensure 'resume' not overwrite saved fp context again. */ |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 651 | lose_fpu(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | |
| 653 | /* Run the emulator */ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 654 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 655 | |
| 656 | /* |
| 657 | * We can't allow the emulated instruction to leave any of |
| 658 | * the cause bit set in $fcr31. |
| 659 | */ |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 660 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 661 | |
| 662 | /* Restore the hardware register state */ |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 663 | own_fpu(1); /* Using the FPU again. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | |
| 665 | /* If something went wrong, signal */ |
| 666 | if (sig) |
| 667 | force_sig(sig, current); |
| 668 | |
| 669 | return; |
Thiemo Seufer | 948a34c | 2007-08-22 01:42:04 +0100 | [diff] [blame] | 670 | } else if (fcr31 & FPU_CSR_INV_X) |
| 671 | info.si_code = FPE_FLTINV; |
| 672 | else if (fcr31 & FPU_CSR_DIV_X) |
| 673 | info.si_code = FPE_FLTDIV; |
| 674 | else if (fcr31 & FPU_CSR_OVF_X) |
| 675 | info.si_code = FPE_FLTOVF; |
| 676 | else if (fcr31 & FPU_CSR_UDF_X) |
| 677 | info.si_code = FPE_FLTUND; |
| 678 | else if (fcr31 & FPU_CSR_INE_X) |
| 679 | info.si_code = FPE_FLTRES; |
| 680 | else |
| 681 | info.si_code = __SI_FAULT; |
| 682 | info.si_signo = SIGFPE; |
| 683 | info.si_errno = 0; |
| 684 | info.si_addr = (void __user *) regs->cp0_epc; |
| 685 | force_sig_info(SIGFPE, &info, current); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 686 | } |
| 687 | |
Ralf Baechle | df27005 | 2008-04-20 16:28:54 +0100 | [diff] [blame] | 688 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
| 689 | const char *str) |
| 690 | { |
| 691 | siginfo_t info; |
| 692 | char b[40]; |
| 693 | |
Jason Wessel | 8854700 | 2008-07-29 15:58:53 -0500 | [diff] [blame] | 694 | if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) |
| 695 | return; |
| 696 | |
Ralf Baechle | df27005 | 2008-04-20 16:28:54 +0100 | [diff] [blame] | 697 | /* |
| 698 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
| 699 | * insns, even for trap and break codes that indicate arithmetic |
| 700 | * failures. Weird ... |
| 701 | * But should we continue the brokenness??? --macro |
| 702 | */ |
| 703 | switch (code) { |
| 704 | case BRK_OVERFLOW: |
| 705 | case BRK_DIVZERO: |
| 706 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
| 707 | die_if_kernel(b, regs); |
| 708 | if (code == BRK_DIVZERO) |
| 709 | info.si_code = FPE_INTDIV; |
| 710 | else |
| 711 | info.si_code = FPE_INTOVF; |
| 712 | info.si_signo = SIGFPE; |
| 713 | info.si_errno = 0; |
| 714 | info.si_addr = (void __user *) regs->cp0_epc; |
| 715 | force_sig_info(SIGFPE, &info, current); |
| 716 | break; |
| 717 | case BRK_BUG: |
| 718 | die_if_kernel("Kernel bug detected", regs); |
| 719 | force_sig(SIGTRAP, current); |
| 720 | break; |
| 721 | default: |
| 722 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
| 723 | die_if_kernel(b, regs); |
| 724 | force_sig(SIGTRAP, current); |
| 725 | } |
| 726 | } |
| 727 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 728 | asmlinkage void do_bp(struct pt_regs *regs) |
| 729 | { |
| 730 | unsigned int opcode, bcode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 731 | |
Atsushi Nemoto | ba755f8 | 2007-04-12 20:02:54 +0900 | [diff] [blame] | 732 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
Ralf Baechle | e567988 | 2006-11-30 01:14:47 +0000 | [diff] [blame] | 733 | goto out_sigsegv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 734 | |
| 735 | /* |
| 736 | * There is the ancient bug in the MIPS assemblers that the break |
| 737 | * code starts left to bit 16 instead to bit 6 in the opcode. |
| 738 | * Gas is bug-compatible, but not always, grrr... |
| 739 | * We handle both cases with a simple heuristics. --macro |
| 740 | */ |
| 741 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); |
Ralf Baechle | df27005 | 2008-04-20 16:28:54 +0100 | [diff] [blame] | 742 | if (bcode >= (1 << 10)) |
| 743 | bcode >>= 10; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | |
Ralf Baechle | df27005 | 2008-04-20 16:28:54 +0100 | [diff] [blame] | 745 | do_trap_or_bp(regs, bcode, "Break"); |
Atsushi Nemoto | 90fccb1 | 2007-02-06 16:02:21 +0900 | [diff] [blame] | 746 | return; |
Ralf Baechle | e567988 | 2006-11-30 01:14:47 +0000 | [diff] [blame] | 747 | |
| 748 | out_sigsegv: |
| 749 | force_sig(SIGSEGV, current); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | asmlinkage void do_tr(struct pt_regs *regs) |
| 753 | { |
| 754 | unsigned int opcode, tcode = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | |
Atsushi Nemoto | ba755f8 | 2007-04-12 20:02:54 +0900 | [diff] [blame] | 756 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
Ralf Baechle | e567988 | 2006-11-30 01:14:47 +0000 | [diff] [blame] | 757 | goto out_sigsegv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | |
| 759 | /* Immediate versions don't provide a code. */ |
| 760 | if (!(opcode & OPCODE)) |
| 761 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); |
| 762 | |
Ralf Baechle | df27005 | 2008-04-20 16:28:54 +0100 | [diff] [blame] | 763 | do_trap_or_bp(regs, tcode, "Trap"); |
Atsushi Nemoto | 90fccb1 | 2007-02-06 16:02:21 +0900 | [diff] [blame] | 764 | return; |
Ralf Baechle | e567988 | 2006-11-30 01:14:47 +0000 | [diff] [blame] | 765 | |
| 766 | out_sigsegv: |
| 767 | force_sig(SIGSEGV, current); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 768 | } |
| 769 | |
| 770 | asmlinkage void do_ri(struct pt_regs *regs) |
| 771 | { |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 772 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
| 773 | unsigned long old_epc = regs->cp0_epc; |
| 774 | unsigned int opcode = 0; |
| 775 | int status = -1; |
| 776 | |
Jason Wessel | 8854700 | 2008-07-29 15:58:53 -0500 | [diff] [blame] | 777 | if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) |
| 778 | == NOTIFY_STOP) |
| 779 | return; |
| 780 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | die_if_kernel("Reserved instruction in kernel code", regs); |
| 782 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 783 | if (unlikely(compute_return_epc(regs) < 0)) |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 784 | return; |
| 785 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 786 | if (unlikely(get_user(opcode, epc) < 0)) |
| 787 | status = SIGSEGV; |
| 788 | |
| 789 | if (!cpu_has_llsc && status < 0) |
| 790 | status = simulate_llsc(regs, opcode); |
| 791 | |
| 792 | if (status < 0) |
| 793 | status = simulate_rdhwr(regs, opcode); |
| 794 | |
| 795 | if (status < 0) |
| 796 | status = simulate_sync(regs, opcode); |
| 797 | |
| 798 | if (status < 0) |
| 799 | status = SIGILL; |
| 800 | |
| 801 | if (unlikely(status > 0)) { |
| 802 | regs->cp0_epc = old_epc; /* Undo skip-over. */ |
| 803 | force_sig(status, current); |
| 804 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | } |
| 806 | |
Ralf Baechle | d223a861 | 2007-07-10 17:33:02 +0100 | [diff] [blame] | 807 | /* |
| 808 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've |
| 809 | * emulated more than some threshold number of instructions, force migration to |
| 810 | * a "CPU" that has FP support. |
| 811 | */ |
| 812 | static void mt_ase_fp_affinity(void) |
| 813 | { |
| 814 | #ifdef CONFIG_MIPS_MT_FPAFF |
| 815 | if (mt_fpemul_threshold > 0 && |
| 816 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { |
| 817 | /* |
| 818 | * If there's no FPU present, or if the application has already |
| 819 | * restricted the allowed set to exclude any CPUs with FPUs, |
| 820 | * we'll skip the procedure. |
| 821 | */ |
| 822 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { |
| 823 | cpumask_t tmask; |
| 824 | |
| 825 | cpus_and(tmask, current->thread.user_cpus_allowed, |
| 826 | mt_fpu_cpumask); |
| 827 | set_cpus_allowed(current, tmask); |
Ralf Baechle | 293c5bd | 2007-07-25 16:19:33 +0100 | [diff] [blame] | 828 | set_thread_flag(TIF_FPUBOUND); |
Ralf Baechle | d223a861 | 2007-07-10 17:33:02 +0100 | [diff] [blame] | 829 | } |
| 830 | } |
| 831 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
| 832 | } |
| 833 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | asmlinkage void do_cpu(struct pt_regs *regs) |
| 835 | { |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 836 | unsigned int __user *epc; |
| 837 | unsigned long old_epc; |
| 838 | unsigned int opcode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | unsigned int cpid; |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 840 | int status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 841 | |
Atsushi Nemoto | 5323180 | 2007-04-14 02:37:26 +0900 | [diff] [blame] | 842 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
| 843 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 844 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
| 845 | |
| 846 | switch (cpid) { |
| 847 | case 0: |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 848 | epc = (unsigned int __user *)exception_epc(regs); |
| 849 | old_epc = regs->cp0_epc; |
| 850 | opcode = 0; |
| 851 | status = -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 853 | if (unlikely(compute_return_epc(regs) < 0)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | return; |
Ralf Baechle | 3c37026 | 2005-04-13 17:43:59 +0000 | [diff] [blame] | 855 | |
Maciej W. Rozycki | 60b0d65 | 2007-10-16 18:43:26 +0100 | [diff] [blame] | 856 | if (unlikely(get_user(opcode, epc) < 0)) |
| 857 | status = SIGSEGV; |
| 858 | |
| 859 | if (!cpu_has_llsc && status < 0) |
| 860 | status = simulate_llsc(regs, opcode); |
| 861 | |
| 862 | if (status < 0) |
| 863 | status = simulate_rdhwr(regs, opcode); |
| 864 | |
| 865 | if (status < 0) |
| 866 | status = SIGILL; |
| 867 | |
| 868 | if (unlikely(status > 0)) { |
| 869 | regs->cp0_epc = old_epc; /* Undo skip-over. */ |
| 870 | force_sig(status, current); |
| 871 | } |
| 872 | |
| 873 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 874 | |
| 875 | case 1: |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 876 | if (used_math()) /* Using the FPU again. */ |
| 877 | own_fpu(1); |
| 878 | else { /* First time FPU user. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 879 | init_fpu(); |
| 880 | set_used_math(); |
| 881 | } |
| 882 | |
Atsushi Nemoto | 5323180 | 2007-04-14 02:37:26 +0900 | [diff] [blame] | 883 | if (!raw_cpu_has_fpu) { |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 884 | int sig; |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 885 | sig = fpu_emulator_cop1Handler(regs, |
| 886 | ¤t->thread.fpu, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 887 | if (sig) |
| 888 | force_sig(sig, current); |
Ralf Baechle | d223a861 | 2007-07-10 17:33:02 +0100 | [diff] [blame] | 889 | else |
| 890 | mt_ase_fp_affinity(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | } |
| 892 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | return; |
| 894 | |
| 895 | case 2: |
| 896 | case 3: |
| 897 | break; |
| 898 | } |
| 899 | |
| 900 | force_sig(SIGILL, current); |
| 901 | } |
| 902 | |
| 903 | asmlinkage void do_mdmx(struct pt_regs *regs) |
| 904 | { |
| 905 | force_sig(SIGILL, current); |
| 906 | } |
| 907 | |
| 908 | asmlinkage void do_watch(struct pt_regs *regs) |
| 909 | { |
| 910 | /* |
| 911 | * We use the watch exception where available to detect stack |
| 912 | * overflows. |
| 913 | */ |
| 914 | dump_tlb_all(); |
| 915 | show_regs(regs); |
| 916 | panic("Caught WATCH exception - probably caused by stack overflow."); |
| 917 | } |
| 918 | |
| 919 | asmlinkage void do_mcheck(struct pt_regs *regs) |
| 920 | { |
Ralf Baechle | cac4bcb | 2006-05-24 16:51:02 +0100 | [diff] [blame] | 921 | const int field = 2 * sizeof(unsigned long); |
| 922 | int multi_match = regs->cp0_status & ST0_TS; |
| 923 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | show_regs(regs); |
Ralf Baechle | cac4bcb | 2006-05-24 16:51:02 +0100 | [diff] [blame] | 925 | |
| 926 | if (multi_match) { |
| 927 | printk("Index : %0x\n", read_c0_index()); |
| 928 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
| 929 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); |
| 930 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); |
| 931 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); |
| 932 | printk("\n"); |
| 933 | dump_tlb_all(); |
| 934 | } |
| 935 | |
Atsushi Nemoto | e1bb8289 | 2007-07-13 23:51:46 +0900 | [diff] [blame] | 936 | show_code((unsigned int __user *) regs->cp0_epc); |
Ralf Baechle | cac4bcb | 2006-05-24 16:51:02 +0100 | [diff] [blame] | 937 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | /* |
| 939 | * Some chips may have other causes of machine check (e.g. SB1 |
| 940 | * graduation timer) |
| 941 | */ |
| 942 | panic("Caught Machine Check exception - %scaused by multiple " |
| 943 | "matching entries in the TLB.", |
Ralf Baechle | cac4bcb | 2006-05-24 16:51:02 +0100 | [diff] [blame] | 944 | (multi_match) ? "" : "not "); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 945 | } |
| 946 | |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 947 | asmlinkage void do_mt(struct pt_regs *regs) |
| 948 | { |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 949 | int subcode; |
| 950 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 951 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
| 952 | >> VPECONTROL_EXCPT_SHIFT; |
| 953 | switch (subcode) { |
| 954 | case 0: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 955 | printk(KERN_DEBUG "Thread Underflow\n"); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 956 | break; |
| 957 | case 1: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 958 | printk(KERN_DEBUG "Thread Overflow\n"); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 959 | break; |
| 960 | case 2: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 961 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 962 | break; |
| 963 | case 3: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 964 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 965 | break; |
| 966 | case 4: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 967 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 968 | break; |
| 969 | case 5: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 970 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 971 | break; |
| 972 | default: |
Chris Dearman | e35a5e3 | 2006-06-30 14:19:45 +0100 | [diff] [blame] | 973 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 974 | subcode); |
| 975 | break; |
| 976 | } |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 977 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
| 978 | |
| 979 | force_sig(SIGILL, current); |
| 980 | } |
| 981 | |
| 982 | |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 983 | asmlinkage void do_dsp(struct pt_regs *regs) |
| 984 | { |
| 985 | if (cpu_has_dsp) |
| 986 | panic("Unexpected DSP exception\n"); |
| 987 | |
| 988 | force_sig(SIGILL, current); |
| 989 | } |
| 990 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | asmlinkage void do_reserved(struct pt_regs *regs) |
| 992 | { |
| 993 | /* |
| 994 | * Game over - no way to handle this if it ever occurs. Most probably |
| 995 | * caused by a new unknown cpu type or after another deadly |
| 996 | * hard/software error. |
| 997 | */ |
| 998 | show_regs(regs); |
| 999 | panic("Caught reserved exception %ld - should not happen.", |
| 1000 | (regs->cp0_cause & 0x7f) >> 2); |
| 1001 | } |
| 1002 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1003 | static int __initdata l1parity = 1; |
| 1004 | static int __init nol1parity(char *s) |
| 1005 | { |
| 1006 | l1parity = 0; |
| 1007 | return 1; |
| 1008 | } |
| 1009 | __setup("nol1par", nol1parity); |
| 1010 | static int __initdata l2parity = 1; |
| 1011 | static int __init nol2parity(char *s) |
| 1012 | { |
| 1013 | l2parity = 0; |
| 1014 | return 1; |
| 1015 | } |
| 1016 | __setup("nol2par", nol2parity); |
| 1017 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | /* |
| 1019 | * Some MIPS CPUs can enable/disable for cache parity detection, but do |
| 1020 | * it different ways. |
| 1021 | */ |
| 1022 | static inline void parity_protection_init(void) |
| 1023 | { |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1024 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1025 | case CPU_24K: |
Nigel Stephens | 98a41de | 2006-04-27 15:50:32 +0100 | [diff] [blame] | 1026 | case CPU_34K: |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1027 | case CPU_74K: |
| 1028 | case CPU_1004K: |
| 1029 | { |
| 1030 | #define ERRCTL_PE 0x80000000 |
| 1031 | #define ERRCTL_L2P 0x00800000 |
| 1032 | unsigned long errctl; |
| 1033 | unsigned int l1parity_present, l2parity_present; |
| 1034 | |
| 1035 | errctl = read_c0_ecc(); |
| 1036 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); |
| 1037 | |
| 1038 | /* probe L1 parity support */ |
| 1039 | write_c0_ecc(errctl | ERRCTL_PE); |
| 1040 | back_to_back_c0_hazard(); |
| 1041 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); |
| 1042 | |
| 1043 | /* probe L2 parity support */ |
| 1044 | write_c0_ecc(errctl|ERRCTL_L2P); |
| 1045 | back_to_back_c0_hazard(); |
| 1046 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); |
| 1047 | |
| 1048 | if (l1parity_present && l2parity_present) { |
| 1049 | if (l1parity) |
| 1050 | errctl |= ERRCTL_PE; |
| 1051 | if (l1parity ^ l2parity) |
| 1052 | errctl |= ERRCTL_L2P; |
| 1053 | } else if (l1parity_present) { |
| 1054 | if (l1parity) |
| 1055 | errctl |= ERRCTL_PE; |
| 1056 | } else if (l2parity_present) { |
| 1057 | if (l2parity) |
| 1058 | errctl |= ERRCTL_L2P; |
| 1059 | } else { |
| 1060 | /* No parity available */ |
| 1061 | } |
| 1062 | |
| 1063 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); |
| 1064 | |
| 1065 | write_c0_ecc(errctl); |
| 1066 | back_to_back_c0_hazard(); |
| 1067 | errctl = read_c0_ecc(); |
| 1068 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); |
| 1069 | |
| 1070 | if (l1parity_present) |
| 1071 | printk(KERN_INFO "Cache parity protection %sabled\n", |
| 1072 | (errctl & ERRCTL_PE) ? "en" : "dis"); |
| 1073 | |
| 1074 | if (l2parity_present) { |
| 1075 | if (l1parity_present && l1parity) |
| 1076 | errctl ^= ERRCTL_L2P; |
| 1077 | printk(KERN_INFO "L2 cache parity protection %sabled\n", |
| 1078 | (errctl & ERRCTL_L2P) ? "en" : "dis"); |
| 1079 | } |
| 1080 | } |
| 1081 | break; |
| 1082 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | case CPU_5KC: |
Ralf Baechle | 14f18b7 | 2005-03-01 18:15:08 +0000 | [diff] [blame] | 1084 | write_c0_ecc(0x80000000); |
| 1085 | back_to_back_c0_hazard(); |
| 1086 | /* Set the PE bit (bit 31) in the c0_errctl register. */ |
| 1087 | printk(KERN_INFO "Cache parity protection %sabled\n", |
| 1088 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1089 | break; |
| 1090 | case CPU_20KC: |
| 1091 | case CPU_25KF: |
| 1092 | /* Clear the DE bit (bit 16) in the c0_status register. */ |
| 1093 | printk(KERN_INFO "Enable cache parity protection for " |
| 1094 | "MIPS 20KC/25KF CPUs.\n"); |
| 1095 | clear_c0_status(ST0_DE); |
| 1096 | break; |
| 1097 | default: |
| 1098 | break; |
| 1099 | } |
| 1100 | } |
| 1101 | |
| 1102 | asmlinkage void cache_parity_error(void) |
| 1103 | { |
| 1104 | const int field = 2 * sizeof(unsigned long); |
| 1105 | unsigned int reg_val; |
| 1106 | |
| 1107 | /* For the moment, report the problem and hang. */ |
| 1108 | printk("Cache error exception:\n"); |
| 1109 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); |
| 1110 | reg_val = read_c0_cacheerr(); |
| 1111 | printk("c0_cacheerr == %08x\n", reg_val); |
| 1112 | |
| 1113 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", |
| 1114 | reg_val & (1<<30) ? "secondary" : "primary", |
| 1115 | reg_val & (1<<31) ? "data" : "insn"); |
| 1116 | printk("Error bits: %s%s%s%s%s%s%s\n", |
| 1117 | reg_val & (1<<29) ? "ED " : "", |
| 1118 | reg_val & (1<<28) ? "ET " : "", |
| 1119 | reg_val & (1<<26) ? "EE " : "", |
| 1120 | reg_val & (1<<25) ? "EB " : "", |
| 1121 | reg_val & (1<<24) ? "EI " : "", |
| 1122 | reg_val & (1<<23) ? "E1 " : "", |
| 1123 | reg_val & (1<<22) ? "E0 " : ""); |
| 1124 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); |
| 1125 | |
Ralf Baechle | ec917c2c | 2005-10-07 16:58:15 +0100 | [diff] [blame] | 1126 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1127 | if (reg_val & (1<<22)) |
| 1128 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); |
| 1129 | |
| 1130 | if (reg_val & (1<<23)) |
| 1131 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); |
| 1132 | #endif |
| 1133 | |
| 1134 | panic("Can't handle the cache error!"); |
| 1135 | } |
| 1136 | |
| 1137 | /* |
| 1138 | * SDBBP EJTAG debug exception handler. |
| 1139 | * We skip the instruction and return to the next instruction. |
| 1140 | */ |
| 1141 | void ejtag_exception_handler(struct pt_regs *regs) |
| 1142 | { |
| 1143 | const int field = 2 * sizeof(unsigned long); |
| 1144 | unsigned long depc, old_epc; |
| 1145 | unsigned int debug; |
| 1146 | |
Chris Dearman | 70ae612 | 2006-06-30 12:32:37 +0100 | [diff] [blame] | 1147 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1148 | depc = read_c0_depc(); |
| 1149 | debug = read_c0_debug(); |
Chris Dearman | 70ae612 | 2006-06-30 12:32:37 +0100 | [diff] [blame] | 1150 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | if (debug & 0x80000000) { |
| 1152 | /* |
| 1153 | * In branch delay slot. |
| 1154 | * We cheat a little bit here and use EPC to calculate the |
| 1155 | * debug return address (DEPC). EPC is restored after the |
| 1156 | * calculation. |
| 1157 | */ |
| 1158 | old_epc = regs->cp0_epc; |
| 1159 | regs->cp0_epc = depc; |
| 1160 | __compute_return_epc(regs); |
| 1161 | depc = regs->cp0_epc; |
| 1162 | regs->cp0_epc = old_epc; |
| 1163 | } else |
| 1164 | depc += 4; |
| 1165 | write_c0_depc(depc); |
| 1166 | |
| 1167 | #if 0 |
Chris Dearman | 70ae612 | 2006-06-30 12:32:37 +0100 | [diff] [blame] | 1168 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | write_c0_debug(debug | 0x100); |
| 1170 | #endif |
| 1171 | } |
| 1172 | |
| 1173 | /* |
| 1174 | * NMI exception handler. |
| 1175 | */ |
Thiemo Seufer | 34412c7 | 2007-08-20 23:43:49 +0100 | [diff] [blame] | 1176 | NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1177 | { |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1178 | bust_spinlocks(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | printk("NMI taken!!!!\n"); |
| 1180 | die("NMI", regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | } |
| 1182 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1183 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
| 1184 | |
| 1185 | unsigned long ebase; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1186 | unsigned long exception_handlers[32]; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1187 | unsigned long vi_handlers[64]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1188 | |
| 1189 | /* |
| 1190 | * As a side effect of the way this is implemented we're limited |
| 1191 | * to interrupt handlers in the address range from |
| 1192 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... |
| 1193 | */ |
| 1194 | void *set_except_vector(int n, void *addr) |
| 1195 | { |
| 1196 | unsigned long handler = (unsigned long) addr; |
| 1197 | unsigned long old_handler = exception_handlers[n]; |
| 1198 | |
| 1199 | exception_handlers[n] = handler; |
| 1200 | if (n == 0 && cpu_has_divec) { |
Ralf Baechle | ec70f65 | 2007-10-11 23:46:03 +0100 | [diff] [blame] | 1201 | *(u32 *)(ebase + 0x200) = 0x08000000 | |
| 1202 | (0x03ffffff & (handler >> 2)); |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1203 | local_flush_icache_range(ebase + 0x200, ebase + 0x204); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1204 | } |
| 1205 | return (void *)old_handler; |
| 1206 | } |
| 1207 | |
Atsushi Nemoto | 6ba07e5 | 2007-05-21 23:45:38 +0900 | [diff] [blame] | 1208 | static asmlinkage void do_default_vi(void) |
| 1209 | { |
| 1210 | show_regs(get_irq_regs()); |
| 1211 | panic("Caught unexpected vectored interrupt."); |
| 1212 | } |
| 1213 | |
Ralf Baechle | ef300e4 | 2007-05-06 18:31:18 +0100 | [diff] [blame] | 1214 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1215 | { |
| 1216 | unsigned long handler; |
| 1217 | unsigned long old_handler = vi_handlers[n]; |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 1218 | int srssets = current_cpu_data.srsets; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1219 | u32 *w; |
| 1220 | unsigned char *b; |
| 1221 | |
| 1222 | if (!cpu_has_veic && !cpu_has_vint) |
| 1223 | BUG(); |
| 1224 | |
| 1225 | if (addr == NULL) { |
| 1226 | handler = (unsigned long) do_default_vi; |
| 1227 | srs = 0; |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1228 | } else |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1229 | handler = (unsigned long) addr; |
| 1230 | vi_handlers[n] = (unsigned long) addr; |
| 1231 | |
| 1232 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); |
| 1233 | |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 1234 | if (srs >= srssets) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1235 | panic("Shadow register set %d not supported", srs); |
| 1236 | |
| 1237 | if (cpu_has_veic) { |
| 1238 | if (board_bind_eic_interrupt) |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1239 | board_bind_eic_interrupt(n, srs); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1240 | } else if (cpu_has_vint) { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1241 | /* SRSMap is only defined if shadow sets are implemented */ |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 1242 | if (srssets > 1) |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1243 | change_c0_srsmap(0xf << n*4, srs << n*4); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1244 | } |
| 1245 | |
| 1246 | if (srs == 0) { |
| 1247 | /* |
| 1248 | * If no shadow set is selected then use the default handler |
| 1249 | * that does normal register saving and a standard interrupt exit |
| 1250 | */ |
| 1251 | |
| 1252 | extern char except_vec_vi, except_vec_vi_lui; |
| 1253 | extern char except_vec_vi_ori, except_vec_vi_end; |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1254 | #ifdef CONFIG_MIPS_MT_SMTC |
| 1255 | /* |
| 1256 | * We need to provide the SMTC vectored interrupt handler |
| 1257 | * not only with the address of the handler, but with the |
| 1258 | * Status.IM bit to be masked before going there. |
| 1259 | */ |
| 1260 | extern char except_vec_vi_mori; |
| 1261 | const int mori_offset = &except_vec_vi_mori - &except_vec_vi; |
| 1262 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1263 | const int handler_len = &except_vec_vi_end - &except_vec_vi; |
| 1264 | const int lui_offset = &except_vec_vi_lui - &except_vec_vi; |
| 1265 | const int ori_offset = &except_vec_vi_ori - &except_vec_vi; |
| 1266 | |
| 1267 | if (handler_len > VECTORSPACING) { |
| 1268 | /* |
| 1269 | * Sigh... panicing won't help as the console |
| 1270 | * is probably not configured :( |
| 1271 | */ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1272 | panic("VECTORSPACING too small"); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1273 | } |
| 1274 | |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1275 | memcpy(b, &except_vec_vi, handler_len); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1276 | #ifdef CONFIG_MIPS_MT_SMTC |
Ralf Baechle | 8e8a52e | 2007-05-31 14:00:19 +0100 | [diff] [blame] | 1277 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
| 1278 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1279 | w = (u32 *)(b + mori_offset); |
| 1280 | *w = (*w & 0xffff0000) | (0x100 << n); |
| 1281 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1282 | w = (u32 *)(b + lui_offset); |
| 1283 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); |
| 1284 | w = (u32 *)(b + ori_offset); |
| 1285 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1286 | local_flush_icache_range((unsigned long)b, |
| 1287 | (unsigned long)(b+handler_len)); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1288 | } |
| 1289 | else { |
| 1290 | /* |
| 1291 | * In other cases jump directly to the interrupt handler |
| 1292 | * |
| 1293 | * It is the handlers responsibility to save registers if required |
| 1294 | * (eg hi/lo) and return from the exception using "eret" |
| 1295 | */ |
| 1296 | w = (u32 *)b; |
| 1297 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ |
| 1298 | *w = 0; |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1299 | local_flush_icache_range((unsigned long)b, |
| 1300 | (unsigned long)(b+8)); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1301 | } |
| 1302 | |
| 1303 | return (void *)old_handler; |
| 1304 | } |
| 1305 | |
Ralf Baechle | ef300e4 | 2007-05-06 18:31:18 +0100 | [diff] [blame] | 1306 | void *set_vi_handler(int n, vi_handler_t addr) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1307 | { |
Ralf Baechle | ff3eab2 | 2006-03-29 14:12:58 +0100 | [diff] [blame] | 1308 | return set_vi_srs_handler(n, addr, 0); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1309 | } |
Ralf Baechle | f41ae0b | 2006-06-05 17:24:46 +0100 | [diff] [blame] | 1310 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1311 | /* |
| 1312 | * This is used by native signal handling |
| 1313 | */ |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1314 | asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); |
| 1315 | asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1316 | |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1317 | extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); |
| 1318 | extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1320 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); |
| 1321 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1322 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1323 | #ifdef CONFIG_SMP |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1324 | static int smp_save_fp_context(struct sigcontext __user *sc) |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1325 | { |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1326 | return raw_cpu_has_fpu |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1327 | ? _save_fp_context(sc) |
| 1328 | : fpu_emulator_save_context(sc); |
| 1329 | } |
| 1330 | |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1331 | static int smp_restore_fp_context(struct sigcontext __user *sc) |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1332 | { |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1333 | return raw_cpu_has_fpu |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1334 | ? _restore_fp_context(sc) |
| 1335 | : fpu_emulator_restore_context(sc); |
| 1336 | } |
| 1337 | #endif |
| 1338 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1339 | static inline void signal_init(void) |
| 1340 | { |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1341 | #ifdef CONFIG_SMP |
| 1342 | /* For now just do the cpu_has_fpu check when the functions are invoked */ |
| 1343 | save_fp_context = smp_save_fp_context; |
| 1344 | restore_fp_context = smp_restore_fp_context; |
| 1345 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | if (cpu_has_fpu) { |
| 1347 | save_fp_context = _save_fp_context; |
| 1348 | restore_fp_context = _restore_fp_context; |
| 1349 | } else { |
| 1350 | save_fp_context = fpu_emulator_save_context; |
| 1351 | restore_fp_context = fpu_emulator_restore_context; |
| 1352 | } |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1353 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | } |
| 1355 | |
| 1356 | #ifdef CONFIG_MIPS32_COMPAT |
| 1357 | |
| 1358 | /* |
| 1359 | * This is used by 32-bit signal stuff on the 64-bit kernel |
| 1360 | */ |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1361 | asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); |
| 1362 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1364 | extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); |
| 1365 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1366 | |
Atsushi Nemoto | 53dc802 | 2007-03-10 01:07:45 +0900 | [diff] [blame] | 1367 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); |
| 1368 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1369 | |
| 1370 | static inline void signal32_init(void) |
| 1371 | { |
| 1372 | if (cpu_has_fpu) { |
| 1373 | save_fp_context32 = _save_fp_context32; |
| 1374 | restore_fp_context32 = _restore_fp_context32; |
| 1375 | } else { |
| 1376 | save_fp_context32 = fpu_emulator_save_context32; |
| 1377 | restore_fp_context32 = fpu_emulator_restore_context32; |
| 1378 | } |
| 1379 | } |
| 1380 | #endif |
| 1381 | |
| 1382 | extern void cpu_cache_init(void); |
| 1383 | extern void tlb_init(void); |
Ralf Baechle | 1d40cfc | 2005-07-15 15:23:23 +0000 | [diff] [blame] | 1384 | extern void flush_tlb_handlers(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1385 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 1386 | /* |
| 1387 | * Timer interrupt |
| 1388 | */ |
| 1389 | int cp0_compare_irq; |
| 1390 | |
| 1391 | /* |
| 1392 | * Performance counter IRQ or -1 if shared with timer |
| 1393 | */ |
| 1394 | int cp0_perfcount_irq; |
| 1395 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); |
| 1396 | |
Chris Dearman | bdc94eb | 2007-10-03 10:43:56 +0100 | [diff] [blame] | 1397 | static int __cpuinitdata noulri; |
| 1398 | |
| 1399 | static int __init ulri_disable(char *s) |
| 1400 | { |
| 1401 | pr_info("Disabling ulri\n"); |
| 1402 | noulri = 1; |
| 1403 | |
| 1404 | return 1; |
| 1405 | } |
| 1406 | __setup("noulri", ulri_disable); |
| 1407 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 1408 | void __cpuinit per_cpu_trap_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1409 | { |
| 1410 | unsigned int cpu = smp_processor_id(); |
| 1411 | unsigned int status_set = ST0_CU0; |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1412 | #ifdef CONFIG_MIPS_MT_SMTC |
| 1413 | int secondaryTC = 0; |
| 1414 | int bootTC = (cpu == 0); |
| 1415 | |
| 1416 | /* |
| 1417 | * Only do per_cpu_trap_init() for first TC of Each VPE. |
| 1418 | * Note that this hack assumes that the SMTC init code |
| 1419 | * assigns TCs consecutively and in ascending order. |
| 1420 | */ |
| 1421 | |
| 1422 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && |
| 1423 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) |
| 1424 | secondaryTC = 1; |
| 1425 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1426 | |
| 1427 | /* |
| 1428 | * Disable coprocessors and select 32-bit or 64-bit addressing |
| 1429 | * and the 16/32 or 32/32 FPR register model. Reset the BEV |
| 1430 | * flag that some firmware may have left set and the TS bit (for |
| 1431 | * IP27). Set XX for ISA IV code to work. |
| 1432 | */ |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 1433 | #ifdef CONFIG_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1434 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
| 1435 | #endif |
| 1436 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) |
| 1437 | status_set |= ST0_XX; |
Chris Dearman | bbaf238 | 2007-12-13 22:42:19 +0000 | [diff] [blame] | 1438 | if (cpu_has_dsp) |
| 1439 | status_set |= ST0_MX; |
| 1440 | |
Ralf Baechle | b38c739 | 2006-02-07 01:20:43 +0000 | [diff] [blame] | 1441 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1442 | status_set); |
| 1443 | |
Ralf Baechle | a369202 | 2007-07-10 17:33:02 +0100 | [diff] [blame] | 1444 | if (cpu_has_mips_r2) { |
| 1445 | unsigned int enable = 0x0000000f; |
| 1446 | |
Chris Dearman | bdc94eb | 2007-10-03 10:43:56 +0100 | [diff] [blame] | 1447 | if (!noulri && cpu_has_userlocal) |
Ralf Baechle | a369202 | 2007-07-10 17:33:02 +0100 | [diff] [blame] | 1448 | enable |= (1 << 29); |
| 1449 | |
| 1450 | write_c0_hwrena(enable); |
| 1451 | } |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1452 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1453 | #ifdef CONFIG_MIPS_MT_SMTC |
| 1454 | if (!secondaryTC) { |
| 1455 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 1456 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1457 | if (cpu_has_veic || cpu_has_vint) { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1458 | write_c0_ebase(ebase); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1459 | /* Setting vector spacing enables EI/VI mode */ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1460 | change_c0_intctl(0x3e0, VECTORSPACING); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1461 | } |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 1462 | if (cpu_has_divec) { |
| 1463 | if (cpu_has_mipsmt) { |
| 1464 | unsigned int vpflags = dvpe(); |
| 1465 | set_c0_cause(CAUSEF_IV); |
| 1466 | evpe(vpflags); |
| 1467 | } else |
| 1468 | set_c0_cause(CAUSEF_IV); |
| 1469 | } |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 1470 | |
| 1471 | /* |
| 1472 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: |
| 1473 | * |
| 1474 | * o read IntCtl.IPTI to determine the timer interrupt |
| 1475 | * o read IntCtl.IPPCI to determine the performance counter interrupt |
| 1476 | */ |
| 1477 | if (cpu_has_mips_r2) { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1478 | cp0_compare_irq = (read_c0_intctl() >> 29) & 7; |
| 1479 | cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; |
Chris Dearman | c3e838a | 2007-06-21 12:59:57 +0100 | [diff] [blame] | 1480 | if (cp0_perfcount_irq == cp0_compare_irq) |
| 1481 | cp0_perfcount_irq = -1; |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 1482 | } else { |
| 1483 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; |
Chris Dearman | c3e838a | 2007-06-21 12:59:57 +0100 | [diff] [blame] | 1484 | cp0_perfcount_irq = -1; |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 1485 | } |
| 1486 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1487 | #ifdef CONFIG_MIPS_MT_SMTC |
| 1488 | } |
| 1489 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1490 | |
| 1491 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; |
| 1492 | TLBMISS_HANDLER_SETUP(); |
| 1493 | |
| 1494 | atomic_inc(&init_mm.mm_count); |
| 1495 | current->active_mm = &init_mm; |
| 1496 | BUG_ON(current->mm); |
| 1497 | enter_lazy_tlb(&init_mm, current); |
| 1498 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1499 | #ifdef CONFIG_MIPS_MT_SMTC |
| 1500 | if (bootTC) { |
| 1501 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 1502 | cpu_cache_init(); |
| 1503 | tlb_init(); |
| 1504 | #ifdef CONFIG_MIPS_MT_SMTC |
Ralf Baechle | 6a05888 | 2007-05-31 14:03:45 +0100 | [diff] [blame] | 1505 | } else if (!secondaryTC) { |
| 1506 | /* |
| 1507 | * First TC in non-boot VPE must do subset of tlb_init() |
| 1508 | * for MMU countrol registers. |
| 1509 | */ |
| 1510 | write_c0_pagemask(PM_DEFAULT_MASK); |
| 1511 | write_c0_wired(0); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1512 | } |
| 1513 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1514 | } |
| 1515 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1516 | /* Install CPU exception handler */ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1517 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1518 | { |
| 1519 | memcpy((void *)(ebase + offset), addr, size); |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1520 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1521 | } |
| 1522 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 1523 | static char panic_null_cerr[] __cpuinitdata = |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1524 | "Trying to set NULL cache error exception handler"; |
| 1525 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1526 | /* Install uncached CPU exception handler */ |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 1527 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
| 1528 | unsigned long size) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1529 | { |
| 1530 | #ifdef CONFIG_32BIT |
| 1531 | unsigned long uncached_ebase = KSEG1ADDR(ebase); |
| 1532 | #endif |
| 1533 | #ifdef CONFIG_64BIT |
| 1534 | unsigned long uncached_ebase = TO_UNCAC(ebase); |
| 1535 | #endif |
| 1536 | |
Ralf Baechle | 641e97f | 2007-10-11 23:46:05 +0100 | [diff] [blame] | 1537 | if (!addr) |
| 1538 | panic(panic_null_cerr); |
| 1539 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1540 | memcpy((void *)(uncached_ebase + offset), addr, size); |
| 1541 | } |
| 1542 | |
Atsushi Nemoto | 5b10496 | 2006-09-11 17:50:29 +0900 | [diff] [blame] | 1543 | static int __initdata rdhwr_noopt; |
| 1544 | static int __init set_rdhwr_noopt(char *str) |
| 1545 | { |
| 1546 | rdhwr_noopt = 1; |
| 1547 | return 1; |
| 1548 | } |
| 1549 | |
| 1550 | __setup("rdhwr_noopt", set_rdhwr_noopt); |
| 1551 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1552 | void __init trap_init(void) |
| 1553 | { |
| 1554 | extern char except_vec3_generic, except_vec3_r4000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1555 | extern char except_vec4; |
| 1556 | unsigned long i; |
| 1557 | |
Jason Wessel | 8854700 | 2008-07-29 15:58:53 -0500 | [diff] [blame] | 1558 | #if defined(CONFIG_KGDB) |
| 1559 | if (kgdb_early_setup) |
| 1560 | return; /* Already done */ |
| 1561 | #endif |
| 1562 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1563 | if (cpu_has_veic || cpu_has_vint) |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1564 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1565 | else |
| 1566 | ebase = CAC_BASE; |
| 1567 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | per_cpu_trap_init(); |
| 1569 | |
| 1570 | /* |
| 1571 | * Copy the generic exception handlers to their final destination. |
| 1572 | * This will be overriden later as suitable for a particular |
| 1573 | * configuration. |
| 1574 | */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1575 | set_handler(0x180, &except_vec3_generic, 0x80); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1576 | |
| 1577 | /* |
| 1578 | * Setup default vectors |
| 1579 | */ |
| 1580 | for (i = 0; i <= 31; i++) |
| 1581 | set_except_vector(i, handle_reserved); |
| 1582 | |
| 1583 | /* |
| 1584 | * Copy the EJTAG debug exception vector handler code to it's final |
| 1585 | * destination. |
| 1586 | */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1587 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1588 | board_ejtag_handler_setup(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | |
| 1590 | /* |
| 1591 | * Only some CPUs have the watch exceptions. |
| 1592 | */ |
| 1593 | if (cpu_has_watch) |
| 1594 | set_except_vector(23, handle_watch); |
| 1595 | |
| 1596 | /* |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1597 | * Initialise interrupt handlers |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1599 | if (cpu_has_veic || cpu_has_vint) { |
| 1600 | int nvec = cpu_has_veic ? 64 : 8; |
| 1601 | for (i = 0; i < nvec; i++) |
Ralf Baechle | ff3eab2 | 2006-03-29 14:12:58 +0100 | [diff] [blame] | 1602 | set_vi_handler(i, NULL); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1603 | } |
| 1604 | else if (cpu_has_divec) |
| 1605 | set_handler(0x200, &except_vec4, 0x8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1606 | |
| 1607 | /* |
| 1608 | * Some CPUs can enable/disable for cache parity detection, but does |
| 1609 | * it different ways. |
| 1610 | */ |
| 1611 | parity_protection_init(); |
| 1612 | |
| 1613 | /* |
| 1614 | * The Data Bus Errors / Instruction Bus Errors are signaled |
| 1615 | * by external hardware. Therefore these two exceptions |
| 1616 | * may have board specific handlers. |
| 1617 | */ |
| 1618 | if (board_be_init) |
| 1619 | board_be_init(); |
| 1620 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 1621 | set_except_vector(0, handle_int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1622 | set_except_vector(1, handle_tlbm); |
| 1623 | set_except_vector(2, handle_tlbl); |
| 1624 | set_except_vector(3, handle_tlbs); |
| 1625 | |
| 1626 | set_except_vector(4, handle_adel); |
| 1627 | set_except_vector(5, handle_ades); |
| 1628 | |
| 1629 | set_except_vector(6, handle_ibe); |
| 1630 | set_except_vector(7, handle_dbe); |
| 1631 | |
| 1632 | set_except_vector(8, handle_sys); |
| 1633 | set_except_vector(9, handle_bp); |
Atsushi Nemoto | 5b10496 | 2006-09-11 17:50:29 +0900 | [diff] [blame] | 1634 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
| 1635 | (cpu_has_vtag_icache ? |
| 1636 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | set_except_vector(11, handle_cpu); |
| 1638 | set_except_vector(12, handle_ov); |
| 1639 | set_except_vector(13, handle_tr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1640 | |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1641 | if (current_cpu_type() == CPU_R6000 || |
| 1642 | current_cpu_type() == CPU_R6000A) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | /* |
| 1644 | * The R6000 is the only R-series CPU that features a machine |
| 1645 | * check exception (similar to the R4000 cache error) and |
| 1646 | * unaligned ldc1/sdc1 exception. The handlers have not been |
| 1647 | * written yet. Well, anyway there is no R6000 machine on the |
| 1648 | * current list of targets for Linux/MIPS. |
| 1649 | * (Duh, crap, there is someone with a triple R6k machine) |
| 1650 | */ |
| 1651 | //set_except_vector(14, handle_mc); |
| 1652 | //set_except_vector(15, handle_ndc); |
| 1653 | } |
| 1654 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 1655 | |
| 1656 | if (board_nmi_handler_setup) |
| 1657 | board_nmi_handler_setup(); |
| 1658 | |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 1659 | if (cpu_has_fpu && !cpu_has_nofpuex) |
| 1660 | set_except_vector(15, handle_fpe); |
| 1661 | |
| 1662 | set_except_vector(22, handle_mdmx); |
| 1663 | |
| 1664 | if (cpu_has_mcheck) |
| 1665 | set_except_vector(24, handle_mcheck); |
| 1666 | |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 1667 | if (cpu_has_mipsmt) |
| 1668 | set_except_vector(25, handle_mt); |
| 1669 | |
Chris Dearman | acaec42 | 2007-05-24 22:30:18 +0100 | [diff] [blame] | 1670 | set_except_vector(26, handle_dsp); |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 1671 | |
| 1672 | if (cpu_has_vce) |
| 1673 | /* Special exception: R4[04]00 uses also the divec space. */ |
| 1674 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); |
| 1675 | else if (cpu_has_4kex) |
| 1676 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); |
| 1677 | else |
| 1678 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); |
| 1679 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1680 | signal_init(); |
| 1681 | #ifdef CONFIG_MIPS32_COMPAT |
| 1682 | signal32_init(); |
| 1683 | #endif |
| 1684 | |
Thomas Bogendoerfer | e0cee3e | 2008-08-04 20:53:57 +0200 | [diff] [blame] | 1685 | local_flush_icache_range(ebase, ebase + 0x400); |
Ralf Baechle | 1d40cfc | 2005-07-15 15:23:23 +0000 | [diff] [blame] | 1686 | flush_tlb_handlers(); |
Thomas Bogendoerfer | 0510617 | 2008-08-04 19:44:34 +0200 | [diff] [blame] | 1687 | |
| 1688 | sort_extable(__start___dbe_table, __stop___dbe_table); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1689 | } |