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Kristian Høgsbergc781c062007-05-07 20:33:32 -04001/*
2 * Driver for OHCI 1394 controllers
Kristian Høgsberged568912006-12-19 19:58:35 -05003 *
Kristian Høgsberged568912006-12-19 19:58:35 -05004 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/poll.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080028#include <linux/dma-mapping.h>
Al Virofaa2fb42007-05-15 20:36:10 +010029#include <linux/mm.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080030
Kristian Høgsberged568912006-12-19 19:58:35 -050031#include <asm/uaccess.h>
32#include <asm/semaphore.h>
Stefan Richteree71c2f2007-08-25 14:08:19 +020033#include <asm/system.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050034
35#include "fw-transaction.h"
36#include "fw-ohci.h"
37
Kristian Høgsberga77754a2007-05-07 20:33:35 -040038#define DESCRIPTOR_OUTPUT_MORE 0
39#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
40#define DESCRIPTOR_INPUT_MORE (2 << 12)
41#define DESCRIPTOR_INPUT_LAST (3 << 12)
42#define DESCRIPTOR_STATUS (1 << 11)
43#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
44#define DESCRIPTOR_PING (1 << 7)
45#define DESCRIPTOR_YY (1 << 6)
46#define DESCRIPTOR_NO_IRQ (0 << 4)
47#define DESCRIPTOR_IRQ_ERROR (1 << 4)
48#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
49#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
50#define DESCRIPTOR_WAIT (3 << 0)
Kristian Høgsberged568912006-12-19 19:58:35 -050051
52struct descriptor {
53 __le16 req_count;
54 __le16 control;
55 __le32 data_address;
56 __le32 branch_address;
57 __le16 res_count;
58 __le16 transfer_status;
59} __attribute__((aligned(16)));
60
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -050061struct db_descriptor {
62 __le16 first_size;
63 __le16 control;
64 __le16 second_req_count;
65 __le16 first_req_count;
66 __le32 branch_address;
67 __le16 second_res_count;
68 __le16 first_res_count;
69 __le32 reserved0;
70 __le32 first_buffer;
71 __le32 second_buffer;
72 __le32 reserved1;
73} __attribute__((aligned(16)));
74
Kristian Høgsberga77754a2007-05-07 20:33:35 -040075#define CONTROL_SET(regs) (regs)
76#define CONTROL_CLEAR(regs) ((regs) + 4)
77#define COMMAND_PTR(regs) ((regs) + 12)
78#define CONTEXT_MATCH(regs) ((regs) + 16)
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050079
Kristian Høgsberg32b46092007-02-06 14:49:30 -050080struct ar_buffer {
81 struct descriptor descriptor;
82 struct ar_buffer *next;
83 __le32 data[0];
84};
85
Kristian Høgsberged568912006-12-19 19:58:35 -050086struct ar_context {
87 struct fw_ohci *ohci;
Kristian Høgsberg32b46092007-02-06 14:49:30 -050088 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
90 void *pointer;
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050091 u32 regs;
Kristian Høgsberged568912006-12-19 19:58:35 -050092 struct tasklet_struct tasklet;
93};
94
Kristian Høgsberg30200732007-02-16 17:34:39 -050095struct context;
96
97typedef int (*descriptor_callback_t)(struct context *ctx,
98 struct descriptor *d,
99 struct descriptor *last);
100struct context {
Stefan Richter373b2ed2007-03-04 14:45:18 +0100101 struct fw_ohci *ohci;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500102 u32 regs;
Stefan Richter373b2ed2007-03-04 14:45:18 +0100103
Kristian Høgsberg30200732007-02-16 17:34:39 -0500104 struct descriptor *buffer;
105 dma_addr_t buffer_bus;
106 size_t buffer_size;
107 struct descriptor *head_descriptor;
108 struct descriptor *tail_descriptor;
109 struct descriptor *tail_descriptor_last;
110 struct descriptor *prev_descriptor;
111
112 descriptor_callback_t callback;
113
Stefan Richter373b2ed2007-03-04 14:45:18 +0100114 struct tasklet_struct tasklet;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500115};
Kristian Høgsberg30200732007-02-16 17:34:39 -0500116
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400117#define IT_HEADER_SY(v) ((v) << 0)
118#define IT_HEADER_TCODE(v) ((v) << 4)
119#define IT_HEADER_CHANNEL(v) ((v) << 8)
120#define IT_HEADER_TAG(v) ((v) << 14)
121#define IT_HEADER_SPEED(v) ((v) << 16)
122#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
Kristian Høgsberged568912006-12-19 19:58:35 -0500123
124struct iso_context {
125 struct fw_iso_context base;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500126 struct context context;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500127 void *header;
128 size_t header_length;
Kristian Høgsberged568912006-12-19 19:58:35 -0500129};
130
131#define CONFIG_ROM_SIZE 1024
132
133struct fw_ohci {
134 struct fw_card card;
135
Kristian Høgsberge364cf42007-02-16 17:34:49 -0500136 u32 version;
Kristian Høgsberged568912006-12-19 19:58:35 -0500137 __iomem char *registers;
138 dma_addr_t self_id_bus;
139 __le32 *self_id_cpu;
140 struct tasklet_struct bus_reset_tasklet;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500141 int node_id;
Kristian Høgsberged568912006-12-19 19:58:35 -0500142 int generation;
143 int request_generation;
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -0500144 u32 bus_seconds;
Kristian Høgsberged568912006-12-19 19:58:35 -0500145
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400146 /*
147 * Spinlock for accessing fw_ohci data. Never call out of
148 * this driver with this lock held.
149 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500150 spinlock_t lock;
151 u32 self_id_buffer[512];
152
153 /* Config rom buffers */
154 __be32 *config_rom;
155 dma_addr_t config_rom_bus;
156 __be32 *next_config_rom;
157 dma_addr_t next_config_rom_bus;
158 u32 next_header;
159
160 struct ar_context ar_request_ctx;
161 struct ar_context ar_response_ctx;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500162 struct context at_request_ctx;
163 struct context at_response_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -0500164
165 u32 it_context_mask;
166 struct iso_context *it_context_list;
167 u32 ir_context_mask;
168 struct iso_context *ir_context_list;
169};
170
Adrian Bunk95688e92007-01-22 19:17:37 +0100171static inline struct fw_ohci *fw_ohci(struct fw_card *card)
Kristian Høgsberged568912006-12-19 19:58:35 -0500172{
173 return container_of(card, struct fw_ohci, card);
174}
175
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500176#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
177#define IR_CONTEXT_BUFFER_FILL 0x80000000
178#define IR_CONTEXT_ISOCH_HEADER 0x40000000
179#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
180#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
181#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
Kristian Høgsberged568912006-12-19 19:58:35 -0500182
183#define CONTEXT_RUN 0x8000
184#define CONTEXT_WAKE 0x1000
185#define CONTEXT_DEAD 0x0800
186#define CONTEXT_ACTIVE 0x0400
187
188#define OHCI1394_MAX_AT_REQ_RETRIES 0x2
189#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
190#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
191
192#define FW_OHCI_MAJOR 240
193#define OHCI1394_REGISTER_SIZE 0x800
194#define OHCI_LOOP_COUNT 500
195#define OHCI1394_PCI_HCI_Control 0x40
196#define SELF_ID_BUF_SIZE 0x800
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500197#define OHCI_TCODE_PHY_PACKET 0x0e
Kristian Høgsberge364cf42007-02-16 17:34:49 -0500198#define OHCI_VERSION_1_1 0x010010
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500199#define ISO_BUFFER_SIZE (64 * 1024)
200#define AT_BUFFER_SIZE 4096
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500201
Kristian Høgsberged568912006-12-19 19:58:35 -0500202static char ohci_driver_name[] = KBUILD_MODNAME;
203
Adrian Bunk95688e92007-01-22 19:17:37 +0100204static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
Kristian Høgsberged568912006-12-19 19:58:35 -0500205{
206 writel(data, ohci->registers + offset);
207}
208
Adrian Bunk95688e92007-01-22 19:17:37 +0100209static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
Kristian Høgsberged568912006-12-19 19:58:35 -0500210{
211 return readl(ohci->registers + offset);
212}
213
Adrian Bunk95688e92007-01-22 19:17:37 +0100214static inline void flush_writes(const struct fw_ohci *ohci)
Kristian Høgsberged568912006-12-19 19:58:35 -0500215{
216 /* Do a dummy read to flush writes. */
217 reg_read(ohci, OHCI1394_Version);
218}
219
220static int
221ohci_update_phy_reg(struct fw_card *card, int addr,
222 int clear_bits, int set_bits)
223{
224 struct fw_ohci *ohci = fw_ohci(card);
225 u32 val, old;
226
227 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
Stefan Richter362e9012007-07-12 22:24:19 +0200228 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -0500229 msleep(2);
230 val = reg_read(ohci, OHCI1394_PhyControl);
231 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
232 fw_error("failed to set phy reg bits.\n");
233 return -EBUSY;
234 }
235
236 old = OHCI1394_PhyControl_ReadData(val);
237 old = (old & ~clear_bits) | set_bits;
238 reg_write(ohci, OHCI1394_PhyControl,
239 OHCI1394_PhyControl_Write(addr, old));
240
241 return 0;
242}
243
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500244static int ar_context_add_page(struct ar_context *ctx)
Kristian Høgsberged568912006-12-19 19:58:35 -0500245{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500246 struct device *dev = ctx->ohci->card.device;
247 struct ar_buffer *ab;
248 dma_addr_t ab_bus;
249 size_t offset;
250
251 ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
252 if (ab == NULL)
253 return -ENOMEM;
254
255 ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
256 if (dma_mapping_error(ab_bus)) {
257 free_page((unsigned long) ab);
258 return -ENOMEM;
259 }
260
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400261 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400262 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
263 DESCRIPTOR_STATUS |
264 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500265 offset = offsetof(struct ar_buffer, data);
266 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
267 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
268 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
269 ab->descriptor.branch_address = 0;
270
271 dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
272
Kristian Høgsbergec839e42007-05-22 18:55:48 -0400273 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500274 ctx->last_buffer->next = ab;
275 ctx->last_buffer = ab;
276
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400277 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberged568912006-12-19 19:58:35 -0500278 flush_writes(ctx->ohci);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500279
280 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -0500281}
282
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500283static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
Kristian Høgsberged568912006-12-19 19:58:35 -0500284{
Kristian Høgsberged568912006-12-19 19:58:35 -0500285 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500286 struct fw_packet p;
287 u32 status, length, tcode;
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500288
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500289 p.header[0] = le32_to_cpu(buffer[0]);
290 p.header[1] = le32_to_cpu(buffer[1]);
291 p.header[2] = le32_to_cpu(buffer[2]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500292
293 tcode = (p.header[0] >> 4) & 0x0f;
294 switch (tcode) {
295 case TCODE_WRITE_QUADLET_REQUEST:
296 case TCODE_READ_QUADLET_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500297 p.header[3] = (__force __u32) buffer[3];
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500298 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500299 p.payload_length = 0;
300 break;
301
302 case TCODE_READ_BLOCK_REQUEST :
303 p.header[3] = le32_to_cpu(buffer[3]);
304 p.header_length = 16;
305 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500306 break;
307
308 case TCODE_WRITE_BLOCK_REQUEST:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500309 case TCODE_READ_BLOCK_RESPONSE:
310 case TCODE_LOCK_REQUEST:
311 case TCODE_LOCK_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500312 p.header[3] = le32_to_cpu(buffer[3]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500313 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500314 p.payload_length = p.header[3] >> 16;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500315 break;
316
317 case TCODE_WRITE_RESPONSE:
318 case TCODE_READ_QUADLET_REQUEST:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500319 case OHCI_TCODE_PHY_PACKET:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500320 p.header_length = 12;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500321 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500322 break;
323 }
324
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500325 p.payload = (void *) buffer + p.header_length;
326
327 /* FIXME: What to do about evt_* errors? */
328 length = (p.header_length + p.payload_length + 3) / 4;
329 status = le32_to_cpu(buffer[length]);
330
331 p.ack = ((status >> 16) & 0x1f) - 16;
332 p.speed = (status >> 21) & 0x7;
333 p.timestamp = status & 0xffff;
334 p.generation = ohci->request_generation;
Kristian Høgsberged568912006-12-19 19:58:35 -0500335
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400336 /*
337 * The OHCI bus reset handler synthesizes a phy packet with
Kristian Høgsberged568912006-12-19 19:58:35 -0500338 * the new generation number when a bus reset happens (see
339 * section 8.4.2.3). This helps us determine when a request
340 * was received and make sure we send the response in the same
341 * generation. We only need this for requests; for responses
342 * we use the unique tlabel for finding the matching
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400343 * request.
344 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500345
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500346 if (p.ack + 16 == 0x09)
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500347 ohci->request_generation = (buffer[2] >> 16) & 0xff;
Kristian Høgsberged568912006-12-19 19:58:35 -0500348 else if (ctx == &ohci->ar_request_ctx)
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500349 fw_core_handle_request(&ohci->card, &p);
Kristian Høgsberged568912006-12-19 19:58:35 -0500350 else
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500351 fw_core_handle_response(&ohci->card, &p);
Kristian Høgsberged568912006-12-19 19:58:35 -0500352
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500353 return buffer + length + 1;
354}
Kristian Høgsberged568912006-12-19 19:58:35 -0500355
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500356static void ar_context_tasklet(unsigned long data)
357{
358 struct ar_context *ctx = (struct ar_context *)data;
359 struct fw_ohci *ohci = ctx->ohci;
360 struct ar_buffer *ab;
361 struct descriptor *d;
362 void *buffer, *end;
Kristian Høgsberged568912006-12-19 19:58:35 -0500363
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500364 ab = ctx->current_buffer;
365 d = &ab->descriptor;
Kristian Høgsberged568912006-12-19 19:58:35 -0500366
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500367 if (d->res_count == 0) {
368 size_t size, rest, offset;
369
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400370 /*
371 * This descriptor is finished and we may have a
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500372 * packet split across this and the next buffer. We
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400373 * reuse the page for reassembling the split packet.
374 */
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500375
376 offset = offsetof(struct ar_buffer, data);
377 dma_unmap_single(ohci->card.device,
Stefan Richter0a9972b2007-06-23 20:28:17 +0200378 le32_to_cpu(ab->descriptor.data_address) - offset,
379 PAGE_SIZE, DMA_BIDIRECTIONAL);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500380
381 buffer = ab;
382 ab = ab->next;
383 d = &ab->descriptor;
384 size = buffer + PAGE_SIZE - ctx->pointer;
385 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
386 memmove(buffer, ctx->pointer, size);
387 memcpy(buffer + size, ab->data, rest);
388 ctx->current_buffer = ab;
389 ctx->pointer = (void *) ab->data + rest;
390 end = buffer + size + rest;
391
392 while (buffer < end)
393 buffer = handle_ar_packet(ctx, buffer);
394
395 free_page((unsigned long)buffer);
396 ar_context_add_page(ctx);
397 } else {
398 buffer = ctx->pointer;
399 ctx->pointer = end =
400 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
401
402 while (buffer < end)
403 buffer = handle_ar_packet(ctx, buffer);
404 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500405}
406
407static int
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500408ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
Kristian Høgsberged568912006-12-19 19:58:35 -0500409{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500410 struct ar_buffer ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500411
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500412 ctx->regs = regs;
413 ctx->ohci = ohci;
414 ctx->last_buffer = &ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500415 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
416
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500417 ar_context_add_page(ctx);
418 ar_context_add_page(ctx);
419 ctx->current_buffer = ab.next;
420 ctx->pointer = ctx->current_buffer->data;
421
Kristian Høgsberg2aef4692007-05-30 19:06:35 -0400422 return 0;
423}
424
425static void ar_context_run(struct ar_context *ctx)
426{
427 struct ar_buffer *ab = ctx->current_buffer;
428 dma_addr_t ab_bus;
429 size_t offset;
430
431 offset = offsetof(struct ar_buffer, data);
Stefan Richter0a9972b2007-06-23 20:28:17 +0200432 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -0400433
434 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400435 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500436 flush_writes(ctx->ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -0500437}
Stefan Richter373b2ed2007-03-04 14:45:18 +0100438
Kristian Høgsberg30200732007-02-16 17:34:39 -0500439static void context_tasklet(unsigned long data)
440{
441 struct context *ctx = (struct context *) data;
442 struct fw_ohci *ohci = ctx->ohci;
443 struct descriptor *d, *last;
444 u32 address;
445 int z;
446
447 dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
448 ctx->buffer_size, DMA_TO_DEVICE);
449
450 d = ctx->tail_descriptor;
451 last = ctx->tail_descriptor_last;
452
453 while (last->branch_address != 0) {
454 address = le32_to_cpu(last->branch_address);
455 z = address & 0xf;
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400456 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500457 last = (z == 2) ? d : d + z - 1;
458
459 if (!ctx->callback(ctx, d, last))
460 break;
461
462 ctx->tail_descriptor = d;
463 ctx->tail_descriptor_last = last;
464 }
465}
466
467static int
468context_init(struct context *ctx, struct fw_ohci *ohci,
469 size_t buffer_size, u32 regs,
470 descriptor_callback_t callback)
471{
472 ctx->ohci = ohci;
473 ctx->regs = regs;
474 ctx->buffer_size = buffer_size;
475 ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
476 if (ctx->buffer == NULL)
477 return -ENOMEM;
478
479 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
480 ctx->callback = callback;
481
482 ctx->buffer_bus =
483 dma_map_single(ohci->card.device, ctx->buffer,
484 buffer_size, DMA_TO_DEVICE);
485 if (dma_mapping_error(ctx->buffer_bus)) {
486 kfree(ctx->buffer);
487 return -ENOMEM;
488 }
489
490 ctx->head_descriptor = ctx->buffer;
491 ctx->prev_descriptor = ctx->buffer;
492 ctx->tail_descriptor = ctx->buffer;
493 ctx->tail_descriptor_last = ctx->buffer;
494
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400495 /*
496 * We put a dummy descriptor in the buffer that has a NULL
Kristian Høgsberg30200732007-02-16 17:34:39 -0500497 * branch address and looks like it's been sent. That way we
498 * have a descriptor to append DMA programs to. Also, the
499 * ring buffer invariant is that it always has at least one
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400500 * element so that head == tail means buffer full.
501 */
Kristian Høgsberg30200732007-02-16 17:34:39 -0500502
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400503 memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400504 ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500505 ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
506 ctx->head_descriptor++;
507
508 return 0;
509}
510
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500511static void
Kristian Høgsberg30200732007-02-16 17:34:39 -0500512context_release(struct context *ctx)
513{
514 struct fw_card *card = &ctx->ohci->card;
515
516 dma_unmap_single(card->device, ctx->buffer_bus,
517 ctx->buffer_size, DMA_TO_DEVICE);
518 kfree(ctx->buffer);
519}
520
521static struct descriptor *
522context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
523{
524 struct descriptor *d, *tail, *end;
525
526 d = ctx->head_descriptor;
527 tail = ctx->tail_descriptor;
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400528 end = ctx->buffer + ctx->buffer_size / sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500529
530 if (d + z <= tail) {
531 goto has_space;
532 } else if (d > tail && d + z <= end) {
533 goto has_space;
534 } else if (d > tail && ctx->buffer + z <= tail) {
535 d = ctx->buffer;
536 goto has_space;
537 }
538
539 return NULL;
540
541 has_space:
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400542 memset(d, 0, z * sizeof(*d));
543 *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500544
545 return d;
546}
547
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500548static void context_run(struct context *ctx, u32 extra)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500549{
550 struct fw_ohci *ohci = ctx->ohci;
551
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400552 reg_write(ohci, COMMAND_PTR(ctx->regs),
Kristian Høgsberg30200732007-02-16 17:34:39 -0500553 le32_to_cpu(ctx->tail_descriptor_last->branch_address));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400554 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
555 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500556 flush_writes(ohci);
557}
558
559static void context_append(struct context *ctx,
560 struct descriptor *d, int z, int extra)
561{
562 dma_addr_t d_bus;
563
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400564 d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500565
566 ctx->head_descriptor = d + z + extra;
567 ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
568 ctx->prev_descriptor = z == 2 ? d : d + z - 1;
569
570 dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
571 ctx->buffer_size, DMA_TO_DEVICE);
572
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400573 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500574 flush_writes(ctx->ohci);
575}
576
577static void context_stop(struct context *ctx)
578{
579 u32 reg;
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500580 int i;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500581
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400582 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500583 flush_writes(ctx->ohci);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500584
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500585 for (i = 0; i < 10; i++) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400586 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500587 if ((reg & CONTEXT_ACTIVE) == 0)
588 break;
589
590 fw_notify("context_stop: still active (0x%08x)\n", reg);
Stefan Richterb980f5a2007-07-12 22:25:14 +0200591 mdelay(1);
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500592 }
Kristian Høgsberg30200732007-02-16 17:34:39 -0500593}
Kristian Høgsberged568912006-12-19 19:58:35 -0500594
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500595struct driver_data {
Kristian Høgsberged568912006-12-19 19:58:35 -0500596 struct fw_packet *packet;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500597};
598
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400599/*
600 * This function apppends a packet to the DMA queue for transmission.
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500601 * Must always be called with the ochi->lock held to ensure proper
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400602 * generation handling and locking around packet queue manipulation.
603 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500604static int
605at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
606{
Kristian Høgsberged568912006-12-19 19:58:35 -0500607 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500608 dma_addr_t d_bus, payload_bus;
609 struct driver_data *driver_data;
610 struct descriptor *d, *last;
611 __le32 *header;
Kristian Høgsberged568912006-12-19 19:58:35 -0500612 int z, tcode;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500613 u32 reg;
Kristian Høgsberged568912006-12-19 19:58:35 -0500614
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500615 d = context_get_descriptors(ctx, 4, &d_bus);
616 if (d == NULL) {
617 packet->ack = RCODE_SEND_ERROR;
618 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -0500619 }
620
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400621 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500622 d[0].res_count = cpu_to_le16(packet->timestamp);
623
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400624 /*
625 * The DMA format for asyncronous link packets is different
Kristian Høgsberged568912006-12-19 19:58:35 -0500626 * from the IEEE1394 layout, so shift the fields around
627 * accordingly. If header_length is 8, it's a PHY packet, to
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400628 * which we need to prepend an extra quadlet.
629 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500630
631 header = (__le32 *) &d[1];
Kristian Høgsberged568912006-12-19 19:58:35 -0500632 if (packet->header_length > 8) {
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500633 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
634 (packet->speed << 16));
635 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
636 (packet->header[0] & 0xffff0000));
637 header[2] = cpu_to_le32(packet->header[2]);
Kristian Høgsberged568912006-12-19 19:58:35 -0500638
639 tcode = (packet->header[0] >> 4) & 0x0f;
640 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500641 header[3] = cpu_to_le32(packet->header[3]);
Kristian Høgsberged568912006-12-19 19:58:35 -0500642 else
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500643 header[3] = (__force __le32) packet->header[3];
644
645 d[0].req_count = cpu_to_le16(packet->header_length);
Kristian Høgsberged568912006-12-19 19:58:35 -0500646 } else {
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500647 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
648 (packet->speed << 16));
649 header[1] = cpu_to_le32(packet->header[0]);
650 header[2] = cpu_to_le32(packet->header[1]);
651 d[0].req_count = cpu_to_le16(12);
Kristian Høgsberged568912006-12-19 19:58:35 -0500652 }
653
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500654 driver_data = (struct driver_data *) &d[3];
655 driver_data->packet = packet;
Kristian Høgsberg20d11672007-03-26 19:18:19 -0400656 packet->driver_data = driver_data;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500657
658 if (packet->payload_length > 0) {
659 payload_bus =
660 dma_map_single(ohci->card.device, packet->payload,
661 packet->payload_length, DMA_TO_DEVICE);
662 if (dma_mapping_error(payload_bus)) {
663 packet->ack = RCODE_SEND_ERROR;
664 return -1;
665 }
666
667 d[2].req_count = cpu_to_le16(packet->payload_length);
668 d[2].data_address = cpu_to_le32(payload_bus);
669 last = &d[2];
670 z = 3;
671 } else {
672 last = &d[0];
673 z = 2;
674 }
675
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400676 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
677 DESCRIPTOR_IRQ_ALWAYS |
678 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500679
Kristian Høgsberged568912006-12-19 19:58:35 -0500680 /* FIXME: Document how the locking works. */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500681 if (ohci->generation != packet->generation) {
682 packet->ack = RCODE_GENERATION;
683 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -0500684 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500685
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500686 context_append(ctx, d, z, 4 - z);
Kristian Høgsberged568912006-12-19 19:58:35 -0500687
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500688 /* If the context isn't already running, start it up. */
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400689 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
Kristian Høgsberg053b3082007-04-10 18:11:17 -0400690 if ((reg & CONTEXT_RUN) == 0)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500691 context_run(ctx, 0);
Kristian Høgsberged568912006-12-19 19:58:35 -0500692
693 return 0;
694}
695
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500696static int handle_at_packet(struct context *context,
697 struct descriptor *d,
698 struct descriptor *last)
699{
700 struct driver_data *driver_data;
701 struct fw_packet *packet;
702 struct fw_ohci *ohci = context->ohci;
703 dma_addr_t payload_bus;
704 int evt;
705
706 if (last->transfer_status == 0)
707 /* This descriptor isn't done yet, stop iteration. */
708 return 0;
709
710 driver_data = (struct driver_data *) &d[3];
711 packet = driver_data->packet;
712 if (packet == NULL)
713 /* This packet was cancelled, just continue. */
714 return 1;
715
716 payload_bus = le32_to_cpu(last->data_address);
717 if (payload_bus != 0)
718 dma_unmap_single(ohci->card.device, payload_bus,
719 packet->payload_length, DMA_TO_DEVICE);
720
721 evt = le16_to_cpu(last->transfer_status) & 0x1f;
722 packet->timestamp = le16_to_cpu(last->res_count);
723
724 switch (evt) {
725 case OHCI1394_evt_timeout:
726 /* Async response transmit timed out. */
727 packet->ack = RCODE_CANCELLED;
728 break;
729
730 case OHCI1394_evt_flushed:
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400731 /*
732 * The packet was flushed should give same error as
733 * when we try to use a stale generation count.
734 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500735 packet->ack = RCODE_GENERATION;
736 break;
737
738 case OHCI1394_evt_missing_ack:
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400739 /*
740 * Using a valid (current) generation count, but the
741 * node is not on the bus or not sending acks.
742 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500743 packet->ack = RCODE_NO_ACK;
744 break;
745
746 case ACK_COMPLETE + 0x10:
747 case ACK_PENDING + 0x10:
748 case ACK_BUSY_X + 0x10:
749 case ACK_BUSY_A + 0x10:
750 case ACK_BUSY_B + 0x10:
751 case ACK_DATA_ERROR + 0x10:
752 case ACK_TYPE_ERROR + 0x10:
753 packet->ack = evt - 0x10;
754 break;
755
756 default:
757 packet->ack = RCODE_SEND_ERROR;
758 break;
759 }
760
761 packet->callback(packet, &ohci->card, packet->ack);
762
763 return 1;
764}
765
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400766#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
767#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
768#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
769#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
770#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500771
772static void
773handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
774{
775 struct fw_packet response;
776 int tcode, length, i;
777
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400778 tcode = HEADER_GET_TCODE(packet->header[0]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500779 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400780 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500781 else
782 length = 4;
783
784 i = csr - CSR_CONFIG_ROM;
785 if (i + length > CONFIG_ROM_SIZE) {
786 fw_fill_response(&response, packet->header,
787 RCODE_ADDRESS_ERROR, NULL, 0);
788 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
789 fw_fill_response(&response, packet->header,
790 RCODE_TYPE_ERROR, NULL, 0);
791 } else {
792 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
793 (void *) ohci->config_rom + i, length);
794 }
795
796 fw_core_handle_response(&ohci->card, &response);
797}
798
799static void
800handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
801{
802 struct fw_packet response;
803 int tcode, length, ext_tcode, sel;
804 __be32 *payload, lock_old;
805 u32 lock_arg, lock_data;
806
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400807 tcode = HEADER_GET_TCODE(packet->header[0]);
808 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500809 payload = packet->payload;
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400810 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500811
812 if (tcode == TCODE_LOCK_REQUEST &&
813 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
814 lock_arg = be32_to_cpu(payload[0]);
815 lock_data = be32_to_cpu(payload[1]);
816 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
817 lock_arg = 0;
818 lock_data = 0;
819 } else {
820 fw_fill_response(&response, packet->header,
821 RCODE_TYPE_ERROR, NULL, 0);
822 goto out;
823 }
824
825 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
826 reg_write(ohci, OHCI1394_CSRData, lock_data);
827 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
828 reg_write(ohci, OHCI1394_CSRControl, sel);
829
830 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
831 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
832 else
833 fw_notify("swap not done yet\n");
834
835 fw_fill_response(&response, packet->header,
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400836 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500837 out:
838 fw_core_handle_response(&ohci->card, &response);
839}
840
841static void
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500842handle_local_request(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500843{
844 u64 offset;
845 u32 csr;
846
Kristian Høgsberg473d28c2007-03-07 12:12:55 -0500847 if (ctx == &ctx->ohci->at_request_ctx) {
848 packet->ack = ACK_PENDING;
849 packet->callback(packet, &ctx->ohci->card, packet->ack);
850 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500851
852 offset =
853 ((unsigned long long)
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400854 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500855 packet->header[2];
856 csr = offset - CSR_REGISTER_BASE;
857
858 /* Handle config rom reads. */
859 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
860 handle_local_rom(ctx->ohci, packet, csr);
861 else switch (csr) {
862 case CSR_BUS_MANAGER_ID:
863 case CSR_BANDWIDTH_AVAILABLE:
864 case CSR_CHANNELS_AVAILABLE_HI:
865 case CSR_CHANNELS_AVAILABLE_LO:
866 handle_local_lock(ctx->ohci, packet, csr);
867 break;
868 default:
869 if (ctx == &ctx->ohci->at_request_ctx)
870 fw_core_handle_request(&ctx->ohci->card, packet);
871 else
872 fw_core_handle_response(&ctx->ohci->card, packet);
873 break;
874 }
Kristian Høgsberg473d28c2007-03-07 12:12:55 -0500875
876 if (ctx == &ctx->ohci->at_response_ctx) {
877 packet->ack = ACK_COMPLETE;
878 packet->callback(packet, &ctx->ohci->card, packet->ack);
879 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500880}
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500881
Kristian Høgsberged568912006-12-19 19:58:35 -0500882static void
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500883at_context_transmit(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberged568912006-12-19 19:58:35 -0500884{
Kristian Høgsberged568912006-12-19 19:58:35 -0500885 unsigned long flags;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500886 int retval;
Kristian Høgsberged568912006-12-19 19:58:35 -0500887
888 spin_lock_irqsave(&ctx->ohci->lock, flags);
889
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400890 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500891 ctx->ohci->generation == packet->generation) {
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500892 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
893 handle_local_request(ctx, packet);
894 return;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500895 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500896
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500897 retval = at_context_queue_packet(ctx, packet);
Kristian Høgsberged568912006-12-19 19:58:35 -0500898 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
899
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500900 if (retval < 0)
901 packet->callback(packet, &ctx->ohci->card, packet->ack);
902
Kristian Høgsberged568912006-12-19 19:58:35 -0500903}
904
905static void bus_reset_tasklet(unsigned long data)
906{
907 struct fw_ohci *ohci = (struct fw_ohci *)data;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500908 int self_id_count, i, j, reg;
Kristian Høgsberged568912006-12-19 19:58:35 -0500909 int generation, new_generation;
910 unsigned long flags;
Stefan Richter4eaff7d2007-07-25 19:18:08 +0200911 void *free_rom = NULL;
912 dma_addr_t free_rom_bus = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -0500913
914 reg = reg_read(ohci, OHCI1394_NodeID);
915 if (!(reg & OHCI1394_NodeID_idValid)) {
916 fw_error("node ID not valid, new bus reset in progress\n");
917 return;
918 }
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500919 ohci->node_id = reg & 0xffff;
Kristian Høgsberged568912006-12-19 19:58:35 -0500920
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400921 /*
922 * The count in the SelfIDCount register is the number of
Kristian Høgsberged568912006-12-19 19:58:35 -0500923 * bytes in the self ID receive buffer. Since we also receive
924 * the inverted quadlets and a header quadlet, we shift one
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400925 * bit extra to get the actual number of self IDs.
926 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500927
928 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
929 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
Stefan Richteree71c2f2007-08-25 14:08:19 +0200930 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -0500931
932 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
933 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
934 fw_error("inconsistent self IDs\n");
935 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
936 }
Stefan Richteree71c2f2007-08-25 14:08:19 +0200937 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -0500938
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400939 /*
940 * Check the consistency of the self IDs we just read. The
Kristian Høgsberged568912006-12-19 19:58:35 -0500941 * problem we face is that a new bus reset can start while we
942 * read out the self IDs from the DMA buffer. If this happens,
943 * the DMA buffer will be overwritten with new self IDs and we
944 * will read out inconsistent data. The OHCI specification
945 * (section 11.2) recommends a technique similar to
946 * linux/seqlock.h, where we remember the generation of the
947 * self IDs in the buffer before reading them out and compare
948 * it to the current generation after reading them out. If
949 * the two generations match we know we have a consistent set
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400950 * of self IDs.
951 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500952
953 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
954 if (new_generation != generation) {
955 fw_notify("recursive bus reset detected, "
956 "discarding self ids\n");
957 return;
958 }
959
960 /* FIXME: Document how the locking works. */
961 spin_lock_irqsave(&ohci->lock, flags);
962
963 ohci->generation = generation;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500964 context_stop(&ohci->at_request_ctx);
965 context_stop(&ohci->at_response_ctx);
Kristian Høgsberged568912006-12-19 19:58:35 -0500966 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
967
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400968 /*
969 * This next bit is unrelated to the AT context stuff but we
Kristian Høgsberged568912006-12-19 19:58:35 -0500970 * have to do it under the spinlock also. If a new config rom
971 * was set up before this reset, the old one is now no longer
972 * in use and we can free it. Update the config rom pointers
973 * to point to the current config rom and clear the
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400974 * next_config_rom pointer so a new udpate can take place.
975 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500976
977 if (ohci->next_config_rom != NULL) {
Stefan Richter4eaff7d2007-07-25 19:18:08 +0200978 free_rom = ohci->config_rom;
979 free_rom_bus = ohci->config_rom_bus;
Kristian Høgsberged568912006-12-19 19:58:35 -0500980 ohci->config_rom = ohci->next_config_rom;
981 ohci->config_rom_bus = ohci->next_config_rom_bus;
982 ohci->next_config_rom = NULL;
983
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400984 /*
985 * Restore config_rom image and manually update
Kristian Høgsberged568912006-12-19 19:58:35 -0500986 * config_rom registers. Writing the header quadlet
987 * will indicate that the config rom is ready, so we
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400988 * do that last.
989 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500990 reg_write(ohci, OHCI1394_BusOptions,
991 be32_to_cpu(ohci->config_rom[2]));
992 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
993 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
994 }
995
996 spin_unlock_irqrestore(&ohci->lock, flags);
997
Stefan Richter4eaff7d2007-07-25 19:18:08 +0200998 if (free_rom)
999 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1000 free_rom, free_rom_bus);
1001
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001002 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
Kristian Høgsberged568912006-12-19 19:58:35 -05001003 self_id_count, ohci->self_id_buffer);
1004}
1005
1006static irqreturn_t irq_handler(int irq, void *data)
1007{
1008 struct fw_ohci *ohci = data;
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001009 u32 event, iso_event, cycle_time;
Kristian Høgsberged568912006-12-19 19:58:35 -05001010 int i;
1011
1012 event = reg_read(ohci, OHCI1394_IntEventClear);
1013
Stefan Richtera5159582007-06-09 19:31:14 +02001014 if (!event || !~event)
Kristian Høgsberged568912006-12-19 19:58:35 -05001015 return IRQ_NONE;
1016
1017 reg_write(ohci, OHCI1394_IntEventClear, event);
1018
1019 if (event & OHCI1394_selfIDComplete)
1020 tasklet_schedule(&ohci->bus_reset_tasklet);
1021
1022 if (event & OHCI1394_RQPkt)
1023 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1024
1025 if (event & OHCI1394_RSPkt)
1026 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1027
1028 if (event & OHCI1394_reqTxComplete)
1029 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1030
1031 if (event & OHCI1394_respTxComplete)
1032 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1033
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001034 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001035 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1036
1037 while (iso_event) {
1038 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001039 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001040 iso_event &= ~(1 << i);
1041 }
1042
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001043 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001044 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1045
1046 while (iso_event) {
1047 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001048 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001049 iso_event &= ~(1 << i);
1050 }
1051
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001052 if (event & OHCI1394_cycle64Seconds) {
1053 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1054 if ((cycle_time & 0x80000000) == 0)
1055 ohci->bus_seconds++;
1056 }
1057
Kristian Høgsberged568912006-12-19 19:58:35 -05001058 return IRQ_HANDLED;
1059}
1060
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001061static int software_reset(struct fw_ohci *ohci)
1062{
1063 int i;
1064
1065 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1066
1067 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1068 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1069 OHCI1394_HCControl_softReset) == 0)
1070 return 0;
1071 msleep(1);
1072 }
1073
1074 return -EBUSY;
1075}
1076
Kristian Høgsberged568912006-12-19 19:58:35 -05001077static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1078{
1079 struct fw_ohci *ohci = fw_ohci(card);
1080 struct pci_dev *dev = to_pci_dev(card->device);
1081
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001082 if (software_reset(ohci)) {
1083 fw_error("Failed to reset ohci card.\n");
1084 return -EBUSY;
1085 }
1086
1087 /*
1088 * Now enable LPS, which we need in order to start accessing
1089 * most of the registers. In fact, on some cards (ALI M5251),
1090 * accessing registers in the SClk domain without LPS enabled
1091 * will lock up the machine. Wait 50msec to make sure we have
1092 * full link enabled.
1093 */
1094 reg_write(ohci, OHCI1394_HCControlSet,
1095 OHCI1394_HCControl_LPS |
1096 OHCI1394_HCControl_postedWriteEnable);
1097 flush_writes(ohci);
1098 msleep(50);
1099
1100 reg_write(ohci, OHCI1394_HCControlClear,
1101 OHCI1394_HCControl_noByteSwapData);
1102
1103 reg_write(ohci, OHCI1394_LinkControlSet,
1104 OHCI1394_LinkControl_rcvSelfID |
1105 OHCI1394_LinkControl_cycleTimerEnable |
1106 OHCI1394_LinkControl_cycleMaster);
1107
1108 reg_write(ohci, OHCI1394_ATRetries,
1109 OHCI1394_MAX_AT_REQ_RETRIES |
1110 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1111 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1112
1113 ar_context_run(&ohci->ar_request_ctx);
1114 ar_context_run(&ohci->ar_response_ctx);
1115
1116 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1117 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1118 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1119 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1120 reg_write(ohci, OHCI1394_IntMaskSet,
1121 OHCI1394_selfIDComplete |
1122 OHCI1394_RQPkt | OHCI1394_RSPkt |
1123 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1124 OHCI1394_isochRx | OHCI1394_isochTx |
1125 OHCI1394_masterIntEnable |
1126 OHCI1394_cycle64Seconds);
1127
1128 /* Activate link_on bit and contender bit in our self ID packets.*/
1129 if (ohci_update_phy_reg(card, 4, 0,
1130 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1131 return -EIO;
1132
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001133 /*
1134 * When the link is not yet enabled, the atomic config rom
Kristian Høgsberged568912006-12-19 19:58:35 -05001135 * update mechanism described below in ohci_set_config_rom()
1136 * is not active. We have to update ConfigRomHeader and
1137 * BusOptions manually, and the write to ConfigROMmap takes
1138 * effect immediately. We tie this to the enabling of the
1139 * link, so we have a valid config rom before enabling - the
1140 * OHCI requires that ConfigROMhdr and BusOptions have valid
1141 * values before enabling.
1142 *
1143 * However, when the ConfigROMmap is written, some controllers
1144 * always read back quadlets 0 and 2 from the config rom to
1145 * the ConfigRomHeader and BusOptions registers on bus reset.
1146 * They shouldn't do that in this initial case where the link
1147 * isn't enabled. This means we have to use the same
1148 * workaround here, setting the bus header to 0 and then write
1149 * the right values in the bus reset tasklet.
1150 */
1151
1152 ohci->next_config_rom =
1153 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1154 &ohci->next_config_rom_bus, GFP_KERNEL);
1155 if (ohci->next_config_rom == NULL)
1156 return -ENOMEM;
1157
1158 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1159 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1160
1161 ohci->next_header = config_rom[0];
1162 ohci->next_config_rom[0] = 0;
1163 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1164 reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1165 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1166
1167 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1168
1169 if (request_irq(dev->irq, irq_handler,
Thomas Gleixner65efffa2007-03-05 18:19:51 -08001170 IRQF_SHARED, ohci_driver_name, ohci)) {
Kristian Høgsberged568912006-12-19 19:58:35 -05001171 fw_error("Failed to allocate shared interrupt %d.\n",
1172 dev->irq);
1173 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1174 ohci->config_rom, ohci->config_rom_bus);
1175 return -EIO;
1176 }
1177
1178 reg_write(ohci, OHCI1394_HCControlSet,
1179 OHCI1394_HCControl_linkEnable |
1180 OHCI1394_HCControl_BIBimageValid);
1181 flush_writes(ohci);
1182
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001183 /*
1184 * We are ready to go, initiate bus reset to finish the
1185 * initialization.
1186 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001187
1188 fw_core_initiate_bus_reset(&ohci->card, 1);
1189
1190 return 0;
1191}
1192
1193static int
1194ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1195{
1196 struct fw_ohci *ohci;
1197 unsigned long flags;
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001198 int retval = -EBUSY;
Kristian Høgsberged568912006-12-19 19:58:35 -05001199 __be32 *next_config_rom;
1200 dma_addr_t next_config_rom_bus;
1201
1202 ohci = fw_ohci(card);
1203
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001204 /*
1205 * When the OHCI controller is enabled, the config rom update
Kristian Høgsberged568912006-12-19 19:58:35 -05001206 * mechanism is a bit tricky, but easy enough to use. See
1207 * section 5.5.6 in the OHCI specification.
1208 *
1209 * The OHCI controller caches the new config rom address in a
1210 * shadow register (ConfigROMmapNext) and needs a bus reset
1211 * for the changes to take place. When the bus reset is
1212 * detected, the controller loads the new values for the
1213 * ConfigRomHeader and BusOptions registers from the specified
1214 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1215 * shadow register. All automatically and atomically.
1216 *
1217 * Now, there's a twist to this story. The automatic load of
1218 * ConfigRomHeader and BusOptions doesn't honor the
1219 * noByteSwapData bit, so with a be32 config rom, the
1220 * controller will load be32 values in to these registers
1221 * during the atomic update, even on litte endian
1222 * architectures. The workaround we use is to put a 0 in the
1223 * header quadlet; 0 is endian agnostic and means that the
1224 * config rom isn't ready yet. In the bus reset tasklet we
1225 * then set up the real values for the two registers.
1226 *
1227 * We use ohci->lock to avoid racing with the code that sets
1228 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1229 */
1230
1231 next_config_rom =
1232 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1233 &next_config_rom_bus, GFP_KERNEL);
1234 if (next_config_rom == NULL)
1235 return -ENOMEM;
1236
1237 spin_lock_irqsave(&ohci->lock, flags);
1238
1239 if (ohci->next_config_rom == NULL) {
1240 ohci->next_config_rom = next_config_rom;
1241 ohci->next_config_rom_bus = next_config_rom_bus;
1242
1243 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1244 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1245 length * 4);
1246
1247 ohci->next_header = config_rom[0];
1248 ohci->next_config_rom[0] = 0;
1249
1250 reg_write(ohci, OHCI1394_ConfigROMmap,
1251 ohci->next_config_rom_bus);
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001252 retval = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001253 }
1254
1255 spin_unlock_irqrestore(&ohci->lock, flags);
1256
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001257 /*
1258 * Now initiate a bus reset to have the changes take
Kristian Høgsberged568912006-12-19 19:58:35 -05001259 * effect. We clean up the old config rom memory and DMA
1260 * mappings in the bus reset tasklet, since the OHCI
1261 * controller could need to access it before the bus reset
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001262 * takes effect.
1263 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001264 if (retval == 0)
1265 fw_core_initiate_bus_reset(&ohci->card, 1);
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001266 else
1267 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1268 next_config_rom, next_config_rom_bus);
Kristian Høgsberged568912006-12-19 19:58:35 -05001269
1270 return retval;
1271}
1272
1273static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1274{
1275 struct fw_ohci *ohci = fw_ohci(card);
1276
1277 at_context_transmit(&ohci->at_request_ctx, packet);
1278}
1279
1280static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1281{
1282 struct fw_ohci *ohci = fw_ohci(card);
1283
1284 at_context_transmit(&ohci->at_response_ctx, packet);
1285}
1286
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001287static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1288{
1289 struct fw_ohci *ohci = fw_ohci(card);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001290 struct context *ctx = &ohci->at_request_ctx;
1291 struct driver_data *driver_data = packet->driver_data;
1292 int retval = -ENOENT;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001293
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001294 tasklet_disable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001295
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001296 if (packet->ack != 0)
1297 goto out;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001298
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001299 driver_data->packet = NULL;
1300 packet->ack = RCODE_CANCELLED;
1301 packet->callback(packet, &ohci->card, packet->ack);
1302 retval = 0;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001303
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001304 out:
1305 tasklet_enable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001306
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001307 return retval;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001308}
1309
Kristian Høgsberged568912006-12-19 19:58:35 -05001310static int
1311ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1312{
1313 struct fw_ohci *ohci = fw_ohci(card);
1314 unsigned long flags;
Stefan Richter907293d2007-01-23 21:11:43 +01001315 int n, retval = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001316
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001317 /*
1318 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1319 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1320 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001321
1322 spin_lock_irqsave(&ohci->lock, flags);
1323
1324 if (ohci->generation != generation) {
1325 retval = -ESTALE;
1326 goto out;
1327 }
1328
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001329 /*
1330 * Note, if the node ID contains a non-local bus ID, physical DMA is
1331 * enabled for _all_ nodes on remote buses.
1332 */
Stefan Richter907293d2007-01-23 21:11:43 +01001333
1334 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1335 if (n < 32)
1336 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1337 else
1338 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1339
Kristian Høgsberged568912006-12-19 19:58:35 -05001340 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05001341 out:
Stefan Richter6cad95f2007-01-21 20:46:45 +01001342 spin_unlock_irqrestore(&ohci->lock, flags);
Kristian Høgsberged568912006-12-19 19:58:35 -05001343 return retval;
1344}
Stefan Richter373b2ed2007-03-04 14:45:18 +01001345
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001346static u64
1347ohci_get_bus_time(struct fw_card *card)
1348{
1349 struct fw_ohci *ohci = fw_ohci(card);
1350 u32 cycle_time;
1351 u64 bus_time;
1352
1353 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1354 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1355
1356 return bus_time;
1357}
1358
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001359static int handle_ir_dualbuffer_packet(struct context *context,
1360 struct descriptor *d,
1361 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05001362{
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001363 struct iso_context *ctx =
1364 container_of(context, struct iso_context, context);
1365 struct db_descriptor *db = (struct db_descriptor *) d;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001366 __le32 *ir_header;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001367 size_t header_length;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001368 void *p, *end;
1369 int i;
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001370
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001371 if (db->first_res_count > 0 && db->second_res_count > 0)
1372 /* This descriptor isn't done yet, stop iteration. */
1373 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001374
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001375 header_length = le16_to_cpu(db->first_req_count) -
1376 le16_to_cpu(db->first_res_count);
1377
1378 i = ctx->header_length;
1379 p = db + 1;
1380 end = p + header_length;
1381 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001382 /*
1383 * The iso header is byteswapped to little endian by
Kristian Høgsberg15536222007-04-10 18:11:16 -04001384 * the controller, but the remaining header quadlets
1385 * are big endian. We want to present all the headers
1386 * as big endian, so we have to swap the first
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001387 * quadlet.
1388 */
Kristian Høgsberg15536222007-04-10 18:11:16 -04001389 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1390 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001391 i += ctx->base.header_size;
1392 p += ctx->base.header_size + 4;
1393 }
1394
1395 ctx->header_length = i;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001396
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001397 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001398 ir_header = (__le32 *) (db + 1);
1399 ctx->base.callback(&ctx->base,
1400 le32_to_cpu(ir_header[0]) & 0xffff,
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001401 ctx->header_length, ctx->header,
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001402 ctx->base.callback_data);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001403 ctx->header_length = 0;
1404 }
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001405
1406 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001407}
1408
Kristian Høgsberg30200732007-02-16 17:34:39 -05001409static int handle_it_packet(struct context *context,
1410 struct descriptor *d,
1411 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05001412{
Kristian Høgsberg30200732007-02-16 17:34:39 -05001413 struct iso_context *ctx =
1414 container_of(context, struct iso_context, context);
Stefan Richter373b2ed2007-03-04 14:45:18 +01001415
Kristian Høgsberg30200732007-02-16 17:34:39 -05001416 if (last->transfer_status == 0)
1417 /* This descriptor isn't done yet, stop iteration. */
1418 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001419
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001420 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001421 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1422 0, NULL, ctx->base.callback_data);
Kristian Høgsberged568912006-12-19 19:58:35 -05001423
Kristian Høgsberg30200732007-02-16 17:34:39 -05001424 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001425}
1426
Kristian Høgsberg30200732007-02-16 17:34:39 -05001427static struct fw_iso_context *
Kristian Høgsbergeb0306e2007-03-14 17:34:54 -04001428ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
Kristian Høgsberged568912006-12-19 19:58:35 -05001429{
1430 struct fw_ohci *ohci = fw_ohci(card);
1431 struct iso_context *ctx, *list;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001432 descriptor_callback_t callback;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001433 u32 *mask, regs;
Kristian Høgsberged568912006-12-19 19:58:35 -05001434 unsigned long flags;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001435 int index, retval = -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001436
1437 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1438 mask = &ohci->it_context_mask;
1439 list = ohci->it_context_list;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001440 callback = handle_it_packet;
Kristian Høgsberged568912006-12-19 19:58:35 -05001441 } else {
Stefan Richter373b2ed2007-03-04 14:45:18 +01001442 mask = &ohci->ir_context_mask;
1443 list = ohci->ir_context_list;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001444 callback = handle_ir_dualbuffer_packet;
Kristian Høgsberged568912006-12-19 19:58:35 -05001445 }
1446
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001447 /* FIXME: We need a fallback for pre 1.1 OHCI. */
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001448 if (callback == handle_ir_dualbuffer_packet &&
1449 ohci->version < OHCI_VERSION_1_1)
1450 return ERR_PTR(-EINVAL);
1451
Kristian Høgsberged568912006-12-19 19:58:35 -05001452 spin_lock_irqsave(&ohci->lock, flags);
1453 index = ffs(*mask) - 1;
1454 if (index >= 0)
1455 *mask &= ~(1 << index);
1456 spin_unlock_irqrestore(&ohci->lock, flags);
1457
1458 if (index < 0)
1459 return ERR_PTR(-EBUSY);
1460
Stefan Richter373b2ed2007-03-04 14:45:18 +01001461 if (type == FW_ISO_CONTEXT_TRANSMIT)
1462 regs = OHCI1394_IsoXmitContextBase(index);
1463 else
1464 regs = OHCI1394_IsoRcvContextBase(index);
1465
Kristian Høgsberged568912006-12-19 19:58:35 -05001466 ctx = &list[index];
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001467 memset(ctx, 0, sizeof(*ctx));
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001468 ctx->header_length = 0;
1469 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1470 if (ctx->header == NULL)
1471 goto out;
1472
Kristian Høgsberg30200732007-02-16 17:34:39 -05001473 retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001474 regs, callback);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001475 if (retval < 0)
1476 goto out_with_header;
Kristian Høgsberged568912006-12-19 19:58:35 -05001477
1478 return &ctx->base;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001479
1480 out_with_header:
1481 free_page((unsigned long)ctx->header);
1482 out:
1483 spin_lock_irqsave(&ohci->lock, flags);
1484 *mask |= 1 << index;
1485 spin_unlock_irqrestore(&ohci->lock, flags);
1486
1487 return ERR_PTR(retval);
Kristian Høgsberged568912006-12-19 19:58:35 -05001488}
1489
Kristian Høgsbergeb0306e2007-03-14 17:34:54 -04001490static int ohci_start_iso(struct fw_iso_context *base,
1491 s32 cycle, u32 sync, u32 tags)
Kristian Høgsberged568912006-12-19 19:58:35 -05001492{
Stefan Richter373b2ed2007-03-04 14:45:18 +01001493 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001494 struct fw_ohci *ohci = ctx->context.ohci;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001495 u32 control, match;
Kristian Høgsberged568912006-12-19 19:58:35 -05001496 int index;
1497
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001498 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1499 index = ctx - ohci->it_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001500 match = 0;
1501 if (cycle >= 0)
1502 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001503 (cycle & 0x7fff) << 16;
Kristian Høgsberg21efb3c2007-02-16 17:34:50 -05001504
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001505 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1506 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001507 context_run(&ctx->context, match);
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001508 } else {
1509 index = ctx - ohci->ir_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001510 control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
1511 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1512 if (cycle >= 0) {
1513 match |= (cycle & 0x07fff) << 12;
1514 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1515 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001516
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001517 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1518 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001519 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001520 context_run(&ctx->context, control);
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001521 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001522
1523 return 0;
1524}
1525
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001526static int ohci_stop_iso(struct fw_iso_context *base)
1527{
1528 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01001529 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001530 int index;
1531
1532 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1533 index = ctx - ohci->it_context_list;
1534 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1535 } else {
1536 index = ctx - ohci->ir_context_list;
1537 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1538 }
1539 flush_writes(ohci);
1540 context_stop(&ctx->context);
1541
1542 return 0;
1543}
1544
Kristian Høgsberged568912006-12-19 19:58:35 -05001545static void ohci_free_iso_context(struct fw_iso_context *base)
1546{
1547 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01001548 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberged568912006-12-19 19:58:35 -05001549 unsigned long flags;
1550 int index;
1551
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001552 ohci_stop_iso(base);
1553 context_release(&ctx->context);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001554 free_page((unsigned long)ctx->header);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001555
Kristian Høgsberged568912006-12-19 19:58:35 -05001556 spin_lock_irqsave(&ohci->lock, flags);
1557
1558 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1559 index = ctx - ohci->it_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001560 ohci->it_context_mask |= 1 << index;
1561 } else {
1562 index = ctx - ohci->ir_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001563 ohci->ir_context_mask |= 1 << index;
1564 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001565
1566 spin_unlock_irqrestore(&ohci->lock, flags);
1567}
1568
1569static int
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001570ohci_queue_iso_transmit(struct fw_iso_context *base,
1571 struct fw_iso_packet *packet,
1572 struct fw_iso_buffer *buffer,
1573 unsigned long payload)
Kristian Høgsberged568912006-12-19 19:58:35 -05001574{
Stefan Richter373b2ed2007-03-04 14:45:18 +01001575 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001576 struct descriptor *d, *last, *pd;
Kristian Høgsberged568912006-12-19 19:58:35 -05001577 struct fw_iso_packet *p;
1578 __le32 *header;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001579 dma_addr_t d_bus, page_bus;
Kristian Høgsberged568912006-12-19 19:58:35 -05001580 u32 z, header_z, payload_z, irq;
1581 u32 payload_index, payload_end_index, next_page_index;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001582 int page, end_page, i, length, offset;
Kristian Høgsberged568912006-12-19 19:58:35 -05001583
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001584 /*
1585 * FIXME: Cycle lost behavior should be configurable: lose
1586 * packet, retransmit or terminate..
1587 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001588
1589 p = packet;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001590 payload_index = payload;
Kristian Høgsberged568912006-12-19 19:58:35 -05001591
1592 if (p->skip)
1593 z = 1;
1594 else
1595 z = 2;
1596 if (p->header_length > 0)
1597 z++;
1598
1599 /* Determine the first page the payload isn't contained in. */
1600 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1601 if (p->payload_length > 0)
1602 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1603 else
1604 payload_z = 0;
1605
1606 z += payload_z;
1607
1608 /* Get header size in number of descriptors. */
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001609 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05001610
Kristian Høgsberg30200732007-02-16 17:34:39 -05001611 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1612 if (d == NULL)
1613 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001614
1615 if (!p->skip) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001616 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsberged568912006-12-19 19:58:35 -05001617 d[0].req_count = cpu_to_le16(8);
1618
1619 header = (__le32 *) &d[1];
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001620 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1621 IT_HEADER_TAG(p->tag) |
1622 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1623 IT_HEADER_CHANNEL(ctx->base.channel) |
1624 IT_HEADER_SPEED(ctx->base.speed));
Kristian Høgsberged568912006-12-19 19:58:35 -05001625 header[1] =
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001626 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
Kristian Høgsberged568912006-12-19 19:58:35 -05001627 p->payload_length));
1628 }
1629
1630 if (p->header_length > 0) {
1631 d[2].req_count = cpu_to_le16(p->header_length);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001632 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05001633 memcpy(&d[z], p->header, p->header_length);
1634 }
1635
1636 pd = d + z - payload_z;
1637 payload_end_index = payload_index + p->payload_length;
1638 for (i = 0; i < payload_z; i++) {
1639 page = payload_index >> PAGE_SHIFT;
1640 offset = payload_index & ~PAGE_MASK;
1641 next_page_index = (page + 1) << PAGE_SHIFT;
1642 length =
1643 min(next_page_index, payload_end_index) - payload_index;
1644 pd[i].req_count = cpu_to_le16(length);
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001645
1646 page_bus = page_private(buffer->pages[page]);
1647 pd[i].data_address = cpu_to_le32(page_bus + offset);
Kristian Høgsberged568912006-12-19 19:58:35 -05001648
1649 payload_index += length;
1650 }
1651
Kristian Høgsberged568912006-12-19 19:58:35 -05001652 if (p->interrupt)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001653 irq = DESCRIPTOR_IRQ_ALWAYS;
Kristian Høgsberged568912006-12-19 19:58:35 -05001654 else
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001655 irq = DESCRIPTOR_NO_IRQ;
Kristian Høgsberged568912006-12-19 19:58:35 -05001656
Kristian Høgsberg30200732007-02-16 17:34:39 -05001657 last = z == 2 ? d : d + z - 1;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001658 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1659 DESCRIPTOR_STATUS |
1660 DESCRIPTOR_BRANCH_ALWAYS |
Kristian Høgsbergcbb59da2007-02-16 17:34:35 -05001661 irq);
Kristian Høgsberged568912006-12-19 19:58:35 -05001662
Kristian Høgsberg30200732007-02-16 17:34:39 -05001663 context_append(&ctx->context, d, z, header_z);
Kristian Høgsberged568912006-12-19 19:58:35 -05001664
1665 return 0;
1666}
Stefan Richter373b2ed2007-03-04 14:45:18 +01001667
Kristian Høgsberg98b6cbe2007-02-16 17:34:51 -05001668static int
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001669ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1670 struct fw_iso_packet *packet,
1671 struct fw_iso_buffer *buffer,
1672 unsigned long payload)
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001673{
1674 struct iso_context *ctx = container_of(base, struct iso_context, base);
1675 struct db_descriptor *db = NULL;
1676 struct descriptor *d;
1677 struct fw_iso_packet *p;
1678 dma_addr_t d_bus, page_bus;
1679 u32 z, header_z, length, rest;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001680 int page, offset, packet_count, header_size;
Stefan Richter373b2ed2007-03-04 14:45:18 +01001681
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001682 /*
1683 * FIXME: Cycle lost behavior should be configurable: lose
1684 * packet, retransmit or terminate..
1685 */
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001686
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001687 if (packet->skip) {
1688 d = context_get_descriptors(&ctx->context, 2, &d_bus);
1689 if (d == NULL)
1690 return -ENOMEM;
1691
1692 db = (struct db_descriptor *) d;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001693 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1694 DESCRIPTOR_BRANCH_ALWAYS |
1695 DESCRIPTOR_WAIT);
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001696 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1697 context_append(&ctx->context, d, 2, 0);
1698 }
Kristian Høgsberg98b6cbe2007-02-16 17:34:51 -05001699
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001700 p = packet;
1701 z = 2;
1702
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001703 /*
1704 * The OHCI controller puts the status word in the header
1705 * buffer too, so we need 4 extra bytes per packet.
1706 */
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001707 packet_count = p->header_length / ctx->base.header_size;
1708 header_size = packet_count * (ctx->base.header_size + 4);
1709
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001710 /* Get header size in number of descriptors. */
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001711 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001712 page = payload >> PAGE_SHIFT;
1713 offset = payload & ~PAGE_MASK;
1714 rest = p->payload_length;
1715
1716 /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001717 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1718 while (rest > 0) {
1719 d = context_get_descriptors(&ctx->context,
1720 z + header_z, &d_bus);
1721 if (d == NULL)
1722 return -ENOMEM;
1723
1724 db = (struct db_descriptor *) d;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001725 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1726 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001727 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1728 db->first_req_count = cpu_to_le16(header_size);
Kristian Høgsberg1e1d1962007-02-16 17:34:45 -05001729 db->first_res_count = db->first_req_count;
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001730 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
Stefan Richter373b2ed2007-03-04 14:45:18 +01001731
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001732 if (offset + rest < PAGE_SIZE)
1733 length = rest;
1734 else
1735 length = PAGE_SIZE - offset;
1736
Kristian Høgsberg1e1d1962007-02-16 17:34:45 -05001737 db->second_req_count = cpu_to_le16(length);
1738 db->second_res_count = db->second_req_count;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001739 page_bus = page_private(buffer->pages[page]);
1740 db->second_buffer = cpu_to_le32(page_bus + offset);
1741
Kristian Høgsbergcb2d2cd2007-02-16 17:34:47 -05001742 if (p->interrupt && length == rest)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001743 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
Kristian Høgsbergcb2d2cd2007-02-16 17:34:47 -05001744
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001745 context_append(&ctx->context, d, z, header_z);
1746 offset = (offset + length) & ~PAGE_MASK;
1747 rest -= length;
1748 page++;
1749 }
1750
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001751 return 0;
1752}
Kristian Høgsberg21efb3c2007-02-16 17:34:50 -05001753
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001754static int
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001755ohci_queue_iso(struct fw_iso_context *base,
1756 struct fw_iso_packet *packet,
1757 struct fw_iso_buffer *buffer,
1758 unsigned long payload)
1759{
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001760 struct iso_context *ctx = container_of(base, struct iso_context, base);
1761
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001762 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1763 return ohci_queue_iso_transmit(base, packet, buffer, payload);
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001764 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001765 return ohci_queue_iso_receive_dualbuffer(base, packet,
1766 buffer, payload);
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001767 else
1768 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1769 return -EINVAL;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001770}
1771
Stefan Richter21ebcd12007-01-14 15:29:07 +01001772static const struct fw_card_driver ohci_driver = {
Kristian Høgsberged568912006-12-19 19:58:35 -05001773 .name = ohci_driver_name,
1774 .enable = ohci_enable,
1775 .update_phy_reg = ohci_update_phy_reg,
1776 .set_config_rom = ohci_set_config_rom,
1777 .send_request = ohci_send_request,
1778 .send_response = ohci_send_response,
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001779 .cancel_packet = ohci_cancel_packet,
Kristian Høgsberged568912006-12-19 19:58:35 -05001780 .enable_phys_dma = ohci_enable_phys_dma,
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001781 .get_bus_time = ohci_get_bus_time,
Kristian Høgsberged568912006-12-19 19:58:35 -05001782
1783 .allocate_iso_context = ohci_allocate_iso_context,
1784 .free_iso_context = ohci_free_iso_context,
1785 .queue_iso = ohci_queue_iso,
Kristian Høgsberg69cdb722007-02-16 17:34:41 -05001786 .start_iso = ohci_start_iso,
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001787 .stop_iso = ohci_stop_iso,
Kristian Høgsberged568912006-12-19 19:58:35 -05001788};
1789
Kristian Høgsberged568912006-12-19 19:58:35 -05001790static int __devinit
1791pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1792{
1793 struct fw_ohci *ohci;
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001794 u32 bus_options, max_receive, link_speed;
Kristian Høgsberged568912006-12-19 19:58:35 -05001795 u64 guid;
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001796 int err;
Kristian Høgsberged568912006-12-19 19:58:35 -05001797 size_t size;
1798
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001799 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
Kristian Høgsberged568912006-12-19 19:58:35 -05001800 if (ohci == NULL) {
1801 fw_error("Could not malloc fw_ohci data.\n");
1802 return -ENOMEM;
1803 }
1804
1805 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1806
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001807 err = pci_enable_device(dev);
1808 if (err) {
Kristian Høgsberged568912006-12-19 19:58:35 -05001809 fw_error("Failed to enable OHCI hardware.\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001810 goto fail_put_card;
Kristian Høgsberged568912006-12-19 19:58:35 -05001811 }
1812
1813 pci_set_master(dev);
1814 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1815 pci_set_drvdata(dev, ohci);
1816
1817 spin_lock_init(&ohci->lock);
1818
1819 tasklet_init(&ohci->bus_reset_tasklet,
1820 bus_reset_tasklet, (unsigned long)ohci);
1821
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001822 err = pci_request_region(dev, 0, ohci_driver_name);
1823 if (err) {
Kristian Høgsberged568912006-12-19 19:58:35 -05001824 fw_error("MMIO resource unavailable\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001825 goto fail_disable;
Kristian Høgsberged568912006-12-19 19:58:35 -05001826 }
1827
1828 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1829 if (ohci->registers == NULL) {
1830 fw_error("Failed to remap registers\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001831 err = -ENXIO;
1832 goto fail_iomem;
Kristian Høgsberged568912006-12-19 19:58:35 -05001833 }
1834
Kristian Høgsberged568912006-12-19 19:58:35 -05001835 ar_context_init(&ohci->ar_request_ctx, ohci,
1836 OHCI1394_AsReqRcvContextControlSet);
1837
1838 ar_context_init(&ohci->ar_response_ctx, ohci,
1839 OHCI1394_AsRspRcvContextControlSet);
1840
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001841 context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
1842 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001843
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001844 context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
1845 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001846
Kristian Høgsberged568912006-12-19 19:58:35 -05001847 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1848 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1849 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1850 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1851 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1852
1853 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1854 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1855 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1856 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1857 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1858
1859 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1860 fw_error("Out of memory for it/ir contexts.\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001861 err = -ENOMEM;
1862 goto fail_registers;
Kristian Høgsberged568912006-12-19 19:58:35 -05001863 }
1864
1865 /* self-id dma buffer allocation */
1866 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1867 SELF_ID_BUF_SIZE,
1868 &ohci->self_id_bus,
1869 GFP_KERNEL);
1870 if (ohci->self_id_cpu == NULL) {
1871 fw_error("Out of memory for self ID buffer.\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001872 err = -ENOMEM;
1873 goto fail_registers;
Kristian Høgsberged568912006-12-19 19:58:35 -05001874 }
1875
Kristian Høgsberged568912006-12-19 19:58:35 -05001876 bus_options = reg_read(ohci, OHCI1394_BusOptions);
1877 max_receive = (bus_options >> 12) & 0xf;
1878 link_speed = bus_options & 0x7;
1879 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1880 reg_read(ohci, OHCI1394_GUIDLo);
1881
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001882 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1883 if (err < 0)
1884 goto fail_self_id;
Kristian Høgsberged568912006-12-19 19:58:35 -05001885
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001886 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
Kristian Høgsberg500be722007-02-16 17:34:43 -05001887 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
Kristian Høgsberge364cf42007-02-16 17:34:49 -05001888 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
Kristian Høgsberged568912006-12-19 19:58:35 -05001889
1890 return 0;
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001891
1892 fail_self_id:
1893 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1894 ohci->self_id_cpu, ohci->self_id_bus);
1895 fail_registers:
1896 kfree(ohci->it_context_list);
1897 kfree(ohci->ir_context_list);
1898 pci_iounmap(dev, ohci->registers);
1899 fail_iomem:
1900 pci_release_region(dev, 0);
1901 fail_disable:
1902 pci_disable_device(dev);
1903 fail_put_card:
1904 fw_card_put(&ohci->card);
1905
1906 return err;
Kristian Høgsberged568912006-12-19 19:58:35 -05001907}
1908
1909static void pci_remove(struct pci_dev *dev)
1910{
1911 struct fw_ohci *ohci;
1912
1913 ohci = pci_get_drvdata(dev);
Kristian Høgsberge254a4b2007-03-07 12:12:38 -05001914 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1915 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05001916 fw_core_remove_card(&ohci->card);
1917
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001918 /*
1919 * FIXME: Fail all pending packets here, now that the upper
1920 * layers can't queue any more.
1921 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001922
1923 software_reset(ohci);
1924 free_irq(dev->irq, ohci);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04001925 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1926 ohci->self_id_cpu, ohci->self_id_bus);
1927 kfree(ohci->it_context_list);
1928 kfree(ohci->ir_context_list);
1929 pci_iounmap(dev, ohci->registers);
1930 pci_release_region(dev, 0);
1931 pci_disable_device(dev);
1932 fw_card_put(&ohci->card);
Kristian Høgsberged568912006-12-19 19:58:35 -05001933
1934 fw_notify("Removed fw-ohci device.\n");
1935}
1936
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001937#ifdef CONFIG_PM
1938static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
1939{
1940 struct fw_ohci *ohci = pci_get_drvdata(pdev);
1941 int err;
1942
1943 software_reset(ohci);
1944 free_irq(pdev->irq, ohci);
1945 err = pci_save_state(pdev);
1946 if (err) {
Stefan Richter8a8cea22007-06-09 19:26:22 +02001947 fw_error("pci_save_state failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001948 return err;
1949 }
1950 err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
Stefan Richter55111422007-09-06 09:50:30 +02001951 if (err)
1952 fw_error("pci_set_power_state failed with %d\n", err);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001953
1954 return 0;
1955}
1956
1957static int pci_resume(struct pci_dev *pdev)
1958{
1959 struct fw_ohci *ohci = pci_get_drvdata(pdev);
1960 int err;
1961
1962 pci_set_power_state(pdev, PCI_D0);
1963 pci_restore_state(pdev);
1964 err = pci_enable_device(pdev);
1965 if (err) {
Stefan Richter8a8cea22007-06-09 19:26:22 +02001966 fw_error("pci_enable_device failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001967 return err;
1968 }
1969
1970 return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE);
1971}
1972#endif
1973
Kristian Høgsberged568912006-12-19 19:58:35 -05001974static struct pci_device_id pci_table[] = {
1975 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1976 { }
1977};
1978
1979MODULE_DEVICE_TABLE(pci, pci_table);
1980
1981static struct pci_driver fw_ohci_pci_driver = {
1982 .name = ohci_driver_name,
1983 .id_table = pci_table,
1984 .probe = pci_probe,
1985 .remove = pci_remove,
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001986#ifdef CONFIG_PM
1987 .resume = pci_resume,
1988 .suspend = pci_suspend,
1989#endif
Kristian Høgsberged568912006-12-19 19:58:35 -05001990};
1991
1992MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1993MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1994MODULE_LICENSE("GPL");
1995
Olaf Hering1e4c7b02007-05-05 23:17:13 +02001996/* Provide a module alias so root-on-sbp2 initrds don't break. */
1997#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
1998MODULE_ALIAS("ohci1394");
1999#endif
2000
Kristian Høgsberged568912006-12-19 19:58:35 -05002001static int __init fw_ohci_init(void)
2002{
2003 return pci_register_driver(&fw_ohci_pci_driver);
2004}
2005
2006static void __exit fw_ohci_cleanup(void)
2007{
2008 pci_unregister_driver(&fw_ohci_pci_driver);
2009}
2010
2011module_init(fw_ohci_init);
2012module_exit(fw_ohci_cleanup);