Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 1 | config SIBYTE_SB1250 |
| 2 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 3 | select CEVT_SB1250 |
| 4 | select CSRC_SB1250 |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 5 | select HW_HAS_PCI |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 6 | select IRQ_CPU |
Ralf Baechle | ca6f549 | 2007-03-09 12:17:32 +0000 | [diff] [blame] | 7 | select SIBYTE_ENABLE_LDT_IF_PCI |
Mark Mason | d619f38 | 2007-03-29 11:39:56 -0700 | [diff] [blame] | 8 | select SIBYTE_HAS_ZBUS_PROFILING |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 9 | select SIBYTE_SB1xxx_SOC |
Ralf Baechle | e73ea27 | 2006-06-04 11:51:46 +0100 | [diff] [blame] | 10 | select SYS_SUPPORTS_SMP |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 11 | |
| 12 | config SIBYTE_BCM1120 |
| 13 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 14 | select CEVT_SB1250 |
| 15 | select CSRC_SB1250 |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 16 | select IRQ_CPU |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 17 | select SIBYTE_BCM112X |
Ralf Baechle | bb9b813 | 2007-03-09 15:59:56 +0000 | [diff] [blame] | 18 | select SIBYTE_HAS_ZBUS_PROFILING |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 19 | select SIBYTE_SB1xxx_SOC |
| 20 | |
| 21 | config SIBYTE_BCM1125 |
| 22 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 23 | select CEVT_SB1250 |
| 24 | select CSRC_SB1250 |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 25 | select HW_HAS_PCI |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 26 | select IRQ_CPU |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 27 | select SIBYTE_BCM112X |
Ralf Baechle | bb9b813 | 2007-03-09 15:59:56 +0000 | [diff] [blame] | 28 | select SIBYTE_HAS_ZBUS_PROFILING |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 29 | select SIBYTE_SB1xxx_SOC |
| 30 | |
| 31 | config SIBYTE_BCM1125H |
| 32 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 33 | select CEVT_SB1250 |
| 34 | select CSRC_SB1250 |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 35 | select HW_HAS_PCI |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 36 | select IRQ_CPU |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 37 | select SIBYTE_BCM112X |
Ralf Baechle | ca6f549 | 2007-03-09 12:17:32 +0000 | [diff] [blame] | 38 | select SIBYTE_ENABLE_LDT_IF_PCI |
Ralf Baechle | bb9b813 | 2007-03-09 15:59:56 +0000 | [diff] [blame] | 39 | select SIBYTE_HAS_ZBUS_PROFILING |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 40 | select SIBYTE_SB1xxx_SOC |
| 41 | |
| 42 | config SIBYTE_BCM112X |
| 43 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 44 | select CEVT_SB1250 |
| 45 | select CSRC_SB1250 |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 46 | select IRQ_CPU |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 47 | select SIBYTE_SB1xxx_SOC |
Ralf Baechle | bb9b813 | 2007-03-09 15:59:56 +0000 | [diff] [blame] | 48 | select SIBYTE_HAS_ZBUS_PROFILING |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 49 | |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 50 | config SIBYTE_BCM1x80 |
| 51 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 52 | select CEVT_BCM1480 |
| 53 | select CSRC_BCM1480 |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 54 | select HW_HAS_PCI |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 55 | select IRQ_CPU |
Mark Mason | d619f38 | 2007-03-29 11:39:56 -0700 | [diff] [blame] | 56 | select SIBYTE_HAS_ZBUS_PROFILING |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 57 | select SIBYTE_SB1xxx_SOC |
Ralf Baechle | e73ea27 | 2006-06-04 11:51:46 +0100 | [diff] [blame] | 58 | select SYS_SUPPORTS_SMP |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 59 | |
| 60 | config SIBYTE_BCM1x55 |
| 61 | bool |
Ralf Baechle | 217dd11 | 2007-11-01 01:57:55 +0000 | [diff] [blame] | 62 | select CEVT_BCM1480 |
| 63 | select CSRC_BCM1480 |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 64 | select HW_HAS_PCI |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 65 | select IRQ_CPU |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 66 | select SIBYTE_SB1xxx_SOC |
Ralf Baechle | bb9b813 | 2007-03-09 15:59:56 +0000 | [diff] [blame] | 67 | select SIBYTE_HAS_ZBUS_PROFILING |
Ralf Baechle | e73ea27 | 2006-06-04 11:51:46 +0100 | [diff] [blame] | 68 | select SYS_SUPPORTS_SMP |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 69 | |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 70 | config SIBYTE_SB1xxx_SOC |
| 71 | bool |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 72 | select DMA_COHERENT |
Ralf Baechle | 7bcf771 | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 73 | select IRQ_CPU |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 74 | select SIBYTE_CFE |
| 75 | select SWAP_IO_SPACE |
| 76 | select SYS_SUPPORTS_32BIT_KERNEL |
| 77 | select SYS_SUPPORTS_64BIT_KERNEL |
Imre Kaloz | 05f94ee | 2009-06-02 14:22:06 +0200 | [diff] [blame] | 78 | select CFE |
| 79 | select SYS_HAS_EARLY_PRINTK |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 80 | |
| 81 | choice |
| 82 | prompt "SiByte SOC Stepping" |
| 83 | depends on SIBYTE_SB1xxx_SOC |
| 84 | |
| 85 | config CPU_SB1_PASS_1 |
| 86 | bool "1250 Pass1" |
| 87 | depends on SIBYTE_SB1250 |
| 88 | select CPU_HAS_PREFETCH |
| 89 | |
| 90 | config CPU_SB1_PASS_2_1250 |
| 91 | bool "1250 An" |
| 92 | depends on SIBYTE_SB1250 |
| 93 | select CPU_SB1_PASS_2 |
| 94 | help |
| 95 | Also called BCM1250 Pass 2 |
| 96 | |
| 97 | config CPU_SB1_PASS_2_2 |
| 98 | bool "1250 Bn" |
| 99 | depends on SIBYTE_SB1250 |
| 100 | select CPU_HAS_PREFETCH |
| 101 | help |
| 102 | Also called BCM1250 Pass 2.2 |
| 103 | |
| 104 | config CPU_SB1_PASS_4 |
| 105 | bool "1250 Cn" |
| 106 | depends on SIBYTE_SB1250 |
| 107 | select CPU_HAS_PREFETCH |
| 108 | help |
| 109 | Also called BCM1250 Pass 3 |
| 110 | |
| 111 | config CPU_SB1_PASS_2_112x |
| 112 | bool "112x Hybrid" |
| 113 | depends on SIBYTE_BCM112X |
| 114 | select CPU_SB1_PASS_2 |
| 115 | |
| 116 | config CPU_SB1_PASS_3 |
| 117 | bool "112x An" |
| 118 | depends on SIBYTE_BCM112X |
| 119 | select CPU_HAS_PREFETCH |
| 120 | |
| 121 | endchoice |
| 122 | |
| 123 | config CPU_SB1_PASS_2 |
| 124 | bool |
| 125 | |
| 126 | config SIBYTE_HAS_LDT |
| 127 | bool |
Ralf Baechle | ca6f549 | 2007-03-09 12:17:32 +0000 | [diff] [blame] | 128 | |
| 129 | config SIBYTE_ENABLE_LDT_IF_PCI |
| 130 | bool |
| 131 | select SIBYTE_HAS_LDT if PCI |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 132 | |
Ralf Baechle | 7760763 | 2005-11-10 16:32:14 +0000 | [diff] [blame] | 133 | config SB1_CEX_ALWAYS_FATAL |
Andrew Isaacson | a4b5bd9 | 2005-10-19 23:57:40 -0700 | [diff] [blame] | 134 | bool "All cache exceptions considered fatal (no recovery attempted)" |
| 135 | depends on SIBYTE_SB1xxx_SOC |
| 136 | |
Ralf Baechle | 7760763 | 2005-11-10 16:32:14 +0000 | [diff] [blame] | 137 | config SB1_CERR_STALL |
Andrew Isaacson | a4b5bd9 | 2005-10-19 23:57:40 -0700 | [diff] [blame] | 138 | bool "Stall (rather than panic) on fatal cache error" |
| 139 | depends on SIBYTE_SB1xxx_SOC |
| 140 | |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 141 | config SIBYTE_CFE_CONSOLE |
| 142 | bool "Use firmware console" |
Imre Kaloz | 05f94ee | 2009-06-02 14:22:06 +0200 | [diff] [blame] | 143 | depends on SIBYTE_SB1xxx_SOC |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 144 | help |
| 145 | Use the CFE API's console write routines during boot. Other console |
| 146 | options (VT console, sb1250 duart console, etc.) should not be |
| 147 | configured. |
| 148 | |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 149 | config SIBYTE_BUS_WATCHER |
| 150 | bool "Support for Bus Watcher statistics" |
| 151 | depends on SIBYTE_SB1xxx_SOC |
| 152 | help |
| 153 | Handle and keep statistics on the bus error interrupts (COR_ECC, |
| 154 | BAD_ECC, IO_BUS). |
| 155 | |
| 156 | config SIBYTE_BW_TRACE |
| 157 | bool "Capture bus trace before bus error" |
| 158 | depends on SIBYTE_BUS_WATCHER |
| 159 | help |
| 160 | Run a continuous bus trace, dumping the raw data as soon as |
| 161 | a ZBbus error is detected. Cannot work if ZBbus profiling |
| 162 | is turned on, and also will interfere with JTAG-based trace |
| 163 | buffer activity. Raw buffer data is dumped to console, and |
| 164 | must be processed off-line. |
| 165 | |
Ralf Baechle | 38b18f72 | 2005-02-03 14:28:23 +0000 | [diff] [blame] | 166 | config SIBYTE_TBPROF |
Ralf Baechle | bb9b813 | 2007-03-09 15:59:56 +0000 | [diff] [blame] | 167 | tristate "Support for ZBbus profiling" |
| 168 | depends on SIBYTE_HAS_ZBUS_PROFILING |
| 169 | |
| 170 | config SIBYTE_HAS_ZBUS_PROFILING |
| 171 | bool |