blob: 80e7d386ce3452e3776e70771233eea336a81e98 [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -06001#include "tegra20.dtsi"
Thierry Reding307e28e2012-09-20 17:06:06 +02002
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
Stephen Warren553c0a22013-12-09 14:43:59 -07007 aliases {
8 rtc0 = "/i2c@7000d000/tps6586x@34";
9 rtc1 = "/rtc@7000e000";
10 };
11
Thierry Reding307e28e2012-09-20 17:06:06 +020012 memory {
13 reg = <0x00000000 0x20000000>;
14 };
15
Stephen Warren58ecb232013-11-25 17:53:16 -070016 host1x@50000000 {
17 hdmi@54280000 {
Thierry Redinge6f09792012-11-16 16:56:50 +010018 vdd-supply = <&hdmi_vdd_reg>;
19 pll-supply = <&hdmi_pll_reg>;
20
21 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070022 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 GPIO_ACTIVE_HIGH>;
Thierry Redinge6f09792012-11-16 16:56:50 +010024 };
25 };
26
Stephen Warren58ecb232013-11-25 17:53:16 -070027 pinmux@70000014 {
Thierry Reding307e28e2012-09-20 17:06:06 +020028 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 ata {
33 nvidia,pins = "ata";
34 nvidia,function = "ide";
35 };
36 atb {
37 nvidia,pins = "atb", "gma", "gme";
38 nvidia,function = "sdio4";
39 };
40 atc {
41 nvidia,pins = "atc";
42 nvidia,function = "nand";
43 };
44 atd {
45 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
46 "spia", "spib", "spic";
47 nvidia,function = "gmi";
48 };
49 cdev1 {
50 nvidia,pins = "cdev1";
51 nvidia,function = "plla_out";
52 };
53 cdev2 {
54 nvidia,pins = "cdev2";
55 nvidia,function = "pllp_out4";
56 };
57 crtp {
58 nvidia,pins = "crtp";
59 nvidia,function = "crt";
60 };
61 csus {
62 nvidia,pins = "csus";
63 nvidia,function = "vi_sensor_clk";
64 };
65 dap1 {
66 nvidia,pins = "dap1";
67 nvidia,function = "dap1";
68 };
69 dap2 {
70 nvidia,pins = "dap2";
71 nvidia,function = "dap2";
72 };
73 dap3 {
74 nvidia,pins = "dap3";
75 nvidia,function = "dap3";
76 };
77 dap4 {
78 nvidia,pins = "dap4";
79 nvidia,function = "dap4";
80 };
Thierry Reding307e28e2012-09-20 17:06:06 +020081 dta {
82 nvidia,pins = "dta", "dtd";
83 nvidia,function = "sdio2";
84 };
85 dtb {
86 nvidia,pins = "dtb", "dtc", "dte";
87 nvidia,function = "rsvd1";
88 };
89 dtf {
90 nvidia,pins = "dtf";
91 nvidia,function = "i2c3";
92 };
93 gmc {
94 nvidia,pins = "gmc";
95 nvidia,function = "uartd";
96 };
97 gpu7 {
98 nvidia,pins = "gpu7";
99 nvidia,function = "rtck";
100 };
101 gpv {
102 nvidia,pins = "gpv", "slxa", "slxk";
103 nvidia,function = "pcie";
104 };
105 hdint {
Thierry Redingec319902012-11-09 14:04:50 +0100106 nvidia,pins = "hdint";
Thierry Reding307e28e2012-09-20 17:06:06 +0200107 nvidia,function = "hdmi";
108 };
109 i2cp {
110 nvidia,pins = "i2cp";
111 nvidia,function = "i2cp";
112 };
113 irrx {
114 nvidia,pins = "irrx", "irtx";
115 nvidia,function = "uarta";
116 };
117 kbca {
118 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
119 "kbce", "kbcf";
120 nvidia,function = "kbc";
121 };
122 lcsn {
123 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
124 "ld3", "ld4", "ld5", "ld6", "ld7",
125 "ld8", "ld9", "ld10", "ld11", "ld12",
126 "ld13", "ld14", "ld15", "ld16", "ld17",
127 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
128 "lhs", "lm0", "lm1", "lpp", "lpw0",
129 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
130 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
131 "lvs";
132 nvidia,function = "displaya";
133 };
134 owc {
135 nvidia,pins = "owc", "spdi", "spdo", "uac";
136 nvidia,function = "rsvd2";
137 };
138 pmc {
139 nvidia,pins = "pmc";
140 nvidia,function = "pwr_on";
141 };
142 rm {
143 nvidia,pins = "rm";
144 nvidia,function = "i2c1";
145 };
146 sdb {
147 nvidia,pins = "sdb", "sdc", "sdd";
148 nvidia,function = "pwm";
149 };
150 sdio1 {
151 nvidia,pins = "sdio1";
152 nvidia,function = "sdio1";
153 };
154 slxc {
155 nvidia,pins = "slxc", "slxd";
156 nvidia,function = "spdif";
157 };
158 spid {
159 nvidia,pins = "spid", "spie", "spif";
160 nvidia,function = "spi1";
161 };
162 spig {
163 nvidia,pins = "spig", "spih";
164 nvidia,function = "spi2_alt";
165 };
166 uaa {
167 nvidia,pins = "uaa", "uab", "uda";
168 nvidia,function = "ulpi";
169 };
170 uad {
171 nvidia,pins = "uad";
172 nvidia,function = "irda";
173 };
174 uca {
175 nvidia,pins = "uca", "ucb";
176 nvidia,function = "uartc";
177 };
178 conf_ata {
179 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
180 "cdev1", "cdev2", "dap1", "dtb", "gma",
181 "gmb", "gmc", "gmd", "gme", "gpu7",
182 "gpv", "i2cp", "pta", "rm", "slxa",
183 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200186 };
187 conf_ck32 {
188 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
189 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200191 };
192 conf_csus {
193 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530194 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
195 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200196 };
197 conf_crtp {
198 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
199 "dtc", "dte", "dtf", "gpu", "sdio1",
200 "slxc", "slxd", "spdi", "spdo", "spig",
201 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200204 };
205 conf_ddc {
206 nvidia,pins = "ddc", "dta", "dtd", "kbca",
207 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
208 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200211 };
212 conf_hdint {
213 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
214 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
215 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530216 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200217 };
218 conf_irrx {
219 nvidia,pins = "irrx", "irtx", "sdd", "spic",
220 "spie", "spih", "uaa", "uab", "uad",
221 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530222 nvidia,pull = <TEGRA_PIN_PULL_UP>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200224 };
225 conf_lc {
226 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200228 };
229 conf_ld0 {
230 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
231 "ld5", "ld6", "ld7", "ld8", "ld9",
232 "ld10", "ld11", "ld12", "ld13", "ld14",
233 "ld15", "ld16", "ld17", "ldi", "lhp0",
234 "lhp1", "lhp2", "lhs", "lm0", "lpp",
235 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
236 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200238 };
239 conf_ld17_0 {
240 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
241 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530242 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200243 };
244 };
Thierry Redingec319902012-11-09 14:04:50 +0100245
246 state_i2cmux_ddc: pinmux_i2cmux_ddc {
247 ddc {
248 nvidia,pins = "ddc";
249 nvidia,function = "i2c2";
250 };
251 pta {
252 nvidia,pins = "pta";
253 nvidia,function = "rsvd4";
254 };
255 };
256
257 state_i2cmux_pta: pinmux_i2cmux_pta {
258 ddc {
259 nvidia,pins = "ddc";
260 nvidia,function = "rsvd4";
261 };
262 pta {
263 nvidia,pins = "pta";
264 nvidia,function = "i2c2";
265 };
266 };
267
268 state_i2cmux_idle: pinmux_i2cmux_idle {
269 ddc {
270 nvidia,pins = "ddc";
271 nvidia,function = "rsvd4";
272 };
273 pta {
274 nvidia,pins = "pta";
275 nvidia,function = "rsvd4";
276 };
277 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200278 };
279
280 i2s@70002800 {
281 status = "okay";
282 };
283
284 serial@70006300 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200285 status = "okay";
286 };
287
288 i2c@7000c000 {
289 clock-frequency = <400000>;
290 status = "okay";
291 };
292
Thierry Redingec319902012-11-09 14:04:50 +0100293 i2c@7000c400 {
294 clock-frequency = <100000>;
295 status = "okay";
296 };
297
298 i2cmux {
299 compatible = "i2c-mux-pinctrl";
300 #address-cells = <1>;
301 #size-cells = <0>;
302
303 i2c-parent = <&{/i2c@7000c400}>;
304
305 pinctrl-names = "ddc", "pta", "idle";
306 pinctrl-0 = <&state_i2cmux_ddc>;
307 pinctrl-1 = <&state_i2cmux_pta>;
308 pinctrl-2 = <&state_i2cmux_idle>;
309
Thierry Redinge6f09792012-11-16 16:56:50 +0100310 hdmi_ddc: i2c@0 {
Thierry Redingec319902012-11-09 14:04:50 +0100311 reg = <0>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 };
315
316 i2c@1 {
317 reg = <1>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 };
321 };
322
Thierry Reding307e28e2012-09-20 17:06:06 +0200323 i2c@7000d000 {
324 clock-frequency = <400000>;
325 status = "okay";
326
327 pmic: tps6586x@34 {
328 compatible = "ti,tps6586x";
329 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700330 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200331
332 ti,system-power-controller;
333
334 #gpio-cells = <2>;
335 gpio-controller;
336
Alban Bedel23e63342014-06-19 15:25:49 +0200337 /* vdd_5v0_reg must be provided by the base board */
Thierry Reding307e28e2012-09-20 17:06:06 +0200338 sys-supply = <&vdd_5v0_reg>;
339 vin-sm0-supply = <&sys_reg>;
340 vin-sm1-supply = <&sys_reg>;
341 vin-sm2-supply = <&sys_reg>;
342 vinldo01-supply = <&sm2_reg>;
343 vinldo23-supply = <&sm2_reg>;
344 vinldo4-supply = <&sm2_reg>;
345 vinldo678-supply = <&sm2_reg>;
346 vinldo9-supply = <&sm2_reg>;
347
348 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600349 sys_reg: sys {
Thierry Reding307e28e2012-09-20 17:06:06 +0200350 regulator-name = "vdd_sys";
351 regulator-always-on;
352 };
353
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600354 sm0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200355 regulator-name = "vdd_sys_sm0,vdd_core";
356 regulator-min-microvolt = <1200000>;
357 regulator-max-microvolt = <1200000>;
358 regulator-always-on;
359 };
360
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600361 sm1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200362 regulator-name = "vdd_sys_sm1,vdd_cpu";
363 regulator-min-microvolt = <1000000>;
364 regulator-max-microvolt = <1000000>;
365 regulator-always-on;
366 };
367
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600368 sm2_reg: sm2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200369 regulator-name = "vdd_sys_sm2,vin_ldo*";
370 regulator-min-microvolt = <3700000>;
371 regulator-max-microvolt = <3700000>;
372 regulator-always-on;
373 };
374
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200375 pci_clk_reg: ldo0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200376 regulator-name = "vdd_ldo0,vddio_pex_clk";
377 regulator-min-microvolt = <3300000>;
378 regulator-max-microvolt = <3300000>;
379 };
380
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600381 ldo1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200382 regulator-name = "vdd_ldo1,avdd_pll*";
383 regulator-min-microvolt = <1100000>;
384 regulator-max-microvolt = <1100000>;
385 regulator-always-on;
386 };
387
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600388 ldo2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200389 regulator-name = "vdd_ldo2,vdd_rtc";
390 regulator-min-microvolt = <1200000>;
391 regulator-max-microvolt = <1200000>;
392 };
393
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600394 ldo3 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200395 regulator-name = "vdd_ldo3,avdd_usb*";
396 regulator-min-microvolt = <3300000>;
397 regulator-max-microvolt = <3300000>;
398 regulator-always-on;
399 };
400
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600401 ldo4 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200402 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
403 regulator-min-microvolt = <1800000>;
404 regulator-max-microvolt = <1800000>;
405 regulator-always-on;
406 };
407
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600408 ldo5 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200409 regulator-name = "vdd_ldo5,vcore_mmc";
410 regulator-min-microvolt = <2850000>;
411 regulator-max-microvolt = <2850000>;
412 };
413
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600414 ldo6 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200415 regulator-name = "vdd_ldo6,avdd_vdac";
416 /*
417 * According to the Tegra 2 Automotive
418 * DataSheet, a typical value for this
419 * would be 2.8V, but the PMIC only
420 * supports 2.85V.
421 */
422 regulator-min-microvolt = <2850000>;
423 regulator-max-microvolt = <2850000>;
424 };
425
Thierry Redinge6f09792012-11-16 16:56:50 +0100426 hdmi_vdd_reg: ldo7 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200427 regulator-name = "vdd_ldo7,avdd_hdmi";
428 regulator-min-microvolt = <3300000>;
429 regulator-max-microvolt = <3300000>;
430 };
431
Thierry Redinge6f09792012-11-16 16:56:50 +0100432 hdmi_pll_reg: ldo8 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200433 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
434 regulator-min-microvolt = <1800000>;
435 regulator-max-microvolt = <1800000>;
436 };
437
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600438 ldo9 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200439 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
440 /*
441 * According to the Tegra 2 Automotive
442 * DataSheet, a typical value for this
443 * would be 2.8V, but the PMIC only
444 * supports 2.85V.
445 */
446 regulator-min-microvolt = <2850000>;
447 regulator-max-microvolt = <2850000>;
448 regulator-always-on;
449 };
450
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600451 ldo_rtc {
Thierry Reding307e28e2012-09-20 17:06:06 +0200452 regulator-name = "vdd_rtc_out";
453 regulator-min-microvolt = <3300000>;
454 regulator-max-microvolt = <3300000>;
455 regulator-always-on;
456 };
457 };
458 };
Thierry Reding840a4082012-11-09 23:00:08 +0100459
460 temperature-sensor@4c {
461 compatible = "onnn,nct1008";
462 reg = <0x4c>;
463 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200464 };
465
Stephen Warren58ecb232013-11-25 17:53:16 -0700466 pmc@7000e400 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200467 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800468 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800469 nvidia,cpu-pwr-good-time = <5000>;
470 nvidia,cpu-pwr-off-time = <5000>;
471 nvidia,core-pwr-good-time = <3845 3845>;
472 nvidia,core-pwr-off-time = <3875>;
473 nvidia,sys-clock-req-active-high;
Thierry Reding307e28e2012-09-20 17:06:06 +0200474 };
475
Stephen Warren58ecb232013-11-25 17:53:16 -0700476 pcie-controller@80003000 {
Thierry Redingcca86142014-05-28 16:49:12 +0200477 avdd-pex-supply = <&pci_vdd_reg>;
478 vdd-pex-supply = <&pci_vdd_reg>;
479 avdd-pex-pll-supply = <&pci_vdd_reg>;
480 avdd-plle-supply = <&pci_vdd_reg>;
481 vddio-pex-clk-supply = <&pci_clk_reg>;
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200482 };
483
Thierry Reding307e28e2012-09-20 17:06:06 +0200484 usb@c5008000 {
485 status = "okay";
486 };
487
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530488 usb-phy@c5008000 {
489 status = "okay";
490 };
491
Thierry Reding307e28e2012-09-20 17:06:06 +0200492 sdhci@c8000600 {
Stephen Warren3325f1b2013-02-12 17:25:15 -0700493 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
494 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200495 bus-width = <4>;
496 status = "okay";
497 };
498
Joseph Lo7021d122013-04-03 19:31:27 +0800499 clocks {
500 compatible = "simple-bus";
501 #address-cells = <1>;
502 #size-cells = <0>;
503
Stephen Warren58ecb232013-11-25 17:53:16 -0700504 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800505 compatible = "fixed-clock";
506 reg=<0>;
507 #clock-cells = <0>;
508 clock-frequency = <32768>;
509 };
510 };
511
Thierry Reding307e28e2012-09-20 17:06:06 +0200512 regulators {
513 compatible = "simple-bus";
514
515 #address-cells = <1>;
516 #size-cells = <0>;
517
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200518 pci_vdd_reg: regulator@1 {
519 compatible = "regulator-fixed";
520 reg = <1>;
521 regulator-name = "vdd_1v05";
522 regulator-min-microvolt = <1050000>;
523 regulator-max-microvolt = <1050000>;
524 gpio = <&pmic 2 0>;
525 enable-active-high;
526 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200527 };
528};