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Stefan Agner99db3982014-04-03 17:47:10 +02001/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
Stefan Agner99db3982014-04-03 17:47:10 +020010#include "vf610.dtsi"
11
12/ {
13 model = "Toradex Colibri VF61 COM";
Stefan Agner10f34a12014-07-18 16:25:18 +020014 compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
Stefan Agner99db3982014-04-03 17:47:10 +020015
16 memory {
17 reg = <0x80000000 0x10000000>;
18 };
19
20 clocks {
21 enet_ext {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <50000000>;
25 };
26 };
27
Bhuvanchandra DVbc202652014-09-22 15:38:12 +053028 bl: backlight {
29 compatible = "pwm-backlight";
30 pwms = <&pwm0 0 5000000 0>;
31 status = "disabled";
32 };
Stefan Agner99db3982014-04-03 17:47:10 +020033};
34
Sanchayan Maityafe25632014-09-26 18:07:22 +053035&adc0 {
36 status = "okay";
37};
38
39&adc1 {
40 status = "okay";
41};
42
Stefan Agnerefb45b32014-11-02 21:36:46 +010043&edma0 {
44 status = "okay";
45};
46
Stefan Agner99db3982014-04-03 17:47:10 +020047&esdhc1 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_esdhc1>;
50 bus-width = <4>;
Stefan Agner99db3982014-04-03 17:47:10 +020051};
52
53&fec1 {
54 phy-mode = "rmii";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_fec1>;
Stefan Agner99db3982014-04-03 17:47:10 +020057};
58
59&L2 {
60 arm,data-latency = <2 1 2>;
61 arm,tag-latency = <3 2 3>;
62};
63
Bhuvanchandra DV9c42fa12014-09-22 15:38:11 +053064&pwm0 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_pwm0>;
67};
68
69&pwm1 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_pwm1>;
72};
73
Stefan Agner99db3982014-04-03 17:47:10 +020074&uart0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_uart0>;
Stefan Agner99db3982014-04-03 17:47:10 +020077};
78
79&uart1 {
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_uart1>;
Stefan Agner99db3982014-04-03 17:47:10 +020082};
83
84&uart2 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_uart2>;
Stefan Agner99db3982014-04-03 17:47:10 +020087};
88
Stefan Agner05009532014-08-18 22:07:16 +020089&usbdev0 {
90 disable-over-current;
91 status = "okay";
92};
93
94&usbh1 {
95 disable-over-current;
96 status = "okay";
97};
98
Stefan Agnerefb45b32014-11-02 21:36:46 +010099&usbphy0 {
100 status = "okay";
101};
102
103&usbphy1 {
104 status = "okay";
105};
106
Stefan Agner99db3982014-04-03 17:47:10 +0200107&iomuxc {
108 vf610-colibri {
109 pinctrl_esdhc1: esdhc1grp {
Stefan Agner10f34a12014-07-18 16:25:18 +0200110 fsl,pins = <
Stefan Agner99db3982014-04-03 17:47:10 +0200111 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
112 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
113 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
114 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
115 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
116 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
117 VF610_PAD_PTB20__GPIO_42 0x219d
118 >;
119 };
120
121 pinctrl_fec1: fec1grp {
122 fsl,pins = <
123 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
124 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
125 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
126 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
127 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
128 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
129 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
130 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
131 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
132 >;
133 };
134
Bhuvanchandra DV9c42fa12014-09-22 15:38:11 +0530135 pinctrl_pwm0: pwm0grp {
136 fsl,pins = <
137 VF610_PAD_PTB0__FTM0_CH0 0x1182
138 VF610_PAD_PTB1__FTM0_CH1 0x1182
139 >;
140 };
141
142 pinctrl_pwm1: pwm1grp {
143 fsl,pins = <
144 VF610_PAD_PTB8__FTM1_CH0 0x1182
145 VF610_PAD_PTB9__FTM1_CH1 0x1182
146 >;
147 };
148
Stefan Agner99db3982014-04-03 17:47:10 +0200149 pinctrl_uart0: uart0grp {
150 fsl,pins = <
151 VF610_PAD_PTB10__UART0_TX 0x21a2
152 VF610_PAD_PTB11__UART0_RX 0x21a1
153 >;
154 };
155
156 pinctrl_uart1: uart1grp {
157 fsl,pins = <
158 VF610_PAD_PTB4__UART1_TX 0x21a2
159 VF610_PAD_PTB5__UART1_RX 0x21a1
160 >;
161 };
162
163 pinctrl_uart2: uart2grp {
164 fsl,pins = <
165 VF610_PAD_PTD0__UART2_TX 0x21a2
166 VF610_PAD_PTD1__UART2_RX 0x21a1
167 VF610_PAD_PTD2__UART2_RTS 0x21a2
168 VF610_PAD_PTD3__UART2_CTS 0x21a1
169 >;
170 };
171 };
172};