blob: 631e4f24aea6424ef265fa1dcb8b4d81a5966eb3 [file] [log] [blame]
Abylay Ospanc184dcd2009-03-03 11:06:00 -03001/*
2 * cimax2.c
3 *
4 * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
5 *
6 * Copyright (C) 2009 NetUP Inc.
7 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
8 * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
Abylay Ospanc184dcd2009-03-03 11:06:00 -030020 */
21
22#include "cx23885.h"
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -030023#include "cimax2.h"
Abylay Ospanc184dcd2009-03-03 11:06:00 -030024#include "dvb_ca_en50221.h"
Mauro Carvalho Chehab278ba83a2013-11-02 06:17:47 -030025
26/* Max transfer size done by I2C transfer functions */
27#define MAX_XFER_SIZE 64
28
Abylay Ospanc184dcd2009-03-03 11:06:00 -030029/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
30 bits 31-16
31+-----------+
32| Reserved |
33+-----------+
34 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
35+-------+-------+-------+-------+-------+-------+-------+-------+
36| WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
37+-------+-------+-------+-------+-------+-------+-------+-------+
38 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
39+-------+-------+-------+-------+-------+-------+-------+-------+
40| DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
41+-------+-------+-------+-------+-------+-------+-------+-------+
42***/
43/* MC417 */
44#define NETUP_DATA 0x000000ff
45#define NETUP_WR 0x00008000
46#define NETUP_RD 0x00004000
47#define NETUP_ACK 0x00001000
48#define NETUP_ADHI 0x00000800
49#define NETUP_ADLO 0x00000400
50#define NETUP_CS1 0x00000200
51#define NETUP_CS0 0x00000100
52#define NETUP_EN_ALL 0x00001000
53#define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
54#define NETUP_CI_CTL 0x04
55#define NETUP_CI_RD 1
56
Abylay Ospan21508b9a2009-12-12 12:16:56 -030057#define NETUP_IRQ_DETAM 0x1
58#define NETUP_IRQ_IRQAM 0x4
Abylay Ospanc184dcd2009-03-03 11:06:00 -030059
60static unsigned int ci_dbg;
61module_param(ci_dbg, int, 0644);
62MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
63
Abylay Ospan2a8f9602010-03-06 15:46:39 -030064static unsigned int ci_irq_enable;
65module_param(ci_irq_enable, int, 0644);
66MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
67
Abylay Ospanc184dcd2009-03-03 11:06:00 -030068#define ci_dbg_print(args...) \
69 do { \
70 if (ci_dbg) \
71 printk(KERN_DEBUG args); \
72 } while (0)
73
Abylay Ospan2a8f9602010-03-06 15:46:39 -030074#define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
75
Abylay Ospanc184dcd2009-03-03 11:06:00 -030076/* stores all private variables for communication with CI */
77struct netup_ci_state {
78 struct dvb_ca_en50221 ca;
79 struct mutex ca_mutex;
80 struct i2c_adapter *i2c_adap;
81 u8 ci_i2c_addr;
82 int status;
83 struct work_struct work;
84 void *priv;
Abylay Ospan21508b9a2009-12-12 12:16:56 -030085 u8 current_irq_mode;
86 int current_ci_flag;
87 unsigned long next_status_checked_time;
Abylay Ospanc184dcd2009-03-03 11:06:00 -030088};
89
Abylay Ospanc184dcd2009-03-03 11:06:00 -030090
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -030091static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
Abylay Ospanc184dcd2009-03-03 11:06:00 -030092 u8 *buf, int len)
93{
94 int ret;
95 struct i2c_msg msg[] = {
96 {
97 .addr = addr,
98 .flags = 0,
99 .buf = &reg,
100 .len = 1
101 }, {
102 .addr = addr,
103 .flags = I2C_M_RD,
104 .buf = buf,
105 .len = len
106 }
107 };
108
109 ret = i2c_transfer(i2c_adap, msg, 2);
110
111 if (ret != 2) {
112 ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
113 __func__, reg, ret);
114
115 return -1;
116 }
117
118 ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
119 __func__, addr, reg, buf[0]);
120
121 return 0;
122}
123
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -0300124static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300125 u8 *buf, int len)
126{
127 int ret;
Mauro Carvalho Chehab278ba83a2013-11-02 06:17:47 -0300128 u8 buffer[MAX_XFER_SIZE];
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300129
130 struct i2c_msg msg = {
131 .addr = addr,
132 .flags = 0,
133 .buf = &buffer[0],
134 .len = len + 1
135 };
136
Mauro Carvalho Chehab278ba83a2013-11-02 06:17:47 -0300137 if (1 + len > sizeof(buffer)) {
138 printk(KERN_WARNING
139 "%s: i2c wr reg=%04x: len=%d is too big!\n",
140 KBUILD_MODNAME, reg, len);
141 return -EINVAL;
142 }
143
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300144 buffer[0] = reg;
145 memcpy(&buffer[1], buf, len);
146
147 ret = i2c_transfer(i2c_adap, &msg, 1);
148
149 if (ret != 1) {
150 ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
151 __func__, reg, ret);
152 return -1;
153 }
154
155 return 0;
156}
157
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -0300158static int netup_ci_get_mem(struct cx23885_dev *dev)
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300159{
160 int mem;
161 unsigned long timeout = jiffies + msecs_to_jiffies(1);
162
163 for (;;) {
164 mem = cx_read(MC417_RWD);
165 if ((mem & NETUP_ACK) == 0)
166 break;
167 if (time_after(jiffies, timeout))
168 break;
169 udelay(1);
170 }
171
172 cx_set(MC417_RWD, NETUP_CTRL_OFF);
173
174 return mem & 0xff;
175}
176
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -0300177static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
Abylay Ospanf1bee692009-03-17 18:13:52 -0300178 u8 flag, u8 read, int addr, u8 data)
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300179{
180 struct netup_ci_state *state = en50221->data;
181 struct cx23885_tsport *port = state->priv;
182 struct cx23885_dev *dev = port->dev;
183
184 u8 store;
185 int mem;
186 int ret;
187
188 if (0 != slot)
189 return -EINVAL;
190
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300191 if (state->current_ci_flag != flag) {
192 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
193 0, &store, 1);
194 if (ret != 0)
195 return ret;
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300196
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300197 store &= ~0x0c;
198 store |= flag;
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300199
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300200 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
201 0, &store, 1);
202 if (ret != 0)
203 return ret;
Peter Senna Tschudinc2c1b412012-09-28 05:37:22 -0300204 }
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300205 state->current_ci_flag = flag;
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300206
Abylay Ospan8386c27f2009-09-16 13:08:06 -0300207 mutex_lock(&dev->gpio_lock);
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300208
209 /* write addr */
210 cx_write(MC417_OEN, NETUP_EN_ALL);
211 cx_write(MC417_RWD, NETUP_CTRL_OFF |
212 NETUP_ADLO | (0xff & addr));
213 cx_clear(MC417_RWD, NETUP_ADLO);
214 cx_write(MC417_RWD, NETUP_CTRL_OFF |
215 NETUP_ADHI | (0xff & (addr >> 8)));
216 cx_clear(MC417_RWD, NETUP_ADHI);
217
Abylay Ospan8386c27f2009-09-16 13:08:06 -0300218 if (read) { /* data in */
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300219 cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
Abylay Ospan8386c27f2009-09-16 13:08:06 -0300220 } else /* data out */
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300221 cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
222
223 /* choose chip */
224 cx_clear(MC417_RWD,
225 (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
226 /* read/write */
227 cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
228 mem = netup_ci_get_mem(dev);
229
Abylay Ospan8386c27f2009-09-16 13:08:06 -0300230 mutex_unlock(&dev->gpio_lock);
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300231
232 if (!read)
233 if (mem < 0)
234 return -EREMOTEIO;
235
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300236 ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
237 (read) ? "read" : "write", state->ci_i2c_addr, addr,
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300238 (flag == NETUP_CI_CTL) ? "ctl" : "mem",
239 (read) ? mem : data);
240
241 if (read)
242 return mem;
243
244 return 0;
245}
246
247int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
248 int slot, int addr)
249{
250 return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
251}
252
253int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
254 int slot, int addr, u8 data)
255{
256 return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
257}
258
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -0300259int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
260 u8 addr)
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300261{
262 return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
263 NETUP_CI_RD, addr, 0);
264}
265
266int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
267 u8 addr, u8 data)
268{
269 return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
270}
271
272int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
273{
274 struct netup_ci_state *state = en50221->data;
275 u8 buf = 0x80;
276 int ret;
277
278 if (0 != slot)
279 return -EINVAL;
280
281 udelay(500);
282 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
283 0, &buf, 1);
284
285 if (ret != 0)
286 return ret;
287
288 udelay(500);
289
290 buf = 0x00;
291 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
292 0, &buf, 1);
293
294 msleep(1000);
295 dvb_ca_en50221_camready_irq(&state->ca, 0);
296
297 return 0;
298
299}
300
301int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
302{
303 /* not implemented */
304 return 0;
305}
306
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -0300307static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300308{
309 struct netup_ci_state *state = en50221->data;
310 int ret;
311
312 if (irq_mode == state->current_irq_mode)
313 return 0;
314
315 ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
316 __func__, state->ci_i2c_addr, irq_mode);
317 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
318 0x1b, &irq_mode, 1);
319
320 if (ret != 0)
321 return ret;
322
323 state->current_irq_mode = irq_mode;
324
325 return 0;
326}
327
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300328int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
329{
330 struct netup_ci_state *state = en50221->data;
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300331 u8 buf;
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300332
333 if (0 != slot)
334 return -EINVAL;
335
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300336 netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
337 0, &buf, 1);
338 buf |= 0x60;
339
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300340 return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
341 0, &buf, 1);
342}
343
344/* work handler */
345static void netup_read_ci_status(struct work_struct *work)
346{
347 struct netup_ci_state *state =
348 container_of(work, struct netup_ci_state, work);
349 u8 buf[33];
350 int ret;
351
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300352 /* CAM module IRQ processing. fast operation */
353 dvb_ca_en50221_frda_irq(&state->ca, 0);
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300354
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300355 /* CAM module INSERT/REMOVE processing. slow operation because of i2c
356 * transfers */
357 if (time_after(jiffies, state->next_status_checked_time)
358 || !state->status) {
359 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
360 0, &buf[0], 33);
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300361
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300362 state->next_status_checked_time = jiffies
363 + msecs_to_jiffies(1000);
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300364
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300365 if (ret != 0)
366 return;
367
368 ci_dbg_print("%s: Slot Status Addr=[0x%04x], "
369 "Reg=[0x%02x], data=%02x, "
370 "TS config = %02x\n", __func__,
371 state->ci_i2c_addr, 0, buf[0],
372 buf[0]);
373
374
375 if (buf[0] & 1)
376 state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
377 DVB_CA_EN50221_POLL_CAM_READY;
378 else
379 state->status = 0;
Igor M. Liplianinebce9a32010-12-31 02:04:38 -0300380 }
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300381}
382
383/* CI irq handler */
384int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
385{
386 struct cx23885_tsport *port = NULL;
387 struct netup_ci_state *state = NULL;
388
Igor M. Liplianinebce9a32010-12-31 02:04:38 -0300389 ci_dbg_print("%s:\n", __func__);
390
391 if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300392 return 0;
393
Igor M. Liplianinebce9a32010-12-31 02:04:38 -0300394 if (pci_status & PCI_MSK_GPIO0) {
395 port = &dev->ts1;
396 state = port->port_priv;
397 schedule_work(&state->work);
398 ci_dbg_print("%s: Wakeup CI0\n", __func__);
399 }
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300400
Igor M. Liplianinebce9a32010-12-31 02:04:38 -0300401 if (pci_status & PCI_MSK_GPIO1) {
402 port = &dev->ts2;
403 state = port->port_priv;
404 schedule_work(&state->work);
405 ci_dbg_print("%s: Wakeup CI1\n", __func__);
406 }
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300407
408 return 1;
409}
410
Mauro Carvalho Chehabada73ee2012-10-27 11:29:23 -0300411int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
412 int slot, int open)
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300413{
414 struct netup_ci_state *state = en50221->data;
415
416 if (0 != slot)
417 return -EINVAL;
418
Abylay Ospan2a8f9602010-03-06 15:46:39 -0300419 netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300420 : NETUP_IRQ_DETAM);
421
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300422 return state->status;
423}
424
425int netup_ci_init(struct cx23885_tsport *port)
426{
427 struct netup_ci_state *state;
428 u8 cimax_init[34] = {
429 0x00, /* module A control*/
430 0x00, /* auto select mask high A */
431 0x00, /* auto select mask low A */
432 0x00, /* auto select pattern high A */
433 0x00, /* auto select pattern low A */
434 0x44, /* memory access time A */
435 0x00, /* invert input A */
436 0x00, /* RFU */
437 0x00, /* RFU */
438 0x00, /* module B control*/
439 0x00, /* auto select mask high B */
440 0x00, /* auto select mask low B */
441 0x00, /* auto select pattern high B */
442 0x00, /* auto select pattern low B */
443 0x44, /* memory access time B */
444 0x00, /* invert input B */
445 0x00, /* RFU */
446 0x00, /* RFU */
447 0x00, /* auto select mask high Ext */
448 0x00, /* auto select mask low Ext */
449 0x00, /* auto select pattern high Ext */
450 0x00, /* auto select pattern low Ext */
451 0x00, /* RFU */
452 0x02, /* destination - module A */
453 0x01, /* power on (use it like store place) */
454 0x00, /* RFU */
455 0x00, /* int status read only */
Abylay Ospan2a8f9602010-03-06 15:46:39 -0300456 ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
Abylay Ospan21508b9a2009-12-12 12:16:56 -0300457 0x05, /* EXTINT=active-high, INT=push-pull */
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300458 0x00, /* USCG1 */
459 0x04, /* ack active low */
460 0x00, /* LOCK = 0 */
461 0x33, /* serial mode, rising in, rising out, MSB first*/
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300462 0x31, /* synchronization */
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300463 };
464 int ret;
465
466 ci_dbg_print("%s\n", __func__);
467 state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
468 if (!state) {
469 ci_dbg_print("%s: Unable create CI structure!\n", __func__);
470 ret = -ENOMEM;
471 goto err;
472 }
473
474 port->port_priv = state;
475
476 switch (port->nr) {
477 case 1:
478 state->ci_i2c_addr = 0x40;
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300479 break;
480 case 2:
481 state->ci_i2c_addr = 0x41;
482 break;
483 }
484
485 state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
486 state->ca.owner = THIS_MODULE;
487 state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
488 state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
489 state->ca.read_cam_control = netup_ci_read_cam_ctl;
490 state->ca.write_cam_control = netup_ci_write_cam_ctl;
491 state->ca.slot_reset = netup_ci_slot_reset;
492 state->ca.slot_shutdown = netup_ci_slot_shutdown;
493 state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
494 state->ca.poll_slot_status = netup_poll_ci_slot_status;
495 state->ca.data = state;
496 state->priv = port;
Abylay Ospan2a8f9602010-03-06 15:46:39 -0300497 state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300498
499 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
500 0, &cimax_init[0], 34);
501 /* lock registers */
502 ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
503 0x1f, &cimax_init[0x18], 1);
504 /* power on slots */
505 ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
506 0x18, &cimax_init[0x18], 1);
507
508 if (0 != ret)
509 goto err;
510
511 ret = dvb_ca_en50221_init(&port->frontends.adapter,
512 &state->ca,
513 /* flags */ 0,
514 /* n_slots */ 1);
515 if (0 != ret)
516 goto err;
517
518 INIT_WORK(&state->work, netup_read_ci_status);
Igor M. Liplianin8db6d632009-07-20 12:27:27 -0300519 schedule_work(&state->work);
Abylay Ospanc184dcd2009-03-03 11:06:00 -0300520
521 ci_dbg_print("%s: CI initialized!\n", __func__);
522
523 return 0;
524err:
525 ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
526 kfree(state);
527 return ret;
528}
529
530void netup_ci_exit(struct cx23885_tsport *port)
531{
532 struct netup_ci_state *state;
533
534 if (NULL == port)
535 return;
536
537 state = (struct netup_ci_state *)port->port_priv;
538 if (NULL == state)
539 return;
540
541 if (NULL == state->ca.data)
542 return;
543
544 dvb_ca_en50221_release(&state->ca);
545 kfree(state);
546}