Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1 | /* |
| 2 | * wm8900.c -- WM8900 ALSA Soc Audio driver |
| 3 | * |
| 4 | * Copyright 2007, 2008 Wolfson Microelectronics PLC. |
| 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * TODO: |
| 13 | * - Tristating. |
| 14 | * - TDM. |
| 15 | * - Jack detect. |
| 16 | * - FLL source configuration, currently only MCLK is supported. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/moduleparam.h> |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/pm.h> |
| 25 | #include <linux/i2c.h> |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 26 | #include <linux/spi/spi.h> |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 27 | #include <linux/platform_device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 29 | #include <sound/core.h> |
| 30 | #include <sound/pcm.h> |
| 31 | #include <sound/pcm_params.h> |
| 32 | #include <sound/soc.h> |
| 33 | #include <sound/soc-dapm.h> |
| 34 | #include <sound/initval.h> |
| 35 | #include <sound/tlv.h> |
| 36 | |
| 37 | #include "wm8900.h" |
| 38 | |
| 39 | /* WM8900 register space */ |
| 40 | #define WM8900_REG_RESET 0x0 |
| 41 | #define WM8900_REG_ID 0x0 |
| 42 | #define WM8900_REG_POWER1 0x1 |
| 43 | #define WM8900_REG_POWER2 0x2 |
| 44 | #define WM8900_REG_POWER3 0x3 |
| 45 | #define WM8900_REG_AUDIO1 0x4 |
| 46 | #define WM8900_REG_AUDIO2 0x5 |
| 47 | #define WM8900_REG_CLOCKING1 0x6 |
| 48 | #define WM8900_REG_CLOCKING2 0x7 |
| 49 | #define WM8900_REG_AUDIO3 0x8 |
| 50 | #define WM8900_REG_AUDIO4 0x9 |
| 51 | #define WM8900_REG_DACCTRL 0xa |
| 52 | #define WM8900_REG_LDAC_DV 0xb |
| 53 | #define WM8900_REG_RDAC_DV 0xc |
| 54 | #define WM8900_REG_SIDETONE 0xd |
| 55 | #define WM8900_REG_ADCCTRL 0xe |
| 56 | #define WM8900_REG_LADC_DV 0xf |
| 57 | #define WM8900_REG_RADC_DV 0x10 |
| 58 | #define WM8900_REG_GPIO 0x12 |
| 59 | #define WM8900_REG_INCTL 0x15 |
| 60 | #define WM8900_REG_LINVOL 0x16 |
| 61 | #define WM8900_REG_RINVOL 0x17 |
| 62 | #define WM8900_REG_INBOOSTMIX1 0x18 |
| 63 | #define WM8900_REG_INBOOSTMIX2 0x19 |
| 64 | #define WM8900_REG_ADCPATH 0x1a |
| 65 | #define WM8900_REG_AUXBOOST 0x1b |
| 66 | #define WM8900_REG_ADDCTL 0x1e |
| 67 | #define WM8900_REG_FLLCTL1 0x24 |
| 68 | #define WM8900_REG_FLLCTL2 0x25 |
| 69 | #define WM8900_REG_FLLCTL3 0x26 |
| 70 | #define WM8900_REG_FLLCTL4 0x27 |
| 71 | #define WM8900_REG_FLLCTL5 0x28 |
| 72 | #define WM8900_REG_FLLCTL6 0x29 |
| 73 | #define WM8900_REG_LOUTMIXCTL1 0x2c |
| 74 | #define WM8900_REG_ROUTMIXCTL1 0x2d |
| 75 | #define WM8900_REG_BYPASS1 0x2e |
| 76 | #define WM8900_REG_BYPASS2 0x2f |
| 77 | #define WM8900_REG_AUXOUT_CTL 0x30 |
| 78 | #define WM8900_REG_LOUT1CTL 0x33 |
| 79 | #define WM8900_REG_ROUT1CTL 0x34 |
| 80 | #define WM8900_REG_LOUT2CTL 0x35 |
| 81 | #define WM8900_REG_ROUT2CTL 0x36 |
| 82 | #define WM8900_REG_HPCTL1 0x3a |
| 83 | #define WM8900_REG_OUTBIASCTL 0x73 |
| 84 | |
| 85 | #define WM8900_MAXREG 0x80 |
| 86 | |
| 87 | #define WM8900_REG_ADDCTL_OUT1_DIS 0x80 |
| 88 | #define WM8900_REG_ADDCTL_OUT2_DIS 0x40 |
| 89 | #define WM8900_REG_ADDCTL_VMID_DIS 0x20 |
| 90 | #define WM8900_REG_ADDCTL_BIAS_SRC 0x10 |
| 91 | #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04 |
| 92 | #define WM8900_REG_ADDCTL_TEMP_SD 0x02 |
| 93 | |
| 94 | #define WM8900_REG_GPIO_TEMP_ENA 0x2 |
| 95 | |
| 96 | #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100 |
| 97 | #define WM8900_REG_POWER1_BIAS_ENA 0x0008 |
| 98 | #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004 |
| 99 | #define WM8900_REG_POWER1_FLL_ENA 0x0040 |
| 100 | |
| 101 | #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000 |
| 102 | #define WM8900_REG_POWER2_ADCL_ENA 0x0002 |
| 103 | #define WM8900_REG_POWER2_ADCR_ENA 0x0001 |
| 104 | |
| 105 | #define WM8900_REG_POWER3_DACL_ENA 0x0002 |
| 106 | #define WM8900_REG_POWER3_DACR_ENA 0x0001 |
| 107 | |
| 108 | #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018 |
| 109 | #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080 |
| 110 | #define WM8900_REG_AUDIO1_BCLK_INV 0x0100 |
| 111 | |
| 112 | #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1 |
| 113 | #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100 |
| 114 | #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e) |
| 115 | #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000) |
| 116 | |
| 117 | #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0 |
| 118 | #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c |
| 119 | |
| 120 | #define WM8900_REG_DACCTRL_MUTE 0x004 |
Mark Brown | 21002e2 | 2009-06-12 17:27:52 +0100 | [diff] [blame] | 121 | #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100 |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 122 | #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400 |
| 123 | |
| 124 | #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800 |
| 125 | |
| 126 | #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800 |
| 127 | |
| 128 | #define WM8900_REG_FLLCTL1_OSC_ENA 0x100 |
| 129 | |
| 130 | #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100 |
| 131 | |
| 132 | #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80 |
| 133 | #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40 |
| 134 | #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20 |
| 135 | #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10 |
| 136 | #define WM8900_REG_HPCTL1_HP_SHORT 0x08 |
| 137 | #define WM8900_REG_HPCTL1_HP_SHORT2 0x04 |
| 138 | |
| 139 | #define WM8900_LRC_MASK 0xfc00 |
| 140 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 141 | struct wm8900_priv { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 142 | enum snd_soc_control_type control_type; |
| 143 | void *control_data; |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 144 | u16 reg_cache[WM8900_MAXREG]; |
| 145 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 146 | u32 fll_in; /* FLL input frequency */ |
| 147 | u32 fll_out; /* FLL output frequency */ |
| 148 | }; |
| 149 | |
| 150 | /* |
| 151 | * wm8900 register cache. We can't read the entire register space and we |
| 152 | * have slow control buses so we cache the registers. |
| 153 | */ |
| 154 | static const u16 wm8900_reg_defaults[WM8900_MAXREG] = { |
| 155 | 0x8900, 0x0000, |
| 156 | 0xc000, 0x0000, |
| 157 | 0x4050, 0x4000, |
| 158 | 0x0008, 0x0000, |
| 159 | 0x0040, 0x0040, |
| 160 | 0x1004, 0x00c0, |
| 161 | 0x00c0, 0x0000, |
| 162 | 0x0100, 0x00c0, |
| 163 | 0x00c0, 0x0000, |
| 164 | 0xb001, 0x0000, |
| 165 | 0x0000, 0x0044, |
| 166 | 0x004c, 0x004c, |
| 167 | 0x0044, 0x0044, |
| 168 | 0x0000, 0x0044, |
| 169 | 0x0000, 0x0000, |
| 170 | 0x0002, 0x0000, |
| 171 | 0x0000, 0x0000, |
| 172 | 0x0000, 0x0000, |
| 173 | 0x0008, 0x0000, |
| 174 | 0x0000, 0x0008, |
| 175 | 0x0097, 0x0100, |
| 176 | 0x0000, 0x0000, |
| 177 | 0x0050, 0x0050, |
| 178 | 0x0055, 0x0055, |
| 179 | 0x0055, 0x0000, |
| 180 | 0x0000, 0x0079, |
| 181 | 0x0079, 0x0079, |
| 182 | 0x0079, 0x0000, |
| 183 | /* Remaining registers all zero */ |
| 184 | }; |
| 185 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 186 | static int wm8900_volatile_register(unsigned int reg) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 187 | { |
| 188 | switch (reg) { |
| 189 | case WM8900_REG_ID: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 190 | case WM8900_REG_POWER1: |
| 191 | return 1; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 192 | default: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 193 | return 0; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 194 | } |
| 195 | } |
| 196 | |
| 197 | static void wm8900_reset(struct snd_soc_codec *codec) |
| 198 | { |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 199 | snd_soc_write(codec, WM8900_REG_RESET, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 200 | |
| 201 | memcpy(codec->reg_cache, wm8900_reg_defaults, |
Julia Lawall | bc25800 | 2009-12-13 12:43:15 +0100 | [diff] [blame] | 202 | sizeof(wm8900_reg_defaults)); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | static int wm8900_hp_event(struct snd_soc_dapm_widget *w, |
| 206 | struct snd_kcontrol *kcontrol, int event) |
| 207 | { |
| 208 | struct snd_soc_codec *codec = w->codec; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 209 | u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 210 | |
| 211 | switch (event) { |
| 212 | case SND_SOC_DAPM_PRE_PMU: |
| 213 | /* Clamp headphone outputs */ |
| 214 | hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | |
| 215 | WM8900_REG_HPCTL1_HP_CLAMP_OP; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 216 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 217 | break; |
| 218 | |
| 219 | case SND_SOC_DAPM_POST_PMU: |
| 220 | /* Enable the input stage */ |
| 221 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP; |
| 222 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | |
| 223 | WM8900_REG_HPCTL1_HP_SHORT2 | |
| 224 | WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 225 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 226 | |
| 227 | msleep(400); |
| 228 | |
| 229 | /* Enable the output stage */ |
| 230 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; |
| 231 | hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 232 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 233 | |
| 234 | /* Remove the shorts */ |
| 235 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 236 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 237 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 238 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 239 | break; |
| 240 | |
| 241 | case SND_SOC_DAPM_PRE_PMD: |
| 242 | /* Short the output */ |
| 243 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 244 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 245 | |
| 246 | /* Disable the output stage */ |
| 247 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 248 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 249 | |
| 250 | /* Clamp the outputs and power down input */ |
| 251 | hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | |
| 252 | WM8900_REG_HPCTL1_HP_CLAMP_OP; |
| 253 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 254 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 255 | break; |
| 256 | |
| 257 | case SND_SOC_DAPM_POST_PMD: |
| 258 | /* Disable everything */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 259 | snd_soc_write(codec, WM8900_REG_HPCTL1, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 260 | break; |
| 261 | |
| 262 | default: |
| 263 | BUG(); |
| 264 | } |
| 265 | |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0); |
| 270 | |
| 271 | static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0); |
| 272 | |
| 273 | static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0); |
| 274 | |
| 275 | static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0); |
| 276 | |
| 277 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); |
| 278 | |
| 279 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); |
| 280 | |
| 281 | static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0); |
| 282 | |
| 283 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1); |
| 284 | |
| 285 | static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" }; |
| 286 | |
| 287 | static const struct soc_enum mic_bias_level = |
| 288 | SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt); |
| 289 | |
| 290 | static const char *dac_mute_rate_txt[] = { "Fast", "Slow" }; |
| 291 | |
| 292 | static const struct soc_enum dac_mute_rate = |
| 293 | SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt); |
| 294 | |
| 295 | static const char *dac_deemphasis_txt[] = { |
| 296 | "Disabled", "32kHz", "44.1kHz", "48kHz" |
| 297 | }; |
| 298 | |
| 299 | static const struct soc_enum dac_deemphasis = |
| 300 | SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt); |
| 301 | |
| 302 | static const char *adc_hpf_cut_txt[] = { |
| 303 | "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3" |
| 304 | }; |
| 305 | |
| 306 | static const struct soc_enum adc_hpf_cut = |
| 307 | SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt); |
| 308 | |
| 309 | static const char *lr_txt[] = { |
| 310 | "Left", "Right" |
| 311 | }; |
| 312 | |
| 313 | static const struct soc_enum aifl_src = |
| 314 | SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt); |
| 315 | |
| 316 | static const struct soc_enum aifr_src = |
| 317 | SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt); |
| 318 | |
| 319 | static const struct soc_enum dacl_src = |
| 320 | SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt); |
| 321 | |
| 322 | static const struct soc_enum dacr_src = |
| 323 | SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt); |
| 324 | |
| 325 | static const char *sidetone_txt[] = { |
| 326 | "Disabled", "Left ADC", "Right ADC" |
| 327 | }; |
| 328 | |
| 329 | static const struct soc_enum dacl_sidetone = |
| 330 | SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt); |
| 331 | |
| 332 | static const struct soc_enum dacr_sidetone = |
| 333 | SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt); |
| 334 | |
| 335 | static const struct snd_kcontrol_new wm8900_snd_controls[] = { |
| 336 | SOC_ENUM("Mic Bias Level", mic_bias_level), |
| 337 | |
| 338 | SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0, |
| 339 | in_pga_tlv), |
| 340 | SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1), |
| 341 | SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0), |
| 342 | |
| 343 | SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0, |
| 344 | in_pga_tlv), |
| 345 | SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1), |
| 346 | SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0), |
| 347 | |
| 348 | SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1), |
| 349 | SOC_ENUM("DAC Mute Rate", dac_mute_rate), |
| 350 | SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0), |
| 351 | SOC_ENUM("DAC Deemphasis", dac_deemphasis), |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 352 | SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL, |
| 353 | 12, 1, 0), |
| 354 | |
| 355 | SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0), |
| 356 | SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut), |
| 357 | SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0), |
| 358 | SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0, |
| 359 | adc_svol_tlv), |
| 360 | SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0, |
| 361 | adc_svol_tlv), |
| 362 | SOC_ENUM("Left Digital Audio Source", aifl_src), |
| 363 | SOC_ENUM("Right Digital Audio Source", aifr_src), |
| 364 | |
| 365 | SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0, |
| 366 | dac_boost_tlv), |
| 367 | SOC_ENUM("Left DAC Source", dacl_src), |
| 368 | SOC_ENUM("Right DAC Source", dacr_src), |
| 369 | SOC_ENUM("Left DAC Sidetone", dacl_sidetone), |
| 370 | SOC_ENUM("Right DAC Sidetone", dacr_sidetone), |
| 371 | SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0), |
| 372 | |
| 373 | SOC_DOUBLE_R_TLV("Digital Playback Volume", |
| 374 | WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV, |
| 375 | 1, 96, 0, dac_tlv), |
| 376 | SOC_DOUBLE_R_TLV("Digital Capture Volume", |
| 377 | WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv), |
| 378 | |
| 379 | SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0, |
| 380 | out_mix_tlv), |
| 381 | SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0, |
| 382 | out_mix_tlv), |
| 383 | SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0, |
| 384 | out_mix_tlv), |
| 385 | SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0, |
| 386 | out_mix_tlv), |
| 387 | |
| 388 | SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0, |
| 389 | out_mix_tlv), |
| 390 | SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0, |
| 391 | out_mix_tlv), |
| 392 | SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0, |
| 393 | out_mix_tlv), |
| 394 | SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0, |
| 395 | out_mix_tlv), |
| 396 | |
| 397 | SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0, |
| 398 | in_boost_tlv), |
| 399 | SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0, |
| 400 | in_boost_tlv), |
| 401 | SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0, |
| 402 | in_boost_tlv), |
| 403 | SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0, |
| 404 | in_boost_tlv), |
| 405 | SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0, |
| 406 | in_boost_tlv), |
| 407 | SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0, |
| 408 | in_boost_tlv), |
| 409 | |
| 410 | SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, |
| 411 | 0, 63, 0, out_pga_tlv), |
| 412 | SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, |
| 413 | 6, 1, 1), |
| 414 | SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, |
| 415 | 7, 1, 0), |
| 416 | |
| 417 | SOC_DOUBLE_R_TLV("LINEOUT2 Volume", |
| 418 | WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, |
| 419 | 0, 63, 0, out_pga_tlv), |
| 420 | SOC_DOUBLE_R("LINEOUT2 Switch", |
| 421 | WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1), |
| 422 | SOC_DOUBLE_R("LINEOUT2 ZC Switch", |
| 423 | WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0), |
| 424 | SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1, |
| 425 | 0, 1, 1), |
| 426 | |
| 427 | }; |
| 428 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 429 | static const struct snd_kcontrol_new wm8900_dapm_loutput2_control = |
| 430 | SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0); |
| 431 | |
| 432 | static const struct snd_kcontrol_new wm8900_dapm_routput2_control = |
| 433 | SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0); |
| 434 | |
| 435 | static const struct snd_kcontrol_new wm8900_loutmix_controls[] = { |
| 436 | SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0), |
| 437 | SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0), |
| 438 | SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0), |
| 439 | SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0), |
| 440 | SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0), |
| 441 | }; |
| 442 | |
| 443 | static const struct snd_kcontrol_new wm8900_routmix_controls[] = { |
| 444 | SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0), |
| 445 | SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0), |
| 446 | SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0), |
| 447 | SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0), |
| 448 | SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0), |
| 449 | }; |
| 450 | |
| 451 | static const struct snd_kcontrol_new wm8900_linmix_controls[] = { |
| 452 | SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1), |
| 453 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1), |
| 454 | SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1), |
| 455 | SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0), |
| 456 | }; |
| 457 | |
| 458 | static const struct snd_kcontrol_new wm8900_rinmix_controls[] = { |
| 459 | SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1), |
| 460 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1), |
| 461 | SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1), |
| 462 | SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0), |
| 463 | }; |
| 464 | |
| 465 | static const struct snd_kcontrol_new wm8900_linpga_controls[] = { |
| 466 | SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0), |
| 467 | SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0), |
| 468 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0), |
| 469 | }; |
| 470 | |
| 471 | static const struct snd_kcontrol_new wm8900_rinpga_controls[] = { |
| 472 | SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0), |
| 473 | SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0), |
| 474 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0), |
| 475 | }; |
| 476 | |
| 477 | static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" }; |
| 478 | |
| 479 | static const struct soc_enum wm8900_lineout2_lp_mux = |
| 480 | SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux); |
| 481 | |
| 482 | static const struct snd_kcontrol_new wm8900_lineout2_lp = |
| 483 | SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux); |
| 484 | |
| 485 | static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = { |
| 486 | |
| 487 | /* Externally visible pins */ |
| 488 | SND_SOC_DAPM_OUTPUT("LINEOUT1L"), |
| 489 | SND_SOC_DAPM_OUTPUT("LINEOUT1R"), |
| 490 | SND_SOC_DAPM_OUTPUT("LINEOUT2L"), |
| 491 | SND_SOC_DAPM_OUTPUT("LINEOUT2R"), |
| 492 | SND_SOC_DAPM_OUTPUT("HP_L"), |
| 493 | SND_SOC_DAPM_OUTPUT("HP_R"), |
| 494 | |
| 495 | SND_SOC_DAPM_INPUT("RINPUT1"), |
| 496 | SND_SOC_DAPM_INPUT("LINPUT1"), |
| 497 | SND_SOC_DAPM_INPUT("RINPUT2"), |
| 498 | SND_SOC_DAPM_INPUT("LINPUT2"), |
| 499 | SND_SOC_DAPM_INPUT("RINPUT3"), |
| 500 | SND_SOC_DAPM_INPUT("LINPUT3"), |
| 501 | SND_SOC_DAPM_INPUT("AUX"), |
| 502 | |
| 503 | SND_SOC_DAPM_VMID("VMID"), |
| 504 | |
| 505 | /* Input */ |
| 506 | SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0, |
| 507 | wm8900_linpga_controls, |
| 508 | ARRAY_SIZE(wm8900_linpga_controls)), |
| 509 | SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0, |
| 510 | wm8900_rinpga_controls, |
| 511 | ARRAY_SIZE(wm8900_rinpga_controls)), |
| 512 | |
| 513 | SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0, |
| 514 | wm8900_linmix_controls, |
| 515 | ARRAY_SIZE(wm8900_linmix_controls)), |
| 516 | SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0, |
| 517 | wm8900_rinmix_controls, |
| 518 | ARRAY_SIZE(wm8900_rinmix_controls)), |
| 519 | |
| 520 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0), |
| 521 | |
| 522 | SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0), |
| 523 | SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0), |
| 524 | |
| 525 | /* Output */ |
| 526 | SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0), |
| 527 | SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0), |
| 528 | |
| 529 | SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0, |
| 530 | wm8900_hp_event, |
| 531 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 532 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 533 | |
| 534 | SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0), |
| 535 | SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0), |
| 536 | |
| 537 | SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp), |
| 538 | SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0), |
| 539 | SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0), |
| 540 | |
| 541 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0, |
| 542 | wm8900_loutmix_controls, |
| 543 | ARRAY_SIZE(wm8900_loutmix_controls)), |
| 544 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0, |
| 545 | wm8900_routmix_controls, |
| 546 | ARRAY_SIZE(wm8900_routmix_controls)), |
| 547 | }; |
| 548 | |
| 549 | /* Target, Path, Source */ |
| 550 | static const struct snd_soc_dapm_route audio_map[] = { |
| 551 | /* Inputs */ |
| 552 | {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"}, |
| 553 | {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"}, |
| 554 | {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"}, |
| 555 | |
| 556 | {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"}, |
| 557 | {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"}, |
| 558 | {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"}, |
| 559 | |
| 560 | {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"}, |
| 561 | {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"}, |
| 562 | {"Left Input Mixer", "AUX Switch", "AUX"}, |
| 563 | {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"}, |
| 564 | |
| 565 | {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"}, |
| 566 | {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"}, |
| 567 | {"Right Input Mixer", "AUX Switch", "AUX"}, |
| 568 | {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"}, |
| 569 | |
| 570 | {"ADCL", NULL, "Left Input Mixer"}, |
| 571 | {"ADCR", NULL, "Right Input Mixer"}, |
| 572 | |
| 573 | /* Outputs */ |
| 574 | {"LINEOUT1L", NULL, "LINEOUT1L PGA"}, |
| 575 | {"LINEOUT1L PGA", NULL, "Left Output Mixer"}, |
| 576 | {"LINEOUT1R", NULL, "LINEOUT1R PGA"}, |
| 577 | {"LINEOUT1R PGA", NULL, "Right Output Mixer"}, |
| 578 | |
| 579 | {"LINEOUT2L PGA", NULL, "Left Output Mixer"}, |
| 580 | {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"}, |
| 581 | {"LINEOUT2 LP", "Enabled", "Left Output Mixer"}, |
| 582 | {"LINEOUT2L", NULL, "LINEOUT2 LP"}, |
| 583 | |
| 584 | {"LINEOUT2R PGA", NULL, "Right Output Mixer"}, |
| 585 | {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"}, |
| 586 | {"LINEOUT2 LP", "Enabled", "Right Output Mixer"}, |
| 587 | {"LINEOUT2R", NULL, "LINEOUT2 LP"}, |
| 588 | |
| 589 | {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"}, |
| 590 | {"Left Output Mixer", "AUX Bypass Switch", "AUX"}, |
| 591 | {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"}, |
| 592 | {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"}, |
| 593 | {"Left Output Mixer", "DACL Switch", "DACL"}, |
| 594 | |
| 595 | {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"}, |
| 596 | {"Right Output Mixer", "AUX Bypass Switch", "AUX"}, |
| 597 | {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"}, |
| 598 | {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"}, |
| 599 | {"Right Output Mixer", "DACR Switch", "DACR"}, |
| 600 | |
| 601 | /* Note that the headphone output stage needs to be connected |
| 602 | * externally to LINEOUT2 via DC blocking capacitors. Other |
| 603 | * configurations are not supported. |
| 604 | * |
| 605 | * Note also that left and right headphone paths are treated as a |
| 606 | * mono path. |
| 607 | */ |
| 608 | {"Headphone Amplifier", NULL, "LINEOUT2 LP"}, |
| 609 | {"Headphone Amplifier", NULL, "LINEOUT2 LP"}, |
| 610 | {"HP_L", NULL, "Headphone Amplifier"}, |
| 611 | {"HP_R", NULL, "Headphone Amplifier"}, |
| 612 | }; |
| 613 | |
| 614 | static int wm8900_add_widgets(struct snd_soc_codec *codec) |
| 615 | { |
| 616 | snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets, |
| 617 | ARRAY_SIZE(wm8900_dapm_widgets)); |
| 618 | |
| 619 | snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); |
| 620 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | static int wm8900_hw_params(struct snd_pcm_substream *substream, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 625 | struct snd_pcm_hw_params *params, |
| 626 | struct snd_soc_dai *dai) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 627 | { |
| 628 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 629 | struct snd_soc_codec *codec = rtd->codec; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 630 | u16 reg; |
| 631 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 632 | reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 633 | |
| 634 | switch (params_format(params)) { |
| 635 | case SNDRV_PCM_FORMAT_S16_LE: |
| 636 | break; |
| 637 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 638 | reg |= 0x20; |
| 639 | break; |
| 640 | case SNDRV_PCM_FORMAT_S24_LE: |
| 641 | reg |= 0x40; |
| 642 | break; |
| 643 | case SNDRV_PCM_FORMAT_S32_LE: |
| 644 | reg |= 0x60; |
| 645 | break; |
| 646 | default: |
| 647 | return -EINVAL; |
| 648 | } |
| 649 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 650 | snd_soc_write(codec, WM8900_REG_AUDIO1, reg); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 651 | |
Mark Brown | 21002e2 | 2009-06-12 17:27:52 +0100 | [diff] [blame] | 652 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 653 | reg = snd_soc_read(codec, WM8900_REG_DACCTRL); |
Mark Brown | 21002e2 | 2009-06-12 17:27:52 +0100 | [diff] [blame] | 654 | |
| 655 | if (params_rate(params) <= 24000) |
| 656 | reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; |
| 657 | else |
| 658 | reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; |
| 659 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 660 | snd_soc_write(codec, WM8900_REG_DACCTRL, reg); |
Mark Brown | 21002e2 | 2009-06-12 17:27:52 +0100 | [diff] [blame] | 661 | } |
| 662 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | /* FLL divisors */ |
| 667 | struct _fll_div { |
| 668 | u16 fll_ratio; |
| 669 | u16 fllclk_div; |
| 670 | u16 fll_slow_lock_ref; |
| 671 | u16 n; |
| 672 | u16 k; |
| 673 | }; |
| 674 | |
| 675 | /* The size in bits of the FLL divide multiplied by 10 |
| 676 | * to allow rounding later */ |
| 677 | #define FIXED_FLL_SIZE ((1 << 16) * 10) |
| 678 | |
| 679 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, |
| 680 | unsigned int Fout) |
| 681 | { |
| 682 | u64 Kpart; |
| 683 | unsigned int K, Ndiv, Nmod, target; |
| 684 | unsigned int div; |
| 685 | |
| 686 | BUG_ON(!Fout); |
| 687 | |
| 688 | /* The FLL must run at 90-100MHz which is then scaled down to |
| 689 | * the output value by FLLCLK_DIV. */ |
| 690 | target = Fout; |
| 691 | div = 1; |
| 692 | while (target < 90000000) { |
| 693 | div *= 2; |
| 694 | target *= 2; |
| 695 | } |
| 696 | |
| 697 | if (target > 100000000) |
Roel Kluin | 449bd54 | 2009-05-27 17:08:39 -0700 | [diff] [blame] | 698 | printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u" |
| 699 | " Fout=%u\n", target, Fref, Fout); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 700 | if (div > 32) { |
| 701 | printk(KERN_ERR "wm8900: Invalid FLL division rate %u, " |
Roel Kluin | 449bd54 | 2009-05-27 17:08:39 -0700 | [diff] [blame] | 702 | "Fref=%u, Fout=%u, target=%u\n", |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 703 | div, Fref, Fout, target); |
| 704 | return -EINVAL; |
| 705 | } |
| 706 | |
| 707 | fll_div->fllclk_div = div >> 2; |
| 708 | |
| 709 | if (Fref < 48000) |
| 710 | fll_div->fll_slow_lock_ref = 1; |
| 711 | else |
| 712 | fll_div->fll_slow_lock_ref = 0; |
| 713 | |
| 714 | Ndiv = target / Fref; |
| 715 | |
| 716 | if (Fref < 1000000) |
| 717 | fll_div->fll_ratio = 8; |
| 718 | else |
| 719 | fll_div->fll_ratio = 1; |
| 720 | |
| 721 | fll_div->n = Ndiv / fll_div->fll_ratio; |
| 722 | Nmod = (target / fll_div->fll_ratio) % Fref; |
| 723 | |
| 724 | /* Calculate fractional part - scale up so we can round. */ |
| 725 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; |
| 726 | |
| 727 | do_div(Kpart, Fref); |
| 728 | |
| 729 | K = Kpart & 0xFFFFFFFF; |
| 730 | |
| 731 | if ((K % 10) >= 5) |
| 732 | K += 5; |
| 733 | |
| 734 | /* Move down to proper range now rounding is done */ |
| 735 | fll_div->k = K / 10; |
| 736 | |
| 737 | BUG_ON(target != Fout * (fll_div->fllclk_div << 2)); |
| 738 | BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n); |
| 739 | |
| 740 | return 0; |
| 741 | } |
| 742 | |
| 743 | static int wm8900_set_fll(struct snd_soc_codec *codec, |
| 744 | int fll_id, unsigned int freq_in, unsigned int freq_out) |
| 745 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 746 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 747 | struct _fll_div fll_div; |
| 748 | unsigned int reg; |
| 749 | |
| 750 | if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) |
| 751 | return 0; |
| 752 | |
| 753 | /* The digital side should be disabled during any change. */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 754 | reg = snd_soc_read(codec, WM8900_REG_POWER1); |
| 755 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 756 | reg & (~WM8900_REG_POWER1_FLL_ENA)); |
| 757 | |
| 758 | /* Disable the FLL? */ |
| 759 | if (!freq_in || !freq_out) { |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 760 | reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); |
| 761 | snd_soc_write(codec, WM8900_REG_CLOCKING1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 762 | reg & (~WM8900_REG_CLOCKING1_MCLK_SRC)); |
| 763 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 764 | reg = snd_soc_read(codec, WM8900_REG_FLLCTL1); |
| 765 | snd_soc_write(codec, WM8900_REG_FLLCTL1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 766 | reg & (~WM8900_REG_FLLCTL1_OSC_ENA)); |
| 767 | |
| 768 | wm8900->fll_in = freq_in; |
| 769 | wm8900->fll_out = freq_out; |
| 770 | |
| 771 | return 0; |
| 772 | } |
| 773 | |
| 774 | if (fll_factors(&fll_div, freq_in, freq_out) != 0) |
| 775 | goto reenable; |
| 776 | |
| 777 | wm8900->fll_in = freq_in; |
| 778 | wm8900->fll_out = freq_out; |
| 779 | |
| 780 | /* The osclilator *MUST* be enabled before we enable the |
| 781 | * digital circuit. */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 782 | snd_soc_write(codec, WM8900_REG_FLLCTL1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 783 | fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); |
| 784 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 785 | snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5); |
| 786 | snd_soc_write(codec, WM8900_REG_FLLCTL5, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 787 | (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); |
| 788 | |
| 789 | if (fll_div.k) { |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 790 | snd_soc_write(codec, WM8900_REG_FLLCTL2, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 791 | (fll_div.k >> 8) | 0x100); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 792 | snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 793 | } else |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 794 | snd_soc_write(codec, WM8900_REG_FLLCTL2, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 795 | |
| 796 | if (fll_div.fll_slow_lock_ref) |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 797 | snd_soc_write(codec, WM8900_REG_FLLCTL6, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 798 | WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); |
| 799 | else |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 800 | snd_soc_write(codec, WM8900_REG_FLLCTL6, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 801 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 802 | reg = snd_soc_read(codec, WM8900_REG_POWER1); |
| 803 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 804 | reg | WM8900_REG_POWER1_FLL_ENA); |
| 805 | |
| 806 | reenable: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 807 | reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); |
| 808 | snd_soc_write(codec, WM8900_REG_CLOCKING1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 809 | reg | WM8900_REG_CLOCKING1_MCLK_SRC); |
| 810 | |
| 811 | return 0; |
| 812 | } |
| 813 | |
Mark Brown | 8548803 | 2009-09-05 18:52:16 +0100 | [diff] [blame] | 814 | static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
| 815 | int source, unsigned int freq_in, unsigned int freq_out) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 816 | { |
| 817 | return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out); |
| 818 | } |
| 819 | |
| 820 | static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
| 821 | int div_id, int div) |
| 822 | { |
| 823 | struct snd_soc_codec *codec = codec_dai->codec; |
| 824 | unsigned int reg; |
| 825 | |
| 826 | switch (div_id) { |
| 827 | case WM8900_BCLK_DIV: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 828 | reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); |
| 829 | snd_soc_write(codec, WM8900_REG_CLOCKING1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 830 | div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK)); |
| 831 | break; |
| 832 | case WM8900_OPCLK_DIV: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 833 | reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); |
| 834 | snd_soc_write(codec, WM8900_REG_CLOCKING1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 835 | div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK)); |
| 836 | break; |
| 837 | case WM8900_DAC_LRCLK: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 838 | reg = snd_soc_read(codec, WM8900_REG_AUDIO4); |
| 839 | snd_soc_write(codec, WM8900_REG_AUDIO4, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 840 | div | (reg & WM8900_LRC_MASK)); |
| 841 | break; |
| 842 | case WM8900_ADC_LRCLK: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 843 | reg = snd_soc_read(codec, WM8900_REG_AUDIO3); |
| 844 | snd_soc_write(codec, WM8900_REG_AUDIO3, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 845 | div | (reg & WM8900_LRC_MASK)); |
| 846 | break; |
| 847 | case WM8900_DAC_CLKDIV: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 848 | reg = snd_soc_read(codec, WM8900_REG_CLOCKING2); |
| 849 | snd_soc_write(codec, WM8900_REG_CLOCKING2, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 850 | div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV)); |
| 851 | break; |
| 852 | case WM8900_ADC_CLKDIV: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 853 | reg = snd_soc_read(codec, WM8900_REG_CLOCKING2); |
| 854 | snd_soc_write(codec, WM8900_REG_CLOCKING2, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 855 | div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV)); |
| 856 | break; |
| 857 | case WM8900_LRCLK_MODE: |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 858 | reg = snd_soc_read(codec, WM8900_REG_DACCTRL); |
| 859 | snd_soc_write(codec, WM8900_REG_DACCTRL, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 860 | div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE)); |
| 861 | break; |
| 862 | default: |
| 863 | return -EINVAL; |
| 864 | } |
| 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
| 869 | |
| 870 | static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, |
| 871 | unsigned int fmt) |
| 872 | { |
| 873 | struct snd_soc_codec *codec = codec_dai->codec; |
| 874 | unsigned int clocking1, aif1, aif3, aif4; |
| 875 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 876 | clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1); |
| 877 | aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1); |
| 878 | aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3); |
| 879 | aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 880 | |
| 881 | /* set master/slave audio interface */ |
| 882 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 883 | case SND_SOC_DAIFMT_CBS_CFS: |
| 884 | clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; |
| 885 | aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; |
| 886 | aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; |
| 887 | break; |
| 888 | case SND_SOC_DAIFMT_CBS_CFM: |
| 889 | clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; |
| 890 | aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; |
| 891 | aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; |
| 892 | break; |
| 893 | case SND_SOC_DAIFMT_CBM_CFM: |
| 894 | clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; |
| 895 | aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; |
| 896 | aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; |
| 897 | break; |
| 898 | case SND_SOC_DAIFMT_CBM_CFS: |
| 899 | clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; |
| 900 | aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; |
| 901 | aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; |
| 902 | break; |
| 903 | default: |
| 904 | return -EINVAL; |
| 905 | } |
| 906 | |
| 907 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 908 | case SND_SOC_DAIFMT_DSP_A: |
| 909 | aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; |
| 910 | aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; |
| 911 | break; |
| 912 | case SND_SOC_DAIFMT_DSP_B: |
| 913 | aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; |
| 914 | aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; |
| 915 | break; |
| 916 | case SND_SOC_DAIFMT_I2S: |
| 917 | aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; |
| 918 | aif1 |= 0x10; |
| 919 | break; |
| 920 | case SND_SOC_DAIFMT_RIGHT_J: |
| 921 | aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; |
| 922 | break; |
| 923 | case SND_SOC_DAIFMT_LEFT_J: |
| 924 | aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; |
| 925 | aif1 |= 0x8; |
| 926 | break; |
| 927 | default: |
| 928 | return -EINVAL; |
| 929 | } |
| 930 | |
| 931 | /* Clock inversion */ |
| 932 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 933 | case SND_SOC_DAIFMT_DSP_A: |
| 934 | case SND_SOC_DAIFMT_DSP_B: |
| 935 | /* frame inversion not valid for DSP modes */ |
| 936 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 937 | case SND_SOC_DAIFMT_NB_NF: |
| 938 | aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; |
| 939 | break; |
| 940 | case SND_SOC_DAIFMT_IB_NF: |
| 941 | aif1 |= WM8900_REG_AUDIO1_BCLK_INV; |
| 942 | break; |
| 943 | default: |
| 944 | return -EINVAL; |
| 945 | } |
| 946 | break; |
| 947 | case SND_SOC_DAIFMT_I2S: |
| 948 | case SND_SOC_DAIFMT_RIGHT_J: |
| 949 | case SND_SOC_DAIFMT_LEFT_J: |
| 950 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 951 | case SND_SOC_DAIFMT_NB_NF: |
| 952 | aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; |
| 953 | aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; |
| 954 | break; |
| 955 | case SND_SOC_DAIFMT_IB_IF: |
| 956 | aif1 |= WM8900_REG_AUDIO1_BCLK_INV; |
| 957 | aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; |
| 958 | break; |
| 959 | case SND_SOC_DAIFMT_IB_NF: |
| 960 | aif1 |= WM8900_REG_AUDIO1_BCLK_INV; |
| 961 | aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; |
| 962 | break; |
| 963 | case SND_SOC_DAIFMT_NB_IF: |
| 964 | aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; |
| 965 | aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; |
| 966 | break; |
| 967 | default: |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | break; |
| 971 | default: |
| 972 | return -EINVAL; |
| 973 | } |
| 974 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 975 | snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1); |
| 976 | snd_soc_write(codec, WM8900_REG_AUDIO1, aif1); |
| 977 | snd_soc_write(codec, WM8900_REG_AUDIO3, aif3); |
| 978 | snd_soc_write(codec, WM8900_REG_AUDIO4, aif4); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute) |
| 984 | { |
| 985 | struct snd_soc_codec *codec = codec_dai->codec; |
| 986 | u16 reg; |
| 987 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 988 | reg = snd_soc_read(codec, WM8900_REG_DACCTRL); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 989 | |
| 990 | if (mute) |
| 991 | reg |= WM8900_REG_DACCTRL_MUTE; |
| 992 | else |
| 993 | reg &= ~WM8900_REG_DACCTRL_MUTE; |
| 994 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 995 | snd_soc_write(codec, WM8900_REG_DACCTRL, reg); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 996 | |
| 997 | return 0; |
| 998 | } |
| 999 | |
| 1000 | #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
| 1001 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ |
| 1002 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) |
| 1003 | |
| 1004 | #define WM8900_PCM_FORMATS \ |
| 1005 | (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \ |
| 1006 | SNDRV_PCM_FORMAT_S24_LE) |
| 1007 | |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 1008 | static struct snd_soc_dai_ops wm8900_dai_ops = { |
| 1009 | .hw_params = wm8900_hw_params, |
| 1010 | .set_clkdiv = wm8900_set_dai_clkdiv, |
| 1011 | .set_pll = wm8900_set_dai_pll, |
| 1012 | .set_fmt = wm8900_set_dai_fmt, |
| 1013 | .digital_mute = wm8900_digital_mute, |
| 1014 | }; |
| 1015 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1016 | static struct snd_soc_dai_driver wm8900_dai = { |
| 1017 | .name = "wm8900-hifi", |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1018 | .playback = { |
| 1019 | .stream_name = "HiFi Playback", |
| 1020 | .channels_min = 1, |
| 1021 | .channels_max = 2, |
| 1022 | .rates = WM8900_RATES, |
| 1023 | .formats = WM8900_PCM_FORMATS, |
| 1024 | }, |
| 1025 | .capture = { |
| 1026 | .stream_name = "HiFi Capture", |
| 1027 | .channels_min = 1, |
| 1028 | .channels_max = 2, |
| 1029 | .rates = WM8900_RATES, |
| 1030 | .formats = WM8900_PCM_FORMATS, |
| 1031 | }, |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 1032 | .ops = &wm8900_dai_ops, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1033 | }; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1034 | |
| 1035 | static int wm8900_set_bias_level(struct snd_soc_codec *codec, |
| 1036 | enum snd_soc_bias_level level) |
| 1037 | { |
| 1038 | u16 reg; |
| 1039 | |
| 1040 | switch (level) { |
| 1041 | case SND_SOC_BIAS_ON: |
| 1042 | /* Enable thermal shutdown */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1043 | reg = snd_soc_read(codec, WM8900_REG_GPIO); |
| 1044 | snd_soc_write(codec, WM8900_REG_GPIO, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1045 | reg | WM8900_REG_GPIO_TEMP_ENA); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1046 | reg = snd_soc_read(codec, WM8900_REG_ADDCTL); |
| 1047 | snd_soc_write(codec, WM8900_REG_ADDCTL, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1048 | reg | WM8900_REG_ADDCTL_TEMP_SD); |
| 1049 | break; |
| 1050 | |
| 1051 | case SND_SOC_BIAS_PREPARE: |
| 1052 | break; |
| 1053 | |
| 1054 | case SND_SOC_BIAS_STANDBY: |
| 1055 | /* Charge capacitors if initial power up */ |
| 1056 | if (codec->bias_level == SND_SOC_BIAS_OFF) { |
| 1057 | /* STARTUP_BIAS_ENA on */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1058 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1059 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
| 1060 | |
| 1061 | /* Startup bias mode */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1062 | snd_soc_write(codec, WM8900_REG_ADDCTL, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1063 | WM8900_REG_ADDCTL_BIAS_SRC | |
| 1064 | WM8900_REG_ADDCTL_VMID_SOFTST); |
| 1065 | |
| 1066 | /* VMID 2x50k */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1067 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1068 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); |
| 1069 | |
| 1070 | /* Allow capacitors to charge */ |
| 1071 | schedule_timeout_interruptible(msecs_to_jiffies(400)); |
| 1072 | |
| 1073 | /* Enable bias */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1074 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1075 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | |
| 1076 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
| 1077 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1078 | snd_soc_write(codec, WM8900_REG_ADDCTL, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1079 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1080 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1081 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
| 1082 | } |
| 1083 | |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1084 | reg = snd_soc_read(codec, WM8900_REG_POWER1); |
| 1085 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1086 | (reg & WM8900_REG_POWER1_FLL_ENA) | |
| 1087 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1088 | snd_soc_write(codec, WM8900_REG_POWER2, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1089 | WM8900_REG_POWER2_SYSCLK_ENA); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1090 | snd_soc_write(codec, WM8900_REG_POWER3, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1091 | break; |
| 1092 | |
| 1093 | case SND_SOC_BIAS_OFF: |
| 1094 | /* Startup bias enable */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1095 | reg = snd_soc_read(codec, WM8900_REG_POWER1); |
| 1096 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1097 | reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1098 | snd_soc_write(codec, WM8900_REG_ADDCTL, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1099 | WM8900_REG_ADDCTL_BIAS_SRC | |
| 1100 | WM8900_REG_ADDCTL_VMID_SOFTST); |
| 1101 | |
| 1102 | /* Discharge caps */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1103 | snd_soc_write(codec, WM8900_REG_POWER1, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1104 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
| 1105 | schedule_timeout_interruptible(msecs_to_jiffies(500)); |
| 1106 | |
| 1107 | /* Remove clamp */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1108 | snd_soc_write(codec, WM8900_REG_HPCTL1, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1109 | |
| 1110 | /* Power down */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1111 | snd_soc_write(codec, WM8900_REG_ADDCTL, 0); |
| 1112 | snd_soc_write(codec, WM8900_REG_POWER1, 0); |
| 1113 | snd_soc_write(codec, WM8900_REG_POWER2, 0); |
| 1114 | snd_soc_write(codec, WM8900_REG_POWER3, 0); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1115 | |
| 1116 | /* Need to let things settle before stopping the clock |
| 1117 | * to ensure that restart works, see "Stopping the |
| 1118 | * master clock" in the datasheet. */ |
| 1119 | schedule_timeout_interruptible(msecs_to_jiffies(1)); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1120 | snd_soc_write(codec, WM8900_REG_POWER2, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1121 | WM8900_REG_POWER2_SYSCLK_ENA); |
| 1122 | break; |
| 1123 | } |
| 1124 | codec->bias_level = level; |
| 1125 | return 0; |
| 1126 | } |
| 1127 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1128 | static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1129 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 1130 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1131 | int fll_out = wm8900->fll_out; |
| 1132 | int fll_in = wm8900->fll_in; |
| 1133 | int ret; |
| 1134 | |
| 1135 | /* Stop the FLL in an orderly fashion */ |
| 1136 | ret = wm8900_set_fll(codec, 0, 0, 0); |
| 1137 | if (ret != 0) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1138 | dev_err(codec->dev, "Failed to stop FLL\n"); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1139 | return ret; |
| 1140 | } |
| 1141 | |
| 1142 | wm8900->fll_out = fll_out; |
| 1143 | wm8900->fll_in = fll_in; |
| 1144 | |
| 1145 | wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1146 | |
| 1147 | return 0; |
| 1148 | } |
| 1149 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1150 | static int wm8900_resume(struct snd_soc_codec *codec) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1151 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 1152 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1153 | u16 *cache; |
| 1154 | int i, ret; |
| 1155 | |
| 1156 | cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults), |
| 1157 | GFP_KERNEL); |
| 1158 | |
| 1159 | wm8900_reset(codec); |
| 1160 | wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1161 | |
| 1162 | /* Restart the FLL? */ |
| 1163 | if (wm8900->fll_out) { |
| 1164 | int fll_out = wm8900->fll_out; |
| 1165 | int fll_in = wm8900->fll_in; |
| 1166 | |
| 1167 | wm8900->fll_in = 0; |
| 1168 | wm8900->fll_out = 0; |
| 1169 | |
| 1170 | ret = wm8900_set_fll(codec, 0, fll_in, fll_out); |
| 1171 | if (ret != 0) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1172 | dev_err(codec->dev, "Failed to restart FLL\n"); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1173 | return ret; |
| 1174 | } |
| 1175 | } |
| 1176 | |
| 1177 | if (cache) { |
| 1178 | for (i = 0; i < WM8900_MAXREG; i++) |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1179 | snd_soc_write(codec, i, cache[i]); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1180 | kfree(cache); |
| 1181 | } else |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1182 | dev_err(codec->dev, "Unable to allocate register cache\n"); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1183 | |
| 1184 | return 0; |
| 1185 | } |
| 1186 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1187 | static int wm8900_probe(struct snd_soc_codec *codec) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1188 | { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1189 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); |
| 1190 | int ret = 0, reg; |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1191 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1192 | codec->control_data = wm8900->control_data; |
| 1193 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type); |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1194 | if (ret != 0) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1195 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 1196 | return ret; |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1197 | } |
| 1198 | |
| 1199 | reg = snd_soc_read(codec, WM8900_REG_ID); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1200 | if (reg != 0x8900) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1201 | dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg); |
| 1202 | return -ENODEV; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1203 | } |
| 1204 | |
| 1205 | /* Read back from the chip */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1206 | reg = snd_soc_read(codec, WM8900_REG_POWER1); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1207 | reg = (reg >> 12) & 0xf; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1208 | dev_info(codec->dev, "WM8900 revision %d\n", reg); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1209 | |
| 1210 | wm8900_reset(codec); |
| 1211 | |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1212 | /* Turn the chip on */ |
| 1213 | wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1214 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1215 | /* Latch the volume update bits */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1216 | snd_soc_write(codec, WM8900_REG_LINVOL, |
| 1217 | snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100); |
| 1218 | snd_soc_write(codec, WM8900_REG_RINVOL, |
| 1219 | snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100); |
| 1220 | snd_soc_write(codec, WM8900_REG_LOUT1CTL, |
| 1221 | snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100); |
| 1222 | snd_soc_write(codec, WM8900_REG_ROUT1CTL, |
| 1223 | snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100); |
| 1224 | snd_soc_write(codec, WM8900_REG_LOUT2CTL, |
| 1225 | snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100); |
| 1226 | snd_soc_write(codec, WM8900_REG_ROUT2CTL, |
| 1227 | snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100); |
| 1228 | snd_soc_write(codec, WM8900_REG_LDAC_DV, |
| 1229 | snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100); |
| 1230 | snd_soc_write(codec, WM8900_REG_RDAC_DV, |
| 1231 | snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100); |
| 1232 | snd_soc_write(codec, WM8900_REG_LADC_DV, |
| 1233 | snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100); |
| 1234 | snd_soc_write(codec, WM8900_REG_RADC_DV, |
| 1235 | snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1236 | |
| 1237 | /* Set the DAC and mixer output bias */ |
Mark Brown | 8d50e44 | 2009-07-10 23:12:01 +0100 | [diff] [blame] | 1238 | snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1239 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1240 | snd_soc_add_controls(codec, wm8900_snd_controls, |
| 1241 | ARRAY_SIZE(wm8900_snd_controls)); |
| 1242 | wm8900_add_widgets(codec); |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1243 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1244 | return 0; |
| 1245 | } |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1246 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1247 | /* power down chip */ |
| 1248 | static int wm8900_remove(struct snd_soc_codec *codec) |
| 1249 | { |
| 1250 | wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1251 | return 0; |
| 1252 | } |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1253 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1254 | static struct snd_soc_codec_driver soc_codec_dev_wm8900 = { |
| 1255 | .probe = wm8900_probe, |
| 1256 | .remove = wm8900_remove, |
| 1257 | .suspend = wm8900_suspend, |
| 1258 | .resume = wm8900_resume, |
| 1259 | .set_bias_level = wm8900_set_bias_level, |
| 1260 | .volatile_register = wm8900_volatile_register, |
| 1261 | .reg_cache_size = sizeof(wm8900_reg_defaults), |
| 1262 | .reg_word_size = sizeof(u16), |
| 1263 | .reg_cache_default = wm8900_reg_defaults, |
| 1264 | }; |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1265 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1266 | #if defined(CONFIG_SPI_MASTER) |
| 1267 | static int __devinit wm8900_spi_probe(struct spi_device *spi) |
| 1268 | { |
| 1269 | struct wm8900_priv *wm8900; |
| 1270 | int ret; |
| 1271 | |
| 1272 | wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL); |
| 1273 | if (wm8900 == NULL) |
| 1274 | return -ENOMEM; |
| 1275 | |
| 1276 | wm8900->control_data = spi; |
| 1277 | wm8900->control_type = SND_SOC_SPI; |
| 1278 | spi_set_drvdata(spi, wm8900); |
| 1279 | |
| 1280 | ret = snd_soc_register_codec(&spi->dev, |
| 1281 | &soc_codec_dev_wm8900, &wm8900_dai, 1); |
| 1282 | if (ret < 0) |
| 1283 | kfree(wm8900); |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1284 | return ret; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1285 | } |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1286 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1287 | static int __devexit wm8900_spi_remove(struct spi_device *spi) |
| 1288 | { |
| 1289 | snd_soc_unregister_codec(&spi->dev); |
| 1290 | kfree(spi_get_drvdata(spi)); |
| 1291 | return 0; |
| 1292 | } |
| 1293 | |
| 1294 | static struct spi_driver wm8900_spi_driver = { |
| 1295 | .driver = { |
| 1296 | .name = "wm8900-codec", |
| 1297 | .bus = &spi_bus_type, |
| 1298 | .owner = THIS_MODULE, |
| 1299 | }, |
| 1300 | .probe = wm8900_spi_probe, |
| 1301 | .remove = __devexit_p(wm8900_spi_remove), |
| 1302 | }; |
| 1303 | #endif /* CONFIG_SPI_MASTER */ |
| 1304 | |
| 1305 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1306 | static __devinit int wm8900_i2c_probe(struct i2c_client *i2c, |
| 1307 | const struct i2c_device_id *id) |
| 1308 | { |
| 1309 | struct wm8900_priv *wm8900; |
| 1310 | int ret; |
| 1311 | |
| 1312 | wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL); |
| 1313 | if (wm8900 == NULL) |
| 1314 | return -ENOMEM; |
| 1315 | |
| 1316 | i2c_set_clientdata(i2c, wm8900); |
| 1317 | wm8900->control_data = i2c; |
| 1318 | wm8900->control_type = SND_SOC_I2C; |
| 1319 | |
| 1320 | ret = snd_soc_register_codec(&i2c->dev, |
| 1321 | &soc_codec_dev_wm8900, &wm8900_dai, 1); |
| 1322 | if (ret < 0) |
| 1323 | kfree(wm8900); |
Mark Brown | 78e19a3 | 2008-12-10 15:38:36 +0000 | [diff] [blame] | 1324 | return ret; |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1325 | } |
| 1326 | |
Mark Brown | c6f2981 | 2009-02-18 21:25:40 +0000 | [diff] [blame] | 1327 | static __devexit int wm8900_i2c_remove(struct i2c_client *client) |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1328 | { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1329 | snd_soc_unregister_codec(&client->dev); |
| 1330 | kfree(i2c_get_clientdata(client)); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1331 | return 0; |
| 1332 | } |
| 1333 | |
Jean Delvare | 8ae6a55 | 2008-10-15 19:58:12 +0200 | [diff] [blame] | 1334 | static const struct i2c_device_id wm8900_i2c_id[] = { |
| 1335 | { "wm8900", 0 }, |
| 1336 | { } |
| 1337 | }; |
| 1338 | MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id); |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1339 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1340 | static struct i2c_driver wm8900_i2c_driver = { |
| 1341 | .driver = { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1342 | .name = "wm8900-codec", |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1343 | .owner = THIS_MODULE, |
| 1344 | }, |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1345 | .probe = wm8900_i2c_probe, |
| 1346 | .remove = __devexit_p(wm8900_i2c_remove), |
Jean Delvare | 8ae6a55 | 2008-10-15 19:58:12 +0200 | [diff] [blame] | 1347 | .id_table = wm8900_i2c_id, |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1348 | }; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1349 | #endif |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1350 | |
Takashi Iwai | c9b3a40 | 2008-12-10 07:47:22 +0100 | [diff] [blame] | 1351 | static int __init wm8900_modinit(void) |
Mark Brown | 64089b8 | 2008-12-08 19:17:58 +0000 | [diff] [blame] | 1352 | { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1353 | int ret = 0; |
| 1354 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1355 | ret = i2c_add_driver(&wm8900_i2c_driver); |
| 1356 | if (ret != 0) { |
| 1357 | printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n", |
| 1358 | ret); |
| 1359 | } |
| 1360 | #endif |
| 1361 | #if defined(CONFIG_SPI_MASTER) |
| 1362 | ret = spi_register_driver(&wm8900_spi_driver); |
| 1363 | if (ret != 0) { |
| 1364 | printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n", |
| 1365 | ret); |
| 1366 | } |
| 1367 | #endif |
| 1368 | return ret; |
Mark Brown | 64089b8 | 2008-12-08 19:17:58 +0000 | [diff] [blame] | 1369 | } |
| 1370 | module_init(wm8900_modinit); |
| 1371 | |
| 1372 | static void __exit wm8900_exit(void) |
| 1373 | { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1374 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
Mark Brown | f075233 | 2008-12-09 12:51:56 +0000 | [diff] [blame] | 1375 | i2c_del_driver(&wm8900_i2c_driver); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame^] | 1376 | #endif |
| 1377 | #if defined(CONFIG_SPI_MASTER) |
| 1378 | spi_unregister_driver(&wm8900_spi_driver); |
| 1379 | #endif |
Mark Brown | 64089b8 | 2008-12-08 19:17:58 +0000 | [diff] [blame] | 1380 | } |
| 1381 | module_exit(wm8900_exit); |
| 1382 | |
Mark Brown | 0e0e16a | 2008-08-04 12:06:45 +0100 | [diff] [blame] | 1383 | MODULE_DESCRIPTION("ASoC WM8900 driver"); |
| 1384 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>"); |
| 1385 | MODULE_LICENSE("GPL"); |