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John Linnb85a3ef2011-06-20 11:47:27 -06001/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060013/include/ "skeleton.dtsi"
John Linnb85a3ef2011-06-20 11:47:27 -060014
John Linnb85a3ef2011-06-20 11:47:27 -060015/ {
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060016 compatible = "xlnx,zynq-7000";
John Linnb85a3ef2011-06-20 11:47:27 -060017
Michal Simek268a8202013-03-20 13:37:01 +010018 pmu {
19 compatible = "arm,cortex-a9-pmu";
20 interrupts = <0 5 4>, <0 6 4>;
21 interrupt-parent = <&intc>;
22 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
23 };
24
John Linnb85a3ef2011-06-20 11:47:27 -060025 amba {
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <1>;
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060029 interrupt-parent = <&intc>;
John Linnb85a3ef2011-06-20 11:47:27 -060030 ranges;
31
32 intc: interrupt-controller@f8f01000 {
Josh Cartwrightf447ed22012-10-17 19:46:49 -050033 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
35 #address-cells = <1>;
John Linnb85a3ef2011-06-20 11:47:27 -060036 interrupt-controller;
Josh Cartwrightf447ed22012-10-17 19:46:49 -050037 reg = <0xF8F01000 0x1000>,
38 <0xF8F00100 0x100>;
John Linnb85a3ef2011-06-20 11:47:27 -060039 };
40
Josh Cartwright0fcfdbc2012-10-23 17:34:22 -050041 L2: cache-controller {
42 compatible = "arm,pl310-cache";
43 reg = <0xF8F02000 0x1000>;
Soren Brinkmann39c41df92013-07-31 16:24:59 -070044 arm,data-latency = <3 2 2>;
45 arm,tag-latency = <2 2 2>;
Josh Cartwright0fcfdbc2012-10-23 17:34:22 -050046 cache-unified;
47 cache-level = <2>;
48 };
49
John Linnb85a3ef2011-06-20 11:47:27 -060050 uart0: uart@e0000000 {
51 compatible = "xlnx,xuartps";
Soren Brinkmannec11ebc2013-06-13 09:37:16 -070052 status = "disabled";
Soren Brinkmann30e1e282013-05-13 10:46:38 -070053 clocks = <&clkc 23>, <&clkc 40>;
54 clock-names = "ref_clk", "aper_clk";
John Linnb85a3ef2011-06-20 11:47:27 -060055 reg = <0xE0000000 0x1000>;
Josh Cartwrightf447ed22012-10-17 19:46:49 -050056 interrupts = <0 27 4>;
John Linnb85a3ef2011-06-20 11:47:27 -060057 };
Josh Cartwright78d67852012-10-31 13:45:17 -060058
59 uart1: uart@e0001000 {
60 compatible = "xlnx,xuartps";
Soren Brinkmannec11ebc2013-06-13 09:37:16 -070061 status = "disabled";
Soren Brinkmann30e1e282013-05-13 10:46:38 -070062 clocks = <&clkc 24>, <&clkc 41>;
63 clock-names = "ref_clk", "aper_clk";
Josh Cartwright78d67852012-10-31 13:45:17 -060064 reg = <0xE0001000 0x1000>;
65 interrupts = <0 50 4>;
Josh Cartwright78d67852012-10-31 13:45:17 -060066 };
Josh Cartwright0f586fb2012-11-08 12:04:26 -060067
68 slcr: slcr@f8000000 {
69 compatible = "xlnx,zynq-slcr";
70 reg = <0xF8000000 0x1000>;
71
72 clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
Soren Brinkmann30e1e282013-05-13 10:46:38 -070076 clkc: clkc {
Josh Cartwright0f586fb2012-11-08 12:04:26 -060077 #clock-cells = <1>;
Soren Brinkmann30e1e282013-05-13 10:46:38 -070078 compatible = "xlnx,ps7-clkc";
79 ps-clk-frequency = <33333333>;
80 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
81 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
82 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
83 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
84 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
85 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
86 "gem1_aper", "sdio0_aper", "sdio1_aper",
87 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
88 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
89 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
90 "dbg_trc", "dbg_apb";
Josh Cartwright0f586fb2012-11-08 12:04:26 -060091 };
92 };
93 };
Josh Cartwright91dc9852012-10-31 13:56:14 -060094
95 ttc0: ttc0@f8001000 {
Michal Simeke9329002013-03-20 10:15:28 +010096 interrupt-parent = <&intc>;
97 interrupts = < 0 10 4 0 11 4 0 12 4 >;
98 compatible = "cdns,ttc";
Soren Brinkmann30e1e282013-05-13 10:46:38 -070099 clocks = <&clkc 6>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600100 reg = <0xF8001000 0x1000>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600101 clock-ranges;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600102 };
103
104 ttc1: ttc1@f8002000 {
Michal Simeke9329002013-03-20 10:15:28 +0100105 interrupt-parent = <&intc>;
106 interrupts = < 0 37 4 0 38 4 0 39 4 >;
107 compatible = "cdns,ttc";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700108 clocks = <&clkc 6>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600109 reg = <0xF8002000 0x1000>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600110 clock-ranges;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600111 };
Michal Simek2f34e0a2013-03-27 13:36:39 +0100112 scutimer: scutimer@f8f00600 {
113 interrupt-parent = <&intc>;
114 interrupts = < 1 13 0x301 >;
115 compatible = "arm,cortex-a9-twd-timer";
116 reg = < 0xf8f00600 0x20 >;
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700117 clocks = <&clkc 4>;
Michal Simek2f34e0a2013-03-27 13:36:39 +0100118 } ;
John Linnb85a3ef2011-06-20 11:47:27 -0600119 };
120};