Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. |
| 4 | * Copyright (C) 2001 Ralf Baechle |
| 5 | * |
| 6 | * This program is free software; you can distribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License (Version 2) as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 13 | * for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 18 | * |
| 19 | * Routines for generic manipulation of the interrupts found on the MIPS |
| 20 | * Malta board. |
| 21 | * The interrupt controller is located in the South Bridge a PIIX4 device |
| 22 | * with two internal 82C95 interrupt controllers. |
| 23 | */ |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/kernel_stat.h> |
Ahmed S. Darwish | 25b8ac3 | 2007-02-05 04:42:11 +0200 | [diff] [blame] | 30 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include <linux/random.h> |
| 32 | |
| 33 | #include <asm/i8259.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 34 | #include <asm/irq_cpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/io.h> |
Ralf Baechle | ba38cdf | 2006-10-15 09:17:43 +0100 | [diff] [blame] | 36 | #include <asm/irq_regs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #include <asm/mips-boards/malta.h> |
| 38 | #include <asm/mips-boards/maltaint.h> |
| 39 | #include <asm/mips-boards/piix4.h> |
| 40 | #include <asm/gt64120.h> |
| 41 | #include <asm/mips-boards/generic.h> |
| 42 | #include <asm/mips-boards/msc01_pci.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 43 | #include <asm/msc01_ic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 45 | extern void mips_timer_interrupt(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
| 47 | static DEFINE_SPINLOCK(mips_irq_lock); |
| 48 | |
| 49 | static inline int mips_pcibios_iack(void) |
| 50 | { |
| 51 | int irq; |
| 52 | u32 dummy; |
| 53 | |
| 54 | /* |
| 55 | * Determine highest priority pending interrupt by performing |
| 56 | * a PCI Interrupt Acknowledge cycle. |
| 57 | */ |
| 58 | switch(mips_revision_corid) { |
| 59 | case MIPS_REVISION_CORID_CORE_MSC: |
| 60 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 61 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Chris Dearman | 7a83419 | 2006-04-15 00:31:16 +0100 | [diff] [blame] | 62 | case MIPS_REVISION_CORID_CORE_24K: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 64 | MSC_READ(MSC01_PCI_IACK, irq); |
| 65 | irq &= 0xff; |
| 66 | break; |
| 67 | case MIPS_REVISION_CORID_QED_RM5261: |
| 68 | case MIPS_REVISION_CORID_CORE_LV: |
| 69 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 70 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
| 71 | irq = GT_READ(GT_PCI0_IACK_OFS); |
| 72 | irq &= 0xff; |
| 73 | break; |
| 74 | case MIPS_REVISION_CORID_BONITO64: |
| 75 | case MIPS_REVISION_CORID_CORE_20K: |
| 76 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
| 77 | /* The following will generate a PCI IACK cycle on the |
| 78 | * Bonito controller. It's a little bit kludgy, but it |
| 79 | * was the easiest way to implement it in hardware at |
| 80 | * the given time. |
| 81 | */ |
| 82 | BONITO_PCIMAP_CFG = 0x20000; |
| 83 | |
| 84 | /* Flush Bonito register block */ |
| 85 | dummy = BONITO_PCIMAP_CFG; |
| 86 | iob(); /* sync */ |
| 87 | |
Ralf Baechle | f197465 | 2007-04-26 15:46:24 +0100 | [diff] [blame^] | 88 | irq = readl((u32 *)_pcictrl_bonito_pcicfg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | iob(); /* sync */ |
| 90 | irq &= 0xff; |
| 91 | BONITO_PCIMAP_CFG = 0; |
| 92 | break; |
| 93 | default: |
| 94 | printk("Unknown Core card, don't know the system controller.\n"); |
| 95 | return -1; |
| 96 | } |
| 97 | return irq; |
| 98 | } |
| 99 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 100 | static inline int get_int(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | { |
| 102 | unsigned long flags; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 103 | int irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | spin_lock_irqsave(&mips_irq_lock, flags); |
| 105 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 106 | irq = mips_pcibios_iack(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | |
| 108 | /* |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 109 | * The only way we can decide if an interrupt is spurious |
| 110 | * is by checking the 8259 registers. This needs a spinlock |
| 111 | * on an SMP system, so leave it up to the generic code... |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | |
| 114 | spin_unlock_irqrestore(&mips_irq_lock, flags); |
| 115 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 116 | return irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | } |
| 118 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 119 | static void malta_hw0_irqdispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | { |
| 121 | int irq; |
| 122 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 123 | irq = get_int(); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 124 | if (irq < 0) { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 125 | return; /* interrupt has already been cleared */ |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 126 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 128 | do_IRQ(MALTA_INT_BASE + irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | } |
| 130 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 131 | static void corehi_irqdispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 133 | unsigned int intedge, intsteer, pcicmd, pcibadaddr; |
| 134 | unsigned int pcimstat, intisr, inten, intpol; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 135 | unsigned int intrcause,datalo,datahi; |
Ralf Baechle | ba38cdf | 2006-10-15 09:17:43 +0100 | [diff] [blame] | 136 | struct pt_regs *regs = get_irq_regs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | |
| 138 | printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 139 | printk("epc : %08lx\nStatus: %08lx\n" |
| 140 | "Cause : %08lx\nbadVaddr : %08lx\n", |
| 141 | regs->cp0_epc, regs->cp0_status, |
| 142 | regs->cp0_cause, regs->cp0_badvaddr); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 143 | |
| 144 | /* Read all the registers and then print them as there is a |
| 145 | problem with interspersed printk's upsetting the Bonito controller. |
| 146 | Do it for the others too. |
| 147 | */ |
| 148 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | switch(mips_revision_corid) { |
| 150 | case MIPS_REVISION_CORID_CORE_MSC: |
| 151 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 152 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Chris Dearman | 7a83419 | 2006-04-15 00:31:16 +0100 | [diff] [blame] | 153 | case MIPS_REVISION_CORID_CORE_24K: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 154 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 155 | ll_msc_irq(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | break; |
| 157 | case MIPS_REVISION_CORID_QED_RM5261: |
| 158 | case MIPS_REVISION_CORID_CORE_LV: |
| 159 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 160 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 161 | intrcause = GT_READ(GT_INTRCAUSE_OFS); |
| 162 | datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 164 | printk("GT_INTRCAUSE = %08x\n", intrcause); |
| 165 | printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | break; |
| 167 | case MIPS_REVISION_CORID_BONITO64: |
| 168 | case MIPS_REVISION_CORID_CORE_20K: |
| 169 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 170 | pcibadaddr = BONITO_PCIBADADDR; |
| 171 | pcimstat = BONITO_PCIMSTAT; |
| 172 | intisr = BONITO_INTISR; |
| 173 | inten = BONITO_INTEN; |
| 174 | intpol = BONITO_INTPOL; |
| 175 | intedge = BONITO_INTEDGE; |
| 176 | intsteer = BONITO_INTSTEER; |
| 177 | pcicmd = BONITO_PCICMD; |
| 178 | printk("BONITO_INTISR = %08x\n", intisr); |
| 179 | printk("BONITO_INTEN = %08x\n", inten); |
| 180 | printk("BONITO_INTPOL = %08x\n", intpol); |
| 181 | printk("BONITO_INTEDGE = %08x\n", intedge); |
| 182 | printk("BONITO_INTSTEER = %08x\n", intsteer); |
| 183 | printk("BONITO_PCICMD = %08x\n", pcicmd); |
| 184 | printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); |
| 185 | printk("BONITO_PCIMSTAT = %08x\n", pcimstat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | break; |
| 187 | } |
| 188 | |
| 189 | /* We die here*/ |
| 190 | die("CoreHi interrupt", regs); |
| 191 | } |
| 192 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 193 | static inline int clz(unsigned long x) |
| 194 | { |
| 195 | __asm__ ( |
| 196 | " .set push \n" |
| 197 | " .set mips32 \n" |
| 198 | " clz %0, %1 \n" |
| 199 | " .set pop \n" |
| 200 | : "=r" (x) |
| 201 | : "r" (x)); |
| 202 | |
| 203 | return x; |
| 204 | } |
| 205 | |
| 206 | /* |
| 207 | * Version of ffs that only looks at bits 12..15. |
| 208 | */ |
| 209 | static inline unsigned int irq_ffs(unsigned int pending) |
| 210 | { |
| 211 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
| 212 | return -clz(pending) + 31 - CAUSEB_IP; |
| 213 | #else |
| 214 | unsigned int a0 = 7; |
| 215 | unsigned int t0; |
| 216 | |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 217 | t0 = pending & 0xf000; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 218 | t0 = t0 < 1; |
| 219 | t0 = t0 << 2; |
| 220 | a0 = a0 - t0; |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 221 | pending = pending << t0; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 222 | |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 223 | t0 = pending & 0xc000; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 224 | t0 = t0 < 1; |
| 225 | t0 = t0 << 1; |
| 226 | a0 = a0 - t0; |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 227 | pending = pending << t0; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 228 | |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 229 | t0 = pending & 0x8000; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 230 | t0 = t0 < 1; |
| 231 | //t0 = t0 << 2; |
| 232 | a0 = a0 - t0; |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 233 | //pending = pending << t0; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 234 | |
| 235 | return a0; |
| 236 | #endif |
| 237 | } |
| 238 | |
| 239 | /* |
| 240 | * IRQs on the Malta board look basically (barring software IRQs which we |
| 241 | * don't use at all and all external interrupt sources are combined together |
| 242 | * on hardware interrupt 0 (MIPS IRQ 2)) like: |
| 243 | * |
| 244 | * MIPS IRQ Source |
| 245 | * -------- ------ |
| 246 | * 0 Software (ignored) |
| 247 | * 1 Software (ignored) |
| 248 | * 2 Combined hardware interrupt (hw0) |
| 249 | * 3 Hardware (ignored) |
| 250 | * 4 Hardware (ignored) |
| 251 | * 5 Hardware (ignored) |
| 252 | * 6 Hardware (ignored) |
| 253 | * 7 R4k timer (what we use) |
| 254 | * |
| 255 | * We handle the IRQ according to _our_ priority which is: |
| 256 | * |
| 257 | * Highest ---- R4k Timer |
| 258 | * Lowest ---- Combined hardware interrupt |
| 259 | * |
| 260 | * then we just return, if multiple IRQs are pending then we will just take |
| 261 | * another exception, big deal. |
| 262 | */ |
| 263 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 264 | asmlinkage void plat_irq_dispatch(void) |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 265 | { |
| 266 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; |
| 267 | int irq; |
| 268 | |
| 269 | irq = irq_ffs(pending); |
| 270 | |
| 271 | if (irq == MIPSCPU_INT_I8259A) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 272 | malta_hw0_irqdispatch(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 273 | else if (irq > 0) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 274 | do_IRQ(MIPSCPU_INT_BASE + irq); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 275 | else |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 276 | spurious_interrupt(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 277 | } |
| 278 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 279 | static struct irqaction i8259irq = { |
| 280 | .handler = no_action, |
| 281 | .name = "XT-PIC cascade" |
| 282 | }; |
| 283 | |
| 284 | static struct irqaction corehi_irqaction = { |
| 285 | .handler = no_action, |
| 286 | .name = "CoreHi" |
| 287 | }; |
| 288 | |
| 289 | msc_irqmap_t __initdata msc_irqmap[] = { |
| 290 | {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 291 | {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 292 | }; |
Ahmed S. Darwish | 25b8ac3 | 2007-02-05 04:42:11 +0200 | [diff] [blame] | 293 | int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 294 | |
| 295 | msc_irqmap_t __initdata msc_eicirqmap[] = { |
| 296 | {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, |
| 297 | {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, |
| 298 | {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, |
| 299 | {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, |
| 300 | {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, |
| 301 | {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, |
| 302 | {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 303 | {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 304 | {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, |
| 305 | {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} |
| 306 | }; |
Ahmed S. Darwish | 25b8ac3 | 2007-02-05 04:42:11 +0200 | [diff] [blame] | 307 | int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 308 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | void __init arch_init_irq(void) |
| 310 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | init_i8259_irqs(); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 312 | |
| 313 | if (!cpu_has_veic) |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 314 | mips_cpu_irq_init(); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 315 | |
| 316 | switch(mips_revision_corid) { |
| 317 | case MIPS_REVISION_CORID_CORE_MSC: |
| 318 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 319 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Chris Dearman | 7a83419 | 2006-04-15 00:31:16 +0100 | [diff] [blame] | 320 | case MIPS_REVISION_CORID_CORE_24K: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 321 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 322 | if (cpu_has_veic) |
| 323 | init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); |
| 324 | else |
| 325 | init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); |
| 326 | } |
| 327 | |
| 328 | if (cpu_has_veic) { |
| 329 | set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); |
| 330 | set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); |
| 331 | setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); |
| 332 | setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); |
| 333 | } |
| 334 | else if (cpu_has_vint) { |
| 335 | set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); |
| 336 | set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 337 | #ifdef CONFIG_MIPS_MT_SMTC |
| 338 | setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq, |
| 339 | (0x100 << MIPSCPU_INT_I8259A)); |
| 340 | setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, |
| 341 | &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); |
| 342 | #else /* Not SMTC */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 343 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
| 344 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 345 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 346 | } |
| 347 | else { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 348 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
| 349 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); |
| 350 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | } |