blob: 39c3969ac1c7fc7d6b977fc3d65cb995ba208aee [file] [log] [blame]
Dmitry Baryshkov9c636342008-09-10 05:01:17 +04001/*
2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
3 * which contain:
4 *
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/clk.h>
18#include <linux/delay.h>
Paul Gortmakerda155d52011-07-15 12:38:28 -040019#include <linux/module.h>
Rob Herring23019a72012-03-20 14:33:19 -050020#include <linux/io.h>
Mike Dunn3b4bc7b2013-01-07 13:55:13 -080021#include <linux/gpio.h>
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040022
23#include <sound/ac97_codec.h>
24#include <sound/pxa2xx-lib.h>
25
Rob Herring9482ee72012-01-03 17:10:17 -060026#include <mach/irqs.h>
Eric Miao1f017a92008-11-28 14:19:33 +080027#include <mach/regs-ac97.h>
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040028#include <mach/audio.h>
29
30static DEFINE_MUTEX(car_mutex);
31static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
32static volatile long gsr_bits;
33static struct clk *ac97_clk;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040034static struct clk *ac97conf_clk;
Robert Jarzmik26ade892009-03-15 14:10:54 +010035static int reset_gpio;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040036
Mike Dunn053fe0f2013-01-07 13:55:14 -080037extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
Eric Miaofb1bf8c2010-01-04 16:30:58 +080038
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040039/*
40 * Beware PXA27x bugs:
41 *
42 * o Slot 12 read from modem space will hang controller.
43 * o CDONE, SDONE interrupt fails after any slot 12 IO.
44 *
45 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
46 * 1 jiffy timeout if interrupt never comes).
47 */
48
49unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
50{
51 unsigned short val = -1;
52 volatile u32 *reg_addr;
53
54 mutex_lock(&car_mutex);
55
56 /* set up primary or secondary codec space */
Marc Zyngier8825e8e2008-10-14 09:57:05 +010057 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040058 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
59 else
60 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040061 reg_addr += (reg >> 1);
62
63 /* start read access across the ac97 link */
64 GSR = GSR_CDONE | GSR_SDONE;
65 gsr_bits = 0;
66 val = *reg_addr;
67 if (reg == AC97_GPIO_STATUS)
68 goto out;
69 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
70 !((GSR | gsr_bits) & GSR_SDONE)) {
71 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
72 __func__, reg, GSR | gsr_bits);
73 val = -1;
74 goto out;
75 }
76
77 /* valid data now */
78 GSR = GSR_CDONE | GSR_SDONE;
79 gsr_bits = 0;
80 val = *reg_addr;
81 /* but we've just started another cycle... */
82 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
83
84out: mutex_unlock(&car_mutex);
85 return val;
86}
87EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
88
89void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
90 unsigned short val)
91{
92 volatile u32 *reg_addr;
93
94 mutex_lock(&car_mutex);
95
96 /* set up primary or secondary codec space */
Marc Zyngier8825e8e2008-10-14 09:57:05 +010097 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040098 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
99 else
100 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400101 reg_addr += (reg >> 1);
102
103 GSR = GSR_CDONE | GSR_SDONE;
104 gsr_bits = 0;
105 *reg_addr = val;
106 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
107 !((GSR | gsr_bits) & GSR_CDONE))
108 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
109 __func__, reg, GSR | gsr_bits);
110
111 mutex_unlock(&car_mutex);
112}
113EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
114
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400115#ifdef CONFIG_PXA25x
116static inline void pxa_ac97_warm_pxa25x(void)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400117{
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400118 gsr_bits = 0;
119
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400120 GCR |= GCR_WARM_RST;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400121}
122
123static inline void pxa_ac97_cold_pxa25x(void)
124{
125 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
126 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
127
128 gsr_bits = 0;
129
130 GCR = GCR_COLD_RST;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400131}
132#endif
133
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400134#ifdef CONFIG_PXA27x
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400135static inline void pxa_ac97_warm_pxa27x(void)
136{
137 gsr_bits = 0;
138
Eric Miaofb1bf8c2010-01-04 16:30:58 +0800139 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
Mike Dunn053fe0f2013-01-07 13:55:14 -0800140 pxa27x_configure_ac97reset(reset_gpio, true);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400141 udelay(10);
142 GCR |= GCR_WARM_RST;
Mike Dunn053fe0f2013-01-07 13:55:14 -0800143 pxa27x_configure_ac97reset(reset_gpio, false);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400144 udelay(500);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400145}
146
147static inline void pxa_ac97_cold_pxa27x(void)
148{
149 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
150 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
151
152 gsr_bits = 0;
153
154 /* PXA27x Developers Manual section 13.5.2.2.1 */
Robert Jarzmik4091d342014-06-09 21:59:12 +0200155 clk_prepare_enable(ac97conf_clk);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400156 udelay(5);
Robert Jarzmik4091d342014-06-09 21:59:12 +0200157 clk_disable_unprepare(ac97conf_clk);
Mike Dunn41b645c2013-01-07 13:55:12 -0800158 GCR = GCR_COLD_RST | GCR_WARM_RST;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400159}
160#endif
161
162#ifdef CONFIG_PXA3xx
163static inline void pxa_ac97_warm_pxa3xx(void)
164{
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400165 gsr_bits = 0;
166
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400167 /* Can't use interrupts */
168 GCR |= GCR_WARM_RST;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400169}
170
171static inline void pxa_ac97_cold_pxa3xx(void)
172{
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400173 /* Hold CLKBPB for 100us */
174 GCR = 0;
175 GCR = GCR_CLKBPB;
176 udelay(100);
177 GCR = 0;
178
179 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
180 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
181
182 gsr_bits = 0;
183
184 /* Can't use interrupts on PXA3xx */
185 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
186
187 GCR = GCR_WARM_RST | GCR_COLD_RST;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400188}
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400189#endif
190
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400191bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
192{
Luotao Fu057de502009-03-26 13:18:03 +0100193 unsigned long gsr;
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400194 unsigned int timeout = 100;
Luotao Fu057de502009-03-26 13:18:03 +0100195
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400196#ifdef CONFIG_PXA25x
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100197 if (cpu_is_pxa25x())
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400198 pxa_ac97_warm_pxa25x();
199 else
200#endif
201#ifdef CONFIG_PXA27x
202 if (cpu_is_pxa27x())
203 pxa_ac97_warm_pxa27x();
204 else
205#endif
206#ifdef CONFIG_PXA3xx
207 if (cpu_is_pxa3xx())
208 pxa_ac97_warm_pxa3xx();
209 else
210#endif
Takashi Iwai88ec7ae2013-11-05 15:33:40 +0100211 snd_BUG();
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400212
213 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
214 mdelay(1);
215
Luotao Fu057de502009-03-26 13:18:03 +0100216 gsr = GSR | gsr_bits;
217 if (!(gsr & (GSR_PCR | GSR_SCR))) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400218 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
Luotao Fu057de502009-03-26 13:18:03 +0100219 __func__, gsr);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400220
221 return false;
222 }
223
224 return true;
225}
226EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
227
228bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
229{
Luotao Fu057de502009-03-26 13:18:03 +0100230 unsigned long gsr;
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400231 unsigned int timeout = 1000;
Luotao Fu057de502009-03-26 13:18:03 +0100232
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400233#ifdef CONFIG_PXA25x
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100234 if (cpu_is_pxa25x())
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400235 pxa_ac97_cold_pxa25x();
236 else
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400237#endif
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400238#ifdef CONFIG_PXA27x
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400239 if (cpu_is_pxa27x())
240 pxa_ac97_cold_pxa27x();
241 else
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400242#endif
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400243#ifdef CONFIG_PXA3xx
244 if (cpu_is_pxa3xx())
245 pxa_ac97_cold_pxa3xx();
246 else
247#endif
Takashi Iwai88ec7ae2013-11-05 15:33:40 +0100248 snd_BUG();
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400249
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400250 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
251 mdelay(1);
252
Luotao Fu057de502009-03-26 13:18:03 +0100253 gsr = GSR | gsr_bits;
254 if (!(gsr & (GSR_PCR | GSR_SCR))) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400255 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
Luotao Fu057de502009-03-26 13:18:03 +0100256 __func__, gsr);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400257
258 return false;
259 }
260
261 return true;
262}
263EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
264
265
266void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
267{
268 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
269 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
270}
271EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
272
273static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
274{
275 long status;
276
277 status = GSR;
278 if (status) {
279 GSR = status;
280 gsr_bits |= status;
281 wake_up(&gsr_wq);
282
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400283 /* Although we don't use those we still need to clear them
284 since they tend to spuriously trigger when MMC is used
285 (hardware bug? go figure)... */
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400286 if (cpu_is_pxa27x()) {
287 MISR = MISR_EOC;
288 PISR = PISR_EOC;
289 MCSR = MCSR_EOC;
290 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400291
292 return IRQ_HANDLED;
293 }
294
295 return IRQ_NONE;
296}
297
298#ifdef CONFIG_PM
299int pxa2xx_ac97_hw_suspend(void)
300{
301 GCR |= GCR_ACLINK_OFF;
Robert Jarzmik4091d342014-06-09 21:59:12 +0200302 clk_disable_unprepare(ac97_clk);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400303 return 0;
304}
305EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
306
307int pxa2xx_ac97_hw_resume(void)
308{
Robert Jarzmik4091d342014-06-09 21:59:12 +0200309 clk_prepare_enable(ac97_clk);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400310 return 0;
311}
312EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
313#endif
314
Bill Pembertone21596b2012-12-06 12:35:12 -0500315int pxa2xx_ac97_hw_probe(struct platform_device *dev)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400316{
317 int ret;
Mark Browneae17752009-04-13 11:48:03 +0100318 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
Robert Jarzmik26ade892009-03-15 14:10:54 +0100319
320 if (pdata) {
321 switch (pdata->reset_gpio) {
322 case 95:
323 case 113:
324 reset_gpio = pdata->reset_gpio;
325 break;
326 case 0:
327 reset_gpio = 113;
328 break;
329 case -1:
330 break;
331 default:
Takashi Iwai1f218692009-03-19 14:08:58 +0100332 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
Robert Jarzmik26ade892009-03-15 14:10:54 +0100333 pdata->reset_gpio);
334 }
335 } else {
336 if (cpu_is_pxa27x())
337 reset_gpio = 113;
338 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400339
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400340 if (cpu_is_pxa27x()) {
Mike Dunn3b4bc7b2013-01-07 13:55:13 -0800341 /*
342 * This gpio is needed for a work-around to a bug in the ac97
343 * controller during warm reset. The direction and level is set
344 * here so that it is an output driven high when switching from
345 * AC97_nRESET alt function to generic gpio.
346 */
347 ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
348 "pxa27x ac97 reset");
349 if (ret < 0) {
350 pr_err("%s: gpio_request_one() failed: %d\n",
351 __func__, ret);
352 goto err_conf;
353 }
Mike Dunn053fe0f2013-01-07 13:55:14 -0800354 pxa27x_configure_ac97reset(reset_gpio, false);
Mike Dunn3b4bc7b2013-01-07 13:55:13 -0800355
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400356 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
357 if (IS_ERR(ac97conf_clk)) {
358 ret = PTR_ERR(ac97conf_clk);
359 ac97conf_clk = NULL;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300360 goto err_conf;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400361 }
362 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400363
364 ac97_clk = clk_get(&dev->dev, "AC97CLK");
365 if (IS_ERR(ac97_clk)) {
366 ret = PTR_ERR(ac97_clk);
367 ac97_clk = NULL;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300368 goto err_clk;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400369 }
370
Robert Jarzmik4091d342014-06-09 21:59:12 +0200371 ret = clk_prepare_enable(ac97_clk);
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300372 if (ret)
373 goto err_clk2;
374
Yong Zhang88e24c32011-09-22 16:59:20 +0800375 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300376 if (ret < 0)
377 goto err_irq;
378
379 return 0;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400380
381err_irq:
382 GCR |= GCR_ACLINK_OFF;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300383err_clk2:
384 clk_put(ac97_clk);
385 ac97_clk = NULL;
386err_clk:
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400387 if (ac97conf_clk) {
388 clk_put(ac97conf_clk);
389 ac97conf_clk = NULL;
390 }
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300391err_conf:
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400392 return ret;
393}
394EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
395
396void pxa2xx_ac97_hw_remove(struct platform_device *dev)
397{
Mike Dunn3b4bc7b2013-01-07 13:55:13 -0800398 if (cpu_is_pxa27x())
399 gpio_free(reset_gpio);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400400 GCR |= GCR_ACLINK_OFF;
401 free_irq(IRQ_AC97, NULL);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400402 if (ac97conf_clk) {
403 clk_put(ac97conf_clk);
404 ac97conf_clk = NULL;
405 }
Robert Jarzmik4091d342014-06-09 21:59:12 +0200406 clk_disable_unprepare(ac97_clk);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400407 clk_put(ac97_clk);
408 ac97_clk = NULL;
409}
410EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
411
412MODULE_AUTHOR("Nicolas Pitre");
413MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
414MODULE_LICENSE("GPL");
415