Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/char/synclink.c |
| 3 | * |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 4 | * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Device driver for Microgate SyncLink ISA and PCI |
| 7 | * high speed multiprotocol serial adapters. |
| 8 | * |
| 9 | * written by Paul Fulghum for Microgate Corporation |
| 10 | * paulkf@microgate.com |
| 11 | * |
| 12 | * Microgate and SyncLink are trademarks of Microgate Corporation |
| 13 | * |
| 14 | * Derived from serial.c written by Theodore Ts'o and Linus Torvalds |
| 15 | * |
| 16 | * Original release 01/11/99 |
| 17 | * |
| 18 | * This code is released under the GNU General Public License (GPL) |
| 19 | * |
| 20 | * This driver is primarily intended for use in synchronous |
| 21 | * HDLC mode. Asynchronous mode is also provided. |
| 22 | * |
| 23 | * When operating in synchronous mode, each call to mgsl_write() |
| 24 | * contains exactly one complete HDLC frame. Calling mgsl_put_char |
| 25 | * will start assembling an HDLC frame that will not be sent until |
| 26 | * mgsl_flush_chars or mgsl_write is called. |
| 27 | * |
| 28 | * Synchronous receive data is reported as complete frames. To accomplish |
| 29 | * this, the TTY flip buffer is bypassed (too small to hold largest |
| 30 | * frame and may fragment frames) and the line discipline |
| 31 | * receive entry point is called directly. |
| 32 | * |
| 33 | * This driver has been tested with a slightly modified ppp.c driver |
| 34 | * for synchronous PPP. |
| 35 | * |
| 36 | * 2000/02/16 |
| 37 | * Added interface for syncppp.c driver (an alternate synchronous PPP |
| 38 | * implementation that also supports Cisco HDLC). Each device instance |
| 39 | * registers as a tty device AND a network device (if dosyncppp option |
| 40 | * is set for the device). The functionality is determined by which |
| 41 | * device interface is opened. |
| 42 | * |
| 43 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 44 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 45 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 46 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, |
| 47 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 48 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 49 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 50 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 51 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 52 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
| 53 | * OF THE POSSIBILITY OF SUCH DAMAGE. |
| 54 | */ |
| 55 | |
| 56 | #if defined(__i386__) |
| 57 | # define BREAKPOINT() asm(" int $3"); |
| 58 | #else |
| 59 | # define BREAKPOINT() { } |
| 60 | #endif |
| 61 | |
| 62 | #define MAX_ISA_DEVICES 10 |
| 63 | #define MAX_PCI_DEVICES 10 |
| 64 | #define MAX_TOTAL_DEVICES 20 |
| 65 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | #include <linux/module.h> |
| 67 | #include <linux/errno.h> |
| 68 | #include <linux/signal.h> |
| 69 | #include <linux/sched.h> |
| 70 | #include <linux/timer.h> |
| 71 | #include <linux/interrupt.h> |
| 72 | #include <linux/pci.h> |
| 73 | #include <linux/tty.h> |
| 74 | #include <linux/tty_flip.h> |
| 75 | #include <linux/serial.h> |
| 76 | #include <linux/major.h> |
| 77 | #include <linux/string.h> |
| 78 | #include <linux/fcntl.h> |
| 79 | #include <linux/ptrace.h> |
| 80 | #include <linux/ioport.h> |
| 81 | #include <linux/mm.h> |
| 82 | #include <linux/slab.h> |
| 83 | #include <linux/delay.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | #include <linux/netdevice.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | #include <linux/vmalloc.h> |
| 86 | #include <linux/init.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | #include <linux/ioctl.h> |
Robert P. J. Day | 3dd1247 | 2008-02-06 01:37:17 -0800 | [diff] [blame] | 88 | #include <linux/synclink.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | |
| 90 | #include <asm/system.h> |
| 91 | #include <asm/io.h> |
| 92 | #include <asm/irq.h> |
| 93 | #include <asm/dma.h> |
| 94 | #include <linux/bitops.h> |
| 95 | #include <asm/types.h> |
| 96 | #include <linux/termios.h> |
| 97 | #include <linux/workqueue.h> |
| 98 | #include <linux/hdlc.h> |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 99 | #include <linux/dma-mapping.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 101 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE)) |
| 102 | #define SYNCLINK_GENERIC_HDLC 1 |
| 103 | #else |
| 104 | #define SYNCLINK_GENERIC_HDLC 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | #endif |
| 106 | |
| 107 | #define GET_USER(error,value,addr) error = get_user(value,addr) |
| 108 | #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 |
| 109 | #define PUT_USER(error,value,addr) error = put_user(value,addr) |
| 110 | #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 |
| 111 | |
| 112 | #include <asm/uaccess.h> |
| 113 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | #define RCLRVALUE 0xffff |
| 115 | |
| 116 | static MGSL_PARAMS default_params = { |
| 117 | MGSL_MODE_HDLC, /* unsigned long mode */ |
| 118 | 0, /* unsigned char loopback; */ |
| 119 | HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ |
| 120 | HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ |
| 121 | 0, /* unsigned long clock_speed; */ |
| 122 | 0xff, /* unsigned char addr_filter; */ |
| 123 | HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ |
| 124 | HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ |
| 125 | HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ |
| 126 | 9600, /* unsigned long data_rate; */ |
| 127 | 8, /* unsigned char data_bits; */ |
| 128 | 1, /* unsigned char stop_bits; */ |
| 129 | ASYNC_PARITY_NONE /* unsigned char parity; */ |
| 130 | }; |
| 131 | |
| 132 | #define SHARED_MEM_ADDRESS_SIZE 0x40000 |
Paul Fulghum | 623a439 | 2006-10-17 00:09:27 -0700 | [diff] [blame] | 133 | #define BUFFERLISTSIZE 4096 |
| 134 | #define DMABUFFERSIZE 4096 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | #define MAXRXFRAMES 7 |
| 136 | |
| 137 | typedef struct _DMABUFFERENTRY |
| 138 | { |
| 139 | u32 phys_addr; /* 32-bit flat physical address of data buffer */ |
Paul Fulghum | 4a918bc | 2005-09-09 13:02:12 -0700 | [diff] [blame] | 140 | volatile u16 count; /* buffer size/data count */ |
| 141 | volatile u16 status; /* Control/status field */ |
| 142 | volatile u16 rcc; /* character count field */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | u16 reserved; /* padding required by 16C32 */ |
| 144 | u32 link; /* 32-bit flat link to next buffer entry */ |
| 145 | char *virt_addr; /* virtual address of data buffer */ |
| 146 | u32 phys_entry; /* physical address of this buffer entry */ |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 147 | dma_addr_t dma_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | } DMABUFFERENTRY, *DMAPBUFFERENTRY; |
| 149 | |
| 150 | /* The queue of BH actions to be performed */ |
| 151 | |
| 152 | #define BH_RECEIVE 1 |
| 153 | #define BH_TRANSMIT 2 |
| 154 | #define BH_STATUS 4 |
| 155 | |
| 156 | #define IO_PIN_SHUTDOWN_LIMIT 100 |
| 157 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | struct _input_signal_events { |
| 159 | int ri_up; |
| 160 | int ri_down; |
| 161 | int dsr_up; |
| 162 | int dsr_down; |
| 163 | int dcd_up; |
| 164 | int dcd_down; |
| 165 | int cts_up; |
| 166 | int cts_down; |
| 167 | }; |
| 168 | |
| 169 | /* transmit holding buffer definitions*/ |
| 170 | #define MAX_TX_HOLDING_BUFFERS 5 |
| 171 | struct tx_holding_buffer { |
| 172 | int buffer_size; |
| 173 | unsigned char * buffer; |
| 174 | }; |
| 175 | |
| 176 | |
| 177 | /* |
| 178 | * Device instance data structure |
| 179 | */ |
| 180 | |
| 181 | struct mgsl_struct { |
| 182 | int magic; |
| 183 | int flags; |
| 184 | int count; /* count of opens */ |
| 185 | int line; |
| 186 | int hw_version; |
| 187 | unsigned short close_delay; |
| 188 | unsigned short closing_wait; /* time to wait before closing */ |
| 189 | |
| 190 | struct mgsl_icount icount; |
| 191 | |
| 192 | struct tty_struct *tty; |
| 193 | int timeout; |
| 194 | int x_char; /* xon/xoff character */ |
| 195 | int blocked_open; /* # of blocked opens */ |
| 196 | u16 read_status_mask; |
| 197 | u16 ignore_status_mask; |
| 198 | unsigned char *xmit_buf; |
| 199 | int xmit_head; |
| 200 | int xmit_tail; |
| 201 | int xmit_cnt; |
| 202 | |
| 203 | wait_queue_head_t open_wait; |
| 204 | wait_queue_head_t close_wait; |
| 205 | |
| 206 | wait_queue_head_t status_event_wait_q; |
| 207 | wait_queue_head_t event_wait_q; |
| 208 | struct timer_list tx_timer; /* HDLC transmit timeout timer */ |
| 209 | struct mgsl_struct *next_device; /* device list link */ |
| 210 | |
| 211 | spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */ |
| 212 | struct work_struct task; /* task structure for scheduling bh */ |
| 213 | |
| 214 | u32 EventMask; /* event trigger mask */ |
| 215 | u32 RecordedEvents; /* pending events */ |
| 216 | |
| 217 | u32 max_frame_size; /* as set by device config */ |
| 218 | |
| 219 | u32 pending_bh; |
| 220 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 221 | bool bh_running; /* Protection from multiple */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | int isr_overflow; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 223 | bool bh_requested; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | |
| 225 | int dcd_chkcount; /* check counts to prevent */ |
| 226 | int cts_chkcount; /* too many IRQs if a signal */ |
| 227 | int dsr_chkcount; /* is floating */ |
| 228 | int ri_chkcount; |
| 229 | |
| 230 | char *buffer_list; /* virtual address of Rx & Tx buffer lists */ |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 231 | u32 buffer_list_phys; |
| 232 | dma_addr_t buffer_list_dma_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | |
| 234 | unsigned int rx_buffer_count; /* count of total allocated Rx buffers */ |
| 235 | DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */ |
| 236 | unsigned int current_rx_buffer; |
| 237 | |
| 238 | int num_tx_dma_buffers; /* number of tx dma frames required */ |
| 239 | int tx_dma_buffers_used; |
| 240 | unsigned int tx_buffer_count; /* count of total allocated Tx buffers */ |
| 241 | DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */ |
| 242 | int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */ |
| 243 | int current_tx_buffer; /* next tx dma buffer to be loaded */ |
| 244 | |
| 245 | unsigned char *intermediate_rxbuffer; |
| 246 | |
| 247 | int num_tx_holding_buffers; /* number of tx holding buffer allocated */ |
| 248 | int get_tx_holding_index; /* next tx holding buffer for adapter to load */ |
| 249 | int put_tx_holding_index; /* next tx holding buffer to store user request */ |
| 250 | int tx_holding_count; /* number of tx holding buffers waiting */ |
| 251 | struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS]; |
| 252 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 253 | bool rx_enabled; |
| 254 | bool rx_overflow; |
| 255 | bool rx_rcc_underrun; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 257 | bool tx_enabled; |
| 258 | bool tx_active; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | u32 idle_mode; |
| 260 | |
| 261 | u16 cmr_value; |
| 262 | u16 tcsr_value; |
| 263 | |
| 264 | char device_name[25]; /* device instance name */ |
| 265 | |
| 266 | unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ |
| 267 | unsigned char bus; /* expansion bus number (zero based) */ |
| 268 | unsigned char function; /* PCI device number */ |
| 269 | |
| 270 | unsigned int io_base; /* base I/O address of adapter */ |
| 271 | unsigned int io_addr_size; /* size of the I/O address range */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 272 | bool io_addr_requested; /* true if I/O address requested */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 273 | |
| 274 | unsigned int irq_level; /* interrupt level */ |
| 275 | unsigned long irq_flags; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 276 | bool irq_requested; /* true if IRQ requested */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | |
| 278 | unsigned int dma_level; /* DMA channel */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 279 | bool dma_requested; /* true if dma channel requested */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | |
| 281 | u16 mbre_bit; |
| 282 | u16 loopback_bits; |
| 283 | u16 usc_idle_mode; |
| 284 | |
| 285 | MGSL_PARAMS params; /* communications parameters */ |
| 286 | |
| 287 | unsigned char serial_signals; /* current serial signal states */ |
| 288 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 289 | bool irq_occurred; /* for diagnostics use */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | unsigned int init_error; /* Initialization startup error (DIAGS) */ |
| 291 | int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */ |
| 292 | |
| 293 | u32 last_mem_alloc; |
| 294 | unsigned char* memory_base; /* shared memory address (PCI only) */ |
| 295 | u32 phys_memory_base; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 296 | bool shared_mem_requested; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | |
| 298 | unsigned char* lcr_base; /* local config registers (PCI only) */ |
| 299 | u32 phys_lcr_base; |
| 300 | u32 lcr_offset; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 301 | bool lcr_mem_requested; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | |
| 303 | u32 misc_ctrl_value; |
| 304 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; |
| 305 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 306 | bool drop_rts_on_tx_done; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 307 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 308 | bool loopmode_insert_requested; |
| 309 | bool loopmode_send_done_requested; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | |
| 311 | struct _input_signal_events input_signal_events; |
| 312 | |
| 313 | /* generic HDLC device parts */ |
| 314 | int netcount; |
| 315 | int dosyncppp; |
| 316 | spinlock_t netlock; |
| 317 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 318 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | struct net_device *netdev; |
| 320 | #endif |
| 321 | }; |
| 322 | |
| 323 | #define MGSL_MAGIC 0x5401 |
| 324 | |
| 325 | /* |
| 326 | * The size of the serial xmit buffer is 1 page, or 4096 bytes |
| 327 | */ |
| 328 | #ifndef SERIAL_XMIT_SIZE |
| 329 | #define SERIAL_XMIT_SIZE 4096 |
| 330 | #endif |
| 331 | |
| 332 | /* |
| 333 | * These macros define the offsets used in calculating the |
| 334 | * I/O address of the specified USC registers. |
| 335 | */ |
| 336 | |
| 337 | |
| 338 | #define DCPIN 2 /* Bit 1 of I/O address */ |
| 339 | #define SDPIN 4 /* Bit 2 of I/O address */ |
| 340 | |
| 341 | #define DCAR 0 /* DMA command/address register */ |
| 342 | #define CCAR SDPIN /* channel command/address register */ |
| 343 | #define DATAREG DCPIN + SDPIN /* serial data register */ |
| 344 | #define MSBONLY 0x41 |
| 345 | #define LSBONLY 0x40 |
| 346 | |
| 347 | /* |
| 348 | * These macros define the register address (ordinal number) |
| 349 | * used for writing address/value pairs to the USC. |
| 350 | */ |
| 351 | |
| 352 | #define CMR 0x02 /* Channel mode Register */ |
| 353 | #define CCSR 0x04 /* Channel Command/status Register */ |
| 354 | #define CCR 0x06 /* Channel Control Register */ |
| 355 | #define PSR 0x08 /* Port status Register */ |
| 356 | #define PCR 0x0a /* Port Control Register */ |
| 357 | #define TMDR 0x0c /* Test mode Data Register */ |
| 358 | #define TMCR 0x0e /* Test mode Control Register */ |
| 359 | #define CMCR 0x10 /* Clock mode Control Register */ |
| 360 | #define HCR 0x12 /* Hardware Configuration Register */ |
| 361 | #define IVR 0x14 /* Interrupt Vector Register */ |
| 362 | #define IOCR 0x16 /* Input/Output Control Register */ |
| 363 | #define ICR 0x18 /* Interrupt Control Register */ |
| 364 | #define DCCR 0x1a /* Daisy Chain Control Register */ |
| 365 | #define MISR 0x1c /* Misc Interrupt status Register */ |
| 366 | #define SICR 0x1e /* status Interrupt Control Register */ |
| 367 | #define RDR 0x20 /* Receive Data Register */ |
| 368 | #define RMR 0x22 /* Receive mode Register */ |
| 369 | #define RCSR 0x24 /* Receive Command/status Register */ |
| 370 | #define RICR 0x26 /* Receive Interrupt Control Register */ |
| 371 | #define RSR 0x28 /* Receive Sync Register */ |
| 372 | #define RCLR 0x2a /* Receive count Limit Register */ |
| 373 | #define RCCR 0x2c /* Receive Character count Register */ |
| 374 | #define TC0R 0x2e /* Time Constant 0 Register */ |
| 375 | #define TDR 0x30 /* Transmit Data Register */ |
| 376 | #define TMR 0x32 /* Transmit mode Register */ |
| 377 | #define TCSR 0x34 /* Transmit Command/status Register */ |
| 378 | #define TICR 0x36 /* Transmit Interrupt Control Register */ |
| 379 | #define TSR 0x38 /* Transmit Sync Register */ |
| 380 | #define TCLR 0x3a /* Transmit count Limit Register */ |
| 381 | #define TCCR 0x3c /* Transmit Character count Register */ |
| 382 | #define TC1R 0x3e /* Time Constant 1 Register */ |
| 383 | |
| 384 | |
| 385 | /* |
| 386 | * MACRO DEFINITIONS FOR DMA REGISTERS |
| 387 | */ |
| 388 | |
| 389 | #define DCR 0x06 /* DMA Control Register (shared) */ |
| 390 | #define DACR 0x08 /* DMA Array count Register (shared) */ |
| 391 | #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */ |
| 392 | #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */ |
| 393 | #define DICR 0x18 /* DMA Interrupt Control Register (shared) */ |
| 394 | #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */ |
| 395 | #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */ |
| 396 | |
| 397 | #define TDMR 0x02 /* Transmit DMA mode Register */ |
| 398 | #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */ |
| 399 | #define TBCR 0x2a /* Transmit Byte count Register */ |
| 400 | #define TARL 0x2c /* Transmit Address Register (low) */ |
| 401 | #define TARU 0x2e /* Transmit Address Register (high) */ |
| 402 | #define NTBCR 0x3a /* Next Transmit Byte count Register */ |
| 403 | #define NTARL 0x3c /* Next Transmit Address Register (low) */ |
| 404 | #define NTARU 0x3e /* Next Transmit Address Register (high) */ |
| 405 | |
| 406 | #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */ |
| 407 | #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */ |
| 408 | #define RBCR 0xaa /* Receive Byte count Register */ |
| 409 | #define RARL 0xac /* Receive Address Register (low) */ |
| 410 | #define RARU 0xae /* Receive Address Register (high) */ |
| 411 | #define NRBCR 0xba /* Next Receive Byte count Register */ |
| 412 | #define NRARL 0xbc /* Next Receive Address Register (low) */ |
| 413 | #define NRARU 0xbe /* Next Receive Address Register (high) */ |
| 414 | |
| 415 | |
| 416 | /* |
| 417 | * MACRO DEFINITIONS FOR MODEM STATUS BITS |
| 418 | */ |
| 419 | |
| 420 | #define MODEMSTATUS_DTR 0x80 |
| 421 | #define MODEMSTATUS_DSR 0x40 |
| 422 | #define MODEMSTATUS_RTS 0x20 |
| 423 | #define MODEMSTATUS_CTS 0x10 |
| 424 | #define MODEMSTATUS_RI 0x04 |
| 425 | #define MODEMSTATUS_DCD 0x01 |
| 426 | |
| 427 | |
| 428 | /* |
| 429 | * Channel Command/Address Register (CCAR) Command Codes |
| 430 | */ |
| 431 | |
| 432 | #define RTCmd_Null 0x0000 |
| 433 | #define RTCmd_ResetHighestIus 0x1000 |
| 434 | #define RTCmd_TriggerChannelLoadDma 0x2000 |
| 435 | #define RTCmd_TriggerRxDma 0x2800 |
| 436 | #define RTCmd_TriggerTxDma 0x3000 |
| 437 | #define RTCmd_TriggerRxAndTxDma 0x3800 |
| 438 | #define RTCmd_PurgeRxFifo 0x4800 |
| 439 | #define RTCmd_PurgeTxFifo 0x5000 |
| 440 | #define RTCmd_PurgeRxAndTxFifo 0x5800 |
| 441 | #define RTCmd_LoadRcc 0x6800 |
| 442 | #define RTCmd_LoadTcc 0x7000 |
| 443 | #define RTCmd_LoadRccAndTcc 0x7800 |
| 444 | #define RTCmd_LoadTC0 0x8800 |
| 445 | #define RTCmd_LoadTC1 0x9000 |
| 446 | #define RTCmd_LoadTC0AndTC1 0x9800 |
| 447 | #define RTCmd_SerialDataLSBFirst 0xa000 |
| 448 | #define RTCmd_SerialDataMSBFirst 0xa800 |
| 449 | #define RTCmd_SelectBigEndian 0xb000 |
| 450 | #define RTCmd_SelectLittleEndian 0xb800 |
| 451 | |
| 452 | |
| 453 | /* |
| 454 | * DMA Command/Address Register (DCAR) Command Codes |
| 455 | */ |
| 456 | |
| 457 | #define DmaCmd_Null 0x0000 |
| 458 | #define DmaCmd_ResetTxChannel 0x1000 |
| 459 | #define DmaCmd_ResetRxChannel 0x1200 |
| 460 | #define DmaCmd_StartTxChannel 0x2000 |
| 461 | #define DmaCmd_StartRxChannel 0x2200 |
| 462 | #define DmaCmd_ContinueTxChannel 0x3000 |
| 463 | #define DmaCmd_ContinueRxChannel 0x3200 |
| 464 | #define DmaCmd_PauseTxChannel 0x4000 |
| 465 | #define DmaCmd_PauseRxChannel 0x4200 |
| 466 | #define DmaCmd_AbortTxChannel 0x5000 |
| 467 | #define DmaCmd_AbortRxChannel 0x5200 |
| 468 | #define DmaCmd_InitTxChannel 0x7000 |
| 469 | #define DmaCmd_InitRxChannel 0x7200 |
| 470 | #define DmaCmd_ResetHighestDmaIus 0x8000 |
| 471 | #define DmaCmd_ResetAllChannels 0x9000 |
| 472 | #define DmaCmd_StartAllChannels 0xa000 |
| 473 | #define DmaCmd_ContinueAllChannels 0xb000 |
| 474 | #define DmaCmd_PauseAllChannels 0xc000 |
| 475 | #define DmaCmd_AbortAllChannels 0xd000 |
| 476 | #define DmaCmd_InitAllChannels 0xf000 |
| 477 | |
| 478 | #define TCmd_Null 0x0000 |
| 479 | #define TCmd_ClearTxCRC 0x2000 |
| 480 | #define TCmd_SelectTicrTtsaData 0x4000 |
| 481 | #define TCmd_SelectTicrTxFifostatus 0x5000 |
| 482 | #define TCmd_SelectTicrIntLevel 0x6000 |
| 483 | #define TCmd_SelectTicrdma_level 0x7000 |
| 484 | #define TCmd_SendFrame 0x8000 |
| 485 | #define TCmd_SendAbort 0x9000 |
| 486 | #define TCmd_EnableDleInsertion 0xc000 |
| 487 | #define TCmd_DisableDleInsertion 0xd000 |
| 488 | #define TCmd_ClearEofEom 0xe000 |
| 489 | #define TCmd_SetEofEom 0xf000 |
| 490 | |
| 491 | #define RCmd_Null 0x0000 |
| 492 | #define RCmd_ClearRxCRC 0x2000 |
| 493 | #define RCmd_EnterHuntmode 0x3000 |
| 494 | #define RCmd_SelectRicrRtsaData 0x4000 |
| 495 | #define RCmd_SelectRicrRxFifostatus 0x5000 |
| 496 | #define RCmd_SelectRicrIntLevel 0x6000 |
| 497 | #define RCmd_SelectRicrdma_level 0x7000 |
| 498 | |
| 499 | /* |
| 500 | * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR) |
| 501 | */ |
| 502 | |
| 503 | #define RECEIVE_STATUS BIT5 |
| 504 | #define RECEIVE_DATA BIT4 |
| 505 | #define TRANSMIT_STATUS BIT3 |
| 506 | #define TRANSMIT_DATA BIT2 |
| 507 | #define IO_PIN BIT1 |
| 508 | #define MISC BIT0 |
| 509 | |
| 510 | |
| 511 | /* |
| 512 | * Receive status Bits in Receive Command/status Register RCSR |
| 513 | */ |
| 514 | |
| 515 | #define RXSTATUS_SHORT_FRAME BIT8 |
| 516 | #define RXSTATUS_CODE_VIOLATION BIT8 |
| 517 | #define RXSTATUS_EXITED_HUNT BIT7 |
| 518 | #define RXSTATUS_IDLE_RECEIVED BIT6 |
| 519 | #define RXSTATUS_BREAK_RECEIVED BIT5 |
| 520 | #define RXSTATUS_ABORT_RECEIVED BIT5 |
| 521 | #define RXSTATUS_RXBOUND BIT4 |
| 522 | #define RXSTATUS_CRC_ERROR BIT3 |
| 523 | #define RXSTATUS_FRAMING_ERROR BIT3 |
| 524 | #define RXSTATUS_ABORT BIT2 |
| 525 | #define RXSTATUS_PARITY_ERROR BIT2 |
| 526 | #define RXSTATUS_OVERRUN BIT1 |
| 527 | #define RXSTATUS_DATA_AVAILABLE BIT0 |
| 528 | #define RXSTATUS_ALL 0x01f6 |
| 529 | #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) ) |
| 530 | |
| 531 | /* |
| 532 | * Values for setting transmit idle mode in |
| 533 | * Transmit Control/status Register (TCSR) |
| 534 | */ |
| 535 | #define IDLEMODE_FLAGS 0x0000 |
| 536 | #define IDLEMODE_ALT_ONE_ZERO 0x0100 |
| 537 | #define IDLEMODE_ZERO 0x0200 |
| 538 | #define IDLEMODE_ONE 0x0300 |
| 539 | #define IDLEMODE_ALT_MARK_SPACE 0x0500 |
| 540 | #define IDLEMODE_SPACE 0x0600 |
| 541 | #define IDLEMODE_MARK 0x0700 |
| 542 | #define IDLEMODE_MASK 0x0700 |
| 543 | |
| 544 | /* |
| 545 | * IUSC revision identifiers |
| 546 | */ |
| 547 | #define IUSC_SL1660 0x4d44 |
| 548 | #define IUSC_PRE_SL1660 0x4553 |
| 549 | |
| 550 | /* |
| 551 | * Transmit status Bits in Transmit Command/status Register (TCSR) |
| 552 | */ |
| 553 | |
| 554 | #define TCSR_PRESERVE 0x0F00 |
| 555 | |
| 556 | #define TCSR_UNDERWAIT BIT11 |
| 557 | #define TXSTATUS_PREAMBLE_SENT BIT7 |
| 558 | #define TXSTATUS_IDLE_SENT BIT6 |
| 559 | #define TXSTATUS_ABORT_SENT BIT5 |
| 560 | #define TXSTATUS_EOF_SENT BIT4 |
| 561 | #define TXSTATUS_EOM_SENT BIT4 |
| 562 | #define TXSTATUS_CRC_SENT BIT3 |
| 563 | #define TXSTATUS_ALL_SENT BIT2 |
| 564 | #define TXSTATUS_UNDERRUN BIT1 |
| 565 | #define TXSTATUS_FIFO_EMPTY BIT0 |
| 566 | #define TXSTATUS_ALL 0x00fa |
| 567 | #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) ) |
| 568 | |
| 569 | |
| 570 | #define MISCSTATUS_RXC_LATCHED BIT15 |
| 571 | #define MISCSTATUS_RXC BIT14 |
| 572 | #define MISCSTATUS_TXC_LATCHED BIT13 |
| 573 | #define MISCSTATUS_TXC BIT12 |
| 574 | #define MISCSTATUS_RI_LATCHED BIT11 |
| 575 | #define MISCSTATUS_RI BIT10 |
| 576 | #define MISCSTATUS_DSR_LATCHED BIT9 |
| 577 | #define MISCSTATUS_DSR BIT8 |
| 578 | #define MISCSTATUS_DCD_LATCHED BIT7 |
| 579 | #define MISCSTATUS_DCD BIT6 |
| 580 | #define MISCSTATUS_CTS_LATCHED BIT5 |
| 581 | #define MISCSTATUS_CTS BIT4 |
| 582 | #define MISCSTATUS_RCC_UNDERRUN BIT3 |
| 583 | #define MISCSTATUS_DPLL_NO_SYNC BIT2 |
| 584 | #define MISCSTATUS_BRG1_ZERO BIT1 |
| 585 | #define MISCSTATUS_BRG0_ZERO BIT0 |
| 586 | |
| 587 | #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0)) |
| 588 | #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f)) |
| 589 | |
| 590 | #define SICR_RXC_ACTIVE BIT15 |
| 591 | #define SICR_RXC_INACTIVE BIT14 |
| 592 | #define SICR_RXC (BIT15+BIT14) |
| 593 | #define SICR_TXC_ACTIVE BIT13 |
| 594 | #define SICR_TXC_INACTIVE BIT12 |
| 595 | #define SICR_TXC (BIT13+BIT12) |
| 596 | #define SICR_RI_ACTIVE BIT11 |
| 597 | #define SICR_RI_INACTIVE BIT10 |
| 598 | #define SICR_RI (BIT11+BIT10) |
| 599 | #define SICR_DSR_ACTIVE BIT9 |
| 600 | #define SICR_DSR_INACTIVE BIT8 |
| 601 | #define SICR_DSR (BIT9+BIT8) |
| 602 | #define SICR_DCD_ACTIVE BIT7 |
| 603 | #define SICR_DCD_INACTIVE BIT6 |
| 604 | #define SICR_DCD (BIT7+BIT6) |
| 605 | #define SICR_CTS_ACTIVE BIT5 |
| 606 | #define SICR_CTS_INACTIVE BIT4 |
| 607 | #define SICR_CTS (BIT5+BIT4) |
| 608 | #define SICR_RCC_UNDERFLOW BIT3 |
| 609 | #define SICR_DPLL_NO_SYNC BIT2 |
| 610 | #define SICR_BRG1_ZERO BIT1 |
| 611 | #define SICR_BRG0_ZERO BIT0 |
| 612 | |
| 613 | void usc_DisableMasterIrqBit( struct mgsl_struct *info ); |
| 614 | void usc_EnableMasterIrqBit( struct mgsl_struct *info ); |
| 615 | void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask ); |
| 616 | void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask ); |
| 617 | void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask ); |
| 618 | |
| 619 | #define usc_EnableInterrupts( a, b ) \ |
| 620 | usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) ) |
| 621 | |
| 622 | #define usc_DisableInterrupts( a, b ) \ |
| 623 | usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) ) |
| 624 | |
| 625 | #define usc_EnableMasterIrqBit(a) \ |
| 626 | usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) ) |
| 627 | |
| 628 | #define usc_DisableMasterIrqBit(a) \ |
| 629 | usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) ) |
| 630 | |
| 631 | #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) ) |
| 632 | |
| 633 | /* |
| 634 | * Transmit status Bits in Transmit Control status Register (TCSR) |
| 635 | * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) |
| 636 | */ |
| 637 | |
| 638 | #define TXSTATUS_PREAMBLE_SENT BIT7 |
| 639 | #define TXSTATUS_IDLE_SENT BIT6 |
| 640 | #define TXSTATUS_ABORT_SENT BIT5 |
| 641 | #define TXSTATUS_EOF BIT4 |
| 642 | #define TXSTATUS_CRC_SENT BIT3 |
| 643 | #define TXSTATUS_ALL_SENT BIT2 |
| 644 | #define TXSTATUS_UNDERRUN BIT1 |
| 645 | #define TXSTATUS_FIFO_EMPTY BIT0 |
| 646 | |
| 647 | #define DICR_MASTER BIT15 |
| 648 | #define DICR_TRANSMIT BIT0 |
| 649 | #define DICR_RECEIVE BIT1 |
| 650 | |
| 651 | #define usc_EnableDmaInterrupts(a,b) \ |
| 652 | usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) ) |
| 653 | |
| 654 | #define usc_DisableDmaInterrupts(a,b) \ |
| 655 | usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) ) |
| 656 | |
| 657 | #define usc_EnableStatusIrqs(a,b) \ |
| 658 | usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) ) |
| 659 | |
| 660 | #define usc_DisablestatusIrqs(a,b) \ |
| 661 | usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) ) |
| 662 | |
| 663 | /* Transmit status Bits in Transmit Control status Register (TCSR) */ |
| 664 | /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */ |
| 665 | |
| 666 | |
| 667 | #define DISABLE_UNCONDITIONAL 0 |
| 668 | #define DISABLE_END_OF_FRAME 1 |
| 669 | #define ENABLE_UNCONDITIONAL 2 |
| 670 | #define ENABLE_AUTO_CTS 3 |
| 671 | #define ENABLE_AUTO_DCD 3 |
| 672 | #define usc_EnableTransmitter(a,b) \ |
| 673 | usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) ) |
| 674 | #define usc_EnableReceiver(a,b) \ |
| 675 | usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) ) |
| 676 | |
| 677 | static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port ); |
| 678 | static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value ); |
| 679 | static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd ); |
| 680 | |
| 681 | static u16 usc_InReg( struct mgsl_struct *info, u16 Port ); |
| 682 | static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value ); |
| 683 | static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd ); |
| 684 | void usc_RCmd( struct mgsl_struct *info, u16 Cmd ); |
| 685 | void usc_TCmd( struct mgsl_struct *info, u16 Cmd ); |
| 686 | |
| 687 | #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b))) |
| 688 | #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b)) |
| 689 | |
| 690 | #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1)) |
| 691 | |
| 692 | static void usc_process_rxoverrun_sync( struct mgsl_struct *info ); |
| 693 | static void usc_start_receiver( struct mgsl_struct *info ); |
| 694 | static void usc_stop_receiver( struct mgsl_struct *info ); |
| 695 | |
| 696 | static void usc_start_transmitter( struct mgsl_struct *info ); |
| 697 | static void usc_stop_transmitter( struct mgsl_struct *info ); |
| 698 | static void usc_set_txidle( struct mgsl_struct *info ); |
| 699 | static void usc_load_txfifo( struct mgsl_struct *info ); |
| 700 | |
| 701 | static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate ); |
| 702 | static void usc_enable_loopback( struct mgsl_struct *info, int enable ); |
| 703 | |
| 704 | static void usc_get_serial_signals( struct mgsl_struct *info ); |
| 705 | static void usc_set_serial_signals( struct mgsl_struct *info ); |
| 706 | |
| 707 | static void usc_reset( struct mgsl_struct *info ); |
| 708 | |
| 709 | static void usc_set_sync_mode( struct mgsl_struct *info ); |
| 710 | static void usc_set_sdlc_mode( struct mgsl_struct *info ); |
| 711 | static void usc_set_async_mode( struct mgsl_struct *info ); |
| 712 | static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate ); |
| 713 | |
| 714 | static void usc_loopback_frame( struct mgsl_struct *info ); |
| 715 | |
| 716 | static void mgsl_tx_timeout(unsigned long context); |
| 717 | |
| 718 | |
| 719 | static void usc_loopmode_cancel_transmit( struct mgsl_struct * info ); |
| 720 | static void usc_loopmode_insert_request( struct mgsl_struct * info ); |
| 721 | static int usc_loopmode_active( struct mgsl_struct * info); |
| 722 | static void usc_loopmode_send_done( struct mgsl_struct * info ); |
| 723 | |
| 724 | static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg); |
| 725 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 726 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
| 728 | static void hdlcdev_tx_done(struct mgsl_struct *info); |
| 729 | static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size); |
| 730 | static int hdlcdev_init(struct mgsl_struct *info); |
| 731 | static void hdlcdev_exit(struct mgsl_struct *info); |
| 732 | #endif |
| 733 | |
| 734 | /* |
| 735 | * Defines a BUS descriptor value for the PCI adapter |
| 736 | * local bus address ranges. |
| 737 | */ |
| 738 | |
| 739 | #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \ |
| 740 | (0x00400020 + \ |
| 741 | ((WrHold) << 30) + \ |
| 742 | ((WrDly) << 28) + \ |
| 743 | ((RdDly) << 26) + \ |
| 744 | ((Nwdd) << 20) + \ |
| 745 | ((Nwad) << 15) + \ |
| 746 | ((Nxda) << 13) + \ |
| 747 | ((Nrdd) << 11) + \ |
| 748 | ((Nrad) << 6) ) |
| 749 | |
| 750 | static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit); |
| 751 | |
| 752 | /* |
| 753 | * Adapter diagnostic routines |
| 754 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 755 | static bool mgsl_register_test( struct mgsl_struct *info ); |
| 756 | static bool mgsl_irq_test( struct mgsl_struct *info ); |
| 757 | static bool mgsl_dma_test( struct mgsl_struct *info ); |
| 758 | static bool mgsl_memory_test( struct mgsl_struct *info ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | static int mgsl_adapter_test( struct mgsl_struct *info ); |
| 760 | |
| 761 | /* |
| 762 | * device and resource management routines |
| 763 | */ |
| 764 | static int mgsl_claim_resources(struct mgsl_struct *info); |
| 765 | static void mgsl_release_resources(struct mgsl_struct *info); |
| 766 | static void mgsl_add_device(struct mgsl_struct *info); |
| 767 | static struct mgsl_struct* mgsl_allocate_device(void); |
| 768 | |
| 769 | /* |
| 770 | * DMA buffer manupulation functions. |
| 771 | */ |
| 772 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 773 | static bool mgsl_get_rx_frame( struct mgsl_struct *info ); |
| 774 | static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ); |
| 776 | static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info ); |
| 777 | static int num_free_tx_dma_buffers(struct mgsl_struct *info); |
| 778 | static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize); |
| 779 | static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count); |
| 780 | |
| 781 | /* |
| 782 | * DMA and Shared Memory buffer allocation and formatting |
| 783 | */ |
| 784 | static int mgsl_allocate_dma_buffers(struct mgsl_struct *info); |
| 785 | static void mgsl_free_dma_buffers(struct mgsl_struct *info); |
| 786 | static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount); |
| 787 | static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount); |
| 788 | static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info); |
| 789 | static void mgsl_free_buffer_list_memory(struct mgsl_struct *info); |
| 790 | static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info); |
| 791 | static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info); |
| 792 | static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info); |
| 793 | static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 794 | static bool load_next_tx_holding_buffer(struct mgsl_struct *info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize); |
| 796 | |
| 797 | /* |
| 798 | * Bottom half interrupt handlers |
| 799 | */ |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 800 | static void mgsl_bh_handler(struct work_struct *work); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | static void mgsl_bh_receive(struct mgsl_struct *info); |
| 802 | static void mgsl_bh_transmit(struct mgsl_struct *info); |
| 803 | static void mgsl_bh_status(struct mgsl_struct *info); |
| 804 | |
| 805 | /* |
| 806 | * Interrupt handler routines and dispatch table. |
| 807 | */ |
| 808 | static void mgsl_isr_null( struct mgsl_struct *info ); |
| 809 | static void mgsl_isr_transmit_data( struct mgsl_struct *info ); |
| 810 | static void mgsl_isr_receive_data( struct mgsl_struct *info ); |
| 811 | static void mgsl_isr_receive_status( struct mgsl_struct *info ); |
| 812 | static void mgsl_isr_transmit_status( struct mgsl_struct *info ); |
| 813 | static void mgsl_isr_io_pin( struct mgsl_struct *info ); |
| 814 | static void mgsl_isr_misc( struct mgsl_struct *info ); |
| 815 | static void mgsl_isr_receive_dma( struct mgsl_struct *info ); |
| 816 | static void mgsl_isr_transmit_dma( struct mgsl_struct *info ); |
| 817 | |
| 818 | typedef void (*isr_dispatch_func)(struct mgsl_struct *); |
| 819 | |
| 820 | static isr_dispatch_func UscIsrTable[7] = |
| 821 | { |
| 822 | mgsl_isr_null, |
| 823 | mgsl_isr_misc, |
| 824 | mgsl_isr_io_pin, |
| 825 | mgsl_isr_transmit_data, |
| 826 | mgsl_isr_transmit_status, |
| 827 | mgsl_isr_receive_data, |
| 828 | mgsl_isr_receive_status |
| 829 | }; |
| 830 | |
| 831 | /* |
| 832 | * ioctl call handlers |
| 833 | */ |
| 834 | static int tiocmget(struct tty_struct *tty, struct file *file); |
| 835 | static int tiocmset(struct tty_struct *tty, struct file *file, |
| 836 | unsigned int set, unsigned int clear); |
| 837 | static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount |
| 838 | __user *user_icount); |
| 839 | static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params); |
| 840 | static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params); |
| 841 | static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode); |
| 842 | static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode); |
| 843 | static int mgsl_txenable(struct mgsl_struct * info, int enable); |
| 844 | static int mgsl_txabort(struct mgsl_struct * info); |
| 845 | static int mgsl_rxenable(struct mgsl_struct * info, int enable); |
| 846 | static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask); |
| 847 | static int mgsl_loopmode_send_done( struct mgsl_struct * info ); |
| 848 | |
| 849 | /* set non-zero on successful registration with PCI subsystem */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 850 | static bool pci_registered; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | |
| 852 | /* |
| 853 | * Global linked list of SyncLink devices |
| 854 | */ |
| 855 | static struct mgsl_struct *mgsl_device_list; |
| 856 | static int mgsl_device_count; |
| 857 | |
| 858 | /* |
| 859 | * Set this param to non-zero to load eax with the |
| 860 | * .text section address and breakpoint on module load. |
| 861 | * This is useful for use with gdb and add-symbol-file command. |
| 862 | */ |
| 863 | static int break_on_load; |
| 864 | |
| 865 | /* |
| 866 | * Driver major number, defaults to zero to get auto |
| 867 | * assigned major number. May be forced as module parameter. |
| 868 | */ |
| 869 | static int ttymajor; |
| 870 | |
| 871 | /* |
| 872 | * Array of user specified options for ISA adapters. |
| 873 | */ |
| 874 | static int io[MAX_ISA_DEVICES]; |
| 875 | static int irq[MAX_ISA_DEVICES]; |
| 876 | static int dma[MAX_ISA_DEVICES]; |
| 877 | static int debug_level; |
| 878 | static int maxframe[MAX_TOTAL_DEVICES]; |
| 879 | static int dosyncppp[MAX_TOTAL_DEVICES]; |
| 880 | static int txdmabufs[MAX_TOTAL_DEVICES]; |
| 881 | static int txholdbufs[MAX_TOTAL_DEVICES]; |
| 882 | |
| 883 | module_param(break_on_load, bool, 0); |
| 884 | module_param(ttymajor, int, 0); |
| 885 | module_param_array(io, int, NULL, 0); |
| 886 | module_param_array(irq, int, NULL, 0); |
| 887 | module_param_array(dma, int, NULL, 0); |
| 888 | module_param(debug_level, int, 0); |
| 889 | module_param_array(maxframe, int, NULL, 0); |
| 890 | module_param_array(dosyncppp, int, NULL, 0); |
| 891 | module_param_array(txdmabufs, int, NULL, 0); |
| 892 | module_param_array(txholdbufs, int, NULL, 0); |
| 893 | |
| 894 | static char *driver_name = "SyncLink serial driver"; |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 895 | static char *driver_version = "$Revision: 4.38 $"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | |
| 897 | static int synclink_init_one (struct pci_dev *dev, |
| 898 | const struct pci_device_id *ent); |
| 899 | static void synclink_remove_one (struct pci_dev *dev); |
| 900 | |
| 901 | static struct pci_device_id synclink_pci_tbl[] = { |
| 902 | { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, }, |
| 903 | { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, }, |
| 904 | { 0, }, /* terminate list */ |
| 905 | }; |
| 906 | MODULE_DEVICE_TABLE(pci, synclink_pci_tbl); |
| 907 | |
| 908 | MODULE_LICENSE("GPL"); |
| 909 | |
| 910 | static struct pci_driver synclink_pci_driver = { |
| 911 | .name = "synclink", |
| 912 | .id_table = synclink_pci_tbl, |
| 913 | .probe = synclink_init_one, |
| 914 | .remove = __devexit_p(synclink_remove_one), |
| 915 | }; |
| 916 | |
| 917 | static struct tty_driver *serial_driver; |
| 918 | |
| 919 | /* number of characters left in xmit buffer before we ask for more */ |
| 920 | #define WAKEUP_CHARS 256 |
| 921 | |
| 922 | |
| 923 | static void mgsl_change_params(struct mgsl_struct *info); |
| 924 | static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout); |
| 925 | |
| 926 | /* |
| 927 | * 1st function defined in .text section. Calling this function in |
| 928 | * init_module() followed by a breakpoint allows a remote debugger |
| 929 | * (gdb) to get the .text address for the add-symbol-file command. |
| 930 | * This allows remote debugging of dynamically loadable modules. |
| 931 | */ |
| 932 | static void* mgsl_get_text_ptr(void) |
| 933 | { |
| 934 | return mgsl_get_text_ptr; |
| 935 | } |
| 936 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | static inline int mgsl_paranoia_check(struct mgsl_struct *info, |
| 938 | char *name, const char *routine) |
| 939 | { |
| 940 | #ifdef MGSL_PARANOIA_CHECK |
| 941 | static const char *badmagic = |
| 942 | "Warning: bad magic number for mgsl struct (%s) in %s\n"; |
| 943 | static const char *badinfo = |
| 944 | "Warning: null mgsl_struct for (%s) in %s\n"; |
| 945 | |
| 946 | if (!info) { |
| 947 | printk(badinfo, name, routine); |
| 948 | return 1; |
| 949 | } |
| 950 | if (info->magic != MGSL_MAGIC) { |
| 951 | printk(badmagic, name, routine); |
| 952 | return 1; |
| 953 | } |
| 954 | #else |
| 955 | if (!info) |
| 956 | return 1; |
| 957 | #endif |
| 958 | return 0; |
| 959 | } |
| 960 | |
| 961 | /** |
| 962 | * line discipline callback wrappers |
| 963 | * |
| 964 | * The wrappers maintain line discipline references |
| 965 | * while calling into the line discipline. |
| 966 | * |
| 967 | * ldisc_receive_buf - pass receive data to line discipline |
| 968 | */ |
| 969 | |
| 970 | static void ldisc_receive_buf(struct tty_struct *tty, |
| 971 | const __u8 *data, char *flags, int count) |
| 972 | { |
| 973 | struct tty_ldisc *ld; |
| 974 | if (!tty) |
| 975 | return; |
| 976 | ld = tty_ldisc_ref(tty); |
| 977 | if (ld) { |
| 978 | if (ld->receive_buf) |
| 979 | ld->receive_buf(tty, data, flags, count); |
| 980 | tty_ldisc_deref(ld); |
| 981 | } |
| 982 | } |
| 983 | |
| 984 | /* mgsl_stop() throttle (stop) transmitter |
| 985 | * |
| 986 | * Arguments: tty pointer to tty info structure |
| 987 | * Return Value: None |
| 988 | */ |
| 989 | static void mgsl_stop(struct tty_struct *tty) |
| 990 | { |
| 991 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 992 | unsigned long flags; |
| 993 | |
| 994 | if (mgsl_paranoia_check(info, tty->name, "mgsl_stop")) |
| 995 | return; |
| 996 | |
| 997 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 998 | printk("mgsl_stop(%s)\n",info->device_name); |
| 999 | |
| 1000 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1001 | if (info->tx_enabled) |
| 1002 | usc_stop_transmitter(info); |
| 1003 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1004 | |
| 1005 | } /* end of mgsl_stop() */ |
| 1006 | |
| 1007 | /* mgsl_start() release (start) transmitter |
| 1008 | * |
| 1009 | * Arguments: tty pointer to tty info structure |
| 1010 | * Return Value: None |
| 1011 | */ |
| 1012 | static void mgsl_start(struct tty_struct *tty) |
| 1013 | { |
| 1014 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 1015 | unsigned long flags; |
| 1016 | |
| 1017 | if (mgsl_paranoia_check(info, tty->name, "mgsl_start")) |
| 1018 | return; |
| 1019 | |
| 1020 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 1021 | printk("mgsl_start(%s)\n",info->device_name); |
| 1022 | |
| 1023 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1024 | if (!info->tx_enabled) |
| 1025 | usc_start_transmitter(info); |
| 1026 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1027 | |
| 1028 | } /* end of mgsl_start() */ |
| 1029 | |
| 1030 | /* |
| 1031 | * Bottom half work queue access functions |
| 1032 | */ |
| 1033 | |
| 1034 | /* mgsl_bh_action() Return next bottom half action to perform. |
| 1035 | * Return Value: BH action code or 0 if nothing to do. |
| 1036 | */ |
| 1037 | static int mgsl_bh_action(struct mgsl_struct *info) |
| 1038 | { |
| 1039 | unsigned long flags; |
| 1040 | int rc = 0; |
| 1041 | |
| 1042 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1043 | |
| 1044 | if (info->pending_bh & BH_RECEIVE) { |
| 1045 | info->pending_bh &= ~BH_RECEIVE; |
| 1046 | rc = BH_RECEIVE; |
| 1047 | } else if (info->pending_bh & BH_TRANSMIT) { |
| 1048 | info->pending_bh &= ~BH_TRANSMIT; |
| 1049 | rc = BH_TRANSMIT; |
| 1050 | } else if (info->pending_bh & BH_STATUS) { |
| 1051 | info->pending_bh &= ~BH_STATUS; |
| 1052 | rc = BH_STATUS; |
| 1053 | } |
| 1054 | |
| 1055 | if (!rc) { |
| 1056 | /* Mark BH routine as complete */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1057 | info->bh_running = false; |
| 1058 | info->bh_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | } |
| 1060 | |
| 1061 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1062 | |
| 1063 | return rc; |
| 1064 | } |
| 1065 | |
| 1066 | /* |
| 1067 | * Perform bottom half processing of work items queued by ISR. |
| 1068 | */ |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 1069 | static void mgsl_bh_handler(struct work_struct *work) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | { |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 1071 | struct mgsl_struct *info = |
| 1072 | container_of(work, struct mgsl_struct, task); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1073 | int action; |
| 1074 | |
| 1075 | if (!info) |
| 1076 | return; |
| 1077 | |
| 1078 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 1079 | printk( "%s(%d):mgsl_bh_handler(%s) entry\n", |
| 1080 | __FILE__,__LINE__,info->device_name); |
| 1081 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1082 | info->bh_running = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | |
| 1084 | while((action = mgsl_bh_action(info)) != 0) { |
| 1085 | |
| 1086 | /* Process work item */ |
| 1087 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 1088 | printk( "%s(%d):mgsl_bh_handler() work item action=%d\n", |
| 1089 | __FILE__,__LINE__,action); |
| 1090 | |
| 1091 | switch (action) { |
| 1092 | |
| 1093 | case BH_RECEIVE: |
| 1094 | mgsl_bh_receive(info); |
| 1095 | break; |
| 1096 | case BH_TRANSMIT: |
| 1097 | mgsl_bh_transmit(info); |
| 1098 | break; |
| 1099 | case BH_STATUS: |
| 1100 | mgsl_bh_status(info); |
| 1101 | break; |
| 1102 | default: |
| 1103 | /* unknown work item ID */ |
| 1104 | printk("Unknown work item ID=%08X!\n", action); |
| 1105 | break; |
| 1106 | } |
| 1107 | } |
| 1108 | |
| 1109 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 1110 | printk( "%s(%d):mgsl_bh_handler(%s) exit\n", |
| 1111 | __FILE__,__LINE__,info->device_name); |
| 1112 | } |
| 1113 | |
| 1114 | static void mgsl_bh_receive(struct mgsl_struct *info) |
| 1115 | { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1116 | bool (*get_rx_frame)(struct mgsl_struct *info) = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame); |
| 1118 | |
| 1119 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 1120 | printk( "%s(%d):mgsl_bh_receive(%s)\n", |
| 1121 | __FILE__,__LINE__,info->device_name); |
| 1122 | |
| 1123 | do |
| 1124 | { |
| 1125 | if (info->rx_rcc_underrun) { |
| 1126 | unsigned long flags; |
| 1127 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1128 | usc_start_receiver(info); |
| 1129 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1130 | return; |
| 1131 | } |
| 1132 | } while(get_rx_frame(info)); |
| 1133 | } |
| 1134 | |
| 1135 | static void mgsl_bh_transmit(struct mgsl_struct *info) |
| 1136 | { |
| 1137 | struct tty_struct *tty = info->tty; |
| 1138 | unsigned long flags; |
| 1139 | |
| 1140 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 1141 | printk( "%s(%d):mgsl_bh_transmit() entry on %s\n", |
| 1142 | __FILE__,__LINE__,info->device_name); |
| 1143 | |
Jiri Slaby | b963a84 | 2007-02-10 01:44:55 -0800 | [diff] [blame] | 1144 | if (tty) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | tty_wakeup(tty); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | |
| 1147 | /* if transmitter idle and loopmode_send_done_requested |
| 1148 | * then start echoing RxD to TxD |
| 1149 | */ |
| 1150 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1151 | if ( !info->tx_active && info->loopmode_send_done_requested ) |
| 1152 | usc_loopmode_send_done( info ); |
| 1153 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1154 | } |
| 1155 | |
| 1156 | static void mgsl_bh_status(struct mgsl_struct *info) |
| 1157 | { |
| 1158 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 1159 | printk( "%s(%d):mgsl_bh_status() entry on %s\n", |
| 1160 | __FILE__,__LINE__,info->device_name); |
| 1161 | |
| 1162 | info->ri_chkcount = 0; |
| 1163 | info->dsr_chkcount = 0; |
| 1164 | info->dcd_chkcount = 0; |
| 1165 | info->cts_chkcount = 0; |
| 1166 | } |
| 1167 | |
| 1168 | /* mgsl_isr_receive_status() |
| 1169 | * |
| 1170 | * Service a receive status interrupt. The type of status |
| 1171 | * interrupt is indicated by the state of the RCSR. |
| 1172 | * This is only used for HDLC mode. |
| 1173 | * |
| 1174 | * Arguments: info pointer to device instance data |
| 1175 | * Return Value: None |
| 1176 | */ |
| 1177 | static void mgsl_isr_receive_status( struct mgsl_struct *info ) |
| 1178 | { |
| 1179 | u16 status = usc_InReg( info, RCSR ); |
| 1180 | |
| 1181 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1182 | printk("%s(%d):mgsl_isr_receive_status status=%04X\n", |
| 1183 | __FILE__,__LINE__,status); |
| 1184 | |
| 1185 | if ( (status & RXSTATUS_ABORT_RECEIVED) && |
| 1186 | info->loopmode_insert_requested && |
| 1187 | usc_loopmode_active(info) ) |
| 1188 | { |
| 1189 | ++info->icount.rxabort; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1190 | info->loopmode_insert_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1191 | |
| 1192 | /* clear CMR:13 to start echoing RxD to TxD */ |
| 1193 | info->cmr_value &= ~BIT13; |
| 1194 | usc_OutReg(info, CMR, info->cmr_value); |
| 1195 | |
| 1196 | /* disable received abort irq (no longer required) */ |
| 1197 | usc_OutReg(info, RICR, |
| 1198 | (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED)); |
| 1199 | } |
| 1200 | |
| 1201 | if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) { |
| 1202 | if (status & RXSTATUS_EXITED_HUNT) |
| 1203 | info->icount.exithunt++; |
| 1204 | if (status & RXSTATUS_IDLE_RECEIVED) |
| 1205 | info->icount.rxidle++; |
| 1206 | wake_up_interruptible(&info->event_wait_q); |
| 1207 | } |
| 1208 | |
| 1209 | if (status & RXSTATUS_OVERRUN){ |
| 1210 | info->icount.rxover++; |
| 1211 | usc_process_rxoverrun_sync( info ); |
| 1212 | } |
| 1213 | |
| 1214 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); |
| 1215 | usc_UnlatchRxstatusBits( info, status ); |
| 1216 | |
| 1217 | } /* end of mgsl_isr_receive_status() */ |
| 1218 | |
| 1219 | /* mgsl_isr_transmit_status() |
| 1220 | * |
| 1221 | * Service a transmit status interrupt |
| 1222 | * HDLC mode :end of transmit frame |
| 1223 | * Async mode:all data is sent |
| 1224 | * transmit status is indicated by bits in the TCSR. |
| 1225 | * |
| 1226 | * Arguments: info pointer to device instance data |
| 1227 | * Return Value: None |
| 1228 | */ |
| 1229 | static void mgsl_isr_transmit_status( struct mgsl_struct *info ) |
| 1230 | { |
| 1231 | u16 status = usc_InReg( info, TCSR ); |
| 1232 | |
| 1233 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1234 | printk("%s(%d):mgsl_isr_transmit_status status=%04X\n", |
| 1235 | __FILE__,__LINE__,status); |
| 1236 | |
| 1237 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); |
| 1238 | usc_UnlatchTxstatusBits( info, status ); |
| 1239 | |
| 1240 | if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) ) |
| 1241 | { |
| 1242 | /* finished sending HDLC abort. This may leave */ |
| 1243 | /* the TxFifo with data from the aborted frame */ |
| 1244 | /* so purge the TxFifo. Also shutdown the DMA */ |
| 1245 | /* channel in case there is data remaining in */ |
| 1246 | /* the DMA buffer */ |
| 1247 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); |
| 1248 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
| 1249 | } |
| 1250 | |
| 1251 | if ( status & TXSTATUS_EOF_SENT ) |
| 1252 | info->icount.txok++; |
| 1253 | else if ( status & TXSTATUS_UNDERRUN ) |
| 1254 | info->icount.txunder++; |
| 1255 | else if ( status & TXSTATUS_ABORT_SENT ) |
| 1256 | info->icount.txabort++; |
| 1257 | else |
| 1258 | info->icount.txunder++; |
| 1259 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1260 | info->tx_active = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
| 1262 | del_timer(&info->tx_timer); |
| 1263 | |
| 1264 | if ( info->drop_rts_on_tx_done ) { |
| 1265 | usc_get_serial_signals( info ); |
| 1266 | if ( info->serial_signals & SerialSignal_RTS ) { |
| 1267 | info->serial_signals &= ~SerialSignal_RTS; |
| 1268 | usc_set_serial_signals( info ); |
| 1269 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1270 | info->drop_rts_on_tx_done = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | } |
| 1272 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 1273 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | if (info->netcount) |
| 1275 | hdlcdev_tx_done(info); |
| 1276 | else |
| 1277 | #endif |
| 1278 | { |
| 1279 | if (info->tty->stopped || info->tty->hw_stopped) { |
| 1280 | usc_stop_transmitter(info); |
| 1281 | return; |
| 1282 | } |
| 1283 | info->pending_bh |= BH_TRANSMIT; |
| 1284 | } |
| 1285 | |
| 1286 | } /* end of mgsl_isr_transmit_status() */ |
| 1287 | |
| 1288 | /* mgsl_isr_io_pin() |
| 1289 | * |
| 1290 | * Service an Input/Output pin interrupt. The type of |
| 1291 | * interrupt is indicated by bits in the MISR |
| 1292 | * |
| 1293 | * Arguments: info pointer to device instance data |
| 1294 | * Return Value: None |
| 1295 | */ |
| 1296 | static void mgsl_isr_io_pin( struct mgsl_struct *info ) |
| 1297 | { |
| 1298 | struct mgsl_icount *icount; |
| 1299 | u16 status = usc_InReg( info, MISR ); |
| 1300 | |
| 1301 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1302 | printk("%s(%d):mgsl_isr_io_pin status=%04X\n", |
| 1303 | __FILE__,__LINE__,status); |
| 1304 | |
| 1305 | usc_ClearIrqPendingBits( info, IO_PIN ); |
| 1306 | usc_UnlatchIostatusBits( info, status ); |
| 1307 | |
| 1308 | if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | |
| 1309 | MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { |
| 1310 | icount = &info->icount; |
| 1311 | /* update input line counters */ |
| 1312 | if (status & MISCSTATUS_RI_LATCHED) { |
| 1313 | if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) |
| 1314 | usc_DisablestatusIrqs(info,SICR_RI); |
| 1315 | icount->rng++; |
| 1316 | if ( status & MISCSTATUS_RI ) |
| 1317 | info->input_signal_events.ri_up++; |
| 1318 | else |
| 1319 | info->input_signal_events.ri_down++; |
| 1320 | } |
| 1321 | if (status & MISCSTATUS_DSR_LATCHED) { |
| 1322 | if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) |
| 1323 | usc_DisablestatusIrqs(info,SICR_DSR); |
| 1324 | icount->dsr++; |
| 1325 | if ( status & MISCSTATUS_DSR ) |
| 1326 | info->input_signal_events.dsr_up++; |
| 1327 | else |
| 1328 | info->input_signal_events.dsr_down++; |
| 1329 | } |
| 1330 | if (status & MISCSTATUS_DCD_LATCHED) { |
| 1331 | if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) |
| 1332 | usc_DisablestatusIrqs(info,SICR_DCD); |
| 1333 | icount->dcd++; |
| 1334 | if (status & MISCSTATUS_DCD) { |
| 1335 | info->input_signal_events.dcd_up++; |
| 1336 | } else |
| 1337 | info->input_signal_events.dcd_down++; |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 1338 | #if SYNCLINK_GENERIC_HDLC |
Krzysztof Halasa | fbeff3c | 2006-07-21 14:44:55 -0700 | [diff] [blame] | 1339 | if (info->netcount) { |
| 1340 | if (status & MISCSTATUS_DCD) |
| 1341 | netif_carrier_on(info->netdev); |
| 1342 | else |
| 1343 | netif_carrier_off(info->netdev); |
| 1344 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1345 | #endif |
| 1346 | } |
| 1347 | if (status & MISCSTATUS_CTS_LATCHED) |
| 1348 | { |
| 1349 | if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) |
| 1350 | usc_DisablestatusIrqs(info,SICR_CTS); |
| 1351 | icount->cts++; |
| 1352 | if ( status & MISCSTATUS_CTS ) |
| 1353 | info->input_signal_events.cts_up++; |
| 1354 | else |
| 1355 | info->input_signal_events.cts_down++; |
| 1356 | } |
| 1357 | wake_up_interruptible(&info->status_event_wait_q); |
| 1358 | wake_up_interruptible(&info->event_wait_q); |
| 1359 | |
| 1360 | if ( (info->flags & ASYNC_CHECK_CD) && |
| 1361 | (status & MISCSTATUS_DCD_LATCHED) ) { |
| 1362 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1363 | printk("%s CD now %s...", info->device_name, |
| 1364 | (status & MISCSTATUS_DCD) ? "on" : "off"); |
| 1365 | if (status & MISCSTATUS_DCD) |
| 1366 | wake_up_interruptible(&info->open_wait); |
| 1367 | else { |
| 1368 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1369 | printk("doing serial hangup..."); |
| 1370 | if (info->tty) |
| 1371 | tty_hangup(info->tty); |
| 1372 | } |
| 1373 | } |
| 1374 | |
| 1375 | if ( (info->flags & ASYNC_CTS_FLOW) && |
| 1376 | (status & MISCSTATUS_CTS_LATCHED) ) { |
| 1377 | if (info->tty->hw_stopped) { |
| 1378 | if (status & MISCSTATUS_CTS) { |
| 1379 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1380 | printk("CTS tx start..."); |
| 1381 | if (info->tty) |
| 1382 | info->tty->hw_stopped = 0; |
| 1383 | usc_start_transmitter(info); |
| 1384 | info->pending_bh |= BH_TRANSMIT; |
| 1385 | return; |
| 1386 | } |
| 1387 | } else { |
| 1388 | if (!(status & MISCSTATUS_CTS)) { |
| 1389 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1390 | printk("CTS tx stop..."); |
| 1391 | if (info->tty) |
| 1392 | info->tty->hw_stopped = 1; |
| 1393 | usc_stop_transmitter(info); |
| 1394 | } |
| 1395 | } |
| 1396 | } |
| 1397 | } |
| 1398 | |
| 1399 | info->pending_bh |= BH_STATUS; |
| 1400 | |
| 1401 | /* for diagnostics set IRQ flag */ |
| 1402 | if ( status & MISCSTATUS_TXC_LATCHED ){ |
| 1403 | usc_OutReg( info, SICR, |
| 1404 | (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) ); |
| 1405 | usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED ); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1406 | info->irq_occurred = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1407 | } |
| 1408 | |
| 1409 | } /* end of mgsl_isr_io_pin() */ |
| 1410 | |
| 1411 | /* mgsl_isr_transmit_data() |
| 1412 | * |
| 1413 | * Service a transmit data interrupt (async mode only). |
| 1414 | * |
| 1415 | * Arguments: info pointer to device instance data |
| 1416 | * Return Value: None |
| 1417 | */ |
| 1418 | static void mgsl_isr_transmit_data( struct mgsl_struct *info ) |
| 1419 | { |
| 1420 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1421 | printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n", |
| 1422 | __FILE__,__LINE__,info->xmit_cnt); |
| 1423 | |
| 1424 | usc_ClearIrqPendingBits( info, TRANSMIT_DATA ); |
| 1425 | |
| 1426 | if (info->tty->stopped || info->tty->hw_stopped) { |
| 1427 | usc_stop_transmitter(info); |
| 1428 | return; |
| 1429 | } |
| 1430 | |
| 1431 | if ( info->xmit_cnt ) |
| 1432 | usc_load_txfifo( info ); |
| 1433 | else |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1434 | info->tx_active = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1435 | |
| 1436 | if (info->xmit_cnt < WAKEUP_CHARS) |
| 1437 | info->pending_bh |= BH_TRANSMIT; |
| 1438 | |
| 1439 | } /* end of mgsl_isr_transmit_data() */ |
| 1440 | |
| 1441 | /* mgsl_isr_receive_data() |
| 1442 | * |
| 1443 | * Service a receive data interrupt. This occurs |
| 1444 | * when operating in asynchronous interrupt transfer mode. |
| 1445 | * The receive data FIFO is flushed to the receive data buffers. |
| 1446 | * |
| 1447 | * Arguments: info pointer to device instance data |
| 1448 | * Return Value: None |
| 1449 | */ |
| 1450 | static void mgsl_isr_receive_data( struct mgsl_struct *info ) |
| 1451 | { |
| 1452 | int Fifocount; |
| 1453 | u16 status; |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1454 | int work = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1455 | unsigned char DataByte; |
| 1456 | struct tty_struct *tty = info->tty; |
| 1457 | struct mgsl_icount *icount = &info->icount; |
| 1458 | |
| 1459 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1460 | printk("%s(%d):mgsl_isr_receive_data\n", |
| 1461 | __FILE__,__LINE__); |
| 1462 | |
| 1463 | usc_ClearIrqPendingBits( info, RECEIVE_DATA ); |
| 1464 | |
| 1465 | /* select FIFO status for RICR readback */ |
| 1466 | usc_RCmd( info, RCmd_SelectRicrRxFifostatus ); |
| 1467 | |
| 1468 | /* clear the Wordstatus bit so that status readback */ |
| 1469 | /* only reflects the status of this byte */ |
| 1470 | usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); |
| 1471 | |
| 1472 | /* flush the receive FIFO */ |
| 1473 | |
| 1474 | while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) { |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1475 | int flag; |
| 1476 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | /* read one byte from RxFIFO */ |
| 1478 | outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY), |
| 1479 | info->io_base + CCAR ); |
| 1480 | DataByte = inb( info->io_base + CCAR ); |
| 1481 | |
| 1482 | /* get the status of the received byte */ |
| 1483 | status = usc_InReg(info, RCSR); |
| 1484 | if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR + |
| 1485 | RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) |
| 1486 | usc_UnlatchRxstatusBits(info,RXSTATUS_ALL); |
| 1487 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1488 | icount->rx++; |
| 1489 | |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1490 | flag = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1491 | if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR + |
| 1492 | RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) { |
| 1493 | printk("rxerr=%04X\n",status); |
| 1494 | /* update error statistics */ |
| 1495 | if ( status & RXSTATUS_BREAK_RECEIVED ) { |
| 1496 | status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR); |
| 1497 | icount->brk++; |
| 1498 | } else if (status & RXSTATUS_PARITY_ERROR) |
| 1499 | icount->parity++; |
| 1500 | else if (status & RXSTATUS_FRAMING_ERROR) |
| 1501 | icount->frame++; |
| 1502 | else if (status & RXSTATUS_OVERRUN) { |
| 1503 | /* must issue purge fifo cmd before */ |
| 1504 | /* 16C32 accepts more receive chars */ |
| 1505 | usc_RTCmd(info,RTCmd_PurgeRxFifo); |
| 1506 | icount->overrun++; |
| 1507 | } |
| 1508 | |
| 1509 | /* discard char if tty control flags say so */ |
| 1510 | if (status & info->ignore_status_mask) |
| 1511 | continue; |
| 1512 | |
| 1513 | status &= info->read_status_mask; |
| 1514 | |
| 1515 | if (status & RXSTATUS_BREAK_RECEIVED) { |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1516 | flag = TTY_BREAK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1517 | if (info->flags & ASYNC_SAK) |
| 1518 | do_SAK(tty); |
| 1519 | } else if (status & RXSTATUS_PARITY_ERROR) |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1520 | flag = TTY_PARITY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1521 | else if (status & RXSTATUS_FRAMING_ERROR) |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1522 | flag = TTY_FRAME; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1523 | } /* end of if (error) */ |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1524 | tty_insert_flip_char(tty, DataByte, flag); |
| 1525 | if (status & RXSTATUS_OVERRUN) { |
| 1526 | /* Overrun is special, since it's |
| 1527 | * reported immediately, and doesn't |
| 1528 | * affect the current character |
| 1529 | */ |
| 1530 | work += tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
| 1531 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1532 | } |
| 1533 | |
| 1534 | if ( debug_level >= DEBUG_LEVEL_ISR ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1535 | printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n", |
| 1536 | __FILE__,__LINE__,icount->rx,icount->brk, |
| 1537 | icount->parity,icount->frame,icount->overrun); |
| 1538 | } |
| 1539 | |
Alan Cox | 33f0f88 | 2006-01-09 20:54:13 -0800 | [diff] [blame] | 1540 | if(work) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1541 | tty_flip_buffer_push(tty); |
| 1542 | } |
| 1543 | |
| 1544 | /* mgsl_isr_misc() |
| 1545 | * |
Joe Perches | 8dfba4d | 2008-02-03 17:11:42 +0200 | [diff] [blame] | 1546 | * Service a miscellaneous interrupt source. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1547 | * |
| 1548 | * Arguments: info pointer to device extension (instance data) |
| 1549 | * Return Value: None |
| 1550 | */ |
| 1551 | static void mgsl_isr_misc( struct mgsl_struct *info ) |
| 1552 | { |
| 1553 | u16 status = usc_InReg( info, MISR ); |
| 1554 | |
| 1555 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1556 | printk("%s(%d):mgsl_isr_misc status=%04X\n", |
| 1557 | __FILE__,__LINE__,status); |
| 1558 | |
| 1559 | if ((status & MISCSTATUS_RCC_UNDERRUN) && |
| 1560 | (info->params.mode == MGSL_MODE_HDLC)) { |
| 1561 | |
| 1562 | /* turn off receiver and rx DMA */ |
| 1563 | usc_EnableReceiver(info,DISABLE_UNCONDITIONAL); |
| 1564 | usc_DmaCmd(info, DmaCmd_ResetRxChannel); |
| 1565 | usc_UnlatchRxstatusBits(info, RXSTATUS_ALL); |
| 1566 | usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS); |
| 1567 | usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS); |
| 1568 | |
| 1569 | /* schedule BH handler to restart receiver */ |
| 1570 | info->pending_bh |= BH_RECEIVE; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1571 | info->rx_rcc_underrun = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1572 | } |
| 1573 | |
| 1574 | usc_ClearIrqPendingBits( info, MISC ); |
| 1575 | usc_UnlatchMiscstatusBits( info, status ); |
| 1576 | |
| 1577 | } /* end of mgsl_isr_misc() */ |
| 1578 | |
| 1579 | /* mgsl_isr_null() |
| 1580 | * |
| 1581 | * Services undefined interrupt vectors from the |
| 1582 | * USC. (hence this function SHOULD never be called) |
| 1583 | * |
| 1584 | * Arguments: info pointer to device extension (instance data) |
| 1585 | * Return Value: None |
| 1586 | */ |
| 1587 | static void mgsl_isr_null( struct mgsl_struct *info ) |
| 1588 | { |
| 1589 | |
| 1590 | } /* end of mgsl_isr_null() */ |
| 1591 | |
| 1592 | /* mgsl_isr_receive_dma() |
| 1593 | * |
| 1594 | * Service a receive DMA channel interrupt. |
| 1595 | * For this driver there are two sources of receive DMA interrupts |
| 1596 | * as identified in the Receive DMA mode Register (RDMR): |
| 1597 | * |
| 1598 | * BIT3 EOA/EOL End of List, all receive buffers in receive |
| 1599 | * buffer list have been filled (no more free buffers |
| 1600 | * available). The DMA controller has shut down. |
| 1601 | * |
| 1602 | * BIT2 EOB End of Buffer. This interrupt occurs when a receive |
| 1603 | * DMA buffer is terminated in response to completion |
| 1604 | * of a good frame or a frame with errors. The status |
| 1605 | * of the frame is stored in the buffer entry in the |
| 1606 | * list of receive buffer entries. |
| 1607 | * |
| 1608 | * Arguments: info pointer to device instance data |
| 1609 | * Return Value: None |
| 1610 | */ |
| 1611 | static void mgsl_isr_receive_dma( struct mgsl_struct *info ) |
| 1612 | { |
| 1613 | u16 status; |
| 1614 | |
| 1615 | /* clear interrupt pending and IUS bit for Rx DMA IRQ */ |
| 1616 | usc_OutDmaReg( info, CDIR, BIT9+BIT1 ); |
| 1617 | |
| 1618 | /* Read the receive DMA status to identify interrupt type. */ |
| 1619 | /* This also clears the status bits. */ |
| 1620 | status = usc_InDmaReg( info, RDMR ); |
| 1621 | |
| 1622 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1623 | printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n", |
| 1624 | __FILE__,__LINE__,info->device_name,status); |
| 1625 | |
| 1626 | info->pending_bh |= BH_RECEIVE; |
| 1627 | |
| 1628 | if ( status & BIT3 ) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1629 | info->rx_overflow = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1630 | info->icount.buf_overrun++; |
| 1631 | } |
| 1632 | |
| 1633 | } /* end of mgsl_isr_receive_dma() */ |
| 1634 | |
| 1635 | /* mgsl_isr_transmit_dma() |
| 1636 | * |
| 1637 | * This function services a transmit DMA channel interrupt. |
| 1638 | * |
| 1639 | * For this driver there is one source of transmit DMA interrupts |
| 1640 | * as identified in the Transmit DMA Mode Register (TDMR): |
| 1641 | * |
| 1642 | * BIT2 EOB End of Buffer. This interrupt occurs when a |
| 1643 | * transmit DMA buffer has been emptied. |
| 1644 | * |
| 1645 | * The driver maintains enough transmit DMA buffers to hold at least |
| 1646 | * one max frame size transmit frame. When operating in a buffered |
| 1647 | * transmit mode, there may be enough transmit DMA buffers to hold at |
| 1648 | * least two or more max frame size frames. On an EOB condition, |
| 1649 | * determine if there are any queued transmit buffers and copy into |
| 1650 | * transmit DMA buffers if we have room. |
| 1651 | * |
| 1652 | * Arguments: info pointer to device instance data |
| 1653 | * Return Value: None |
| 1654 | */ |
| 1655 | static void mgsl_isr_transmit_dma( struct mgsl_struct *info ) |
| 1656 | { |
| 1657 | u16 status; |
| 1658 | |
| 1659 | /* clear interrupt pending and IUS bit for Tx DMA IRQ */ |
| 1660 | usc_OutDmaReg(info, CDIR, BIT8+BIT0 ); |
| 1661 | |
| 1662 | /* Read the transmit DMA status to identify interrupt type. */ |
| 1663 | /* This also clears the status bits. */ |
| 1664 | |
| 1665 | status = usc_InDmaReg( info, TDMR ); |
| 1666 | |
| 1667 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1668 | printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n", |
| 1669 | __FILE__,__LINE__,info->device_name,status); |
| 1670 | |
| 1671 | if ( status & BIT2 ) { |
| 1672 | --info->tx_dma_buffers_used; |
| 1673 | |
| 1674 | /* if there are transmit frames queued, |
| 1675 | * try to load the next one |
| 1676 | */ |
| 1677 | if ( load_next_tx_holding_buffer(info) ) { |
| 1678 | /* if call returns non-zero value, we have |
| 1679 | * at least one free tx holding buffer |
| 1680 | */ |
| 1681 | info->pending_bh |= BH_TRANSMIT; |
| 1682 | } |
| 1683 | } |
| 1684 | |
| 1685 | } /* end of mgsl_isr_transmit_dma() */ |
| 1686 | |
| 1687 | /* mgsl_interrupt() |
| 1688 | * |
| 1689 | * Interrupt service routine entry point. |
| 1690 | * |
| 1691 | * Arguments: |
| 1692 | * |
| 1693 | * irq interrupt number that caused interrupt |
| 1694 | * dev_id device ID supplied during interrupt registration |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | * |
| 1696 | * Return Value: None |
| 1697 | */ |
Jeff Garzik | a6f97b2 | 2007-10-31 05:20:49 -0400 | [diff] [blame] | 1698 | static irqreturn_t mgsl_interrupt(int dummy, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | { |
Jeff Garzik | a6f97b2 | 2007-10-31 05:20:49 -0400 | [diff] [blame] | 1700 | struct mgsl_struct *info = dev_id; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1701 | u16 UscVector; |
| 1702 | u16 DmaVector; |
| 1703 | |
| 1704 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
Jeff Garzik | a6f97b2 | 2007-10-31 05:20:49 -0400 | [diff] [blame] | 1705 | printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n", |
| 1706 | __FILE__, __LINE__, info->irq_level); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1707 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1708 | spin_lock(&info->irq_spinlock); |
| 1709 | |
| 1710 | for(;;) { |
| 1711 | /* Read the interrupt vectors from hardware. */ |
| 1712 | UscVector = usc_InReg(info, IVR) >> 9; |
| 1713 | DmaVector = usc_InDmaReg(info, DIVR); |
| 1714 | |
| 1715 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1716 | printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n", |
| 1717 | __FILE__,__LINE__,info->device_name,UscVector,DmaVector); |
| 1718 | |
| 1719 | if ( !UscVector && !DmaVector ) |
| 1720 | break; |
| 1721 | |
| 1722 | /* Dispatch interrupt vector */ |
| 1723 | if ( UscVector ) |
| 1724 | (*UscIsrTable[UscVector])(info); |
| 1725 | else if ( (DmaVector&(BIT10|BIT9)) == BIT10) |
| 1726 | mgsl_isr_transmit_dma(info); |
| 1727 | else |
| 1728 | mgsl_isr_receive_dma(info); |
| 1729 | |
| 1730 | if ( info->isr_overflow ) { |
Jeff Garzik | a6f97b2 | 2007-10-31 05:20:49 -0400 | [diff] [blame] | 1731 | printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n", |
| 1732 | __FILE__, __LINE__, info->device_name, info->irq_level); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1733 | usc_DisableMasterIrqBit(info); |
| 1734 | usc_DisableDmaInterrupts(info,DICR_MASTER); |
| 1735 | break; |
| 1736 | } |
| 1737 | } |
| 1738 | |
| 1739 | /* Request bottom half processing if there's something |
| 1740 | * for it to do and the bh is not already running |
| 1741 | */ |
| 1742 | |
| 1743 | if ( info->pending_bh && !info->bh_running && !info->bh_requested ) { |
| 1744 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
| 1745 | printk("%s(%d):%s queueing bh task.\n", |
| 1746 | __FILE__,__LINE__,info->device_name); |
| 1747 | schedule_work(&info->task); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 1748 | info->bh_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1749 | } |
| 1750 | |
| 1751 | spin_unlock(&info->irq_spinlock); |
| 1752 | |
| 1753 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
Jeff Garzik | a6f97b2 | 2007-10-31 05:20:49 -0400 | [diff] [blame] | 1754 | printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n", |
| 1755 | __FILE__, __LINE__, info->irq_level); |
| 1756 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1757 | return IRQ_HANDLED; |
| 1758 | } /* end of mgsl_interrupt() */ |
| 1759 | |
| 1760 | /* startup() |
| 1761 | * |
| 1762 | * Initialize and start device. |
| 1763 | * |
| 1764 | * Arguments: info pointer to device instance data |
| 1765 | * Return Value: 0 if success, otherwise error code |
| 1766 | */ |
| 1767 | static int startup(struct mgsl_struct * info) |
| 1768 | { |
| 1769 | int retval = 0; |
| 1770 | |
| 1771 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 1772 | printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name); |
| 1773 | |
| 1774 | if (info->flags & ASYNC_INITIALIZED) |
| 1775 | return 0; |
| 1776 | |
| 1777 | if (!info->xmit_buf) { |
| 1778 | /* allocate a page of memory for a transmit buffer */ |
| 1779 | info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL); |
| 1780 | if (!info->xmit_buf) { |
| 1781 | printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", |
| 1782 | __FILE__,__LINE__,info->device_name); |
| 1783 | return -ENOMEM; |
| 1784 | } |
| 1785 | } |
| 1786 | |
| 1787 | info->pending_bh = 0; |
| 1788 | |
Paul Fulghum | 9661239 | 2005-09-09 13:02:13 -0700 | [diff] [blame] | 1789 | memset(&info->icount, 0, sizeof(info->icount)); |
| 1790 | |
Jiri Slaby | 40565f1 | 2007-02-12 00:52:31 -0800 | [diff] [blame] | 1791 | setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1792 | |
| 1793 | /* Allocate and claim adapter resources */ |
| 1794 | retval = mgsl_claim_resources(info); |
| 1795 | |
| 1796 | /* perform existence check and diagnostics */ |
| 1797 | if ( !retval ) |
| 1798 | retval = mgsl_adapter_test(info); |
| 1799 | |
| 1800 | if ( retval ) { |
| 1801 | if (capable(CAP_SYS_ADMIN) && info->tty) |
| 1802 | set_bit(TTY_IO_ERROR, &info->tty->flags); |
| 1803 | mgsl_release_resources(info); |
| 1804 | return retval; |
| 1805 | } |
| 1806 | |
| 1807 | /* program hardware for current parameters */ |
| 1808 | mgsl_change_params(info); |
| 1809 | |
| 1810 | if (info->tty) |
| 1811 | clear_bit(TTY_IO_ERROR, &info->tty->flags); |
| 1812 | |
| 1813 | info->flags |= ASYNC_INITIALIZED; |
| 1814 | |
| 1815 | return 0; |
| 1816 | |
| 1817 | } /* end of startup() */ |
| 1818 | |
| 1819 | /* shutdown() |
| 1820 | * |
| 1821 | * Called by mgsl_close() and mgsl_hangup() to shutdown hardware |
| 1822 | * |
| 1823 | * Arguments: info pointer to device instance data |
| 1824 | * Return Value: None |
| 1825 | */ |
| 1826 | static void shutdown(struct mgsl_struct * info) |
| 1827 | { |
| 1828 | unsigned long flags; |
| 1829 | |
| 1830 | if (!(info->flags & ASYNC_INITIALIZED)) |
| 1831 | return; |
| 1832 | |
| 1833 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 1834 | printk("%s(%d):mgsl_shutdown(%s)\n", |
| 1835 | __FILE__,__LINE__, info->device_name ); |
| 1836 | |
| 1837 | /* clear status wait queue because status changes */ |
| 1838 | /* can't happen after shutting down the hardware */ |
| 1839 | wake_up_interruptible(&info->status_event_wait_q); |
| 1840 | wake_up_interruptible(&info->event_wait_q); |
| 1841 | |
Jiri Slaby | 40565f1 | 2007-02-12 00:52:31 -0800 | [diff] [blame] | 1842 | del_timer_sync(&info->tx_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1843 | |
| 1844 | if (info->xmit_buf) { |
| 1845 | free_page((unsigned long) info->xmit_buf); |
| 1846 | info->xmit_buf = NULL; |
| 1847 | } |
| 1848 | |
| 1849 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1850 | usc_DisableMasterIrqBit(info); |
| 1851 | usc_stop_receiver(info); |
| 1852 | usc_stop_transmitter(info); |
| 1853 | usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS + |
| 1854 | TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC ); |
| 1855 | usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE); |
| 1856 | |
| 1857 | /* Disable DMAEN (Port 7, Bit 14) */ |
| 1858 | /* This disconnects the DMA request signal from the ISA bus */ |
| 1859 | /* on the ISA adapter. This has no effect for the PCI adapter */ |
| 1860 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); |
| 1861 | |
| 1862 | /* Disable INTEN (Port 6, Bit12) */ |
| 1863 | /* This disconnects the IRQ request signal to the ISA bus */ |
| 1864 | /* on the ISA adapter. This has no effect for the PCI adapter */ |
| 1865 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); |
| 1866 | |
| 1867 | if (!info->tty || info->tty->termios->c_cflag & HUPCL) { |
| 1868 | info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); |
| 1869 | usc_set_serial_signals(info); |
| 1870 | } |
| 1871 | |
| 1872 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1873 | |
| 1874 | mgsl_release_resources(info); |
| 1875 | |
| 1876 | if (info->tty) |
| 1877 | set_bit(TTY_IO_ERROR, &info->tty->flags); |
| 1878 | |
| 1879 | info->flags &= ~ASYNC_INITIALIZED; |
| 1880 | |
| 1881 | } /* end of shutdown() */ |
| 1882 | |
| 1883 | static void mgsl_program_hw(struct mgsl_struct *info) |
| 1884 | { |
| 1885 | unsigned long flags; |
| 1886 | |
| 1887 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 1888 | |
| 1889 | usc_stop_receiver(info); |
| 1890 | usc_stop_transmitter(info); |
| 1891 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
| 1892 | |
| 1893 | if (info->params.mode == MGSL_MODE_HDLC || |
| 1894 | info->params.mode == MGSL_MODE_RAW || |
| 1895 | info->netcount) |
| 1896 | usc_set_sync_mode(info); |
| 1897 | else |
| 1898 | usc_set_async_mode(info); |
| 1899 | |
| 1900 | usc_set_serial_signals(info); |
| 1901 | |
| 1902 | info->dcd_chkcount = 0; |
| 1903 | info->cts_chkcount = 0; |
| 1904 | info->ri_chkcount = 0; |
| 1905 | info->dsr_chkcount = 0; |
| 1906 | |
| 1907 | usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI); |
| 1908 | usc_EnableInterrupts(info, IO_PIN); |
| 1909 | usc_get_serial_signals(info); |
| 1910 | |
| 1911 | if (info->netcount || info->tty->termios->c_cflag & CREAD) |
| 1912 | usc_start_receiver(info); |
| 1913 | |
| 1914 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 1915 | } |
| 1916 | |
| 1917 | /* Reconfigure adapter based on new parameters |
| 1918 | */ |
| 1919 | static void mgsl_change_params(struct mgsl_struct *info) |
| 1920 | { |
| 1921 | unsigned cflag; |
| 1922 | int bits_per_char; |
| 1923 | |
| 1924 | if (!info->tty || !info->tty->termios) |
| 1925 | return; |
| 1926 | |
| 1927 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 1928 | printk("%s(%d):mgsl_change_params(%s)\n", |
| 1929 | __FILE__,__LINE__, info->device_name ); |
| 1930 | |
| 1931 | cflag = info->tty->termios->c_cflag; |
| 1932 | |
| 1933 | /* if B0 rate (hangup) specified then negate DTR and RTS */ |
| 1934 | /* otherwise assert DTR and RTS */ |
| 1935 | if (cflag & CBAUD) |
| 1936 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; |
| 1937 | else |
| 1938 | info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); |
| 1939 | |
| 1940 | /* byte size and parity */ |
| 1941 | |
| 1942 | switch (cflag & CSIZE) { |
| 1943 | case CS5: info->params.data_bits = 5; break; |
| 1944 | case CS6: info->params.data_bits = 6; break; |
| 1945 | case CS7: info->params.data_bits = 7; break; |
| 1946 | case CS8: info->params.data_bits = 8; break; |
| 1947 | /* Never happens, but GCC is too dumb to figure it out */ |
| 1948 | default: info->params.data_bits = 7; break; |
| 1949 | } |
| 1950 | |
| 1951 | if (cflag & CSTOPB) |
| 1952 | info->params.stop_bits = 2; |
| 1953 | else |
| 1954 | info->params.stop_bits = 1; |
| 1955 | |
| 1956 | info->params.parity = ASYNC_PARITY_NONE; |
| 1957 | if (cflag & PARENB) { |
| 1958 | if (cflag & PARODD) |
| 1959 | info->params.parity = ASYNC_PARITY_ODD; |
| 1960 | else |
| 1961 | info->params.parity = ASYNC_PARITY_EVEN; |
| 1962 | #ifdef CMSPAR |
| 1963 | if (cflag & CMSPAR) |
| 1964 | info->params.parity = ASYNC_PARITY_SPACE; |
| 1965 | #endif |
| 1966 | } |
| 1967 | |
| 1968 | /* calculate number of jiffies to transmit a full |
| 1969 | * FIFO (32 bytes) at specified data rate |
| 1970 | */ |
| 1971 | bits_per_char = info->params.data_bits + |
| 1972 | info->params.stop_bits + 1; |
| 1973 | |
| 1974 | /* if port data rate is set to 460800 or less then |
| 1975 | * allow tty settings to override, otherwise keep the |
| 1976 | * current data rate. |
| 1977 | */ |
| 1978 | if (info->params.data_rate <= 460800) |
| 1979 | info->params.data_rate = tty_get_baud_rate(info->tty); |
| 1980 | |
| 1981 | if ( info->params.data_rate ) { |
| 1982 | info->timeout = (32*HZ*bits_per_char) / |
| 1983 | info->params.data_rate; |
| 1984 | } |
| 1985 | info->timeout += HZ/50; /* Add .02 seconds of slop */ |
| 1986 | |
| 1987 | if (cflag & CRTSCTS) |
| 1988 | info->flags |= ASYNC_CTS_FLOW; |
| 1989 | else |
| 1990 | info->flags &= ~ASYNC_CTS_FLOW; |
| 1991 | |
| 1992 | if (cflag & CLOCAL) |
| 1993 | info->flags &= ~ASYNC_CHECK_CD; |
| 1994 | else |
| 1995 | info->flags |= ASYNC_CHECK_CD; |
| 1996 | |
| 1997 | /* process tty input control flags */ |
| 1998 | |
| 1999 | info->read_status_mask = RXSTATUS_OVERRUN; |
| 2000 | if (I_INPCK(info->tty)) |
| 2001 | info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR; |
| 2002 | if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) |
| 2003 | info->read_status_mask |= RXSTATUS_BREAK_RECEIVED; |
| 2004 | |
| 2005 | if (I_IGNPAR(info->tty)) |
| 2006 | info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR; |
| 2007 | if (I_IGNBRK(info->tty)) { |
| 2008 | info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED; |
| 2009 | /* If ignoring parity and break indicators, ignore |
| 2010 | * overruns too. (For real raw support). |
| 2011 | */ |
| 2012 | if (I_IGNPAR(info->tty)) |
| 2013 | info->ignore_status_mask |= RXSTATUS_OVERRUN; |
| 2014 | } |
| 2015 | |
| 2016 | mgsl_program_hw(info); |
| 2017 | |
| 2018 | } /* end of mgsl_change_params() */ |
| 2019 | |
| 2020 | /* mgsl_put_char() |
| 2021 | * |
| 2022 | * Add a character to the transmit buffer. |
| 2023 | * |
| 2024 | * Arguments: tty pointer to tty information structure |
| 2025 | * ch character to add to transmit buffer |
| 2026 | * |
| 2027 | * Return Value: None |
| 2028 | */ |
Alan Cox | 55da778 | 2008-04-30 00:54:07 -0700 | [diff] [blame] | 2029 | static int mgsl_put_char(struct tty_struct *tty, unsigned char ch) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2030 | { |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2031 | struct mgsl_struct *info = tty->driver_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2032 | unsigned long flags; |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2033 | int ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2034 | |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2035 | if (debug_level >= DEBUG_LEVEL_INFO) { |
Andrew Morton | 5098021 | 2008-05-01 04:35:19 -0700 | [diff] [blame] | 2036 | printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n", |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2037 | __FILE__, __LINE__, ch, info->device_name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2038 | } |
| 2039 | |
| 2040 | if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char")) |
Alan Cox | 55da778 | 2008-04-30 00:54:07 -0700 | [diff] [blame] | 2041 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2042 | |
| 2043 | if (!tty || !info->xmit_buf) |
Alan Cox | 55da778 | 2008-04-30 00:54:07 -0700 | [diff] [blame] | 2044 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2045 | |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2046 | spin_lock_irqsave(&info->irq_spinlock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2047 | |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2048 | if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2049 | if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) { |
| 2050 | info->xmit_buf[info->xmit_head++] = ch; |
| 2051 | info->xmit_head &= SERIAL_XMIT_SIZE-1; |
| 2052 | info->xmit_cnt++; |
Alan Cox | 55da778 | 2008-04-30 00:54:07 -0700 | [diff] [blame] | 2053 | ret = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2054 | } |
| 2055 | } |
Andrew Morton | 0764823 | 2008-05-01 04:35:18 -0700 | [diff] [blame] | 2056 | spin_unlock_irqrestore(&info->irq_spinlock, flags); |
Alan Cox | 55da778 | 2008-04-30 00:54:07 -0700 | [diff] [blame] | 2057 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2058 | |
| 2059 | } /* end of mgsl_put_char() */ |
| 2060 | |
| 2061 | /* mgsl_flush_chars() |
| 2062 | * |
| 2063 | * Enable transmitter so remaining characters in the |
| 2064 | * transmit buffer are sent. |
| 2065 | * |
| 2066 | * Arguments: tty pointer to tty information structure |
| 2067 | * Return Value: None |
| 2068 | */ |
| 2069 | static void mgsl_flush_chars(struct tty_struct *tty) |
| 2070 | { |
| 2071 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2072 | unsigned long flags; |
| 2073 | |
| 2074 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2075 | printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n", |
| 2076 | __FILE__,__LINE__,info->device_name,info->xmit_cnt); |
| 2077 | |
| 2078 | if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars")) |
| 2079 | return; |
| 2080 | |
| 2081 | if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped || |
| 2082 | !info->xmit_buf) |
| 2083 | return; |
| 2084 | |
| 2085 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2086 | printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n", |
| 2087 | __FILE__,__LINE__,info->device_name ); |
| 2088 | |
| 2089 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2090 | |
| 2091 | if (!info->tx_active) { |
| 2092 | if ( (info->params.mode == MGSL_MODE_HDLC || |
| 2093 | info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) { |
| 2094 | /* operating in synchronous (frame oriented) mode */ |
| 2095 | /* copy data from circular xmit_buf to */ |
| 2096 | /* transmit DMA buffer. */ |
| 2097 | mgsl_load_tx_dma_buffer(info, |
| 2098 | info->xmit_buf,info->xmit_cnt); |
| 2099 | } |
| 2100 | usc_start_transmitter(info); |
| 2101 | } |
| 2102 | |
| 2103 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2104 | |
| 2105 | } /* end of mgsl_flush_chars() */ |
| 2106 | |
| 2107 | /* mgsl_write() |
| 2108 | * |
| 2109 | * Send a block of data |
| 2110 | * |
| 2111 | * Arguments: |
| 2112 | * |
| 2113 | * tty pointer to tty information structure |
| 2114 | * buf pointer to buffer containing send data |
| 2115 | * count size of send data in bytes |
| 2116 | * |
| 2117 | * Return Value: number of characters written |
| 2118 | */ |
| 2119 | static int mgsl_write(struct tty_struct * tty, |
| 2120 | const unsigned char *buf, int count) |
| 2121 | { |
| 2122 | int c, ret = 0; |
| 2123 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2124 | unsigned long flags; |
| 2125 | |
| 2126 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2127 | printk( "%s(%d):mgsl_write(%s) count=%d\n", |
| 2128 | __FILE__,__LINE__,info->device_name,count); |
| 2129 | |
| 2130 | if (mgsl_paranoia_check(info, tty->name, "mgsl_write")) |
| 2131 | goto cleanup; |
| 2132 | |
Paul Fulghum | 86a3414 | 2006-03-28 01:56:14 -0800 | [diff] [blame] | 2133 | if (!tty || !info->xmit_buf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2134 | goto cleanup; |
| 2135 | |
| 2136 | if ( info->params.mode == MGSL_MODE_HDLC || |
| 2137 | info->params.mode == MGSL_MODE_RAW ) { |
| 2138 | /* operating in synchronous (frame oriented) mode */ |
| 2139 | /* operating in synchronous (frame oriented) mode */ |
| 2140 | if (info->tx_active) { |
| 2141 | |
| 2142 | if ( info->params.mode == MGSL_MODE_HDLC ) { |
| 2143 | ret = 0; |
| 2144 | goto cleanup; |
| 2145 | } |
| 2146 | /* transmitter is actively sending data - |
| 2147 | * if we have multiple transmit dma and |
| 2148 | * holding buffers, attempt to queue this |
| 2149 | * frame for transmission at a later time. |
| 2150 | */ |
| 2151 | if (info->tx_holding_count >= info->num_tx_holding_buffers ) { |
| 2152 | /* no tx holding buffers available */ |
| 2153 | ret = 0; |
| 2154 | goto cleanup; |
| 2155 | } |
| 2156 | |
| 2157 | /* queue transmit frame request */ |
| 2158 | ret = count; |
| 2159 | save_tx_buffer_request(info,buf,count); |
| 2160 | |
| 2161 | /* if we have sufficient tx dma buffers, |
| 2162 | * load the next buffered tx request |
| 2163 | */ |
| 2164 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2165 | load_next_tx_holding_buffer(info); |
| 2166 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2167 | goto cleanup; |
| 2168 | } |
| 2169 | |
| 2170 | /* if operating in HDLC LoopMode and the adapter */ |
| 2171 | /* has yet to be inserted into the loop, we can't */ |
| 2172 | /* transmit */ |
| 2173 | |
| 2174 | if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) && |
| 2175 | !usc_loopmode_active(info) ) |
| 2176 | { |
| 2177 | ret = 0; |
| 2178 | goto cleanup; |
| 2179 | } |
| 2180 | |
| 2181 | if ( info->xmit_cnt ) { |
| 2182 | /* Send accumulated from send_char() calls */ |
| 2183 | /* as frame and wait before accepting more data. */ |
| 2184 | ret = 0; |
| 2185 | |
| 2186 | /* copy data from circular xmit_buf to */ |
| 2187 | /* transmit DMA buffer. */ |
| 2188 | mgsl_load_tx_dma_buffer(info, |
| 2189 | info->xmit_buf,info->xmit_cnt); |
| 2190 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2191 | printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n", |
| 2192 | __FILE__,__LINE__,info->device_name); |
| 2193 | } else { |
| 2194 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2195 | printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n", |
| 2196 | __FILE__,__LINE__,info->device_name); |
| 2197 | ret = count; |
| 2198 | info->xmit_cnt = count; |
| 2199 | mgsl_load_tx_dma_buffer(info,buf,count); |
| 2200 | } |
| 2201 | } else { |
| 2202 | while (1) { |
| 2203 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2204 | c = min_t(int, count, |
| 2205 | min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, |
| 2206 | SERIAL_XMIT_SIZE - info->xmit_head)); |
| 2207 | if (c <= 0) { |
| 2208 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2209 | break; |
| 2210 | } |
| 2211 | memcpy(info->xmit_buf + info->xmit_head, buf, c); |
| 2212 | info->xmit_head = ((info->xmit_head + c) & |
| 2213 | (SERIAL_XMIT_SIZE-1)); |
| 2214 | info->xmit_cnt += c; |
| 2215 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2216 | buf += c; |
| 2217 | count -= c; |
| 2218 | ret += c; |
| 2219 | } |
| 2220 | } |
| 2221 | |
| 2222 | if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) { |
| 2223 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2224 | if (!info->tx_active) |
| 2225 | usc_start_transmitter(info); |
| 2226 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2227 | } |
| 2228 | cleanup: |
| 2229 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2230 | printk( "%s(%d):mgsl_write(%s) returning=%d\n", |
| 2231 | __FILE__,__LINE__,info->device_name,ret); |
| 2232 | |
| 2233 | return ret; |
| 2234 | |
| 2235 | } /* end of mgsl_write() */ |
| 2236 | |
| 2237 | /* mgsl_write_room() |
| 2238 | * |
| 2239 | * Return the count of free bytes in transmit buffer |
| 2240 | * |
| 2241 | * Arguments: tty pointer to tty info structure |
| 2242 | * Return Value: None |
| 2243 | */ |
| 2244 | static int mgsl_write_room(struct tty_struct *tty) |
| 2245 | { |
| 2246 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2247 | int ret; |
| 2248 | |
| 2249 | if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room")) |
| 2250 | return 0; |
| 2251 | ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; |
| 2252 | if (ret < 0) |
| 2253 | ret = 0; |
| 2254 | |
| 2255 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2256 | printk("%s(%d):mgsl_write_room(%s)=%d\n", |
| 2257 | __FILE__,__LINE__, info->device_name,ret ); |
| 2258 | |
| 2259 | if ( info->params.mode == MGSL_MODE_HDLC || |
| 2260 | info->params.mode == MGSL_MODE_RAW ) { |
| 2261 | /* operating in synchronous (frame oriented) mode */ |
| 2262 | if ( info->tx_active ) |
| 2263 | return 0; |
| 2264 | else |
| 2265 | return HDLC_MAX_FRAME_SIZE; |
| 2266 | } |
| 2267 | |
| 2268 | return ret; |
| 2269 | |
| 2270 | } /* end of mgsl_write_room() */ |
| 2271 | |
| 2272 | /* mgsl_chars_in_buffer() |
| 2273 | * |
| 2274 | * Return the count of bytes in transmit buffer |
| 2275 | * |
| 2276 | * Arguments: tty pointer to tty info structure |
| 2277 | * Return Value: None |
| 2278 | */ |
| 2279 | static int mgsl_chars_in_buffer(struct tty_struct *tty) |
| 2280 | { |
| 2281 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2282 | |
| 2283 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2284 | printk("%s(%d):mgsl_chars_in_buffer(%s)\n", |
| 2285 | __FILE__,__LINE__, info->device_name ); |
| 2286 | |
| 2287 | if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer")) |
| 2288 | return 0; |
| 2289 | |
| 2290 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2291 | printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n", |
| 2292 | __FILE__,__LINE__, info->device_name,info->xmit_cnt ); |
| 2293 | |
| 2294 | if ( info->params.mode == MGSL_MODE_HDLC || |
| 2295 | info->params.mode == MGSL_MODE_RAW ) { |
| 2296 | /* operating in synchronous (frame oriented) mode */ |
| 2297 | if ( info->tx_active ) |
| 2298 | return info->max_frame_size; |
| 2299 | else |
| 2300 | return 0; |
| 2301 | } |
| 2302 | |
| 2303 | return info->xmit_cnt; |
| 2304 | } /* end of mgsl_chars_in_buffer() */ |
| 2305 | |
| 2306 | /* mgsl_flush_buffer() |
| 2307 | * |
| 2308 | * Discard all data in the send buffer |
| 2309 | * |
| 2310 | * Arguments: tty pointer to tty info structure |
| 2311 | * Return Value: None |
| 2312 | */ |
| 2313 | static void mgsl_flush_buffer(struct tty_struct *tty) |
| 2314 | { |
| 2315 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2316 | unsigned long flags; |
| 2317 | |
| 2318 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2319 | printk("%s(%d):mgsl_flush_buffer(%s) entry\n", |
| 2320 | __FILE__,__LINE__, info->device_name ); |
| 2321 | |
| 2322 | if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer")) |
| 2323 | return; |
| 2324 | |
| 2325 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2326 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
| 2327 | del_timer(&info->tx_timer); |
| 2328 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2329 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2330 | tty_wakeup(tty); |
| 2331 | } |
| 2332 | |
| 2333 | /* mgsl_send_xchar() |
| 2334 | * |
| 2335 | * Send a high-priority XON/XOFF character |
| 2336 | * |
| 2337 | * Arguments: tty pointer to tty info structure |
| 2338 | * ch character to send |
| 2339 | * Return Value: None |
| 2340 | */ |
| 2341 | static void mgsl_send_xchar(struct tty_struct *tty, char ch) |
| 2342 | { |
| 2343 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2344 | unsigned long flags; |
| 2345 | |
| 2346 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2347 | printk("%s(%d):mgsl_send_xchar(%s,%d)\n", |
| 2348 | __FILE__,__LINE__, info->device_name, ch ); |
| 2349 | |
| 2350 | if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar")) |
| 2351 | return; |
| 2352 | |
| 2353 | info->x_char = ch; |
| 2354 | if (ch) { |
| 2355 | /* Make sure transmit interrupts are on */ |
| 2356 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2357 | if (!info->tx_enabled) |
| 2358 | usc_start_transmitter(info); |
| 2359 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2360 | } |
| 2361 | } /* end of mgsl_send_xchar() */ |
| 2362 | |
| 2363 | /* mgsl_throttle() |
| 2364 | * |
| 2365 | * Signal remote device to throttle send data (our receive data) |
| 2366 | * |
| 2367 | * Arguments: tty pointer to tty info structure |
| 2368 | * Return Value: None |
| 2369 | */ |
| 2370 | static void mgsl_throttle(struct tty_struct * tty) |
| 2371 | { |
| 2372 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2373 | unsigned long flags; |
| 2374 | |
| 2375 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2376 | printk("%s(%d):mgsl_throttle(%s) entry\n", |
| 2377 | __FILE__,__LINE__, info->device_name ); |
| 2378 | |
| 2379 | if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle")) |
| 2380 | return; |
| 2381 | |
| 2382 | if (I_IXOFF(tty)) |
| 2383 | mgsl_send_xchar(tty, STOP_CHAR(tty)); |
| 2384 | |
| 2385 | if (tty->termios->c_cflag & CRTSCTS) { |
| 2386 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2387 | info->serial_signals &= ~SerialSignal_RTS; |
| 2388 | usc_set_serial_signals(info); |
| 2389 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2390 | } |
| 2391 | } /* end of mgsl_throttle() */ |
| 2392 | |
| 2393 | /* mgsl_unthrottle() |
| 2394 | * |
| 2395 | * Signal remote device to stop throttling send data (our receive data) |
| 2396 | * |
| 2397 | * Arguments: tty pointer to tty info structure |
| 2398 | * Return Value: None |
| 2399 | */ |
| 2400 | static void mgsl_unthrottle(struct tty_struct * tty) |
| 2401 | { |
| 2402 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2403 | unsigned long flags; |
| 2404 | |
| 2405 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2406 | printk("%s(%d):mgsl_unthrottle(%s) entry\n", |
| 2407 | __FILE__,__LINE__, info->device_name ); |
| 2408 | |
| 2409 | if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle")) |
| 2410 | return; |
| 2411 | |
| 2412 | if (I_IXOFF(tty)) { |
| 2413 | if (info->x_char) |
| 2414 | info->x_char = 0; |
| 2415 | else |
| 2416 | mgsl_send_xchar(tty, START_CHAR(tty)); |
| 2417 | } |
| 2418 | |
| 2419 | if (tty->termios->c_cflag & CRTSCTS) { |
| 2420 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2421 | info->serial_signals |= SerialSignal_RTS; |
| 2422 | usc_set_serial_signals(info); |
| 2423 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2424 | } |
| 2425 | |
| 2426 | } /* end of mgsl_unthrottle() */ |
| 2427 | |
| 2428 | /* mgsl_get_stats() |
| 2429 | * |
| 2430 | * get the current serial parameters information |
| 2431 | * |
| 2432 | * Arguments: info pointer to device instance data |
| 2433 | * user_icount pointer to buffer to hold returned stats |
| 2434 | * |
| 2435 | * Return Value: 0 if success, otherwise error code |
| 2436 | */ |
| 2437 | static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount) |
| 2438 | { |
| 2439 | int err; |
| 2440 | |
| 2441 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2442 | printk("%s(%d):mgsl_get_params(%s)\n", |
| 2443 | __FILE__,__LINE__, info->device_name); |
| 2444 | |
Paul Fulghum | 9661239 | 2005-09-09 13:02:13 -0700 | [diff] [blame] | 2445 | if (!user_icount) { |
| 2446 | memset(&info->icount, 0, sizeof(info->icount)); |
| 2447 | } else { |
| 2448 | COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); |
| 2449 | if (err) |
| 2450 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2451 | } |
| 2452 | |
| 2453 | return 0; |
| 2454 | |
| 2455 | } /* end of mgsl_get_stats() */ |
| 2456 | |
| 2457 | /* mgsl_get_params() |
| 2458 | * |
| 2459 | * get the current serial parameters information |
| 2460 | * |
| 2461 | * Arguments: info pointer to device instance data |
| 2462 | * user_params pointer to buffer to hold returned params |
| 2463 | * |
| 2464 | * Return Value: 0 if success, otherwise error code |
| 2465 | */ |
| 2466 | static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params) |
| 2467 | { |
| 2468 | int err; |
| 2469 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2470 | printk("%s(%d):mgsl_get_params(%s)\n", |
| 2471 | __FILE__,__LINE__, info->device_name); |
| 2472 | |
| 2473 | COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); |
| 2474 | if (err) { |
| 2475 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2476 | printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n", |
| 2477 | __FILE__,__LINE__,info->device_name); |
| 2478 | return -EFAULT; |
| 2479 | } |
| 2480 | |
| 2481 | return 0; |
| 2482 | |
| 2483 | } /* end of mgsl_get_params() */ |
| 2484 | |
| 2485 | /* mgsl_set_params() |
| 2486 | * |
| 2487 | * set the serial parameters |
| 2488 | * |
| 2489 | * Arguments: |
| 2490 | * |
| 2491 | * info pointer to device instance data |
| 2492 | * new_params user buffer containing new serial params |
| 2493 | * |
| 2494 | * Return Value: 0 if success, otherwise error code |
| 2495 | */ |
| 2496 | static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params) |
| 2497 | { |
| 2498 | unsigned long flags; |
| 2499 | MGSL_PARAMS tmp_params; |
| 2500 | int err; |
| 2501 | |
| 2502 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2503 | printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__, |
| 2504 | info->device_name ); |
| 2505 | COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); |
| 2506 | if (err) { |
| 2507 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2508 | printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n", |
| 2509 | __FILE__,__LINE__,info->device_name); |
| 2510 | return -EFAULT; |
| 2511 | } |
| 2512 | |
| 2513 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2514 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); |
| 2515 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2516 | |
| 2517 | mgsl_change_params(info); |
| 2518 | |
| 2519 | return 0; |
| 2520 | |
| 2521 | } /* end of mgsl_set_params() */ |
| 2522 | |
| 2523 | /* mgsl_get_txidle() |
| 2524 | * |
| 2525 | * get the current transmit idle mode |
| 2526 | * |
| 2527 | * Arguments: info pointer to device instance data |
| 2528 | * idle_mode pointer to buffer to hold returned idle mode |
| 2529 | * |
| 2530 | * Return Value: 0 if success, otherwise error code |
| 2531 | */ |
| 2532 | static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode) |
| 2533 | { |
| 2534 | int err; |
| 2535 | |
| 2536 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2537 | printk("%s(%d):mgsl_get_txidle(%s)=%d\n", |
| 2538 | __FILE__,__LINE__, info->device_name, info->idle_mode); |
| 2539 | |
| 2540 | COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); |
| 2541 | if (err) { |
| 2542 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 2543 | printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n", |
| 2544 | __FILE__,__LINE__,info->device_name); |
| 2545 | return -EFAULT; |
| 2546 | } |
| 2547 | |
| 2548 | return 0; |
| 2549 | |
| 2550 | } /* end of mgsl_get_txidle() */ |
| 2551 | |
| 2552 | /* mgsl_set_txidle() service ioctl to set transmit idle mode |
| 2553 | * |
| 2554 | * Arguments: info pointer to device instance data |
| 2555 | * idle_mode new idle mode |
| 2556 | * |
| 2557 | * Return Value: 0 if success, otherwise error code |
| 2558 | */ |
| 2559 | static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode) |
| 2560 | { |
| 2561 | unsigned long flags; |
| 2562 | |
| 2563 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2564 | printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__, |
| 2565 | info->device_name, idle_mode ); |
| 2566 | |
| 2567 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2568 | info->idle_mode = idle_mode; |
| 2569 | usc_set_txidle( info ); |
| 2570 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2571 | return 0; |
| 2572 | |
| 2573 | } /* end of mgsl_set_txidle() */ |
| 2574 | |
| 2575 | /* mgsl_txenable() |
| 2576 | * |
| 2577 | * enable or disable the transmitter |
| 2578 | * |
| 2579 | * Arguments: |
| 2580 | * |
| 2581 | * info pointer to device instance data |
| 2582 | * enable 1 = enable, 0 = disable |
| 2583 | * |
| 2584 | * Return Value: 0 if success, otherwise error code |
| 2585 | */ |
| 2586 | static int mgsl_txenable(struct mgsl_struct * info, int enable) |
| 2587 | { |
| 2588 | unsigned long flags; |
| 2589 | |
| 2590 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2591 | printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__, |
| 2592 | info->device_name, enable); |
| 2593 | |
| 2594 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2595 | if ( enable ) { |
| 2596 | if ( !info->tx_enabled ) { |
| 2597 | |
| 2598 | usc_start_transmitter(info); |
| 2599 | /*-------------------------------------------------- |
| 2600 | * if HDLC/SDLC Loop mode, attempt to insert the |
| 2601 | * station in the 'loop' by setting CMR:13. Upon |
| 2602 | * receipt of the next GoAhead (RxAbort) sequence, |
| 2603 | * the OnLoop indicator (CCSR:7) should go active |
| 2604 | * to indicate that we are on the loop |
| 2605 | *--------------------------------------------------*/ |
| 2606 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) |
| 2607 | usc_loopmode_insert_request( info ); |
| 2608 | } |
| 2609 | } else { |
| 2610 | if ( info->tx_enabled ) |
| 2611 | usc_stop_transmitter(info); |
| 2612 | } |
| 2613 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2614 | return 0; |
| 2615 | |
| 2616 | } /* end of mgsl_txenable() */ |
| 2617 | |
| 2618 | /* mgsl_txabort() abort send HDLC frame |
| 2619 | * |
| 2620 | * Arguments: info pointer to device instance data |
| 2621 | * Return Value: 0 if success, otherwise error code |
| 2622 | */ |
| 2623 | static int mgsl_txabort(struct mgsl_struct * info) |
| 2624 | { |
| 2625 | unsigned long flags; |
| 2626 | |
| 2627 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2628 | printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__, |
| 2629 | info->device_name); |
| 2630 | |
| 2631 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2632 | if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) |
| 2633 | { |
| 2634 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) |
| 2635 | usc_loopmode_cancel_transmit( info ); |
| 2636 | else |
| 2637 | usc_TCmd(info,TCmd_SendAbort); |
| 2638 | } |
| 2639 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2640 | return 0; |
| 2641 | |
| 2642 | } /* end of mgsl_txabort() */ |
| 2643 | |
| 2644 | /* mgsl_rxenable() enable or disable the receiver |
| 2645 | * |
| 2646 | * Arguments: info pointer to device instance data |
| 2647 | * enable 1 = enable, 0 = disable |
| 2648 | * Return Value: 0 if success, otherwise error code |
| 2649 | */ |
| 2650 | static int mgsl_rxenable(struct mgsl_struct * info, int enable) |
| 2651 | { |
| 2652 | unsigned long flags; |
| 2653 | |
| 2654 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2655 | printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__, |
| 2656 | info->device_name, enable); |
| 2657 | |
| 2658 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2659 | if ( enable ) { |
| 2660 | if ( !info->rx_enabled ) |
| 2661 | usc_start_receiver(info); |
| 2662 | } else { |
| 2663 | if ( info->rx_enabled ) |
| 2664 | usc_stop_receiver(info); |
| 2665 | } |
| 2666 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2667 | return 0; |
| 2668 | |
| 2669 | } /* end of mgsl_rxenable() */ |
| 2670 | |
| 2671 | /* mgsl_wait_event() wait for specified event to occur |
| 2672 | * |
| 2673 | * Arguments: info pointer to device instance data |
| 2674 | * mask pointer to bitmask of events to wait for |
| 2675 | * Return Value: 0 if successful and bit mask updated with |
| 2676 | * of events triggerred, |
| 2677 | * otherwise error code |
| 2678 | */ |
| 2679 | static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr) |
| 2680 | { |
| 2681 | unsigned long flags; |
| 2682 | int s; |
| 2683 | int rc=0; |
| 2684 | struct mgsl_icount cprev, cnow; |
| 2685 | int events; |
| 2686 | int mask; |
| 2687 | struct _input_signal_events oldsigs, newsigs; |
| 2688 | DECLARE_WAITQUEUE(wait, current); |
| 2689 | |
| 2690 | COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); |
| 2691 | if (rc) { |
| 2692 | return -EFAULT; |
| 2693 | } |
| 2694 | |
| 2695 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2696 | printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__, |
| 2697 | info->device_name, mask); |
| 2698 | |
| 2699 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2700 | |
| 2701 | /* return immediately if state matches requested events */ |
| 2702 | usc_get_serial_signals(info); |
| 2703 | s = info->serial_signals; |
| 2704 | events = mask & |
| 2705 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + |
| 2706 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + |
| 2707 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + |
| 2708 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); |
| 2709 | if (events) { |
| 2710 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2711 | goto exit; |
| 2712 | } |
| 2713 | |
| 2714 | /* save current irq counts */ |
| 2715 | cprev = info->icount; |
| 2716 | oldsigs = info->input_signal_events; |
| 2717 | |
| 2718 | /* enable hunt and idle irqs if needed */ |
| 2719 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { |
| 2720 | u16 oldreg = usc_InReg(info,RICR); |
| 2721 | u16 newreg = oldreg + |
| 2722 | (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) + |
| 2723 | (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0); |
| 2724 | if (oldreg != newreg) |
| 2725 | usc_OutReg(info, RICR, newreg); |
| 2726 | } |
| 2727 | |
| 2728 | set_current_state(TASK_INTERRUPTIBLE); |
| 2729 | add_wait_queue(&info->event_wait_q, &wait); |
| 2730 | |
| 2731 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2732 | |
| 2733 | |
| 2734 | for(;;) { |
| 2735 | schedule(); |
| 2736 | if (signal_pending(current)) { |
| 2737 | rc = -ERESTARTSYS; |
| 2738 | break; |
| 2739 | } |
| 2740 | |
| 2741 | /* get current irq counts */ |
| 2742 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2743 | cnow = info->icount; |
| 2744 | newsigs = info->input_signal_events; |
| 2745 | set_current_state(TASK_INTERRUPTIBLE); |
| 2746 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2747 | |
| 2748 | /* if no change, wait aborted for some reason */ |
| 2749 | if (newsigs.dsr_up == oldsigs.dsr_up && |
| 2750 | newsigs.dsr_down == oldsigs.dsr_down && |
| 2751 | newsigs.dcd_up == oldsigs.dcd_up && |
| 2752 | newsigs.dcd_down == oldsigs.dcd_down && |
| 2753 | newsigs.cts_up == oldsigs.cts_up && |
| 2754 | newsigs.cts_down == oldsigs.cts_down && |
| 2755 | newsigs.ri_up == oldsigs.ri_up && |
| 2756 | newsigs.ri_down == oldsigs.ri_down && |
| 2757 | cnow.exithunt == cprev.exithunt && |
| 2758 | cnow.rxidle == cprev.rxidle) { |
| 2759 | rc = -EIO; |
| 2760 | break; |
| 2761 | } |
| 2762 | |
| 2763 | events = mask & |
| 2764 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + |
| 2765 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + |
| 2766 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + |
| 2767 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + |
| 2768 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + |
| 2769 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + |
| 2770 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + |
| 2771 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + |
| 2772 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + |
| 2773 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); |
| 2774 | if (events) |
| 2775 | break; |
| 2776 | |
| 2777 | cprev = cnow; |
| 2778 | oldsigs = newsigs; |
| 2779 | } |
| 2780 | |
| 2781 | remove_wait_queue(&info->event_wait_q, &wait); |
| 2782 | set_current_state(TASK_RUNNING); |
| 2783 | |
| 2784 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { |
| 2785 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2786 | if (!waitqueue_active(&info->event_wait_q)) { |
| 2787 | /* disable enable exit hunt mode/idle rcvd IRQs */ |
| 2788 | usc_OutReg(info, RICR, usc_InReg(info,RICR) & |
| 2789 | ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)); |
| 2790 | } |
| 2791 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2792 | } |
| 2793 | exit: |
| 2794 | if ( rc == 0 ) |
| 2795 | PUT_USER(rc, events, mask_ptr); |
| 2796 | |
| 2797 | return rc; |
| 2798 | |
| 2799 | } /* end of mgsl_wait_event() */ |
| 2800 | |
| 2801 | static int modem_input_wait(struct mgsl_struct *info,int arg) |
| 2802 | { |
| 2803 | unsigned long flags; |
| 2804 | int rc; |
| 2805 | struct mgsl_icount cprev, cnow; |
| 2806 | DECLARE_WAITQUEUE(wait, current); |
| 2807 | |
| 2808 | /* save current irq counts */ |
| 2809 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2810 | cprev = info->icount; |
| 2811 | add_wait_queue(&info->status_event_wait_q, &wait); |
| 2812 | set_current_state(TASK_INTERRUPTIBLE); |
| 2813 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2814 | |
| 2815 | for(;;) { |
| 2816 | schedule(); |
| 2817 | if (signal_pending(current)) { |
| 2818 | rc = -ERESTARTSYS; |
| 2819 | break; |
| 2820 | } |
| 2821 | |
| 2822 | /* get new irq counts */ |
| 2823 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2824 | cnow = info->icount; |
| 2825 | set_current_state(TASK_INTERRUPTIBLE); |
| 2826 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2827 | |
| 2828 | /* if no change, wait aborted for some reason */ |
| 2829 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && |
| 2830 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { |
| 2831 | rc = -EIO; |
| 2832 | break; |
| 2833 | } |
| 2834 | |
| 2835 | /* check for change in caller specified modem input */ |
| 2836 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || |
| 2837 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || |
| 2838 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || |
| 2839 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { |
| 2840 | rc = 0; |
| 2841 | break; |
| 2842 | } |
| 2843 | |
| 2844 | cprev = cnow; |
| 2845 | } |
| 2846 | remove_wait_queue(&info->status_event_wait_q, &wait); |
| 2847 | set_current_state(TASK_RUNNING); |
| 2848 | return rc; |
| 2849 | } |
| 2850 | |
| 2851 | /* return the state of the serial control and status signals |
| 2852 | */ |
| 2853 | static int tiocmget(struct tty_struct *tty, struct file *file) |
| 2854 | { |
| 2855 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2856 | unsigned int result; |
| 2857 | unsigned long flags; |
| 2858 | |
| 2859 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2860 | usc_get_serial_signals(info); |
| 2861 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2862 | |
| 2863 | result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) + |
| 2864 | ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) + |
| 2865 | ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) + |
| 2866 | ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) + |
| 2867 | ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) + |
| 2868 | ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0); |
| 2869 | |
| 2870 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2871 | printk("%s(%d):%s tiocmget() value=%08X\n", |
| 2872 | __FILE__,__LINE__, info->device_name, result ); |
| 2873 | return result; |
| 2874 | } |
| 2875 | |
| 2876 | /* set modem control signals (DTR/RTS) |
| 2877 | */ |
| 2878 | static int tiocmset(struct tty_struct *tty, struct file *file, |
| 2879 | unsigned int set, unsigned int clear) |
| 2880 | { |
| 2881 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 2882 | unsigned long flags; |
| 2883 | |
| 2884 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2885 | printk("%s(%d):%s tiocmset(%x,%x)\n", |
| 2886 | __FILE__,__LINE__,info->device_name, set, clear); |
| 2887 | |
| 2888 | if (set & TIOCM_RTS) |
| 2889 | info->serial_signals |= SerialSignal_RTS; |
| 2890 | if (set & TIOCM_DTR) |
| 2891 | info->serial_signals |= SerialSignal_DTR; |
| 2892 | if (clear & TIOCM_RTS) |
| 2893 | info->serial_signals &= ~SerialSignal_RTS; |
| 2894 | if (clear & TIOCM_DTR) |
| 2895 | info->serial_signals &= ~SerialSignal_DTR; |
| 2896 | |
| 2897 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2898 | usc_set_serial_signals(info); |
| 2899 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2900 | |
| 2901 | return 0; |
| 2902 | } |
| 2903 | |
| 2904 | /* mgsl_break() Set or clear transmit break condition |
| 2905 | * |
| 2906 | * Arguments: tty pointer to tty instance data |
| 2907 | * break_state -1=set break condition, 0=clear |
| 2908 | * Return Value: None |
| 2909 | */ |
| 2910 | static void mgsl_break(struct tty_struct *tty, int break_state) |
| 2911 | { |
| 2912 | struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data; |
| 2913 | unsigned long flags; |
| 2914 | |
| 2915 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2916 | printk("%s(%d):mgsl_break(%s,%d)\n", |
| 2917 | __FILE__,__LINE__, info->device_name, break_state); |
| 2918 | |
| 2919 | if (mgsl_paranoia_check(info, tty->name, "mgsl_break")) |
| 2920 | return; |
| 2921 | |
| 2922 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 2923 | if (break_state == -1) |
| 2924 | usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); |
| 2925 | else |
| 2926 | usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); |
| 2927 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 2928 | |
| 2929 | } /* end of mgsl_break() */ |
| 2930 | |
| 2931 | /* mgsl_ioctl() Service an IOCTL request |
| 2932 | * |
| 2933 | * Arguments: |
| 2934 | * |
| 2935 | * tty pointer to tty instance data |
| 2936 | * file pointer to associated file object for device |
| 2937 | * cmd IOCTL command code |
| 2938 | * arg command argument/context |
| 2939 | * |
| 2940 | * Return Value: 0 if success, otherwise error code |
| 2941 | */ |
| 2942 | static int mgsl_ioctl(struct tty_struct *tty, struct file * file, |
| 2943 | unsigned int cmd, unsigned long arg) |
| 2944 | { |
| 2945 | struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data; |
Alan Cox | 1f8cabb | 2008-04-30 00:53:24 -0700 | [diff] [blame] | 2946 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2947 | |
| 2948 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 2949 | printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__, |
| 2950 | info->device_name, cmd ); |
| 2951 | |
| 2952 | if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl")) |
| 2953 | return -ENODEV; |
| 2954 | |
| 2955 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && |
| 2956 | (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { |
| 2957 | if (tty->flags & (1 << TTY_IO_ERROR)) |
| 2958 | return -EIO; |
| 2959 | } |
| 2960 | |
Alan Cox | 1f8cabb | 2008-04-30 00:53:24 -0700 | [diff] [blame] | 2961 | lock_kernel(); |
| 2962 | ret = mgsl_ioctl_common(info, cmd, arg); |
| 2963 | unlock_kernel(); |
| 2964 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2965 | } |
| 2966 | |
| 2967 | static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg) |
| 2968 | { |
| 2969 | int error; |
| 2970 | struct mgsl_icount cnow; /* kernel counter temps */ |
| 2971 | void __user *argp = (void __user *)arg; |
| 2972 | struct serial_icounter_struct __user *p_cuser; /* user space */ |
| 2973 | unsigned long flags; |
| 2974 | |
| 2975 | switch (cmd) { |
| 2976 | case MGSL_IOCGPARAMS: |
| 2977 | return mgsl_get_params(info, argp); |
| 2978 | case MGSL_IOCSPARAMS: |
| 2979 | return mgsl_set_params(info, argp); |
| 2980 | case MGSL_IOCGTXIDLE: |
| 2981 | return mgsl_get_txidle(info, argp); |
| 2982 | case MGSL_IOCSTXIDLE: |
| 2983 | return mgsl_set_txidle(info,(int)arg); |
| 2984 | case MGSL_IOCTXENABLE: |
| 2985 | return mgsl_txenable(info,(int)arg); |
| 2986 | case MGSL_IOCRXENABLE: |
| 2987 | return mgsl_rxenable(info,(int)arg); |
| 2988 | case MGSL_IOCTXABORT: |
| 2989 | return mgsl_txabort(info); |
| 2990 | case MGSL_IOCGSTATS: |
| 2991 | return mgsl_get_stats(info, argp); |
| 2992 | case MGSL_IOCWAITEVENT: |
| 2993 | return mgsl_wait_event(info, argp); |
| 2994 | case MGSL_IOCLOOPTXDONE: |
| 2995 | return mgsl_loopmode_send_done(info); |
| 2996 | /* Wait for modem input (DCD,RI,DSR,CTS) change |
| 2997 | * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) |
| 2998 | */ |
| 2999 | case TIOCMIWAIT: |
| 3000 | return modem_input_wait(info,(int)arg); |
| 3001 | |
| 3002 | /* |
| 3003 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) |
| 3004 | * Return: write counters to the user passed counter struct |
| 3005 | * NB: both 1->0 and 0->1 transitions are counted except for |
| 3006 | * RI where only 0->1 is counted. |
| 3007 | */ |
| 3008 | case TIOCGICOUNT: |
| 3009 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3010 | cnow = info->icount; |
| 3011 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3012 | p_cuser = argp; |
| 3013 | PUT_USER(error,cnow.cts, &p_cuser->cts); |
| 3014 | if (error) return error; |
| 3015 | PUT_USER(error,cnow.dsr, &p_cuser->dsr); |
| 3016 | if (error) return error; |
| 3017 | PUT_USER(error,cnow.rng, &p_cuser->rng); |
| 3018 | if (error) return error; |
| 3019 | PUT_USER(error,cnow.dcd, &p_cuser->dcd); |
| 3020 | if (error) return error; |
| 3021 | PUT_USER(error,cnow.rx, &p_cuser->rx); |
| 3022 | if (error) return error; |
| 3023 | PUT_USER(error,cnow.tx, &p_cuser->tx); |
| 3024 | if (error) return error; |
| 3025 | PUT_USER(error,cnow.frame, &p_cuser->frame); |
| 3026 | if (error) return error; |
| 3027 | PUT_USER(error,cnow.overrun, &p_cuser->overrun); |
| 3028 | if (error) return error; |
| 3029 | PUT_USER(error,cnow.parity, &p_cuser->parity); |
| 3030 | if (error) return error; |
| 3031 | PUT_USER(error,cnow.brk, &p_cuser->brk); |
| 3032 | if (error) return error; |
| 3033 | PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun); |
| 3034 | if (error) return error; |
| 3035 | return 0; |
| 3036 | default: |
| 3037 | return -ENOIOCTLCMD; |
| 3038 | } |
| 3039 | return 0; |
| 3040 | } |
| 3041 | |
| 3042 | /* mgsl_set_termios() |
| 3043 | * |
| 3044 | * Set new termios settings |
| 3045 | * |
| 3046 | * Arguments: |
| 3047 | * |
| 3048 | * tty pointer to tty structure |
| 3049 | * termios pointer to buffer to hold returned old termios |
| 3050 | * |
| 3051 | * Return Value: None |
| 3052 | */ |
Alan Cox | 606d099 | 2006-12-08 02:38:45 -0800 | [diff] [blame] | 3053 | static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3054 | { |
| 3055 | struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data; |
| 3056 | unsigned long flags; |
| 3057 | |
| 3058 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3059 | printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__, |
| 3060 | tty->driver->name ); |
| 3061 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3062 | mgsl_change_params(info); |
| 3063 | |
| 3064 | /* Handle transition to B0 status */ |
| 3065 | if (old_termios->c_cflag & CBAUD && |
| 3066 | !(tty->termios->c_cflag & CBAUD)) { |
| 3067 | info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); |
| 3068 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3069 | usc_set_serial_signals(info); |
| 3070 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3071 | } |
| 3072 | |
| 3073 | /* Handle transition away from B0 status */ |
| 3074 | if (!(old_termios->c_cflag & CBAUD) && |
| 3075 | tty->termios->c_cflag & CBAUD) { |
| 3076 | info->serial_signals |= SerialSignal_DTR; |
| 3077 | if (!(tty->termios->c_cflag & CRTSCTS) || |
| 3078 | !test_bit(TTY_THROTTLED, &tty->flags)) { |
| 3079 | info->serial_signals |= SerialSignal_RTS; |
| 3080 | } |
| 3081 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3082 | usc_set_serial_signals(info); |
| 3083 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3084 | } |
| 3085 | |
| 3086 | /* Handle turning off CRTSCTS */ |
| 3087 | if (old_termios->c_cflag & CRTSCTS && |
| 3088 | !(tty->termios->c_cflag & CRTSCTS)) { |
| 3089 | tty->hw_stopped = 0; |
| 3090 | mgsl_start(tty); |
| 3091 | } |
| 3092 | |
| 3093 | } /* end of mgsl_set_termios() */ |
| 3094 | |
| 3095 | /* mgsl_close() |
| 3096 | * |
| 3097 | * Called when port is closed. Wait for remaining data to be |
| 3098 | * sent. Disable port and free resources. |
| 3099 | * |
| 3100 | * Arguments: |
| 3101 | * |
| 3102 | * tty pointer to open tty structure |
| 3103 | * filp pointer to open file object |
| 3104 | * |
| 3105 | * Return Value: None |
| 3106 | */ |
| 3107 | static void mgsl_close(struct tty_struct *tty, struct file * filp) |
| 3108 | { |
| 3109 | struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data; |
| 3110 | |
| 3111 | if (mgsl_paranoia_check(info, tty->name, "mgsl_close")) |
| 3112 | return; |
| 3113 | |
| 3114 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3115 | printk("%s(%d):mgsl_close(%s) entry, count=%d\n", |
| 3116 | __FILE__,__LINE__, info->device_name, info->count); |
| 3117 | |
| 3118 | if (!info->count) |
| 3119 | return; |
| 3120 | |
| 3121 | if (tty_hung_up_p(filp)) |
| 3122 | goto cleanup; |
| 3123 | |
| 3124 | if ((tty->count == 1) && (info->count != 1)) { |
| 3125 | /* |
| 3126 | * tty->count is 1 and the tty structure will be freed. |
| 3127 | * info->count should be one in this case. |
| 3128 | * if it's not, correct it so that the port is shutdown. |
| 3129 | */ |
| 3130 | printk("mgsl_close: bad refcount; tty->count is 1, " |
| 3131 | "info->count is %d\n", info->count); |
| 3132 | info->count = 1; |
| 3133 | } |
| 3134 | |
| 3135 | info->count--; |
| 3136 | |
| 3137 | /* if at least one open remaining, leave hardware active */ |
| 3138 | if (info->count) |
| 3139 | goto cleanup; |
| 3140 | |
| 3141 | info->flags |= ASYNC_CLOSING; |
| 3142 | |
| 3143 | /* set tty->closing to notify line discipline to |
| 3144 | * only process XON/XOFF characters. Only the N_TTY |
| 3145 | * discipline appears to use this (ppp does not). |
| 3146 | */ |
| 3147 | tty->closing = 1; |
| 3148 | |
| 3149 | /* wait for transmit data to clear all layers */ |
| 3150 | |
| 3151 | if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) { |
| 3152 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3153 | printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n", |
| 3154 | __FILE__,__LINE__, info->device_name ); |
| 3155 | tty_wait_until_sent(tty, info->closing_wait); |
| 3156 | } |
| 3157 | |
| 3158 | if (info->flags & ASYNC_INITIALIZED) |
| 3159 | mgsl_wait_until_sent(tty, info->timeout); |
| 3160 | |
Alan Cox | 978e595 | 2008-04-30 00:53:59 -0700 | [diff] [blame] | 3161 | mgsl_flush_buffer(tty); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3162 | |
| 3163 | tty_ldisc_flush(tty); |
| 3164 | |
| 3165 | shutdown(info); |
| 3166 | |
| 3167 | tty->closing = 0; |
| 3168 | info->tty = NULL; |
| 3169 | |
| 3170 | if (info->blocked_open) { |
| 3171 | if (info->close_delay) { |
| 3172 | msleep_interruptible(jiffies_to_msecs(info->close_delay)); |
| 3173 | } |
| 3174 | wake_up_interruptible(&info->open_wait); |
| 3175 | } |
| 3176 | |
| 3177 | info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); |
| 3178 | |
| 3179 | wake_up_interruptible(&info->close_wait); |
| 3180 | |
| 3181 | cleanup: |
| 3182 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3183 | printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__, |
| 3184 | tty->driver->name, info->count); |
| 3185 | |
| 3186 | } /* end of mgsl_close() */ |
| 3187 | |
| 3188 | /* mgsl_wait_until_sent() |
| 3189 | * |
| 3190 | * Wait until the transmitter is empty. |
| 3191 | * |
| 3192 | * Arguments: |
| 3193 | * |
| 3194 | * tty pointer to tty info structure |
| 3195 | * timeout time to wait for send completion |
| 3196 | * |
| 3197 | * Return Value: None |
| 3198 | */ |
| 3199 | static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout) |
| 3200 | { |
| 3201 | struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data; |
| 3202 | unsigned long orig_jiffies, char_time; |
| 3203 | |
| 3204 | if (!info ) |
| 3205 | return; |
| 3206 | |
| 3207 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3208 | printk("%s(%d):mgsl_wait_until_sent(%s) entry\n", |
| 3209 | __FILE__,__LINE__, info->device_name ); |
| 3210 | |
| 3211 | if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent")) |
| 3212 | return; |
| 3213 | |
| 3214 | if (!(info->flags & ASYNC_INITIALIZED)) |
| 3215 | goto exit; |
| 3216 | |
| 3217 | orig_jiffies = jiffies; |
| 3218 | |
| 3219 | /* Set check interval to 1/5 of estimated time to |
| 3220 | * send a character, and make it at least 1. The check |
| 3221 | * interval should also be less than the timeout. |
| 3222 | * Note: use tight timings here to satisfy the NIST-PCTS. |
| 3223 | */ |
Alan Cox | 978e595 | 2008-04-30 00:53:59 -0700 | [diff] [blame] | 3224 | |
| 3225 | lock_kernel(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3226 | if ( info->params.data_rate ) { |
| 3227 | char_time = info->timeout/(32 * 5); |
| 3228 | if (!char_time) |
| 3229 | char_time++; |
| 3230 | } else |
| 3231 | char_time = 1; |
| 3232 | |
| 3233 | if (timeout) |
| 3234 | char_time = min_t(unsigned long, char_time, timeout); |
| 3235 | |
| 3236 | if ( info->params.mode == MGSL_MODE_HDLC || |
| 3237 | info->params.mode == MGSL_MODE_RAW ) { |
| 3238 | while (info->tx_active) { |
| 3239 | msleep_interruptible(jiffies_to_msecs(char_time)); |
| 3240 | if (signal_pending(current)) |
| 3241 | break; |
| 3242 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) |
| 3243 | break; |
| 3244 | } |
| 3245 | } else { |
| 3246 | while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) && |
| 3247 | info->tx_enabled) { |
| 3248 | msleep_interruptible(jiffies_to_msecs(char_time)); |
| 3249 | if (signal_pending(current)) |
| 3250 | break; |
| 3251 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) |
| 3252 | break; |
| 3253 | } |
| 3254 | } |
Alan Cox | 978e595 | 2008-04-30 00:53:59 -0700 | [diff] [blame] | 3255 | unlock_kernel(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3256 | |
| 3257 | exit: |
| 3258 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3259 | printk("%s(%d):mgsl_wait_until_sent(%s) exit\n", |
| 3260 | __FILE__,__LINE__, info->device_name ); |
| 3261 | |
| 3262 | } /* end of mgsl_wait_until_sent() */ |
| 3263 | |
| 3264 | /* mgsl_hangup() |
| 3265 | * |
| 3266 | * Called by tty_hangup() when a hangup is signaled. |
| 3267 | * This is the same as to closing all open files for the port. |
| 3268 | * |
| 3269 | * Arguments: tty pointer to associated tty object |
| 3270 | * Return Value: None |
| 3271 | */ |
| 3272 | static void mgsl_hangup(struct tty_struct *tty) |
| 3273 | { |
| 3274 | struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data; |
| 3275 | |
| 3276 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3277 | printk("%s(%d):mgsl_hangup(%s)\n", |
| 3278 | __FILE__,__LINE__, info->device_name ); |
| 3279 | |
| 3280 | if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup")) |
| 3281 | return; |
| 3282 | |
| 3283 | mgsl_flush_buffer(tty); |
| 3284 | shutdown(info); |
| 3285 | |
| 3286 | info->count = 0; |
| 3287 | info->flags &= ~ASYNC_NORMAL_ACTIVE; |
| 3288 | info->tty = NULL; |
| 3289 | |
| 3290 | wake_up_interruptible(&info->open_wait); |
| 3291 | |
| 3292 | } /* end of mgsl_hangup() */ |
| 3293 | |
| 3294 | /* block_til_ready() |
| 3295 | * |
| 3296 | * Block the current process until the specified port |
| 3297 | * is ready to be opened. |
| 3298 | * |
| 3299 | * Arguments: |
| 3300 | * |
| 3301 | * tty pointer to tty info structure |
| 3302 | * filp pointer to open file object |
| 3303 | * info pointer to device instance data |
| 3304 | * |
| 3305 | * Return Value: 0 if success, otherwise error code |
| 3306 | */ |
| 3307 | static int block_til_ready(struct tty_struct *tty, struct file * filp, |
| 3308 | struct mgsl_struct *info) |
| 3309 | { |
| 3310 | DECLARE_WAITQUEUE(wait, current); |
| 3311 | int retval; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 3312 | bool do_clocal = false; |
| 3313 | bool extra_count = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3314 | unsigned long flags; |
| 3315 | |
| 3316 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3317 | printk("%s(%d):block_til_ready on %s\n", |
| 3318 | __FILE__,__LINE__, tty->driver->name ); |
| 3319 | |
| 3320 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ |
| 3321 | /* nonblock mode is set or port is not enabled */ |
| 3322 | info->flags |= ASYNC_NORMAL_ACTIVE; |
| 3323 | return 0; |
| 3324 | } |
| 3325 | |
| 3326 | if (tty->termios->c_cflag & CLOCAL) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 3327 | do_clocal = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3328 | |
| 3329 | /* Wait for carrier detect and the line to become |
| 3330 | * free (i.e., not in use by the callout). While we are in |
| 3331 | * this loop, info->count is dropped by one, so that |
| 3332 | * mgsl_close() knows when to free things. We restore it upon |
| 3333 | * exit, either normal or abnormal. |
| 3334 | */ |
| 3335 | |
| 3336 | retval = 0; |
| 3337 | add_wait_queue(&info->open_wait, &wait); |
| 3338 | |
| 3339 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3340 | printk("%s(%d):block_til_ready before block on %s count=%d\n", |
| 3341 | __FILE__,__LINE__, tty->driver->name, info->count ); |
| 3342 | |
| 3343 | spin_lock_irqsave(&info->irq_spinlock, flags); |
| 3344 | if (!tty_hung_up_p(filp)) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 3345 | extra_count = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3346 | info->count--; |
| 3347 | } |
| 3348 | spin_unlock_irqrestore(&info->irq_spinlock, flags); |
| 3349 | info->blocked_open++; |
| 3350 | |
| 3351 | while (1) { |
| 3352 | if (tty->termios->c_cflag & CBAUD) { |
| 3353 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3354 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; |
| 3355 | usc_set_serial_signals(info); |
| 3356 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3357 | } |
| 3358 | |
| 3359 | set_current_state(TASK_INTERRUPTIBLE); |
| 3360 | |
| 3361 | if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){ |
| 3362 | retval = (info->flags & ASYNC_HUP_NOTIFY) ? |
| 3363 | -EAGAIN : -ERESTARTSYS; |
| 3364 | break; |
| 3365 | } |
| 3366 | |
| 3367 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3368 | usc_get_serial_signals(info); |
| 3369 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3370 | |
| 3371 | if (!(info->flags & ASYNC_CLOSING) && |
| 3372 | (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) { |
| 3373 | break; |
| 3374 | } |
| 3375 | |
| 3376 | if (signal_pending(current)) { |
| 3377 | retval = -ERESTARTSYS; |
| 3378 | break; |
| 3379 | } |
| 3380 | |
| 3381 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3382 | printk("%s(%d):block_til_ready blocking on %s count=%d\n", |
| 3383 | __FILE__,__LINE__, tty->driver->name, info->count ); |
| 3384 | |
| 3385 | schedule(); |
| 3386 | } |
| 3387 | |
| 3388 | set_current_state(TASK_RUNNING); |
| 3389 | remove_wait_queue(&info->open_wait, &wait); |
| 3390 | |
| 3391 | if (extra_count) |
| 3392 | info->count++; |
| 3393 | info->blocked_open--; |
| 3394 | |
| 3395 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3396 | printk("%s(%d):block_til_ready after blocking on %s count=%d\n", |
| 3397 | __FILE__,__LINE__, tty->driver->name, info->count ); |
| 3398 | |
| 3399 | if (!retval) |
| 3400 | info->flags |= ASYNC_NORMAL_ACTIVE; |
| 3401 | |
| 3402 | return retval; |
| 3403 | |
| 3404 | } /* end of block_til_ready() */ |
| 3405 | |
| 3406 | /* mgsl_open() |
| 3407 | * |
| 3408 | * Called when a port is opened. Init and enable port. |
| 3409 | * Perform serial-specific initialization for the tty structure. |
| 3410 | * |
| 3411 | * Arguments: tty pointer to tty info structure |
| 3412 | * filp associated file pointer |
| 3413 | * |
| 3414 | * Return Value: 0 if success, otherwise error code |
| 3415 | */ |
| 3416 | static int mgsl_open(struct tty_struct *tty, struct file * filp) |
| 3417 | { |
| 3418 | struct mgsl_struct *info; |
| 3419 | int retval, line; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3420 | unsigned long flags; |
| 3421 | |
| 3422 | /* verify range of specified line number */ |
| 3423 | line = tty->index; |
| 3424 | if ((line < 0) || (line >= mgsl_device_count)) { |
| 3425 | printk("%s(%d):mgsl_open with invalid line #%d.\n", |
| 3426 | __FILE__,__LINE__,line); |
| 3427 | return -ENODEV; |
| 3428 | } |
| 3429 | |
| 3430 | /* find the info structure for the specified line */ |
| 3431 | info = mgsl_device_list; |
| 3432 | while(info && info->line != line) |
| 3433 | info = info->next_device; |
| 3434 | if (mgsl_paranoia_check(info, tty->name, "mgsl_open")) |
| 3435 | return -ENODEV; |
| 3436 | |
| 3437 | tty->driver_data = info; |
| 3438 | info->tty = tty; |
| 3439 | |
| 3440 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3441 | printk("%s(%d):mgsl_open(%s), old ref count = %d\n", |
| 3442 | __FILE__,__LINE__,tty->driver->name, info->count); |
| 3443 | |
| 3444 | /* If port is closing, signal caller to try again */ |
| 3445 | if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){ |
| 3446 | if (info->flags & ASYNC_CLOSING) |
| 3447 | interruptible_sleep_on(&info->close_wait); |
| 3448 | retval = ((info->flags & ASYNC_HUP_NOTIFY) ? |
| 3449 | -EAGAIN : -ERESTARTSYS); |
| 3450 | goto cleanup; |
| 3451 | } |
| 3452 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3453 | info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
| 3454 | |
| 3455 | spin_lock_irqsave(&info->netlock, flags); |
| 3456 | if (info->netcount) { |
| 3457 | retval = -EBUSY; |
| 3458 | spin_unlock_irqrestore(&info->netlock, flags); |
| 3459 | goto cleanup; |
| 3460 | } |
| 3461 | info->count++; |
| 3462 | spin_unlock_irqrestore(&info->netlock, flags); |
| 3463 | |
| 3464 | if (info->count == 1) { |
| 3465 | /* 1st open on this device, init hardware */ |
| 3466 | retval = startup(info); |
| 3467 | if (retval < 0) |
| 3468 | goto cleanup; |
| 3469 | } |
| 3470 | |
| 3471 | retval = block_til_ready(tty, filp, info); |
| 3472 | if (retval) { |
| 3473 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3474 | printk("%s(%d):block_til_ready(%s) returned %d\n", |
| 3475 | __FILE__,__LINE__, info->device_name, retval); |
| 3476 | goto cleanup; |
| 3477 | } |
| 3478 | |
| 3479 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 3480 | printk("%s(%d):mgsl_open(%s) success\n", |
| 3481 | __FILE__,__LINE__, info->device_name); |
| 3482 | retval = 0; |
| 3483 | |
| 3484 | cleanup: |
| 3485 | if (retval) { |
| 3486 | if (tty->count == 1) |
| 3487 | info->tty = NULL; /* tty layer will release tty struct */ |
| 3488 | if(info->count) |
| 3489 | info->count--; |
| 3490 | } |
| 3491 | |
| 3492 | return retval; |
| 3493 | |
| 3494 | } /* end of mgsl_open() */ |
| 3495 | |
| 3496 | /* |
| 3497 | * /proc fs routines.... |
| 3498 | */ |
| 3499 | |
| 3500 | static inline int line_info(char *buf, struct mgsl_struct *info) |
| 3501 | { |
| 3502 | char stat_buf[30]; |
| 3503 | int ret; |
| 3504 | unsigned long flags; |
| 3505 | |
| 3506 | if (info->bus_type == MGSL_BUS_TYPE_PCI) { |
| 3507 | ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X", |
| 3508 | info->device_name, info->io_base, info->irq_level, |
| 3509 | info->phys_memory_base, info->phys_lcr_base); |
| 3510 | } else { |
| 3511 | ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d", |
| 3512 | info->device_name, info->io_base, |
| 3513 | info->irq_level, info->dma_level); |
| 3514 | } |
| 3515 | |
| 3516 | /* output current serial signal states */ |
| 3517 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3518 | usc_get_serial_signals(info); |
| 3519 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3520 | |
| 3521 | stat_buf[0] = 0; |
| 3522 | stat_buf[1] = 0; |
| 3523 | if (info->serial_signals & SerialSignal_RTS) |
| 3524 | strcat(stat_buf, "|RTS"); |
| 3525 | if (info->serial_signals & SerialSignal_CTS) |
| 3526 | strcat(stat_buf, "|CTS"); |
| 3527 | if (info->serial_signals & SerialSignal_DTR) |
| 3528 | strcat(stat_buf, "|DTR"); |
| 3529 | if (info->serial_signals & SerialSignal_DSR) |
| 3530 | strcat(stat_buf, "|DSR"); |
| 3531 | if (info->serial_signals & SerialSignal_DCD) |
| 3532 | strcat(stat_buf, "|CD"); |
| 3533 | if (info->serial_signals & SerialSignal_RI) |
| 3534 | strcat(stat_buf, "|RI"); |
| 3535 | |
| 3536 | if (info->params.mode == MGSL_MODE_HDLC || |
| 3537 | info->params.mode == MGSL_MODE_RAW ) { |
| 3538 | ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d", |
| 3539 | info->icount.txok, info->icount.rxok); |
| 3540 | if (info->icount.txunder) |
| 3541 | ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder); |
| 3542 | if (info->icount.txabort) |
| 3543 | ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort); |
| 3544 | if (info->icount.rxshort) |
| 3545 | ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort); |
| 3546 | if (info->icount.rxlong) |
| 3547 | ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong); |
| 3548 | if (info->icount.rxover) |
| 3549 | ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover); |
| 3550 | if (info->icount.rxcrc) |
| 3551 | ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc); |
| 3552 | } else { |
| 3553 | ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d", |
| 3554 | info->icount.tx, info->icount.rx); |
| 3555 | if (info->icount.frame) |
| 3556 | ret += sprintf(buf+ret, " fe:%d", info->icount.frame); |
| 3557 | if (info->icount.parity) |
| 3558 | ret += sprintf(buf+ret, " pe:%d", info->icount.parity); |
| 3559 | if (info->icount.brk) |
| 3560 | ret += sprintf(buf+ret, " brk:%d", info->icount.brk); |
| 3561 | if (info->icount.overrun) |
| 3562 | ret += sprintf(buf+ret, " oe:%d", info->icount.overrun); |
| 3563 | } |
| 3564 | |
| 3565 | /* Append serial signal status to end */ |
| 3566 | ret += sprintf(buf+ret, " %s\n", stat_buf+1); |
| 3567 | |
| 3568 | ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
| 3569 | info->tx_active,info->bh_requested,info->bh_running, |
| 3570 | info->pending_bh); |
| 3571 | |
| 3572 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 3573 | { |
| 3574 | u16 Tcsr = usc_InReg( info, TCSR ); |
| 3575 | u16 Tdmr = usc_InDmaReg( info, TDMR ); |
| 3576 | u16 Ticr = usc_InReg( info, TICR ); |
| 3577 | u16 Rscr = usc_InReg( info, RCSR ); |
| 3578 | u16 Rdmr = usc_InDmaReg( info, RDMR ); |
| 3579 | u16 Ricr = usc_InReg( info, RICR ); |
| 3580 | u16 Icr = usc_InReg( info, ICR ); |
| 3581 | u16 Dccr = usc_InReg( info, DCCR ); |
| 3582 | u16 Tmr = usc_InReg( info, TMR ); |
| 3583 | u16 Tccr = usc_InReg( info, TCCR ); |
| 3584 | u16 Ccar = inw( info->io_base + CCAR ); |
| 3585 | ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n" |
| 3586 | "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n", |
| 3587 | Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar ); |
| 3588 | } |
| 3589 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 3590 | |
| 3591 | return ret; |
| 3592 | |
| 3593 | } /* end of line_info() */ |
| 3594 | |
| 3595 | /* mgsl_read_proc() |
| 3596 | * |
| 3597 | * Called to print information about devices |
| 3598 | * |
| 3599 | * Arguments: |
| 3600 | * page page of memory to hold returned info |
| 3601 | * start |
| 3602 | * off |
| 3603 | * count |
| 3604 | * eof |
| 3605 | * data |
| 3606 | * |
| 3607 | * Return Value: |
| 3608 | */ |
| 3609 | static int mgsl_read_proc(char *page, char **start, off_t off, int count, |
| 3610 | int *eof, void *data) |
| 3611 | { |
| 3612 | int len = 0, l; |
| 3613 | off_t begin = 0; |
| 3614 | struct mgsl_struct *info; |
| 3615 | |
| 3616 | len += sprintf(page, "synclink driver:%s\n", driver_version); |
| 3617 | |
| 3618 | info = mgsl_device_list; |
| 3619 | while( info ) { |
| 3620 | l = line_info(page + len, info); |
| 3621 | len += l; |
| 3622 | if (len+begin > off+count) |
| 3623 | goto done; |
| 3624 | if (len+begin < off) { |
| 3625 | begin += len; |
| 3626 | len = 0; |
| 3627 | } |
| 3628 | info = info->next_device; |
| 3629 | } |
| 3630 | |
| 3631 | *eof = 1; |
| 3632 | done: |
| 3633 | if (off >= len+begin) |
| 3634 | return 0; |
| 3635 | *start = page + (off-begin); |
| 3636 | return ((count < begin+len-off) ? count : begin+len-off); |
| 3637 | |
| 3638 | } /* end of mgsl_read_proc() */ |
| 3639 | |
| 3640 | /* mgsl_allocate_dma_buffers() |
| 3641 | * |
| 3642 | * Allocate and format DMA buffers (ISA adapter) |
| 3643 | * or format shared memory buffers (PCI adapter). |
| 3644 | * |
| 3645 | * Arguments: info pointer to device instance data |
| 3646 | * Return Value: 0 if success, otherwise error |
| 3647 | */ |
| 3648 | static int mgsl_allocate_dma_buffers(struct mgsl_struct *info) |
| 3649 | { |
| 3650 | unsigned short BuffersPerFrame; |
| 3651 | |
| 3652 | info->last_mem_alloc = 0; |
| 3653 | |
| 3654 | /* Calculate the number of DMA buffers necessary to hold the */ |
| 3655 | /* largest allowable frame size. Note: If the max frame size is */ |
| 3656 | /* not an even multiple of the DMA buffer size then we need to */ |
| 3657 | /* round the buffer count per frame up one. */ |
| 3658 | |
| 3659 | BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE); |
| 3660 | if ( info->max_frame_size % DMABUFFERSIZE ) |
| 3661 | BuffersPerFrame++; |
| 3662 | |
| 3663 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 3664 | /* |
| 3665 | * The PCI adapter has 256KBytes of shared memory to use. |
| 3666 | * This is 64 PAGE_SIZE buffers. |
| 3667 | * |
| 3668 | * The first page is used for padding at this time so the |
| 3669 | * buffer list does not begin at offset 0 of the PCI |
| 3670 | * adapter's shared memory. |
| 3671 | * |
| 3672 | * The 2nd page is used for the buffer list. A 4K buffer |
| 3673 | * list can hold 128 DMA_BUFFER structures at 32 bytes |
| 3674 | * each. |
| 3675 | * |
| 3676 | * This leaves 62 4K pages. |
| 3677 | * |
| 3678 | * The next N pages are used for transmit frame(s). We |
| 3679 | * reserve enough 4K page blocks to hold the required |
| 3680 | * number of transmit dma buffers (num_tx_dma_buffers), |
| 3681 | * each of MaxFrameSize size. |
| 3682 | * |
| 3683 | * Of the remaining pages (62-N), determine how many can |
| 3684 | * be used to receive full MaxFrameSize inbound frames |
| 3685 | */ |
| 3686 | info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; |
| 3687 | info->rx_buffer_count = 62 - info->tx_buffer_count; |
| 3688 | } else { |
| 3689 | /* Calculate the number of PAGE_SIZE buffers needed for */ |
| 3690 | /* receive and transmit DMA buffers. */ |
| 3691 | |
| 3692 | |
| 3693 | /* Calculate the number of DMA buffers necessary to */ |
| 3694 | /* hold 7 max size receive frames and one max size transmit frame. */ |
| 3695 | /* The receive buffer count is bumped by one so we avoid an */ |
| 3696 | /* End of List condition if all receive buffers are used when */ |
| 3697 | /* using linked list DMA buffers. */ |
| 3698 | |
| 3699 | info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; |
| 3700 | info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6; |
| 3701 | |
| 3702 | /* |
| 3703 | * limit total TxBuffers & RxBuffers to 62 4K total |
| 3704 | * (ala PCI Allocation) |
| 3705 | */ |
| 3706 | |
| 3707 | if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 ) |
| 3708 | info->rx_buffer_count = 62 - info->tx_buffer_count; |
| 3709 | |
| 3710 | } |
| 3711 | |
| 3712 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 3713 | printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n", |
| 3714 | __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count); |
| 3715 | |
| 3716 | if ( mgsl_alloc_buffer_list_memory( info ) < 0 || |
| 3717 | mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 || |
| 3718 | mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 || |
| 3719 | mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 || |
| 3720 | mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) { |
| 3721 | printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__); |
| 3722 | return -ENOMEM; |
| 3723 | } |
| 3724 | |
| 3725 | mgsl_reset_rx_dma_buffers( info ); |
| 3726 | mgsl_reset_tx_dma_buffers( info ); |
| 3727 | |
| 3728 | return 0; |
| 3729 | |
| 3730 | } /* end of mgsl_allocate_dma_buffers() */ |
| 3731 | |
| 3732 | /* |
| 3733 | * mgsl_alloc_buffer_list_memory() |
| 3734 | * |
| 3735 | * Allocate a common DMA buffer for use as the |
| 3736 | * receive and transmit buffer lists. |
| 3737 | * |
| 3738 | * A buffer list is a set of buffer entries where each entry contains |
| 3739 | * a pointer to an actual buffer and a pointer to the next buffer entry |
| 3740 | * (plus some other info about the buffer). |
| 3741 | * |
| 3742 | * The buffer entries for a list are built to form a circular list so |
| 3743 | * that when the entire list has been traversed you start back at the |
| 3744 | * beginning. |
| 3745 | * |
| 3746 | * This function allocates memory for just the buffer entries. |
| 3747 | * The links (pointer to next entry) are filled in with the physical |
| 3748 | * address of the next entry so the adapter can navigate the list |
| 3749 | * using bus master DMA. The pointers to the actual buffers are filled |
| 3750 | * out later when the actual buffers are allocated. |
| 3751 | * |
| 3752 | * Arguments: info pointer to device instance data |
| 3753 | * Return Value: 0 if success, otherwise error |
| 3754 | */ |
| 3755 | static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info ) |
| 3756 | { |
| 3757 | unsigned int i; |
| 3758 | |
| 3759 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 3760 | /* PCI adapter uses shared memory. */ |
| 3761 | info->buffer_list = info->memory_base + info->last_mem_alloc; |
| 3762 | info->buffer_list_phys = info->last_mem_alloc; |
| 3763 | info->last_mem_alloc += BUFFERLISTSIZE; |
| 3764 | } else { |
| 3765 | /* ISA adapter uses system memory. */ |
| 3766 | /* The buffer lists are allocated as a common buffer that both */ |
| 3767 | /* the processor and adapter can access. This allows the driver to */ |
| 3768 | /* inspect portions of the buffer while other portions are being */ |
| 3769 | /* updated by the adapter using Bus Master DMA. */ |
| 3770 | |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3771 | info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL); |
| 3772 | if (info->buffer_list == NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3773 | return -ENOMEM; |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3774 | info->buffer_list_phys = (u32)(info->buffer_list_dma_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3775 | } |
| 3776 | |
| 3777 | /* We got the memory for the buffer entry lists. */ |
| 3778 | /* Initialize the memory block to all zeros. */ |
| 3779 | memset( info->buffer_list, 0, BUFFERLISTSIZE ); |
| 3780 | |
| 3781 | /* Save virtual address pointers to the receive and */ |
| 3782 | /* transmit buffer lists. (Receive 1st). These pointers will */ |
| 3783 | /* be used by the processor to access the lists. */ |
| 3784 | info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list; |
| 3785 | info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list; |
| 3786 | info->tx_buffer_list += info->rx_buffer_count; |
| 3787 | |
| 3788 | /* |
| 3789 | * Build the links for the buffer entry lists such that |
| 3790 | * two circular lists are built. (Transmit and Receive). |
| 3791 | * |
| 3792 | * Note: the links are physical addresses |
| 3793 | * which are read by the adapter to determine the next |
| 3794 | * buffer entry to use. |
| 3795 | */ |
| 3796 | |
| 3797 | for ( i = 0; i < info->rx_buffer_count; i++ ) { |
| 3798 | /* calculate and store physical address of this buffer entry */ |
| 3799 | info->rx_buffer_list[i].phys_entry = |
| 3800 | info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY)); |
| 3801 | |
| 3802 | /* calculate and store physical address of */ |
| 3803 | /* next entry in cirular list of entries */ |
| 3804 | |
| 3805 | info->rx_buffer_list[i].link = info->buffer_list_phys; |
| 3806 | |
| 3807 | if ( i < info->rx_buffer_count - 1 ) |
| 3808 | info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY); |
| 3809 | } |
| 3810 | |
| 3811 | for ( i = 0; i < info->tx_buffer_count; i++ ) { |
| 3812 | /* calculate and store physical address of this buffer entry */ |
| 3813 | info->tx_buffer_list[i].phys_entry = info->buffer_list_phys + |
| 3814 | ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY)); |
| 3815 | |
| 3816 | /* calculate and store physical address of */ |
| 3817 | /* next entry in cirular list of entries */ |
| 3818 | |
| 3819 | info->tx_buffer_list[i].link = info->buffer_list_phys + |
| 3820 | info->rx_buffer_count * sizeof(DMABUFFERENTRY); |
| 3821 | |
| 3822 | if ( i < info->tx_buffer_count - 1 ) |
| 3823 | info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY); |
| 3824 | } |
| 3825 | |
| 3826 | return 0; |
| 3827 | |
| 3828 | } /* end of mgsl_alloc_buffer_list_memory() */ |
| 3829 | |
| 3830 | /* Free DMA buffers allocated for use as the |
| 3831 | * receive and transmit buffer lists. |
| 3832 | * Warning: |
| 3833 | * |
| 3834 | * The data transfer buffers associated with the buffer list |
| 3835 | * MUST be freed before freeing the buffer list itself because |
| 3836 | * the buffer list contains the information necessary to free |
| 3837 | * the individual buffers! |
| 3838 | */ |
| 3839 | static void mgsl_free_buffer_list_memory( struct mgsl_struct *info ) |
| 3840 | { |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3841 | if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI) |
| 3842 | dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3843 | |
| 3844 | info->buffer_list = NULL; |
| 3845 | info->rx_buffer_list = NULL; |
| 3846 | info->tx_buffer_list = NULL; |
| 3847 | |
| 3848 | } /* end of mgsl_free_buffer_list_memory() */ |
| 3849 | |
| 3850 | /* |
| 3851 | * mgsl_alloc_frame_memory() |
| 3852 | * |
| 3853 | * Allocate the frame DMA buffers used by the specified buffer list. |
| 3854 | * Each DMA buffer will be one memory page in size. This is necessary |
| 3855 | * because memory can fragment enough that it may be impossible |
| 3856 | * contiguous pages. |
| 3857 | * |
| 3858 | * Arguments: |
| 3859 | * |
| 3860 | * info pointer to device instance data |
| 3861 | * BufferList pointer to list of buffer entries |
| 3862 | * Buffercount count of buffer entries in buffer list |
| 3863 | * |
| 3864 | * Return Value: 0 if success, otherwise -ENOMEM |
| 3865 | */ |
| 3866 | static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount) |
| 3867 | { |
| 3868 | int i; |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3869 | u32 phys_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3870 | |
| 3871 | /* Allocate page sized buffers for the receive buffer list */ |
| 3872 | |
| 3873 | for ( i = 0; i < Buffercount; i++ ) { |
| 3874 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 3875 | /* PCI adapter uses shared memory buffers. */ |
| 3876 | BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc; |
| 3877 | phys_addr = info->last_mem_alloc; |
| 3878 | info->last_mem_alloc += DMABUFFERSIZE; |
| 3879 | } else { |
| 3880 | /* ISA adapter uses system memory. */ |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3881 | BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL); |
| 3882 | if (BufferList[i].virt_addr == NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3883 | return -ENOMEM; |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3884 | phys_addr = (u32)(BufferList[i].dma_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3885 | } |
| 3886 | BufferList[i].phys_addr = phys_addr; |
| 3887 | } |
| 3888 | |
| 3889 | return 0; |
| 3890 | |
| 3891 | } /* end of mgsl_alloc_frame_memory() */ |
| 3892 | |
| 3893 | /* |
| 3894 | * mgsl_free_frame_memory() |
| 3895 | * |
| 3896 | * Free the buffers associated with |
| 3897 | * each buffer entry of a buffer list. |
| 3898 | * |
| 3899 | * Arguments: |
| 3900 | * |
| 3901 | * info pointer to device instance data |
| 3902 | * BufferList pointer to list of buffer entries |
| 3903 | * Buffercount count of buffer entries in buffer list |
| 3904 | * |
| 3905 | * Return Value: None |
| 3906 | */ |
| 3907 | static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount) |
| 3908 | { |
| 3909 | int i; |
| 3910 | |
| 3911 | if ( BufferList ) { |
| 3912 | for ( i = 0 ; i < Buffercount ; i++ ) { |
| 3913 | if ( BufferList[i].virt_addr ) { |
| 3914 | if ( info->bus_type != MGSL_BUS_TYPE_PCI ) |
Paul Fulghum | 0ff1b2c | 2005-11-13 16:07:19 -0800 | [diff] [blame] | 3915 | dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3916 | BufferList[i].virt_addr = NULL; |
| 3917 | } |
| 3918 | } |
| 3919 | } |
| 3920 | |
| 3921 | } /* end of mgsl_free_frame_memory() */ |
| 3922 | |
| 3923 | /* mgsl_free_dma_buffers() |
| 3924 | * |
| 3925 | * Free DMA buffers |
| 3926 | * |
| 3927 | * Arguments: info pointer to device instance data |
| 3928 | * Return Value: None |
| 3929 | */ |
| 3930 | static void mgsl_free_dma_buffers( struct mgsl_struct *info ) |
| 3931 | { |
| 3932 | mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count ); |
| 3933 | mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count ); |
| 3934 | mgsl_free_buffer_list_memory( info ); |
| 3935 | |
| 3936 | } /* end of mgsl_free_dma_buffers() */ |
| 3937 | |
| 3938 | |
| 3939 | /* |
| 3940 | * mgsl_alloc_intermediate_rxbuffer_memory() |
| 3941 | * |
| 3942 | * Allocate a buffer large enough to hold max_frame_size. This buffer |
| 3943 | * is used to pass an assembled frame to the line discipline. |
| 3944 | * |
| 3945 | * Arguments: |
| 3946 | * |
| 3947 | * info pointer to device instance data |
| 3948 | * |
| 3949 | * Return Value: 0 if success, otherwise -ENOMEM |
| 3950 | */ |
| 3951 | static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info) |
| 3952 | { |
| 3953 | info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA); |
| 3954 | if ( info->intermediate_rxbuffer == NULL ) |
| 3955 | return -ENOMEM; |
| 3956 | |
| 3957 | return 0; |
| 3958 | |
| 3959 | } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */ |
| 3960 | |
| 3961 | /* |
| 3962 | * mgsl_free_intermediate_rxbuffer_memory() |
| 3963 | * |
| 3964 | * |
| 3965 | * Arguments: |
| 3966 | * |
| 3967 | * info pointer to device instance data |
| 3968 | * |
| 3969 | * Return Value: None |
| 3970 | */ |
| 3971 | static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info) |
| 3972 | { |
Jesper Juhl | 735d566 | 2005-11-07 01:01:29 -0800 | [diff] [blame] | 3973 | kfree(info->intermediate_rxbuffer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3974 | info->intermediate_rxbuffer = NULL; |
| 3975 | |
| 3976 | } /* end of mgsl_free_intermediate_rxbuffer_memory() */ |
| 3977 | |
| 3978 | /* |
| 3979 | * mgsl_alloc_intermediate_txbuffer_memory() |
| 3980 | * |
| 3981 | * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size. |
| 3982 | * This buffer is used to load transmit frames into the adapter's dma transfer |
| 3983 | * buffers when there is sufficient space. |
| 3984 | * |
| 3985 | * Arguments: |
| 3986 | * |
| 3987 | * info pointer to device instance data |
| 3988 | * |
| 3989 | * Return Value: 0 if success, otherwise -ENOMEM |
| 3990 | */ |
| 3991 | static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info) |
| 3992 | { |
| 3993 | int i; |
| 3994 | |
| 3995 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 3996 | printk("%s %s(%d) allocating %d tx holding buffers\n", |
| 3997 | info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers); |
| 3998 | |
| 3999 | memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers)); |
| 4000 | |
| 4001 | for ( i=0; i<info->num_tx_holding_buffers; ++i) { |
| 4002 | info->tx_holding_buffers[i].buffer = |
| 4003 | kmalloc(info->max_frame_size, GFP_KERNEL); |
Amit Choudhary | d9a2f4a | 2007-05-08 00:26:13 -0700 | [diff] [blame] | 4004 | if (info->tx_holding_buffers[i].buffer == NULL) { |
| 4005 | for (--i; i >= 0; i--) { |
| 4006 | kfree(info->tx_holding_buffers[i].buffer); |
| 4007 | info->tx_holding_buffers[i].buffer = NULL; |
| 4008 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4009 | return -ENOMEM; |
Amit Choudhary | d9a2f4a | 2007-05-08 00:26:13 -0700 | [diff] [blame] | 4010 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4011 | } |
| 4012 | |
| 4013 | return 0; |
| 4014 | |
| 4015 | } /* end of mgsl_alloc_intermediate_txbuffer_memory() */ |
| 4016 | |
| 4017 | /* |
| 4018 | * mgsl_free_intermediate_txbuffer_memory() |
| 4019 | * |
| 4020 | * |
| 4021 | * Arguments: |
| 4022 | * |
| 4023 | * info pointer to device instance data |
| 4024 | * |
| 4025 | * Return Value: None |
| 4026 | */ |
| 4027 | static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info) |
| 4028 | { |
| 4029 | int i; |
| 4030 | |
| 4031 | for ( i=0; i<info->num_tx_holding_buffers; ++i ) { |
Jesper Juhl | 735d566 | 2005-11-07 01:01:29 -0800 | [diff] [blame] | 4032 | kfree(info->tx_holding_buffers[i].buffer); |
| 4033 | info->tx_holding_buffers[i].buffer = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4034 | } |
| 4035 | |
| 4036 | info->get_tx_holding_index = 0; |
| 4037 | info->put_tx_holding_index = 0; |
| 4038 | info->tx_holding_count = 0; |
| 4039 | |
| 4040 | } /* end of mgsl_free_intermediate_txbuffer_memory() */ |
| 4041 | |
| 4042 | |
| 4043 | /* |
| 4044 | * load_next_tx_holding_buffer() |
| 4045 | * |
| 4046 | * attempts to load the next buffered tx request into the |
| 4047 | * tx dma buffers |
| 4048 | * |
| 4049 | * Arguments: |
| 4050 | * |
| 4051 | * info pointer to device instance data |
| 4052 | * |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4053 | * Return Value: true if next buffered tx request loaded |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4054 | * into adapter's tx dma buffer, |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4055 | * false otherwise |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4056 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4057 | static bool load_next_tx_holding_buffer(struct mgsl_struct *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4058 | { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4059 | bool ret = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4060 | |
| 4061 | if ( info->tx_holding_count ) { |
| 4062 | /* determine if we have enough tx dma buffers |
| 4063 | * to accommodate the next tx frame |
| 4064 | */ |
| 4065 | struct tx_holding_buffer *ptx = |
| 4066 | &info->tx_holding_buffers[info->get_tx_holding_index]; |
| 4067 | int num_free = num_free_tx_dma_buffers(info); |
| 4068 | int num_needed = ptx->buffer_size / DMABUFFERSIZE; |
| 4069 | if ( ptx->buffer_size % DMABUFFERSIZE ) |
| 4070 | ++num_needed; |
| 4071 | |
| 4072 | if (num_needed <= num_free) { |
| 4073 | info->xmit_cnt = ptx->buffer_size; |
| 4074 | mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size); |
| 4075 | |
| 4076 | --info->tx_holding_count; |
| 4077 | if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers) |
| 4078 | info->get_tx_holding_index=0; |
| 4079 | |
| 4080 | /* restart transmit timer */ |
| 4081 | mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000)); |
| 4082 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4083 | ret = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4084 | } |
| 4085 | } |
| 4086 | |
| 4087 | return ret; |
| 4088 | } |
| 4089 | |
| 4090 | /* |
| 4091 | * save_tx_buffer_request() |
| 4092 | * |
| 4093 | * attempt to store transmit frame request for later transmission |
| 4094 | * |
| 4095 | * Arguments: |
| 4096 | * |
| 4097 | * info pointer to device instance data |
| 4098 | * Buffer pointer to buffer containing frame to load |
| 4099 | * BufferSize size in bytes of frame in Buffer |
| 4100 | * |
| 4101 | * Return Value: 1 if able to store, 0 otherwise |
| 4102 | */ |
| 4103 | static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize) |
| 4104 | { |
| 4105 | struct tx_holding_buffer *ptx; |
| 4106 | |
| 4107 | if ( info->tx_holding_count >= info->num_tx_holding_buffers ) { |
| 4108 | return 0; /* all buffers in use */ |
| 4109 | } |
| 4110 | |
| 4111 | ptx = &info->tx_holding_buffers[info->put_tx_holding_index]; |
| 4112 | ptx->buffer_size = BufferSize; |
| 4113 | memcpy( ptx->buffer, Buffer, BufferSize); |
| 4114 | |
| 4115 | ++info->tx_holding_count; |
| 4116 | if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers) |
| 4117 | info->put_tx_holding_index=0; |
| 4118 | |
| 4119 | return 1; |
| 4120 | } |
| 4121 | |
| 4122 | static int mgsl_claim_resources(struct mgsl_struct *info) |
| 4123 | { |
| 4124 | if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) { |
| 4125 | printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n", |
| 4126 | __FILE__,__LINE__,info->device_name, info->io_base); |
| 4127 | return -ENODEV; |
| 4128 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4129 | info->io_addr_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4130 | |
| 4131 | if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags, |
| 4132 | info->device_name, info ) < 0 ) { |
| 4133 | printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n", |
| 4134 | __FILE__,__LINE__,info->device_name, info->irq_level ); |
| 4135 | goto errout; |
| 4136 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4137 | info->irq_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4138 | |
| 4139 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 4140 | if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) { |
| 4141 | printk( "%s(%d):mem addr conflict device %s Addr=%08X\n", |
| 4142 | __FILE__,__LINE__,info->device_name, info->phys_memory_base); |
| 4143 | goto errout; |
| 4144 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4145 | info->shared_mem_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4146 | if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) { |
| 4147 | printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n", |
| 4148 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset); |
| 4149 | goto errout; |
| 4150 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4151 | info->lcr_mem_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4152 | |
Alan Cox | 24cb233 | 2008-04-30 00:54:19 -0700 | [diff] [blame] | 4153 | info->memory_base = ioremap_nocache(info->phys_memory_base, |
| 4154 | 0x40000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4155 | if (!info->memory_base) { |
| 4156 | printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n", |
| 4157 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); |
| 4158 | goto errout; |
| 4159 | } |
| 4160 | |
| 4161 | if ( !mgsl_memory_test(info) ) { |
| 4162 | printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n", |
| 4163 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); |
| 4164 | goto errout; |
| 4165 | } |
| 4166 | |
Alan Cox | 24cb233 | 2008-04-30 00:54:19 -0700 | [diff] [blame] | 4167 | info->lcr_base = ioremap_nocache(info->phys_lcr_base, |
| 4168 | PAGE_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4169 | if (!info->lcr_base) { |
| 4170 | printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n", |
| 4171 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); |
| 4172 | goto errout; |
| 4173 | } |
Alan Cox | 24cb233 | 2008-04-30 00:54:19 -0700 | [diff] [blame] | 4174 | info->lcr_base += info->lcr_offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4175 | |
| 4176 | } else { |
| 4177 | /* claim DMA channel */ |
| 4178 | |
| 4179 | if (request_dma(info->dma_level,info->device_name) < 0){ |
| 4180 | printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n", |
| 4181 | __FILE__,__LINE__,info->device_name, info->dma_level ); |
| 4182 | mgsl_release_resources( info ); |
| 4183 | return -ENODEV; |
| 4184 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4185 | info->dma_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4186 | |
| 4187 | /* ISA adapter uses bus master DMA */ |
| 4188 | set_dma_mode(info->dma_level,DMA_MODE_CASCADE); |
| 4189 | enable_dma(info->dma_level); |
| 4190 | } |
| 4191 | |
| 4192 | if ( mgsl_allocate_dma_buffers(info) < 0 ) { |
| 4193 | printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n", |
| 4194 | __FILE__,__LINE__,info->device_name, info->dma_level ); |
| 4195 | goto errout; |
| 4196 | } |
| 4197 | |
| 4198 | return 0; |
| 4199 | errout: |
| 4200 | mgsl_release_resources(info); |
| 4201 | return -ENODEV; |
| 4202 | |
| 4203 | } /* end of mgsl_claim_resources() */ |
| 4204 | |
| 4205 | static void mgsl_release_resources(struct mgsl_struct *info) |
| 4206 | { |
| 4207 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 4208 | printk( "%s(%d):mgsl_release_resources(%s) entry\n", |
| 4209 | __FILE__,__LINE__,info->device_name ); |
| 4210 | |
| 4211 | if ( info->irq_requested ) { |
| 4212 | free_irq(info->irq_level, info); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4213 | info->irq_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4214 | } |
| 4215 | if ( info->dma_requested ) { |
| 4216 | disable_dma(info->dma_level); |
| 4217 | free_dma(info->dma_level); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4218 | info->dma_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4219 | } |
| 4220 | mgsl_free_dma_buffers(info); |
| 4221 | mgsl_free_intermediate_rxbuffer_memory(info); |
| 4222 | mgsl_free_intermediate_txbuffer_memory(info); |
| 4223 | |
| 4224 | if ( info->io_addr_requested ) { |
| 4225 | release_region(info->io_base,info->io_addr_size); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4226 | info->io_addr_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4227 | } |
| 4228 | if ( info->shared_mem_requested ) { |
| 4229 | release_mem_region(info->phys_memory_base,0x40000); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4230 | info->shared_mem_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4231 | } |
| 4232 | if ( info->lcr_mem_requested ) { |
| 4233 | release_mem_region(info->phys_lcr_base + info->lcr_offset,128); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4234 | info->lcr_mem_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4235 | } |
| 4236 | if (info->memory_base){ |
| 4237 | iounmap(info->memory_base); |
| 4238 | info->memory_base = NULL; |
| 4239 | } |
| 4240 | if (info->lcr_base){ |
| 4241 | iounmap(info->lcr_base - info->lcr_offset); |
| 4242 | info->lcr_base = NULL; |
| 4243 | } |
| 4244 | |
| 4245 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 4246 | printk( "%s(%d):mgsl_release_resources(%s) exit\n", |
| 4247 | __FILE__,__LINE__,info->device_name ); |
| 4248 | |
| 4249 | } /* end of mgsl_release_resources() */ |
| 4250 | |
| 4251 | /* mgsl_add_device() |
| 4252 | * |
| 4253 | * Add the specified device instance data structure to the |
| 4254 | * global linked list of devices and increment the device count. |
| 4255 | * |
| 4256 | * Arguments: info pointer to device instance data |
| 4257 | * Return Value: None |
| 4258 | */ |
| 4259 | static void mgsl_add_device( struct mgsl_struct *info ) |
| 4260 | { |
| 4261 | info->next_device = NULL; |
| 4262 | info->line = mgsl_device_count; |
| 4263 | sprintf(info->device_name,"ttySL%d",info->line); |
| 4264 | |
| 4265 | if (info->line < MAX_TOTAL_DEVICES) { |
| 4266 | if (maxframe[info->line]) |
| 4267 | info->max_frame_size = maxframe[info->line]; |
| 4268 | info->dosyncppp = dosyncppp[info->line]; |
| 4269 | |
| 4270 | if (txdmabufs[info->line]) { |
| 4271 | info->num_tx_dma_buffers = txdmabufs[info->line]; |
| 4272 | if (info->num_tx_dma_buffers < 1) |
| 4273 | info->num_tx_dma_buffers = 1; |
| 4274 | } |
| 4275 | |
| 4276 | if (txholdbufs[info->line]) { |
| 4277 | info->num_tx_holding_buffers = txholdbufs[info->line]; |
| 4278 | if (info->num_tx_holding_buffers < 1) |
| 4279 | info->num_tx_holding_buffers = 1; |
| 4280 | else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS) |
| 4281 | info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS; |
| 4282 | } |
| 4283 | } |
| 4284 | |
| 4285 | mgsl_device_count++; |
| 4286 | |
| 4287 | if ( !mgsl_device_list ) |
| 4288 | mgsl_device_list = info; |
| 4289 | else { |
| 4290 | struct mgsl_struct *current_dev = mgsl_device_list; |
| 4291 | while( current_dev->next_device ) |
| 4292 | current_dev = current_dev->next_device; |
| 4293 | current_dev->next_device = info; |
| 4294 | } |
| 4295 | |
| 4296 | if ( info->max_frame_size < 4096 ) |
| 4297 | info->max_frame_size = 4096; |
| 4298 | else if ( info->max_frame_size > 65535 ) |
| 4299 | info->max_frame_size = 65535; |
| 4300 | |
| 4301 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 4302 | printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n", |
| 4303 | info->hw_version + 1, info->device_name, info->io_base, info->irq_level, |
| 4304 | info->phys_memory_base, info->phys_lcr_base, |
| 4305 | info->max_frame_size ); |
| 4306 | } else { |
| 4307 | printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n", |
| 4308 | info->device_name, info->io_base, info->irq_level, info->dma_level, |
| 4309 | info->max_frame_size ); |
| 4310 | } |
| 4311 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 4312 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4313 | hdlcdev_init(info); |
| 4314 | #endif |
| 4315 | |
| 4316 | } /* end of mgsl_add_device() */ |
| 4317 | |
| 4318 | /* mgsl_allocate_device() |
| 4319 | * |
| 4320 | * Allocate and initialize a device instance structure |
| 4321 | * |
| 4322 | * Arguments: none |
| 4323 | * Return Value: pointer to mgsl_struct if success, otherwise NULL |
| 4324 | */ |
| 4325 | static struct mgsl_struct* mgsl_allocate_device(void) |
| 4326 | { |
| 4327 | struct mgsl_struct *info; |
| 4328 | |
Yoann Padioleau | dd00cc4 | 2007-07-19 01:49:03 -0700 | [diff] [blame] | 4329 | info = kzalloc(sizeof(struct mgsl_struct), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4330 | GFP_KERNEL); |
| 4331 | |
| 4332 | if (!info) { |
| 4333 | printk("Error can't allocate device instance data\n"); |
| 4334 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4335 | info->magic = MGSL_MAGIC; |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 4336 | INIT_WORK(&info->task, mgsl_bh_handler); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4337 | info->max_frame_size = 4096; |
| 4338 | info->close_delay = 5*HZ/10; |
| 4339 | info->closing_wait = 30*HZ; |
| 4340 | init_waitqueue_head(&info->open_wait); |
| 4341 | init_waitqueue_head(&info->close_wait); |
| 4342 | init_waitqueue_head(&info->status_event_wait_q); |
| 4343 | init_waitqueue_head(&info->event_wait_q); |
| 4344 | spin_lock_init(&info->irq_spinlock); |
| 4345 | spin_lock_init(&info->netlock); |
| 4346 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); |
| 4347 | info->idle_mode = HDLC_TXIDLE_FLAGS; |
| 4348 | info->num_tx_dma_buffers = 1; |
| 4349 | info->num_tx_holding_buffers = 0; |
| 4350 | } |
| 4351 | |
| 4352 | return info; |
| 4353 | |
| 4354 | } /* end of mgsl_allocate_device()*/ |
| 4355 | |
Jeff Dike | b68e31d | 2006-10-02 02:17:18 -0700 | [diff] [blame] | 4356 | static const struct tty_operations mgsl_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4357 | .open = mgsl_open, |
| 4358 | .close = mgsl_close, |
| 4359 | .write = mgsl_write, |
| 4360 | .put_char = mgsl_put_char, |
| 4361 | .flush_chars = mgsl_flush_chars, |
| 4362 | .write_room = mgsl_write_room, |
| 4363 | .chars_in_buffer = mgsl_chars_in_buffer, |
| 4364 | .flush_buffer = mgsl_flush_buffer, |
| 4365 | .ioctl = mgsl_ioctl, |
| 4366 | .throttle = mgsl_throttle, |
| 4367 | .unthrottle = mgsl_unthrottle, |
| 4368 | .send_xchar = mgsl_send_xchar, |
| 4369 | .break_ctl = mgsl_break, |
| 4370 | .wait_until_sent = mgsl_wait_until_sent, |
| 4371 | .read_proc = mgsl_read_proc, |
| 4372 | .set_termios = mgsl_set_termios, |
| 4373 | .stop = mgsl_stop, |
| 4374 | .start = mgsl_start, |
| 4375 | .hangup = mgsl_hangup, |
| 4376 | .tiocmget = tiocmget, |
| 4377 | .tiocmset = tiocmset, |
| 4378 | }; |
| 4379 | |
| 4380 | /* |
| 4381 | * perform tty device initialization |
| 4382 | */ |
| 4383 | static int mgsl_init_tty(void) |
| 4384 | { |
| 4385 | int rc; |
| 4386 | |
| 4387 | serial_driver = alloc_tty_driver(128); |
| 4388 | if (!serial_driver) |
| 4389 | return -ENOMEM; |
| 4390 | |
| 4391 | serial_driver->owner = THIS_MODULE; |
| 4392 | serial_driver->driver_name = "synclink"; |
| 4393 | serial_driver->name = "ttySL"; |
| 4394 | serial_driver->major = ttymajor; |
| 4395 | serial_driver->minor_start = 64; |
| 4396 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; |
| 4397 | serial_driver->subtype = SERIAL_TYPE_NORMAL; |
| 4398 | serial_driver->init_termios = tty_std_termios; |
| 4399 | serial_driver->init_termios.c_cflag = |
| 4400 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; |
Alan Cox | 606d099 | 2006-12-08 02:38:45 -0800 | [diff] [blame] | 4401 | serial_driver->init_termios.c_ispeed = 9600; |
| 4402 | serial_driver->init_termios.c_ospeed = 9600; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4403 | serial_driver->flags = TTY_DRIVER_REAL_RAW; |
| 4404 | tty_set_operations(serial_driver, &mgsl_ops); |
| 4405 | if ((rc = tty_register_driver(serial_driver)) < 0) { |
| 4406 | printk("%s(%d):Couldn't register serial driver\n", |
| 4407 | __FILE__,__LINE__); |
| 4408 | put_tty_driver(serial_driver); |
| 4409 | serial_driver = NULL; |
| 4410 | return rc; |
| 4411 | } |
| 4412 | |
| 4413 | printk("%s %s, tty major#%d\n", |
| 4414 | driver_name, driver_version, |
| 4415 | serial_driver->major); |
| 4416 | return 0; |
| 4417 | } |
| 4418 | |
| 4419 | /* enumerate user specified ISA adapters |
| 4420 | */ |
| 4421 | static void mgsl_enum_isa_devices(void) |
| 4422 | { |
| 4423 | struct mgsl_struct *info; |
| 4424 | int i; |
| 4425 | |
| 4426 | /* Check for user specified ISA devices */ |
| 4427 | |
| 4428 | for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){ |
| 4429 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 4430 | printk("ISA device specified io=%04X,irq=%d,dma=%d\n", |
| 4431 | io[i], irq[i], dma[i] ); |
| 4432 | |
| 4433 | info = mgsl_allocate_device(); |
| 4434 | if ( !info ) { |
| 4435 | /* error allocating device instance data */ |
| 4436 | if ( debug_level >= DEBUG_LEVEL_ERROR ) |
| 4437 | printk( "can't allocate device instance data.\n"); |
| 4438 | continue; |
| 4439 | } |
| 4440 | |
| 4441 | /* Copy user configuration info to device instance data */ |
| 4442 | info->io_base = (unsigned int)io[i]; |
| 4443 | info->irq_level = (unsigned int)irq[i]; |
| 4444 | info->irq_level = irq_canonicalize(info->irq_level); |
| 4445 | info->dma_level = (unsigned int)dma[i]; |
| 4446 | info->bus_type = MGSL_BUS_TYPE_ISA; |
| 4447 | info->io_addr_size = 16; |
| 4448 | info->irq_flags = 0; |
| 4449 | |
| 4450 | mgsl_add_device( info ); |
| 4451 | } |
| 4452 | } |
| 4453 | |
| 4454 | static void synclink_cleanup(void) |
| 4455 | { |
| 4456 | int rc; |
| 4457 | struct mgsl_struct *info; |
| 4458 | struct mgsl_struct *tmp; |
| 4459 | |
| 4460 | printk("Unloading %s: %s\n", driver_name, driver_version); |
| 4461 | |
| 4462 | if (serial_driver) { |
| 4463 | if ((rc = tty_unregister_driver(serial_driver))) |
| 4464 | printk("%s(%d) failed to unregister tty driver err=%d\n", |
| 4465 | __FILE__,__LINE__,rc); |
| 4466 | put_tty_driver(serial_driver); |
| 4467 | } |
| 4468 | |
| 4469 | info = mgsl_device_list; |
| 4470 | while(info) { |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 4471 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4472 | hdlcdev_exit(info); |
| 4473 | #endif |
| 4474 | mgsl_release_resources(info); |
| 4475 | tmp = info; |
| 4476 | info = info->next_device; |
| 4477 | kfree(tmp); |
| 4478 | } |
| 4479 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4480 | if (pci_registered) |
| 4481 | pci_unregister_driver(&synclink_pci_driver); |
| 4482 | } |
| 4483 | |
| 4484 | static int __init synclink_init(void) |
| 4485 | { |
| 4486 | int rc; |
| 4487 | |
| 4488 | if (break_on_load) { |
| 4489 | mgsl_get_text_ptr(); |
| 4490 | BREAKPOINT(); |
| 4491 | } |
| 4492 | |
| 4493 | printk("%s %s\n", driver_name, driver_version); |
| 4494 | |
| 4495 | mgsl_enum_isa_devices(); |
| 4496 | if ((rc = pci_register_driver(&synclink_pci_driver)) < 0) |
| 4497 | printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); |
| 4498 | else |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4499 | pci_registered = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4500 | |
| 4501 | if ((rc = mgsl_init_tty()) < 0) |
| 4502 | goto error; |
| 4503 | |
| 4504 | return 0; |
| 4505 | |
| 4506 | error: |
| 4507 | synclink_cleanup(); |
| 4508 | return rc; |
| 4509 | } |
| 4510 | |
| 4511 | static void __exit synclink_exit(void) |
| 4512 | { |
| 4513 | synclink_cleanup(); |
| 4514 | } |
| 4515 | |
| 4516 | module_init(synclink_init); |
| 4517 | module_exit(synclink_exit); |
| 4518 | |
| 4519 | /* |
| 4520 | * usc_RTCmd() |
| 4521 | * |
| 4522 | * Issue a USC Receive/Transmit command to the |
| 4523 | * Channel Command/Address Register (CCAR). |
| 4524 | * |
| 4525 | * Notes: |
| 4526 | * |
| 4527 | * The command is encoded in the most significant 5 bits <15..11> |
| 4528 | * of the CCAR value. Bits <10..7> of the CCAR must be preserved |
| 4529 | * and Bits <6..0> must be written as zeros. |
| 4530 | * |
| 4531 | * Arguments: |
| 4532 | * |
| 4533 | * info pointer to device information structure |
| 4534 | * Cmd command mask (use symbolic macros) |
| 4535 | * |
| 4536 | * Return Value: |
| 4537 | * |
| 4538 | * None |
| 4539 | */ |
| 4540 | static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd ) |
| 4541 | { |
| 4542 | /* output command to CCAR in bits <15..11> */ |
| 4543 | /* preserve bits <10..7>, bits <6..0> must be zero */ |
| 4544 | |
| 4545 | outw( Cmd + info->loopback_bits, info->io_base + CCAR ); |
| 4546 | |
| 4547 | /* Read to flush write to CCAR */ |
| 4548 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 4549 | inw( info->io_base + CCAR ); |
| 4550 | |
| 4551 | } /* end of usc_RTCmd() */ |
| 4552 | |
| 4553 | /* |
| 4554 | * usc_DmaCmd() |
| 4555 | * |
| 4556 | * Issue a DMA command to the DMA Command/Address Register (DCAR). |
| 4557 | * |
| 4558 | * Arguments: |
| 4559 | * |
| 4560 | * info pointer to device information structure |
| 4561 | * Cmd DMA command mask (usc_DmaCmd_XX Macros) |
| 4562 | * |
| 4563 | * Return Value: |
| 4564 | * |
| 4565 | * None |
| 4566 | */ |
| 4567 | static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd ) |
| 4568 | { |
| 4569 | /* write command mask to DCAR */ |
| 4570 | outw( Cmd + info->mbre_bit, info->io_base ); |
| 4571 | |
| 4572 | /* Read to flush write to DCAR */ |
| 4573 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 4574 | inw( info->io_base ); |
| 4575 | |
| 4576 | } /* end of usc_DmaCmd() */ |
| 4577 | |
| 4578 | /* |
| 4579 | * usc_OutDmaReg() |
| 4580 | * |
| 4581 | * Write a 16-bit value to a USC DMA register |
| 4582 | * |
| 4583 | * Arguments: |
| 4584 | * |
| 4585 | * info pointer to device info structure |
| 4586 | * RegAddr register address (number) for write |
| 4587 | * RegValue 16-bit value to write to register |
| 4588 | * |
| 4589 | * Return Value: |
| 4590 | * |
| 4591 | * None |
| 4592 | * |
| 4593 | */ |
| 4594 | static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) |
| 4595 | { |
| 4596 | /* Note: The DCAR is located at the adapter base address */ |
| 4597 | /* Note: must preserve state of BIT8 in DCAR */ |
| 4598 | |
| 4599 | outw( RegAddr + info->mbre_bit, info->io_base ); |
| 4600 | outw( RegValue, info->io_base ); |
| 4601 | |
| 4602 | /* Read to flush write to DCAR */ |
| 4603 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 4604 | inw( info->io_base ); |
| 4605 | |
| 4606 | } /* end of usc_OutDmaReg() */ |
| 4607 | |
| 4608 | /* |
| 4609 | * usc_InDmaReg() |
| 4610 | * |
| 4611 | * Read a 16-bit value from a DMA register |
| 4612 | * |
| 4613 | * Arguments: |
| 4614 | * |
| 4615 | * info pointer to device info structure |
| 4616 | * RegAddr register address (number) to read from |
| 4617 | * |
| 4618 | * Return Value: |
| 4619 | * |
| 4620 | * The 16-bit value read from register |
| 4621 | * |
| 4622 | */ |
| 4623 | static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr ) |
| 4624 | { |
| 4625 | /* Note: The DCAR is located at the adapter base address */ |
| 4626 | /* Note: must preserve state of BIT8 in DCAR */ |
| 4627 | |
| 4628 | outw( RegAddr + info->mbre_bit, info->io_base ); |
| 4629 | return inw( info->io_base ); |
| 4630 | |
| 4631 | } /* end of usc_InDmaReg() */ |
| 4632 | |
| 4633 | /* |
| 4634 | * |
| 4635 | * usc_OutReg() |
| 4636 | * |
| 4637 | * Write a 16-bit value to a USC serial channel register |
| 4638 | * |
| 4639 | * Arguments: |
| 4640 | * |
| 4641 | * info pointer to device info structure |
| 4642 | * RegAddr register address (number) to write to |
| 4643 | * RegValue 16-bit value to write to register |
| 4644 | * |
| 4645 | * Return Value: |
| 4646 | * |
| 4647 | * None |
| 4648 | * |
| 4649 | */ |
| 4650 | static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) |
| 4651 | { |
| 4652 | outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); |
| 4653 | outw( RegValue, info->io_base + CCAR ); |
| 4654 | |
| 4655 | /* Read to flush write to CCAR */ |
| 4656 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 4657 | inw( info->io_base + CCAR ); |
| 4658 | |
| 4659 | } /* end of usc_OutReg() */ |
| 4660 | |
| 4661 | /* |
| 4662 | * usc_InReg() |
| 4663 | * |
| 4664 | * Reads a 16-bit value from a USC serial channel register |
| 4665 | * |
| 4666 | * Arguments: |
| 4667 | * |
| 4668 | * info pointer to device extension |
| 4669 | * RegAddr register address (number) to read from |
| 4670 | * |
| 4671 | * Return Value: |
| 4672 | * |
| 4673 | * 16-bit value read from register |
| 4674 | */ |
| 4675 | static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) |
| 4676 | { |
| 4677 | outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); |
| 4678 | return inw( info->io_base + CCAR ); |
| 4679 | |
| 4680 | } /* end of usc_InReg() */ |
| 4681 | |
| 4682 | /* usc_set_sdlc_mode() |
| 4683 | * |
| 4684 | * Set up the adapter for SDLC DMA communications. |
| 4685 | * |
| 4686 | * Arguments: info pointer to device instance data |
| 4687 | * Return Value: NONE |
| 4688 | */ |
| 4689 | static void usc_set_sdlc_mode( struct mgsl_struct *info ) |
| 4690 | { |
| 4691 | u16 RegValue; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4692 | bool PreSL1660; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4693 | |
| 4694 | /* |
| 4695 | * determine if the IUSC on the adapter is pre-SL1660. If |
| 4696 | * not, take advantage of the UnderWait feature of more |
| 4697 | * modern chips. If an underrun occurs and this bit is set, |
| 4698 | * the transmitter will idle the programmed idle pattern |
| 4699 | * until the driver has time to service the underrun. Otherwise, |
| 4700 | * the dma controller may get the cycles previously requested |
| 4701 | * and begin transmitting queued tx data. |
| 4702 | */ |
| 4703 | usc_OutReg(info,TMCR,0x1f); |
| 4704 | RegValue=usc_InReg(info,TMDR); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 4705 | PreSL1660 = (RegValue == IUSC_PRE_SL1660); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4706 | |
| 4707 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) |
| 4708 | { |
| 4709 | /* |
| 4710 | ** Channel Mode Register (CMR) |
| 4711 | ** |
| 4712 | ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun |
| 4713 | ** <13> 0 0 = Transmit Disabled (initially) |
| 4714 | ** <12> 0 1 = Consecutive Idles share common 0 |
| 4715 | ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop |
| 4716 | ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling |
| 4717 | ** <3..0> 0110 Receiver Mode = HDLC/SDLC |
| 4718 | ** |
| 4719 | ** 1000 1110 0000 0110 = 0x8e06 |
| 4720 | */ |
| 4721 | RegValue = 0x8e06; |
| 4722 | |
| 4723 | /*-------------------------------------------------- |
| 4724 | * ignore user options for UnderRun Actions and |
| 4725 | * preambles |
| 4726 | *--------------------------------------------------*/ |
| 4727 | } |
| 4728 | else |
| 4729 | { |
| 4730 | /* Channel mode Register (CMR) |
| 4731 | * |
| 4732 | * <15..14> 00 Tx Sub modes, Underrun Action |
| 4733 | * <13> 0 1 = Send Preamble before opening flag |
| 4734 | * <12> 0 1 = Consecutive Idles share common 0 |
| 4735 | * <11..8> 0110 Transmitter mode = HDLC/SDLC |
| 4736 | * <7..4> 0000 Rx Sub modes, addr/ctrl field handling |
| 4737 | * <3..0> 0110 Receiver mode = HDLC/SDLC |
| 4738 | * |
| 4739 | * 0000 0110 0000 0110 = 0x0606 |
| 4740 | */ |
| 4741 | if (info->params.mode == MGSL_MODE_RAW) { |
| 4742 | RegValue = 0x0001; /* Set Receive mode = external sync */ |
| 4743 | |
| 4744 | usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */ |
| 4745 | (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); |
| 4746 | |
| 4747 | /* |
| 4748 | * TxSubMode: |
| 4749 | * CMR <15> 0 Don't send CRC on Tx Underrun |
| 4750 | * CMR <14> x undefined |
| 4751 | * CMR <13> 0 Send preamble before openning sync |
| 4752 | * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength |
| 4753 | * |
| 4754 | * TxMode: |
| 4755 | * CMR <11-8) 0100 MonoSync |
| 4756 | * |
| 4757 | * 0x00 0100 xxxx xxxx 04xx |
| 4758 | */ |
| 4759 | RegValue |= 0x0400; |
| 4760 | } |
| 4761 | else { |
| 4762 | |
| 4763 | RegValue = 0x0606; |
| 4764 | |
| 4765 | if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 ) |
| 4766 | RegValue |= BIT14; |
| 4767 | else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG ) |
| 4768 | RegValue |= BIT15; |
| 4769 | else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC ) |
| 4770 | RegValue |= BIT15 + BIT14; |
| 4771 | } |
| 4772 | |
| 4773 | if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE ) |
| 4774 | RegValue |= BIT13; |
| 4775 | } |
| 4776 | |
| 4777 | if ( info->params.mode == MGSL_MODE_HDLC && |
| 4778 | (info->params.flags & HDLC_FLAG_SHARE_ZERO) ) |
| 4779 | RegValue |= BIT12; |
| 4780 | |
| 4781 | if ( info->params.addr_filter != 0xff ) |
| 4782 | { |
| 4783 | /* set up receive address filtering */ |
| 4784 | usc_OutReg( info, RSR, info->params.addr_filter ); |
| 4785 | RegValue |= BIT4; |
| 4786 | } |
| 4787 | |
| 4788 | usc_OutReg( info, CMR, RegValue ); |
| 4789 | info->cmr_value = RegValue; |
| 4790 | |
| 4791 | /* Receiver mode Register (RMR) |
| 4792 | * |
| 4793 | * <15..13> 000 encoding |
| 4794 | * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1) |
| 4795 | * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC) |
| 4796 | * <9> 0 1 = Include Receive chars in CRC |
| 4797 | * <8> 1 1 = Use Abort/PE bit as abort indicator |
| 4798 | * <7..6> 00 Even parity |
| 4799 | * <5> 0 parity disabled |
| 4800 | * <4..2> 000 Receive Char Length = 8 bits |
| 4801 | * <1..0> 00 Disable Receiver |
| 4802 | * |
| 4803 | * 0000 0101 0000 0000 = 0x0500 |
| 4804 | */ |
| 4805 | |
| 4806 | RegValue = 0x0500; |
| 4807 | |
| 4808 | switch ( info->params.encoding ) { |
| 4809 | case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; |
| 4810 | case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; |
| 4811 | case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break; |
| 4812 | case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; |
| 4813 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break; |
| 4814 | case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break; |
| 4815 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break; |
| 4816 | } |
| 4817 | |
| 4818 | if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT ) |
| 4819 | RegValue |= BIT9; |
| 4820 | else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT ) |
| 4821 | RegValue |= ( BIT12 | BIT10 | BIT9 ); |
| 4822 | |
| 4823 | usc_OutReg( info, RMR, RegValue ); |
| 4824 | |
| 4825 | /* Set the Receive count Limit Register (RCLR) to 0xffff. */ |
| 4826 | /* When an opening flag of an SDLC frame is recognized the */ |
| 4827 | /* Receive Character count (RCC) is loaded with the value in */ |
| 4828 | /* RCLR. The RCC is decremented for each received byte. The */ |
| 4829 | /* value of RCC is stored after the closing flag of the frame */ |
| 4830 | /* allowing the frame size to be computed. */ |
| 4831 | |
| 4832 | usc_OutReg( info, RCLR, RCLRVALUE ); |
| 4833 | |
| 4834 | usc_RCmd( info, RCmd_SelectRicrdma_level ); |
| 4835 | |
| 4836 | /* Receive Interrupt Control Register (RICR) |
| 4837 | * |
| 4838 | * <15..8> ? RxFIFO DMA Request Level |
| 4839 | * <7> 0 Exited Hunt IA (Interrupt Arm) |
| 4840 | * <6> 0 Idle Received IA |
| 4841 | * <5> 0 Break/Abort IA |
| 4842 | * <4> 0 Rx Bound IA |
| 4843 | * <3> 1 Queued status reflects oldest 2 bytes in FIFO |
| 4844 | * <2> 0 Abort/PE IA |
| 4845 | * <1> 1 Rx Overrun IA |
| 4846 | * <0> 0 Select TC0 value for readback |
| 4847 | * |
| 4848 | * 0000 0000 0000 1000 = 0x000a |
| 4849 | */ |
| 4850 | |
| 4851 | /* Carry over the Exit Hunt and Idle Received bits */ |
| 4852 | /* in case they have been armed by usc_ArmEvents. */ |
| 4853 | |
| 4854 | RegValue = usc_InReg( info, RICR ) & 0xc0; |
| 4855 | |
| 4856 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 4857 | usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); |
| 4858 | else |
| 4859 | usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); |
| 4860 | |
| 4861 | /* Unlatch all Rx status bits and clear Rx status IRQ Pending */ |
| 4862 | |
| 4863 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); |
| 4864 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); |
| 4865 | |
| 4866 | /* Transmit mode Register (TMR) |
| 4867 | * |
| 4868 | * <15..13> 000 encoding |
| 4869 | * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1) |
| 4870 | * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC) |
| 4871 | * <9> 0 1 = Tx CRC Enabled |
| 4872 | * <8> 0 1 = Append CRC to end of transmit frame |
| 4873 | * <7..6> 00 Transmit parity Even |
| 4874 | * <5> 0 Transmit parity Disabled |
| 4875 | * <4..2> 000 Tx Char Length = 8 bits |
| 4876 | * <1..0> 00 Disable Transmitter |
| 4877 | * |
| 4878 | * 0000 0100 0000 0000 = 0x0400 |
| 4879 | */ |
| 4880 | |
| 4881 | RegValue = 0x0400; |
| 4882 | |
| 4883 | switch ( info->params.encoding ) { |
| 4884 | case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; |
| 4885 | case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; |
| 4886 | case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break; |
| 4887 | case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; |
| 4888 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break; |
| 4889 | case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break; |
| 4890 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break; |
| 4891 | } |
| 4892 | |
| 4893 | if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT ) |
| 4894 | RegValue |= BIT9 + BIT8; |
| 4895 | else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT ) |
| 4896 | RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); |
| 4897 | |
| 4898 | usc_OutReg( info, TMR, RegValue ); |
| 4899 | |
| 4900 | usc_set_txidle( info ); |
| 4901 | |
| 4902 | |
| 4903 | usc_TCmd( info, TCmd_SelectTicrdma_level ); |
| 4904 | |
| 4905 | /* Transmit Interrupt Control Register (TICR) |
| 4906 | * |
| 4907 | * <15..8> ? Transmit FIFO DMA Level |
| 4908 | * <7> 0 Present IA (Interrupt Arm) |
| 4909 | * <6> 0 Idle Sent IA |
| 4910 | * <5> 1 Abort Sent IA |
| 4911 | * <4> 1 EOF/EOM Sent IA |
| 4912 | * <3> 0 CRC Sent IA |
| 4913 | * <2> 1 1 = Wait for SW Trigger to Start Frame |
| 4914 | * <1> 1 Tx Underrun IA |
| 4915 | * <0> 0 TC0 constant on read back |
| 4916 | * |
| 4917 | * 0000 0000 0011 0110 = 0x0036 |
| 4918 | */ |
| 4919 | |
| 4920 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 4921 | usc_OutReg( info, TICR, 0x0736 ); |
| 4922 | else |
| 4923 | usc_OutReg( info, TICR, 0x1436 ); |
| 4924 | |
| 4925 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); |
| 4926 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); |
| 4927 | |
| 4928 | /* |
| 4929 | ** Transmit Command/Status Register (TCSR) |
| 4930 | ** |
| 4931 | ** <15..12> 0000 TCmd |
| 4932 | ** <11> 0/1 UnderWait |
| 4933 | ** <10..08> 000 TxIdle |
| 4934 | ** <7> x PreSent |
| 4935 | ** <6> x IdleSent |
| 4936 | ** <5> x AbortSent |
| 4937 | ** <4> x EOF/EOM Sent |
| 4938 | ** <3> x CRC Sent |
| 4939 | ** <2> x All Sent |
| 4940 | ** <1> x TxUnder |
| 4941 | ** <0> x TxEmpty |
| 4942 | ** |
| 4943 | ** 0000 0000 0000 0000 = 0x0000 |
| 4944 | */ |
| 4945 | info->tcsr_value = 0; |
| 4946 | |
| 4947 | if ( !PreSL1660 ) |
| 4948 | info->tcsr_value |= TCSR_UNDERWAIT; |
| 4949 | |
| 4950 | usc_OutReg( info, TCSR, info->tcsr_value ); |
| 4951 | |
| 4952 | /* Clock mode Control Register (CMCR) |
| 4953 | * |
| 4954 | * <15..14> 00 counter 1 Source = Disabled |
| 4955 | * <13..12> 00 counter 0 Source = Disabled |
| 4956 | * <11..10> 11 BRG1 Input is TxC Pin |
| 4957 | * <9..8> 11 BRG0 Input is TxC Pin |
| 4958 | * <7..6> 01 DPLL Input is BRG1 Output |
| 4959 | * <5..3> XXX TxCLK comes from Port 0 |
| 4960 | * <2..0> XXX RxCLK comes from Port 1 |
| 4961 | * |
| 4962 | * 0000 1111 0111 0111 = 0x0f77 |
| 4963 | */ |
| 4964 | |
| 4965 | RegValue = 0x0f40; |
| 4966 | |
| 4967 | if ( info->params.flags & HDLC_FLAG_RXC_DPLL ) |
| 4968 | RegValue |= 0x0003; /* RxCLK from DPLL */ |
| 4969 | else if ( info->params.flags & HDLC_FLAG_RXC_BRG ) |
| 4970 | RegValue |= 0x0004; /* RxCLK from BRG0 */ |
| 4971 | else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN) |
| 4972 | RegValue |= 0x0006; /* RxCLK from TXC Input */ |
| 4973 | else |
| 4974 | RegValue |= 0x0007; /* RxCLK from Port1 */ |
| 4975 | |
| 4976 | if ( info->params.flags & HDLC_FLAG_TXC_DPLL ) |
| 4977 | RegValue |= 0x0018; /* TxCLK from DPLL */ |
| 4978 | else if ( info->params.flags & HDLC_FLAG_TXC_BRG ) |
| 4979 | RegValue |= 0x0020; /* TxCLK from BRG0 */ |
| 4980 | else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN) |
| 4981 | RegValue |= 0x0038; /* RxCLK from TXC Input */ |
| 4982 | else |
| 4983 | RegValue |= 0x0030; /* TxCLK from Port0 */ |
| 4984 | |
| 4985 | usc_OutReg( info, CMCR, RegValue ); |
| 4986 | |
| 4987 | |
| 4988 | /* Hardware Configuration Register (HCR) |
| 4989 | * |
| 4990 | * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4 |
| 4991 | * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div |
| 4992 | * <12> 0 CVOK:0=report code violation in biphase |
| 4993 | * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4 |
| 4994 | * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level |
| 4995 | * <7..6> 00 reserved |
| 4996 | * <5> 0 BRG1 mode:0=continuous,1=single cycle |
| 4997 | * <4> X BRG1 Enable |
| 4998 | * <3..2> 00 reserved |
| 4999 | * <1> 0 BRG0 mode:0=continuous,1=single cycle |
| 5000 | * <0> 0 BRG0 Enable |
| 5001 | */ |
| 5002 | |
| 5003 | RegValue = 0x0000; |
| 5004 | |
| 5005 | if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) { |
| 5006 | u32 XtalSpeed; |
| 5007 | u32 DpllDivisor; |
| 5008 | u16 Tc; |
| 5009 | |
| 5010 | /* DPLL is enabled. Use BRG1 to provide continuous reference clock */ |
| 5011 | /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */ |
| 5012 | |
| 5013 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 5014 | XtalSpeed = 11059200; |
| 5015 | else |
| 5016 | XtalSpeed = 14745600; |
| 5017 | |
| 5018 | if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { |
| 5019 | DpllDivisor = 16; |
| 5020 | RegValue |= BIT10; |
| 5021 | } |
| 5022 | else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { |
| 5023 | DpllDivisor = 8; |
| 5024 | RegValue |= BIT11; |
| 5025 | } |
| 5026 | else |
| 5027 | DpllDivisor = 32; |
| 5028 | |
| 5029 | /* Tc = (Xtal/Speed) - 1 */ |
| 5030 | /* If twice the remainder of (Xtal/Speed) is greater than Speed */ |
| 5031 | /* then rounding up gives a more precise time constant. Instead */ |
| 5032 | /* of rounding up and then subtracting 1 we just don't subtract */ |
| 5033 | /* the one in this case. */ |
| 5034 | |
| 5035 | /*-------------------------------------------------- |
| 5036 | * ejz: for DPLL mode, application should use the |
| 5037 | * same clock speed as the partner system, even |
| 5038 | * though clocking is derived from the input RxData. |
| 5039 | * In case the user uses a 0 for the clock speed, |
| 5040 | * default to 0xffffffff and don't try to divide by |
| 5041 | * zero |
| 5042 | *--------------------------------------------------*/ |
| 5043 | if ( info->params.clock_speed ) |
| 5044 | { |
| 5045 | Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed); |
| 5046 | if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2) |
| 5047 | / info->params.clock_speed) ) |
| 5048 | Tc--; |
| 5049 | } |
| 5050 | else |
| 5051 | Tc = -1; |
| 5052 | |
| 5053 | |
| 5054 | /* Write 16-bit Time Constant for BRG1 */ |
| 5055 | usc_OutReg( info, TC1R, Tc ); |
| 5056 | |
| 5057 | RegValue |= BIT4; /* enable BRG1 */ |
| 5058 | |
| 5059 | switch ( info->params.encoding ) { |
| 5060 | case HDLC_ENCODING_NRZ: |
| 5061 | case HDLC_ENCODING_NRZB: |
| 5062 | case HDLC_ENCODING_NRZI_MARK: |
| 5063 | case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; |
| 5064 | case HDLC_ENCODING_BIPHASE_MARK: |
| 5065 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; |
| 5066 | case HDLC_ENCODING_BIPHASE_LEVEL: |
| 5067 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break; |
| 5068 | } |
| 5069 | } |
| 5070 | |
| 5071 | usc_OutReg( info, HCR, RegValue ); |
| 5072 | |
| 5073 | |
| 5074 | /* Channel Control/status Register (CCSR) |
| 5075 | * |
| 5076 | * <15> X RCC FIFO Overflow status (RO) |
| 5077 | * <14> X RCC FIFO Not Empty status (RO) |
| 5078 | * <13> 0 1 = Clear RCC FIFO (WO) |
| 5079 | * <12> X DPLL Sync (RW) |
| 5080 | * <11> X DPLL 2 Missed Clocks status (RO) |
| 5081 | * <10> X DPLL 1 Missed Clock status (RO) |
| 5082 | * <9..8> 00 DPLL Resync on rising and falling edges (RW) |
| 5083 | * <7> X SDLC Loop On status (RO) |
| 5084 | * <6> X SDLC Loop Send status (RO) |
| 5085 | * <5> 1 Bypass counters for TxClk and RxClk (RW) |
| 5086 | * <4..2> 000 Last Char of SDLC frame has 8 bits (RW) |
| 5087 | * <1..0> 00 reserved |
| 5088 | * |
| 5089 | * 0000 0000 0010 0000 = 0x0020 |
| 5090 | */ |
| 5091 | |
| 5092 | usc_OutReg( info, CCSR, 0x1020 ); |
| 5093 | |
| 5094 | |
| 5095 | if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) { |
| 5096 | usc_OutReg( info, SICR, |
| 5097 | (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) ); |
| 5098 | } |
| 5099 | |
| 5100 | |
| 5101 | /* enable Master Interrupt Enable bit (MIE) */ |
| 5102 | usc_EnableMasterIrqBit( info ); |
| 5103 | |
| 5104 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA + |
| 5105 | TRANSMIT_STATUS + TRANSMIT_DATA + MISC); |
| 5106 | |
| 5107 | /* arm RCC underflow interrupt */ |
| 5108 | usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); |
| 5109 | usc_EnableInterrupts(info, MISC); |
| 5110 | |
| 5111 | info->mbre_bit = 0; |
| 5112 | outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */ |
| 5113 | usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */ |
| 5114 | info->mbre_bit = BIT8; |
| 5115 | outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */ |
| 5116 | |
| 5117 | if (info->bus_type == MGSL_BUS_TYPE_ISA) { |
| 5118 | /* Enable DMAEN (Port 7, Bit 14) */ |
| 5119 | /* This connects the DMA request signal to the ISA bus */ |
| 5120 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14)); |
| 5121 | } |
| 5122 | |
| 5123 | /* DMA Control Register (DCR) |
| 5124 | * |
| 5125 | * <15..14> 10 Priority mode = Alternating Tx/Rx |
| 5126 | * 01 Rx has priority |
| 5127 | * 00 Tx has priority |
| 5128 | * |
| 5129 | * <13> 1 Enable Priority Preempt per DCR<15..14> |
| 5130 | * (WARNING DCR<11..10> must be 00 when this is 1) |
| 5131 | * 0 Choose activate channel per DCR<11..10> |
| 5132 | * |
| 5133 | * <12> 0 Little Endian for Array/List |
| 5134 | * <11..10> 00 Both Channels can use each bus grant |
| 5135 | * <9..6> 0000 reserved |
| 5136 | * <5> 0 7 CLK - Minimum Bus Re-request Interval |
| 5137 | * <4> 0 1 = drive D/C and S/D pins |
| 5138 | * <3> 1 1 = Add one wait state to all DMA cycles. |
| 5139 | * <2> 0 1 = Strobe /UAS on every transfer. |
| 5140 | * <1..0> 11 Addr incrementing only affects LS24 bits |
| 5141 | * |
| 5142 | * 0110 0000 0000 1011 = 0x600b |
| 5143 | */ |
| 5144 | |
| 5145 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 5146 | /* PCI adapter does not need DMA wait state */ |
| 5147 | usc_OutDmaReg( info, DCR, 0xa00b ); |
| 5148 | } |
| 5149 | else |
| 5150 | usc_OutDmaReg( info, DCR, 0x800b ); |
| 5151 | |
| 5152 | |
| 5153 | /* Receive DMA mode Register (RDMR) |
| 5154 | * |
| 5155 | * <15..14> 11 DMA mode = Linked List Buffer mode |
| 5156 | * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry |
| 5157 | * <12> 1 Clear count of List Entry after fetching |
| 5158 | * <11..10> 00 Address mode = Increment |
| 5159 | * <9> 1 Terminate Buffer on RxBound |
| 5160 | * <8> 0 Bus Width = 16bits |
| 5161 | * <7..0> ? status Bits (write as 0s) |
| 5162 | * |
| 5163 | * 1111 0010 0000 0000 = 0xf200 |
| 5164 | */ |
| 5165 | |
| 5166 | usc_OutDmaReg( info, RDMR, 0xf200 ); |
| 5167 | |
| 5168 | |
| 5169 | /* Transmit DMA mode Register (TDMR) |
| 5170 | * |
| 5171 | * <15..14> 11 DMA mode = Linked List Buffer mode |
| 5172 | * <13> 1 TCBinA/L = fetch Tx Control Block from List entry |
| 5173 | * <12> 1 Clear count of List Entry after fetching |
| 5174 | * <11..10> 00 Address mode = Increment |
| 5175 | * <9> 1 Terminate Buffer on end of frame |
| 5176 | * <8> 0 Bus Width = 16bits |
| 5177 | * <7..0> ? status Bits (Read Only so write as 0) |
| 5178 | * |
| 5179 | * 1111 0010 0000 0000 = 0xf200 |
| 5180 | */ |
| 5181 | |
| 5182 | usc_OutDmaReg( info, TDMR, 0xf200 ); |
| 5183 | |
| 5184 | |
| 5185 | /* DMA Interrupt Control Register (DICR) |
| 5186 | * |
| 5187 | * <15> 1 DMA Interrupt Enable |
| 5188 | * <14> 0 1 = Disable IEO from USC |
| 5189 | * <13> 0 1 = Don't provide vector during IntAck |
| 5190 | * <12> 1 1 = Include status in Vector |
| 5191 | * <10..2> 0 reserved, Must be 0s |
| 5192 | * <1> 0 1 = Rx DMA Interrupt Enabled |
| 5193 | * <0> 0 1 = Tx DMA Interrupt Enabled |
| 5194 | * |
| 5195 | * 1001 0000 0000 0000 = 0x9000 |
| 5196 | */ |
| 5197 | |
| 5198 | usc_OutDmaReg( info, DICR, 0x9000 ); |
| 5199 | |
| 5200 | usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */ |
| 5201 | usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */ |
| 5202 | usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */ |
| 5203 | |
| 5204 | /* Channel Control Register (CCR) |
| 5205 | * |
| 5206 | * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs) |
| 5207 | * <13> 0 Trigger Tx on SW Command Disabled |
| 5208 | * <12> 0 Flag Preamble Disabled |
| 5209 | * <11..10> 00 Preamble Length |
| 5210 | * <9..8> 00 Preamble Pattern |
| 5211 | * <7..6> 10 Use 32-bit Rx status Blocks (RSBs) |
| 5212 | * <5> 0 Trigger Rx on SW Command Disabled |
| 5213 | * <4..0> 0 reserved |
| 5214 | * |
| 5215 | * 1000 0000 1000 0000 = 0x8080 |
| 5216 | */ |
| 5217 | |
| 5218 | RegValue = 0x8080; |
| 5219 | |
| 5220 | switch ( info->params.preamble_length ) { |
| 5221 | case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; |
| 5222 | case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; |
| 5223 | case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break; |
| 5224 | } |
| 5225 | |
| 5226 | switch ( info->params.preamble ) { |
| 5227 | case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break; |
| 5228 | case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; |
| 5229 | case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; |
| 5230 | case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break; |
| 5231 | } |
| 5232 | |
| 5233 | usc_OutReg( info, CCR, RegValue ); |
| 5234 | |
| 5235 | |
| 5236 | /* |
| 5237 | * Burst/Dwell Control Register |
| 5238 | * |
| 5239 | * <15..8> 0x20 Maximum number of transfers per bus grant |
| 5240 | * <7..0> 0x00 Maximum number of clock cycles per bus grant |
| 5241 | */ |
| 5242 | |
| 5243 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 5244 | /* don't limit bus occupancy on PCI adapter */ |
| 5245 | usc_OutDmaReg( info, BDCR, 0x0000 ); |
| 5246 | } |
| 5247 | else |
| 5248 | usc_OutDmaReg( info, BDCR, 0x2000 ); |
| 5249 | |
| 5250 | usc_stop_transmitter(info); |
| 5251 | usc_stop_receiver(info); |
| 5252 | |
| 5253 | } /* end of usc_set_sdlc_mode() */ |
| 5254 | |
| 5255 | /* usc_enable_loopback() |
| 5256 | * |
| 5257 | * Set the 16C32 for internal loopback mode. |
| 5258 | * The TxCLK and RxCLK signals are generated from the BRG0 and |
| 5259 | * the TxD is looped back to the RxD internally. |
| 5260 | * |
| 5261 | * Arguments: info pointer to device instance data |
| 5262 | * enable 1 = enable loopback, 0 = disable |
| 5263 | * Return Value: None |
| 5264 | */ |
| 5265 | static void usc_enable_loopback(struct mgsl_struct *info, int enable) |
| 5266 | { |
| 5267 | if (enable) { |
| 5268 | /* blank external TXD output */ |
| 5269 | usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6)); |
| 5270 | |
| 5271 | /* Clock mode Control Register (CMCR) |
| 5272 | * |
| 5273 | * <15..14> 00 counter 1 Disabled |
| 5274 | * <13..12> 00 counter 0 Disabled |
| 5275 | * <11..10> 11 BRG1 Input is TxC Pin |
| 5276 | * <9..8> 11 BRG0 Input is TxC Pin |
| 5277 | * <7..6> 01 DPLL Input is BRG1 Output |
| 5278 | * <5..3> 100 TxCLK comes from BRG0 |
| 5279 | * <2..0> 100 RxCLK comes from BRG0 |
| 5280 | * |
| 5281 | * 0000 1111 0110 0100 = 0x0f64 |
| 5282 | */ |
| 5283 | |
| 5284 | usc_OutReg( info, CMCR, 0x0f64 ); |
| 5285 | |
| 5286 | /* Write 16-bit Time Constant for BRG0 */ |
| 5287 | /* use clock speed if available, otherwise use 8 for diagnostics */ |
| 5288 | if (info->params.clock_speed) { |
| 5289 | if (info->bus_type == MGSL_BUS_TYPE_PCI) |
| 5290 | usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1)); |
| 5291 | else |
| 5292 | usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1)); |
| 5293 | } else |
| 5294 | usc_OutReg(info, TC0R, (u16)8); |
| 5295 | |
| 5296 | /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0 |
| 5297 | mode = Continuous Set Bit 0 to enable BRG0. */ |
| 5298 | usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); |
| 5299 | |
| 5300 | /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */ |
| 5301 | usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004)); |
| 5302 | |
| 5303 | /* set Internal Data loopback mode */ |
| 5304 | info->loopback_bits = 0x300; |
| 5305 | outw( 0x0300, info->io_base + CCAR ); |
| 5306 | } else { |
| 5307 | /* enable external TXD output */ |
| 5308 | usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6)); |
| 5309 | |
| 5310 | /* clear Internal Data loopback mode */ |
| 5311 | info->loopback_bits = 0; |
| 5312 | outw( 0,info->io_base + CCAR ); |
| 5313 | } |
| 5314 | |
| 5315 | } /* end of usc_enable_loopback() */ |
| 5316 | |
| 5317 | /* usc_enable_aux_clock() |
| 5318 | * |
| 5319 | * Enabled the AUX clock output at the specified frequency. |
| 5320 | * |
| 5321 | * Arguments: |
| 5322 | * |
| 5323 | * info pointer to device extension |
| 5324 | * data_rate data rate of clock in bits per second |
| 5325 | * A data rate of 0 disables the AUX clock. |
| 5326 | * |
| 5327 | * Return Value: None |
| 5328 | */ |
| 5329 | static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate ) |
| 5330 | { |
| 5331 | u32 XtalSpeed; |
| 5332 | u16 Tc; |
| 5333 | |
| 5334 | if ( data_rate ) { |
| 5335 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 5336 | XtalSpeed = 11059200; |
| 5337 | else |
| 5338 | XtalSpeed = 14745600; |
| 5339 | |
| 5340 | |
| 5341 | /* Tc = (Xtal/Speed) - 1 */ |
| 5342 | /* If twice the remainder of (Xtal/Speed) is greater than Speed */ |
| 5343 | /* then rounding up gives a more precise time constant. Instead */ |
| 5344 | /* of rounding up and then subtracting 1 we just don't subtract */ |
| 5345 | /* the one in this case. */ |
| 5346 | |
| 5347 | |
| 5348 | Tc = (u16)(XtalSpeed/data_rate); |
| 5349 | if ( !(((XtalSpeed % data_rate) * 2) / data_rate) ) |
| 5350 | Tc--; |
| 5351 | |
| 5352 | /* Write 16-bit Time Constant for BRG0 */ |
| 5353 | usc_OutReg( info, TC0R, Tc ); |
| 5354 | |
| 5355 | /* |
| 5356 | * Hardware Configuration Register (HCR) |
| 5357 | * Clear Bit 1, BRG0 mode = Continuous |
| 5358 | * Set Bit 0 to enable BRG0. |
| 5359 | */ |
| 5360 | |
| 5361 | usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); |
| 5362 | |
| 5363 | /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */ |
| 5364 | usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); |
| 5365 | } else { |
| 5366 | /* data rate == 0 so turn off BRG0 */ |
| 5367 | usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); |
| 5368 | } |
| 5369 | |
| 5370 | } /* end of usc_enable_aux_clock() */ |
| 5371 | |
| 5372 | /* |
| 5373 | * |
| 5374 | * usc_process_rxoverrun_sync() |
| 5375 | * |
| 5376 | * This function processes a receive overrun by resetting the |
| 5377 | * receive DMA buffers and issuing a Purge Rx FIFO command |
| 5378 | * to allow the receiver to continue receiving. |
| 5379 | * |
| 5380 | * Arguments: |
| 5381 | * |
| 5382 | * info pointer to device extension |
| 5383 | * |
| 5384 | * Return Value: None |
| 5385 | */ |
| 5386 | static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) |
| 5387 | { |
| 5388 | int start_index; |
| 5389 | int end_index; |
| 5390 | int frame_start_index; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5391 | bool start_of_frame_found = false; |
| 5392 | bool end_of_frame_found = false; |
| 5393 | bool reprogram_dma = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5394 | |
| 5395 | DMABUFFERENTRY *buffer_list = info->rx_buffer_list; |
| 5396 | u32 phys_addr; |
| 5397 | |
| 5398 | usc_DmaCmd( info, DmaCmd_PauseRxChannel ); |
| 5399 | usc_RCmd( info, RCmd_EnterHuntmode ); |
| 5400 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 5401 | |
| 5402 | /* CurrentRxBuffer points to the 1st buffer of the next */ |
| 5403 | /* possibly available receive frame. */ |
| 5404 | |
| 5405 | frame_start_index = start_index = end_index = info->current_rx_buffer; |
| 5406 | |
| 5407 | /* Search for an unfinished string of buffers. This means */ |
| 5408 | /* that a receive frame started (at least one buffer with */ |
| 5409 | /* count set to zero) but there is no terminiting buffer */ |
| 5410 | /* (status set to non-zero). */ |
| 5411 | |
| 5412 | while( !buffer_list[end_index].count ) |
| 5413 | { |
| 5414 | /* Count field has been reset to zero by 16C32. */ |
| 5415 | /* This buffer is currently in use. */ |
| 5416 | |
| 5417 | if ( !start_of_frame_found ) |
| 5418 | { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5419 | start_of_frame_found = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5420 | frame_start_index = end_index; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5421 | end_of_frame_found = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5422 | } |
| 5423 | |
| 5424 | if ( buffer_list[end_index].status ) |
| 5425 | { |
| 5426 | /* Status field has been set by 16C32. */ |
| 5427 | /* This is the last buffer of a received frame. */ |
| 5428 | |
| 5429 | /* We want to leave the buffers for this frame intact. */ |
| 5430 | /* Move on to next possible frame. */ |
| 5431 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5432 | start_of_frame_found = false; |
| 5433 | end_of_frame_found = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5434 | } |
| 5435 | |
| 5436 | /* advance to next buffer entry in linked list */ |
| 5437 | end_index++; |
| 5438 | if ( end_index == info->rx_buffer_count ) |
| 5439 | end_index = 0; |
| 5440 | |
| 5441 | if ( start_index == end_index ) |
| 5442 | { |
| 5443 | /* The entire list has been searched with all Counts == 0 and */ |
| 5444 | /* all Status == 0. The receive buffers are */ |
| 5445 | /* completely screwed, reset all receive buffers! */ |
| 5446 | mgsl_reset_rx_dma_buffers( info ); |
| 5447 | frame_start_index = 0; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5448 | start_of_frame_found = false; |
| 5449 | reprogram_dma = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5450 | break; |
| 5451 | } |
| 5452 | } |
| 5453 | |
| 5454 | if ( start_of_frame_found && !end_of_frame_found ) |
| 5455 | { |
| 5456 | /* There is an unfinished string of receive DMA buffers */ |
| 5457 | /* as a result of the receiver overrun. */ |
| 5458 | |
| 5459 | /* Reset the buffers for the unfinished frame */ |
| 5460 | /* and reprogram the receive DMA controller to start */ |
| 5461 | /* at the 1st buffer of unfinished frame. */ |
| 5462 | |
| 5463 | start_index = frame_start_index; |
| 5464 | |
| 5465 | do |
| 5466 | { |
| 5467 | *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE; |
| 5468 | |
| 5469 | /* Adjust index for wrap around. */ |
| 5470 | if ( start_index == info->rx_buffer_count ) |
| 5471 | start_index = 0; |
| 5472 | |
| 5473 | } while( start_index != end_index ); |
| 5474 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5475 | reprogram_dma = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5476 | } |
| 5477 | |
| 5478 | if ( reprogram_dma ) |
| 5479 | { |
| 5480 | usc_UnlatchRxstatusBits(info,RXSTATUS_ALL); |
| 5481 | usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS); |
| 5482 | usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS); |
| 5483 | |
| 5484 | usc_EnableReceiver(info,DISABLE_UNCONDITIONAL); |
| 5485 | |
| 5486 | /* This empties the receive FIFO and loads the RCC with RCLR */ |
| 5487 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); |
| 5488 | |
| 5489 | /* program 16C32 with physical address of 1st DMA buffer entry */ |
| 5490 | phys_addr = info->rx_buffer_list[frame_start_index].phys_entry; |
| 5491 | usc_OutDmaReg( info, NRARL, (u16)phys_addr ); |
| 5492 | usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) ); |
| 5493 | |
| 5494 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); |
| 5495 | usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS ); |
| 5496 | usc_EnableInterrupts( info, RECEIVE_STATUS ); |
| 5497 | |
| 5498 | /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */ |
| 5499 | /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */ |
| 5500 | |
| 5501 | usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 ); |
| 5502 | usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); |
| 5503 | usc_DmaCmd( info, DmaCmd_InitRxChannel ); |
| 5504 | if ( info->params.flags & HDLC_FLAG_AUTO_DCD ) |
| 5505 | usc_EnableReceiver(info,ENABLE_AUTO_DCD); |
| 5506 | else |
| 5507 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); |
| 5508 | } |
| 5509 | else |
| 5510 | { |
| 5511 | /* This empties the receive FIFO and loads the RCC with RCLR */ |
| 5512 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); |
| 5513 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 5514 | } |
| 5515 | |
| 5516 | } /* end of usc_process_rxoverrun_sync() */ |
| 5517 | |
| 5518 | /* usc_stop_receiver() |
| 5519 | * |
| 5520 | * Disable USC receiver |
| 5521 | * |
| 5522 | * Arguments: info pointer to device instance data |
| 5523 | * Return Value: None |
| 5524 | */ |
| 5525 | static void usc_stop_receiver( struct mgsl_struct *info ) |
| 5526 | { |
| 5527 | if (debug_level >= DEBUG_LEVEL_ISR) |
| 5528 | printk("%s(%d):usc_stop_receiver(%s)\n", |
| 5529 | __FILE__,__LINE__, info->device_name ); |
| 5530 | |
| 5531 | /* Disable receive DMA channel. */ |
| 5532 | /* This also disables receive DMA channel interrupts */ |
| 5533 | usc_DmaCmd( info, DmaCmd_ResetRxChannel ); |
| 5534 | |
| 5535 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); |
| 5536 | usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS ); |
| 5537 | usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS ); |
| 5538 | |
| 5539 | usc_EnableReceiver(info,DISABLE_UNCONDITIONAL); |
| 5540 | |
| 5541 | /* This empties the receive FIFO and loads the RCC with RCLR */ |
| 5542 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); |
| 5543 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 5544 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5545 | info->rx_enabled = false; |
| 5546 | info->rx_overflow = false; |
| 5547 | info->rx_rcc_underrun = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5548 | |
| 5549 | } /* end of stop_receiver() */ |
| 5550 | |
| 5551 | /* usc_start_receiver() |
| 5552 | * |
| 5553 | * Enable the USC receiver |
| 5554 | * |
| 5555 | * Arguments: info pointer to device instance data |
| 5556 | * Return Value: None |
| 5557 | */ |
| 5558 | static void usc_start_receiver( struct mgsl_struct *info ) |
| 5559 | { |
| 5560 | u32 phys_addr; |
| 5561 | |
| 5562 | if (debug_level >= DEBUG_LEVEL_ISR) |
| 5563 | printk("%s(%d):usc_start_receiver(%s)\n", |
| 5564 | __FILE__,__LINE__, info->device_name ); |
| 5565 | |
| 5566 | mgsl_reset_rx_dma_buffers( info ); |
| 5567 | usc_stop_receiver( info ); |
| 5568 | |
| 5569 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); |
| 5570 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 5571 | |
| 5572 | if ( info->params.mode == MGSL_MODE_HDLC || |
| 5573 | info->params.mode == MGSL_MODE_RAW ) { |
| 5574 | /* DMA mode Transfers */ |
| 5575 | /* Program the DMA controller. */ |
| 5576 | /* Enable the DMA controller end of buffer interrupt. */ |
| 5577 | |
| 5578 | /* program 16C32 with physical address of 1st DMA buffer entry */ |
| 5579 | phys_addr = info->rx_buffer_list[0].phys_entry; |
| 5580 | usc_OutDmaReg( info, NRARL, (u16)phys_addr ); |
| 5581 | usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) ); |
| 5582 | |
| 5583 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); |
| 5584 | usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS ); |
| 5585 | usc_EnableInterrupts( info, RECEIVE_STATUS ); |
| 5586 | |
| 5587 | /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */ |
| 5588 | /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */ |
| 5589 | |
| 5590 | usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 ); |
| 5591 | usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); |
| 5592 | usc_DmaCmd( info, DmaCmd_InitRxChannel ); |
| 5593 | if ( info->params.flags & HDLC_FLAG_AUTO_DCD ) |
| 5594 | usc_EnableReceiver(info,ENABLE_AUTO_DCD); |
| 5595 | else |
| 5596 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); |
| 5597 | } else { |
| 5598 | usc_UnlatchRxstatusBits(info, RXSTATUS_ALL); |
| 5599 | usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS); |
| 5600 | usc_EnableInterrupts(info, RECEIVE_DATA); |
| 5601 | |
| 5602 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 5603 | usc_RCmd( info, RCmd_EnterHuntmode ); |
| 5604 | |
| 5605 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); |
| 5606 | } |
| 5607 | |
| 5608 | usc_OutReg( info, CCSR, 0x1020 ); |
| 5609 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5610 | info->rx_enabled = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5611 | |
| 5612 | } /* end of usc_start_receiver() */ |
| 5613 | |
| 5614 | /* usc_start_transmitter() |
| 5615 | * |
| 5616 | * Enable the USC transmitter and send a transmit frame if |
| 5617 | * one is loaded in the DMA buffers. |
| 5618 | * |
| 5619 | * Arguments: info pointer to device instance data |
| 5620 | * Return Value: None |
| 5621 | */ |
| 5622 | static void usc_start_transmitter( struct mgsl_struct *info ) |
| 5623 | { |
| 5624 | u32 phys_addr; |
| 5625 | unsigned int FrameSize; |
| 5626 | |
| 5627 | if (debug_level >= DEBUG_LEVEL_ISR) |
| 5628 | printk("%s(%d):usc_start_transmitter(%s)\n", |
| 5629 | __FILE__,__LINE__, info->device_name ); |
| 5630 | |
| 5631 | if ( info->xmit_cnt ) { |
| 5632 | |
| 5633 | /* If auto RTS enabled and RTS is inactive, then assert */ |
| 5634 | /* RTS and set a flag indicating that the driver should */ |
| 5635 | /* negate RTS when the transmission completes. */ |
| 5636 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5637 | info->drop_rts_on_tx_done = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5638 | |
| 5639 | if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { |
| 5640 | usc_get_serial_signals( info ); |
| 5641 | if ( !(info->serial_signals & SerialSignal_RTS) ) { |
| 5642 | info->serial_signals |= SerialSignal_RTS; |
| 5643 | usc_set_serial_signals( info ); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5644 | info->drop_rts_on_tx_done = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5645 | } |
| 5646 | } |
| 5647 | |
| 5648 | |
| 5649 | if ( info->params.mode == MGSL_MODE_ASYNC ) { |
| 5650 | if ( !info->tx_active ) { |
| 5651 | usc_UnlatchTxstatusBits(info, TXSTATUS_ALL); |
| 5652 | usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA); |
| 5653 | usc_EnableInterrupts(info, TRANSMIT_DATA); |
| 5654 | usc_load_txfifo(info); |
| 5655 | } |
| 5656 | } else { |
| 5657 | /* Disable transmit DMA controller while programming. */ |
| 5658 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); |
| 5659 | |
| 5660 | /* Transmit DMA buffer is loaded, so program USC */ |
| 5661 | /* to send the frame contained in the buffers. */ |
| 5662 | |
| 5663 | FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc; |
| 5664 | |
| 5665 | /* if operating in Raw sync mode, reset the rcc component |
| 5666 | * of the tx dma buffer entry, otherwise, the serial controller |
| 5667 | * will send a closing sync char after this count. |
| 5668 | */ |
| 5669 | if ( info->params.mode == MGSL_MODE_RAW ) |
| 5670 | info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0; |
| 5671 | |
| 5672 | /* Program the Transmit Character Length Register (TCLR) */ |
| 5673 | /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */ |
| 5674 | usc_OutReg( info, TCLR, (u16)FrameSize ); |
| 5675 | |
| 5676 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
| 5677 | |
| 5678 | /* Program the address of the 1st DMA Buffer Entry in linked list */ |
| 5679 | phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry; |
| 5680 | usc_OutDmaReg( info, NTARL, (u16)phys_addr ); |
| 5681 | usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) ); |
| 5682 | |
| 5683 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); |
| 5684 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); |
| 5685 | usc_EnableInterrupts( info, TRANSMIT_STATUS ); |
| 5686 | |
| 5687 | if ( info->params.mode == MGSL_MODE_RAW && |
| 5688 | info->num_tx_dma_buffers > 1 ) { |
| 5689 | /* When running external sync mode, attempt to 'stream' transmit */ |
| 5690 | /* by filling tx dma buffers as they become available. To do this */ |
| 5691 | /* we need to enable Tx DMA EOB Status interrupts : */ |
| 5692 | /* */ |
| 5693 | /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */ |
| 5694 | /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */ |
| 5695 | |
| 5696 | usc_OutDmaReg( info, TDIAR, BIT2|BIT3 ); |
| 5697 | usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); |
| 5698 | } |
| 5699 | |
| 5700 | /* Initialize Transmit DMA Channel */ |
| 5701 | usc_DmaCmd( info, DmaCmd_InitTxChannel ); |
| 5702 | |
| 5703 | usc_TCmd( info, TCmd_SendFrame ); |
| 5704 | |
Jiri Slaby | 40565f1 | 2007-02-12 00:52:31 -0800 | [diff] [blame] | 5705 | mod_timer(&info->tx_timer, jiffies + |
| 5706 | msecs_to_jiffies(5000)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5707 | } |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5708 | info->tx_active = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5709 | } |
| 5710 | |
| 5711 | if ( !info->tx_enabled ) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5712 | info->tx_enabled = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5713 | if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) |
| 5714 | usc_EnableTransmitter(info,ENABLE_AUTO_CTS); |
| 5715 | else |
| 5716 | usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL); |
| 5717 | } |
| 5718 | |
| 5719 | } /* end of usc_start_transmitter() */ |
| 5720 | |
| 5721 | /* usc_stop_transmitter() |
| 5722 | * |
| 5723 | * Stops the transmitter and DMA |
| 5724 | * |
| 5725 | * Arguments: info pointer to device isntance data |
| 5726 | * Return Value: None |
| 5727 | */ |
| 5728 | static void usc_stop_transmitter( struct mgsl_struct *info ) |
| 5729 | { |
| 5730 | if (debug_level >= DEBUG_LEVEL_ISR) |
| 5731 | printk("%s(%d):usc_stop_transmitter(%s)\n", |
| 5732 | __FILE__,__LINE__, info->device_name ); |
| 5733 | |
| 5734 | del_timer(&info->tx_timer); |
| 5735 | |
| 5736 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); |
| 5737 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA ); |
| 5738 | usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA ); |
| 5739 | |
| 5740 | usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL); |
| 5741 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); |
| 5742 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
| 5743 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 5744 | info->tx_enabled = false; |
| 5745 | info->tx_active = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5746 | |
| 5747 | } /* end of usc_stop_transmitter() */ |
| 5748 | |
| 5749 | /* usc_load_txfifo() |
| 5750 | * |
| 5751 | * Fill the transmit FIFO until the FIFO is full or |
| 5752 | * there is no more data to load. |
| 5753 | * |
| 5754 | * Arguments: info pointer to device extension (instance data) |
| 5755 | * Return Value: None |
| 5756 | */ |
| 5757 | static void usc_load_txfifo( struct mgsl_struct *info ) |
| 5758 | { |
| 5759 | int Fifocount; |
| 5760 | u8 TwoBytes[2]; |
| 5761 | |
| 5762 | if ( !info->xmit_cnt && !info->x_char ) |
| 5763 | return; |
| 5764 | |
| 5765 | /* Select transmit FIFO status readback in TICR */ |
| 5766 | usc_TCmd( info, TCmd_SelectTicrTxFifostatus ); |
| 5767 | |
| 5768 | /* load the Transmit FIFO until FIFOs full or all data sent */ |
| 5769 | |
| 5770 | while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) { |
| 5771 | /* there is more space in the transmit FIFO and */ |
| 5772 | /* there is more data in transmit buffer */ |
| 5773 | |
| 5774 | if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) { |
| 5775 | /* write a 16-bit word from transmit buffer to 16C32 */ |
| 5776 | |
| 5777 | TwoBytes[0] = info->xmit_buf[info->xmit_tail++]; |
| 5778 | info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); |
| 5779 | TwoBytes[1] = info->xmit_buf[info->xmit_tail++]; |
| 5780 | info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); |
| 5781 | |
| 5782 | outw( *((u16 *)TwoBytes), info->io_base + DATAREG); |
| 5783 | |
| 5784 | info->xmit_cnt -= 2; |
| 5785 | info->icount.tx += 2; |
| 5786 | } else { |
| 5787 | /* only 1 byte left to transmit or 1 FIFO slot left */ |
| 5788 | |
| 5789 | outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY), |
| 5790 | info->io_base + CCAR ); |
| 5791 | |
| 5792 | if (info->x_char) { |
| 5793 | /* transmit pending high priority char */ |
| 5794 | outw( info->x_char,info->io_base + CCAR ); |
| 5795 | info->x_char = 0; |
| 5796 | } else { |
| 5797 | outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR ); |
| 5798 | info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); |
| 5799 | info->xmit_cnt--; |
| 5800 | } |
| 5801 | info->icount.tx++; |
| 5802 | } |
| 5803 | } |
| 5804 | |
| 5805 | } /* end of usc_load_txfifo() */ |
| 5806 | |
| 5807 | /* usc_reset() |
| 5808 | * |
| 5809 | * Reset the adapter to a known state and prepare it for further use. |
| 5810 | * |
| 5811 | * Arguments: info pointer to device instance data |
| 5812 | * Return Value: None |
| 5813 | */ |
| 5814 | static void usc_reset( struct mgsl_struct *info ) |
| 5815 | { |
| 5816 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
| 5817 | int i; |
| 5818 | u32 readval; |
| 5819 | |
| 5820 | /* Set BIT30 of Misc Control Register */ |
| 5821 | /* (Local Control Register 0x50) to force reset of USC. */ |
| 5822 | |
| 5823 | volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); |
| 5824 | u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28); |
| 5825 | |
| 5826 | info->misc_ctrl_value |= BIT30; |
| 5827 | *MiscCtrl = info->misc_ctrl_value; |
| 5828 | |
| 5829 | /* |
| 5830 | * Force at least 170ns delay before clearing |
| 5831 | * reset bit. Each read from LCR takes at least |
| 5832 | * 30ns so 10 times for 300ns to be safe. |
| 5833 | */ |
| 5834 | for(i=0;i<10;i++) |
| 5835 | readval = *MiscCtrl; |
| 5836 | |
| 5837 | info->misc_ctrl_value &= ~BIT30; |
| 5838 | *MiscCtrl = info->misc_ctrl_value; |
| 5839 | |
| 5840 | *LCR0BRDR = BUS_DESCRIPTOR( |
| 5841 | 1, // Write Strobe Hold (0-3) |
| 5842 | 2, // Write Strobe Delay (0-3) |
| 5843 | 2, // Read Strobe Delay (0-3) |
| 5844 | 0, // NWDD (Write data-data) (0-3) |
| 5845 | 4, // NWAD (Write Addr-data) (0-31) |
| 5846 | 0, // NXDA (Read/Write Data-Addr) (0-3) |
| 5847 | 0, // NRDD (Read Data-Data) (0-3) |
| 5848 | 5 // NRAD (Read Addr-Data) (0-31) |
| 5849 | ); |
| 5850 | } else { |
| 5851 | /* do HW reset */ |
| 5852 | outb( 0,info->io_base + 8 ); |
| 5853 | } |
| 5854 | |
| 5855 | info->mbre_bit = 0; |
| 5856 | info->loopback_bits = 0; |
| 5857 | info->usc_idle_mode = 0; |
| 5858 | |
| 5859 | /* |
| 5860 | * Program the Bus Configuration Register (BCR) |
| 5861 | * |
| 5862 | * <15> 0 Don't use separate address |
| 5863 | * <14..6> 0 reserved |
| 5864 | * <5..4> 00 IAckmode = Default, don't care |
| 5865 | * <3> 1 Bus Request Totem Pole output |
| 5866 | * <2> 1 Use 16 Bit data bus |
| 5867 | * <1> 0 IRQ Totem Pole output |
| 5868 | * <0> 0 Don't Shift Right Addr |
| 5869 | * |
| 5870 | * 0000 0000 0000 1100 = 0x000c |
| 5871 | * |
| 5872 | * By writing to io_base + SDPIN the Wait/Ack pin is |
| 5873 | * programmed to work as a Wait pin. |
| 5874 | */ |
| 5875 | |
| 5876 | outw( 0x000c,info->io_base + SDPIN ); |
| 5877 | |
| 5878 | |
| 5879 | outw( 0,info->io_base ); |
| 5880 | outw( 0,info->io_base + CCAR ); |
| 5881 | |
| 5882 | /* select little endian byte ordering */ |
| 5883 | usc_RTCmd( info, RTCmd_SelectLittleEndian ); |
| 5884 | |
| 5885 | |
| 5886 | /* Port Control Register (PCR) |
| 5887 | * |
| 5888 | * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled) |
| 5889 | * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled) |
| 5890 | * <11..10> 00 Port 5 is Input (No Connect, Don't Care) |
| 5891 | * <9..8> 00 Port 4 is Input (No Connect, Don't Care) |
| 5892 | * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled ) |
| 5893 | * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled ) |
| 5894 | * <3..2> 01 Port 1 is Input (Dedicated RxC) |
| 5895 | * <1..0> 01 Port 0 is Input (Dedicated TxC) |
| 5896 | * |
| 5897 | * 1111 0000 1111 0101 = 0xf0f5 |
| 5898 | */ |
| 5899 | |
| 5900 | usc_OutReg( info, PCR, 0xf0f5 ); |
| 5901 | |
| 5902 | |
| 5903 | /* |
| 5904 | * Input/Output Control Register |
| 5905 | * |
| 5906 | * <15..14> 00 CTS is active low input |
| 5907 | * <13..12> 00 DCD is active low input |
| 5908 | * <11..10> 00 TxREQ pin is input (DSR) |
| 5909 | * <9..8> 00 RxREQ pin is input (RI) |
| 5910 | * <7..6> 00 TxD is output (Transmit Data) |
| 5911 | * <5..3> 000 TxC Pin in Input (14.7456MHz Clock) |
| 5912 | * <2..0> 100 RxC is Output (drive with BRG0) |
| 5913 | * |
| 5914 | * 0000 0000 0000 0100 = 0x0004 |
| 5915 | */ |
| 5916 | |
| 5917 | usc_OutReg( info, IOCR, 0x0004 ); |
| 5918 | |
| 5919 | } /* end of usc_reset() */ |
| 5920 | |
| 5921 | /* usc_set_async_mode() |
| 5922 | * |
| 5923 | * Program adapter for asynchronous communications. |
| 5924 | * |
| 5925 | * Arguments: info pointer to device instance data |
| 5926 | * Return Value: None |
| 5927 | */ |
| 5928 | static void usc_set_async_mode( struct mgsl_struct *info ) |
| 5929 | { |
| 5930 | u16 RegValue; |
| 5931 | |
| 5932 | /* disable interrupts while programming USC */ |
| 5933 | usc_DisableMasterIrqBit( info ); |
| 5934 | |
| 5935 | outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */ |
| 5936 | usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */ |
| 5937 | |
| 5938 | usc_loopback_frame( info ); |
| 5939 | |
| 5940 | /* Channel mode Register (CMR) |
| 5941 | * |
| 5942 | * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit |
| 5943 | * <13..12> 00 00 = 16X Clock |
| 5944 | * <11..8> 0000 Transmitter mode = Asynchronous |
| 5945 | * <7..6> 00 reserved? |
| 5946 | * <5..4> 00 Rx Sub modes, 00 = 16X Clock |
| 5947 | * <3..0> 0000 Receiver mode = Asynchronous |
| 5948 | * |
| 5949 | * 0000 0000 0000 0000 = 0x0 |
| 5950 | */ |
| 5951 | |
| 5952 | RegValue = 0; |
| 5953 | if ( info->params.stop_bits != 1 ) |
| 5954 | RegValue |= BIT14; |
| 5955 | usc_OutReg( info, CMR, RegValue ); |
| 5956 | |
| 5957 | |
| 5958 | /* Receiver mode Register (RMR) |
| 5959 | * |
| 5960 | * <15..13> 000 encoding = None |
| 5961 | * <12..08> 00000 reserved (Sync Only) |
| 5962 | * <7..6> 00 Even parity |
| 5963 | * <5> 0 parity disabled |
| 5964 | * <4..2> 000 Receive Char Length = 8 bits |
| 5965 | * <1..0> 00 Disable Receiver |
| 5966 | * |
| 5967 | * 0000 0000 0000 0000 = 0x0 |
| 5968 | */ |
| 5969 | |
| 5970 | RegValue = 0; |
| 5971 | |
| 5972 | if ( info->params.data_bits != 8 ) |
| 5973 | RegValue |= BIT4+BIT3+BIT2; |
| 5974 | |
| 5975 | if ( info->params.parity != ASYNC_PARITY_NONE ) { |
| 5976 | RegValue |= BIT5; |
| 5977 | if ( info->params.parity != ASYNC_PARITY_ODD ) |
| 5978 | RegValue |= BIT6; |
| 5979 | } |
| 5980 | |
| 5981 | usc_OutReg( info, RMR, RegValue ); |
| 5982 | |
| 5983 | |
| 5984 | /* Set IRQ trigger level */ |
| 5985 | |
| 5986 | usc_RCmd( info, RCmd_SelectRicrIntLevel ); |
| 5987 | |
| 5988 | |
| 5989 | /* Receive Interrupt Control Register (RICR) |
| 5990 | * |
| 5991 | * <15..8> ? RxFIFO IRQ Request Level |
| 5992 | * |
| 5993 | * Note: For async mode the receive FIFO level must be set |
Alexey Dobriyan | 7f927fc | 2006-03-28 01:56:53 -0800 | [diff] [blame] | 5994 | * to 0 to avoid the situation where the FIFO contains fewer bytes |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5995 | * than the trigger level and no more data is expected. |
| 5996 | * |
| 5997 | * <7> 0 Exited Hunt IA (Interrupt Arm) |
| 5998 | * <6> 0 Idle Received IA |
| 5999 | * <5> 0 Break/Abort IA |
| 6000 | * <4> 0 Rx Bound IA |
| 6001 | * <3> 0 Queued status reflects oldest byte in FIFO |
| 6002 | * <2> 0 Abort/PE IA |
| 6003 | * <1> 0 Rx Overrun IA |
| 6004 | * <0> 0 Select TC0 value for readback |
| 6005 | * |
| 6006 | * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB) |
| 6007 | */ |
| 6008 | |
| 6009 | usc_OutReg( info, RICR, 0x0000 ); |
| 6010 | |
| 6011 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); |
| 6012 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); |
| 6013 | |
| 6014 | |
| 6015 | /* Transmit mode Register (TMR) |
| 6016 | * |
| 6017 | * <15..13> 000 encoding = None |
| 6018 | * <12..08> 00000 reserved (Sync Only) |
| 6019 | * <7..6> 00 Transmit parity Even |
| 6020 | * <5> 0 Transmit parity Disabled |
| 6021 | * <4..2> 000 Tx Char Length = 8 bits |
| 6022 | * <1..0> 00 Disable Transmitter |
| 6023 | * |
| 6024 | * 0000 0000 0000 0000 = 0x0 |
| 6025 | */ |
| 6026 | |
| 6027 | RegValue = 0; |
| 6028 | |
| 6029 | if ( info->params.data_bits != 8 ) |
| 6030 | RegValue |= BIT4+BIT3+BIT2; |
| 6031 | |
| 6032 | if ( info->params.parity != ASYNC_PARITY_NONE ) { |
| 6033 | RegValue |= BIT5; |
| 6034 | if ( info->params.parity != ASYNC_PARITY_ODD ) |
| 6035 | RegValue |= BIT6; |
| 6036 | } |
| 6037 | |
| 6038 | usc_OutReg( info, TMR, RegValue ); |
| 6039 | |
| 6040 | usc_set_txidle( info ); |
| 6041 | |
| 6042 | |
| 6043 | /* Set IRQ trigger level */ |
| 6044 | |
| 6045 | usc_TCmd( info, TCmd_SelectTicrIntLevel ); |
| 6046 | |
| 6047 | |
| 6048 | /* Transmit Interrupt Control Register (TICR) |
| 6049 | * |
| 6050 | * <15..8> ? Transmit FIFO IRQ Level |
| 6051 | * <7> 0 Present IA (Interrupt Arm) |
| 6052 | * <6> 1 Idle Sent IA |
| 6053 | * <5> 0 Abort Sent IA |
| 6054 | * <4> 0 EOF/EOM Sent IA |
| 6055 | * <3> 0 CRC Sent IA |
| 6056 | * <2> 0 1 = Wait for SW Trigger to Start Frame |
| 6057 | * <1> 0 Tx Underrun IA |
| 6058 | * <0> 0 TC0 constant on read back |
| 6059 | * |
| 6060 | * 0000 0000 0100 0000 = 0x0040 |
| 6061 | */ |
| 6062 | |
| 6063 | usc_OutReg( info, TICR, 0x1f40 ); |
| 6064 | |
| 6065 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); |
| 6066 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); |
| 6067 | |
| 6068 | usc_enable_async_clock( info, info->params.data_rate ); |
| 6069 | |
| 6070 | |
| 6071 | /* Channel Control/status Register (CCSR) |
| 6072 | * |
| 6073 | * <15> X RCC FIFO Overflow status (RO) |
| 6074 | * <14> X RCC FIFO Not Empty status (RO) |
| 6075 | * <13> 0 1 = Clear RCC FIFO (WO) |
| 6076 | * <12> X DPLL in Sync status (RO) |
| 6077 | * <11> X DPLL 2 Missed Clocks status (RO) |
| 6078 | * <10> X DPLL 1 Missed Clock status (RO) |
| 6079 | * <9..8> 00 DPLL Resync on rising and falling edges (RW) |
| 6080 | * <7> X SDLC Loop On status (RO) |
| 6081 | * <6> X SDLC Loop Send status (RO) |
| 6082 | * <5> 1 Bypass counters for TxClk and RxClk (RW) |
| 6083 | * <4..2> 000 Last Char of SDLC frame has 8 bits (RW) |
| 6084 | * <1..0> 00 reserved |
| 6085 | * |
| 6086 | * 0000 0000 0010 0000 = 0x0020 |
| 6087 | */ |
| 6088 | |
| 6089 | usc_OutReg( info, CCSR, 0x0020 ); |
| 6090 | |
| 6091 | usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA + |
| 6092 | RECEIVE_DATA + RECEIVE_STATUS ); |
| 6093 | |
| 6094 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA + |
| 6095 | RECEIVE_DATA + RECEIVE_STATUS ); |
| 6096 | |
| 6097 | usc_EnableMasterIrqBit( info ); |
| 6098 | |
| 6099 | if (info->bus_type == MGSL_BUS_TYPE_ISA) { |
| 6100 | /* Enable INTEN (Port 6, Bit12) */ |
| 6101 | /* This connects the IRQ request signal to the ISA bus */ |
| 6102 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); |
| 6103 | } |
| 6104 | |
Paul Fulghum | 7c1fff5 | 2005-09-09 13:02:14 -0700 | [diff] [blame] | 6105 | if (info->params.loopback) { |
| 6106 | info->loopback_bits = 0x300; |
| 6107 | outw(0x0300, info->io_base + CCAR); |
| 6108 | } |
| 6109 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6110 | } /* end of usc_set_async_mode() */ |
| 6111 | |
| 6112 | /* usc_loopback_frame() |
| 6113 | * |
| 6114 | * Loop back a small (2 byte) dummy SDLC frame. |
| 6115 | * Interrupts and DMA are NOT used. The purpose of this is to |
| 6116 | * clear any 'stale' status info left over from running in async mode. |
| 6117 | * |
| 6118 | * The 16C32 shows the strange behaviour of marking the 1st |
| 6119 | * received SDLC frame with a CRC error even when there is no |
| 6120 | * CRC error. To get around this a small dummy from of 2 bytes |
| 6121 | * is looped back when switching from async to sync mode. |
| 6122 | * |
| 6123 | * Arguments: info pointer to device instance data |
| 6124 | * Return Value: None |
| 6125 | */ |
| 6126 | static void usc_loopback_frame( struct mgsl_struct *info ) |
| 6127 | { |
| 6128 | int i; |
| 6129 | unsigned long oldmode = info->params.mode; |
| 6130 | |
| 6131 | info->params.mode = MGSL_MODE_HDLC; |
| 6132 | |
| 6133 | usc_DisableMasterIrqBit( info ); |
| 6134 | |
| 6135 | usc_set_sdlc_mode( info ); |
| 6136 | usc_enable_loopback( info, 1 ); |
| 6137 | |
| 6138 | /* Write 16-bit Time Constant for BRG0 */ |
| 6139 | usc_OutReg( info, TC0R, 0 ); |
| 6140 | |
| 6141 | /* Channel Control Register (CCR) |
| 6142 | * |
| 6143 | * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs) |
| 6144 | * <13> 0 Trigger Tx on SW Command Disabled |
| 6145 | * <12> 0 Flag Preamble Disabled |
| 6146 | * <11..10> 00 Preamble Length = 8-Bits |
| 6147 | * <9..8> 01 Preamble Pattern = flags |
| 6148 | * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs) |
| 6149 | * <5> 0 Trigger Rx on SW Command Disabled |
| 6150 | * <4..0> 0 reserved |
| 6151 | * |
| 6152 | * 0000 0001 0000 0000 = 0x0100 |
| 6153 | */ |
| 6154 | |
| 6155 | usc_OutReg( info, CCR, 0x0100 ); |
| 6156 | |
| 6157 | /* SETUP RECEIVER */ |
| 6158 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 6159 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); |
| 6160 | |
| 6161 | /* SETUP TRANSMITTER */ |
| 6162 | /* Program the Transmit Character Length Register (TCLR) */ |
| 6163 | /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */ |
| 6164 | usc_OutReg( info, TCLR, 2 ); |
| 6165 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
| 6166 | |
| 6167 | /* unlatch Tx status bits, and start transmit channel. */ |
| 6168 | usc_UnlatchTxstatusBits(info,TXSTATUS_ALL); |
| 6169 | outw(0,info->io_base + DATAREG); |
| 6170 | |
| 6171 | /* ENABLE TRANSMITTER */ |
| 6172 | usc_TCmd( info, TCmd_SendFrame ); |
| 6173 | usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL); |
| 6174 | |
| 6175 | /* WAIT FOR RECEIVE COMPLETE */ |
| 6176 | for (i=0 ; i<1000 ; i++) |
| 6177 | if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1)) |
| 6178 | break; |
| 6179 | |
| 6180 | /* clear Internal Data loopback mode */ |
| 6181 | usc_enable_loopback(info, 0); |
| 6182 | |
| 6183 | usc_EnableMasterIrqBit(info); |
| 6184 | |
| 6185 | info->params.mode = oldmode; |
| 6186 | |
| 6187 | } /* end of usc_loopback_frame() */ |
| 6188 | |
| 6189 | /* usc_set_sync_mode() Programs the USC for SDLC communications. |
| 6190 | * |
| 6191 | * Arguments: info pointer to adapter info structure |
| 6192 | * Return Value: None |
| 6193 | */ |
| 6194 | static void usc_set_sync_mode( struct mgsl_struct *info ) |
| 6195 | { |
| 6196 | usc_loopback_frame( info ); |
| 6197 | usc_set_sdlc_mode( info ); |
| 6198 | |
| 6199 | if (info->bus_type == MGSL_BUS_TYPE_ISA) { |
| 6200 | /* Enable INTEN (Port 6, Bit12) */ |
| 6201 | /* This connects the IRQ request signal to the ISA bus */ |
| 6202 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); |
| 6203 | } |
| 6204 | |
| 6205 | usc_enable_aux_clock(info, info->params.clock_speed); |
| 6206 | |
| 6207 | if (info->params.loopback) |
| 6208 | usc_enable_loopback(info,1); |
| 6209 | |
| 6210 | } /* end of mgsl_set_sync_mode() */ |
| 6211 | |
| 6212 | /* usc_set_txidle() Set the HDLC idle mode for the transmitter. |
| 6213 | * |
| 6214 | * Arguments: info pointer to device instance data |
| 6215 | * Return Value: None |
| 6216 | */ |
| 6217 | static void usc_set_txidle( struct mgsl_struct *info ) |
| 6218 | { |
| 6219 | u16 usc_idle_mode = IDLEMODE_FLAGS; |
| 6220 | |
| 6221 | /* Map API idle mode to USC register bits */ |
| 6222 | |
| 6223 | switch( info->idle_mode ){ |
| 6224 | case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break; |
| 6225 | case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break; |
| 6226 | case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break; |
| 6227 | case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break; |
| 6228 | case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break; |
| 6229 | case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break; |
| 6230 | case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break; |
| 6231 | } |
| 6232 | |
| 6233 | info->usc_idle_mode = usc_idle_mode; |
| 6234 | //usc_OutReg(info, TCSR, usc_idle_mode); |
| 6235 | info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */ |
| 6236 | info->tcsr_value += usc_idle_mode; |
| 6237 | usc_OutReg(info, TCSR, info->tcsr_value); |
| 6238 | |
| 6239 | /* |
| 6240 | * if SyncLink WAN adapter is running in external sync mode, the |
| 6241 | * transmitter has been set to Monosync in order to try to mimic |
| 6242 | * a true raw outbound bit stream. Monosync still sends an open/close |
| 6243 | * sync char at the start/end of a frame. Try to match those sync |
| 6244 | * patterns to the idle mode set here |
| 6245 | */ |
| 6246 | if ( info->params.mode == MGSL_MODE_RAW ) { |
| 6247 | unsigned char syncpat = 0; |
| 6248 | switch( info->idle_mode ) { |
| 6249 | case HDLC_TXIDLE_FLAGS: |
| 6250 | syncpat = 0x7e; |
| 6251 | break; |
| 6252 | case HDLC_TXIDLE_ALT_ZEROS_ONES: |
| 6253 | syncpat = 0x55; |
| 6254 | break; |
| 6255 | case HDLC_TXIDLE_ZEROS: |
| 6256 | case HDLC_TXIDLE_SPACE: |
| 6257 | syncpat = 0x00; |
| 6258 | break; |
| 6259 | case HDLC_TXIDLE_ONES: |
| 6260 | case HDLC_TXIDLE_MARK: |
| 6261 | syncpat = 0xff; |
| 6262 | break; |
| 6263 | case HDLC_TXIDLE_ALT_MARK_SPACE: |
| 6264 | syncpat = 0xaa; |
| 6265 | break; |
| 6266 | } |
| 6267 | |
| 6268 | usc_SetTransmitSyncChars(info,syncpat,syncpat); |
| 6269 | } |
| 6270 | |
| 6271 | } /* end of usc_set_txidle() */ |
| 6272 | |
| 6273 | /* usc_get_serial_signals() |
| 6274 | * |
| 6275 | * Query the adapter for the state of the V24 status (input) signals. |
| 6276 | * |
| 6277 | * Arguments: info pointer to device instance data |
| 6278 | * Return Value: None |
| 6279 | */ |
| 6280 | static void usc_get_serial_signals( struct mgsl_struct *info ) |
| 6281 | { |
| 6282 | u16 status; |
| 6283 | |
| 6284 | /* clear all serial signals except DTR and RTS */ |
| 6285 | info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS; |
| 6286 | |
| 6287 | /* Read the Misc Interrupt status Register (MISR) to get */ |
| 6288 | /* the V24 status signals. */ |
| 6289 | |
| 6290 | status = usc_InReg( info, MISR ); |
| 6291 | |
| 6292 | /* set serial signal bits to reflect MISR */ |
| 6293 | |
| 6294 | if ( status & MISCSTATUS_CTS ) |
| 6295 | info->serial_signals |= SerialSignal_CTS; |
| 6296 | |
| 6297 | if ( status & MISCSTATUS_DCD ) |
| 6298 | info->serial_signals |= SerialSignal_DCD; |
| 6299 | |
| 6300 | if ( status & MISCSTATUS_RI ) |
| 6301 | info->serial_signals |= SerialSignal_RI; |
| 6302 | |
| 6303 | if ( status & MISCSTATUS_DSR ) |
| 6304 | info->serial_signals |= SerialSignal_DSR; |
| 6305 | |
| 6306 | } /* end of usc_get_serial_signals() */ |
| 6307 | |
| 6308 | /* usc_set_serial_signals() |
| 6309 | * |
| 6310 | * Set the state of DTR and RTS based on contents of |
| 6311 | * serial_signals member of device extension. |
| 6312 | * |
| 6313 | * Arguments: info pointer to device instance data |
| 6314 | * Return Value: None |
| 6315 | */ |
| 6316 | static void usc_set_serial_signals( struct mgsl_struct *info ) |
| 6317 | { |
| 6318 | u16 Control; |
| 6319 | unsigned char V24Out = info->serial_signals; |
| 6320 | |
| 6321 | /* get the current value of the Port Control Register (PCR) */ |
| 6322 | |
| 6323 | Control = usc_InReg( info, PCR ); |
| 6324 | |
| 6325 | if ( V24Out & SerialSignal_RTS ) |
| 6326 | Control &= ~(BIT6); |
| 6327 | else |
| 6328 | Control |= BIT6; |
| 6329 | |
| 6330 | if ( V24Out & SerialSignal_DTR ) |
| 6331 | Control &= ~(BIT4); |
| 6332 | else |
| 6333 | Control |= BIT4; |
| 6334 | |
| 6335 | usc_OutReg( info, PCR, Control ); |
| 6336 | |
| 6337 | } /* end of usc_set_serial_signals() */ |
| 6338 | |
| 6339 | /* usc_enable_async_clock() |
| 6340 | * |
| 6341 | * Enable the async clock at the specified frequency. |
| 6342 | * |
| 6343 | * Arguments: info pointer to device instance data |
| 6344 | * data_rate data rate of clock in bps |
| 6345 | * 0 disables the AUX clock. |
| 6346 | * Return Value: None |
| 6347 | */ |
| 6348 | static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate ) |
| 6349 | { |
| 6350 | if ( data_rate ) { |
| 6351 | /* |
| 6352 | * Clock mode Control Register (CMCR) |
| 6353 | * |
| 6354 | * <15..14> 00 counter 1 Disabled |
| 6355 | * <13..12> 00 counter 0 Disabled |
| 6356 | * <11..10> 11 BRG1 Input is TxC Pin |
| 6357 | * <9..8> 11 BRG0 Input is TxC Pin |
| 6358 | * <7..6> 01 DPLL Input is BRG1 Output |
| 6359 | * <5..3> 100 TxCLK comes from BRG0 |
| 6360 | * <2..0> 100 RxCLK comes from BRG0 |
| 6361 | * |
| 6362 | * 0000 1111 0110 0100 = 0x0f64 |
| 6363 | */ |
| 6364 | |
| 6365 | usc_OutReg( info, CMCR, 0x0f64 ); |
| 6366 | |
| 6367 | |
| 6368 | /* |
| 6369 | * Write 16-bit Time Constant for BRG0 |
| 6370 | * Time Constant = (ClkSpeed / data_rate) - 1 |
| 6371 | * ClkSpeed = 921600 (ISA), 691200 (PCI) |
| 6372 | */ |
| 6373 | |
| 6374 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 6375 | usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) ); |
| 6376 | else |
| 6377 | usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) ); |
| 6378 | |
| 6379 | |
| 6380 | /* |
| 6381 | * Hardware Configuration Register (HCR) |
| 6382 | * Clear Bit 1, BRG0 mode = Continuous |
| 6383 | * Set Bit 0 to enable BRG0. |
| 6384 | */ |
| 6385 | |
| 6386 | usc_OutReg( info, HCR, |
| 6387 | (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); |
| 6388 | |
| 6389 | |
| 6390 | /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */ |
| 6391 | |
| 6392 | usc_OutReg( info, IOCR, |
| 6393 | (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); |
| 6394 | } else { |
| 6395 | /* data rate == 0 so turn off BRG0 */ |
| 6396 | usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); |
| 6397 | } |
| 6398 | |
| 6399 | } /* end of usc_enable_async_clock() */ |
| 6400 | |
| 6401 | /* |
| 6402 | * Buffer Structures: |
| 6403 | * |
| 6404 | * Normal memory access uses virtual addresses that can make discontiguous |
| 6405 | * physical memory pages appear to be contiguous in the virtual address |
| 6406 | * space (the processors memory mapping handles the conversions). |
| 6407 | * |
| 6408 | * DMA transfers require physically contiguous memory. This is because |
| 6409 | * the DMA system controller and DMA bus masters deal with memory using |
| 6410 | * only physical addresses. |
| 6411 | * |
| 6412 | * This causes a problem under Windows NT when large DMA buffers are |
| 6413 | * needed. Fragmentation of the nonpaged pool prevents allocations of |
| 6414 | * physically contiguous buffers larger than the PAGE_SIZE. |
| 6415 | * |
| 6416 | * However the 16C32 supports Bus Master Scatter/Gather DMA which |
| 6417 | * allows DMA transfers to physically discontiguous buffers. Information |
| 6418 | * about each data transfer buffer is contained in a memory structure |
| 6419 | * called a 'buffer entry'. A list of buffer entries is maintained |
| 6420 | * to track and control the use of the data transfer buffers. |
| 6421 | * |
| 6422 | * To support this strategy we will allocate sufficient PAGE_SIZE |
| 6423 | * contiguous memory buffers to allow for the total required buffer |
| 6424 | * space. |
| 6425 | * |
| 6426 | * The 16C32 accesses the list of buffer entries using Bus Master |
| 6427 | * DMA. Control information is read from the buffer entries by the |
| 6428 | * 16C32 to control data transfers. status information is written to |
| 6429 | * the buffer entries by the 16C32 to indicate the status of completed |
| 6430 | * transfers. |
| 6431 | * |
| 6432 | * The CPU writes control information to the buffer entries to control |
| 6433 | * the 16C32 and reads status information from the buffer entries to |
| 6434 | * determine information about received and transmitted frames. |
| 6435 | * |
| 6436 | * Because the CPU and 16C32 (adapter) both need simultaneous access |
| 6437 | * to the buffer entries, the buffer entry memory is allocated with |
| 6438 | * HalAllocateCommonBuffer(). This restricts the size of the buffer |
| 6439 | * entry list to PAGE_SIZE. |
| 6440 | * |
| 6441 | * The actual data buffers on the other hand will only be accessed |
| 6442 | * by the CPU or the adapter but not by both simultaneously. This allows |
| 6443 | * Scatter/Gather packet based DMA procedures for using physically |
| 6444 | * discontiguous pages. |
| 6445 | */ |
| 6446 | |
| 6447 | /* |
| 6448 | * mgsl_reset_tx_dma_buffers() |
| 6449 | * |
| 6450 | * Set the count for all transmit buffers to 0 to indicate the |
| 6451 | * buffer is available for use and set the current buffer to the |
| 6452 | * first buffer. This effectively makes all buffers free and |
| 6453 | * discards any data in buffers. |
| 6454 | * |
| 6455 | * Arguments: info pointer to device instance data |
| 6456 | * Return Value: None |
| 6457 | */ |
| 6458 | static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info ) |
| 6459 | { |
| 6460 | unsigned int i; |
| 6461 | |
| 6462 | for ( i = 0; i < info->tx_buffer_count; i++ ) { |
| 6463 | *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0; |
| 6464 | } |
| 6465 | |
| 6466 | info->current_tx_buffer = 0; |
| 6467 | info->start_tx_dma_buffer = 0; |
| 6468 | info->tx_dma_buffers_used = 0; |
| 6469 | |
| 6470 | info->get_tx_holding_index = 0; |
| 6471 | info->put_tx_holding_index = 0; |
| 6472 | info->tx_holding_count = 0; |
| 6473 | |
| 6474 | } /* end of mgsl_reset_tx_dma_buffers() */ |
| 6475 | |
| 6476 | /* |
| 6477 | * num_free_tx_dma_buffers() |
| 6478 | * |
| 6479 | * returns the number of free tx dma buffers available |
| 6480 | * |
| 6481 | * Arguments: info pointer to device instance data |
| 6482 | * Return Value: number of free tx dma buffers |
| 6483 | */ |
| 6484 | static int num_free_tx_dma_buffers(struct mgsl_struct *info) |
| 6485 | { |
| 6486 | return info->tx_buffer_count - info->tx_dma_buffers_used; |
| 6487 | } |
| 6488 | |
| 6489 | /* |
| 6490 | * mgsl_reset_rx_dma_buffers() |
| 6491 | * |
| 6492 | * Set the count for all receive buffers to DMABUFFERSIZE |
| 6493 | * and set the current buffer to the first buffer. This effectively |
| 6494 | * makes all buffers free and discards any data in buffers. |
| 6495 | * |
| 6496 | * Arguments: info pointer to device instance data |
| 6497 | * Return Value: None |
| 6498 | */ |
| 6499 | static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ) |
| 6500 | { |
| 6501 | unsigned int i; |
| 6502 | |
| 6503 | for ( i = 0; i < info->rx_buffer_count; i++ ) { |
| 6504 | *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE; |
| 6505 | // info->rx_buffer_list[i].count = DMABUFFERSIZE; |
| 6506 | // info->rx_buffer_list[i].status = 0; |
| 6507 | } |
| 6508 | |
| 6509 | info->current_rx_buffer = 0; |
| 6510 | |
| 6511 | } /* end of mgsl_reset_rx_dma_buffers() */ |
| 6512 | |
| 6513 | /* |
| 6514 | * mgsl_free_rx_frame_buffers() |
| 6515 | * |
| 6516 | * Free the receive buffers used by a received SDLC |
| 6517 | * frame such that the buffers can be reused. |
| 6518 | * |
| 6519 | * Arguments: |
| 6520 | * |
| 6521 | * info pointer to device instance data |
| 6522 | * StartIndex index of 1st receive buffer of frame |
| 6523 | * EndIndex index of last receive buffer of frame |
| 6524 | * |
| 6525 | * Return Value: None |
| 6526 | */ |
| 6527 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ) |
| 6528 | { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6529 | bool Done = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6530 | DMABUFFERENTRY *pBufEntry; |
| 6531 | unsigned int Index; |
| 6532 | |
| 6533 | /* Starting with 1st buffer entry of the frame clear the status */ |
| 6534 | /* field and set the count field to DMA Buffer Size. */ |
| 6535 | |
| 6536 | Index = StartIndex; |
| 6537 | |
| 6538 | while( !Done ) { |
| 6539 | pBufEntry = &(info->rx_buffer_list[Index]); |
| 6540 | |
| 6541 | if ( Index == EndIndex ) { |
| 6542 | /* This is the last buffer of the frame! */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6543 | Done = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6544 | } |
| 6545 | |
| 6546 | /* reset current buffer for reuse */ |
| 6547 | // pBufEntry->status = 0; |
| 6548 | // pBufEntry->count = DMABUFFERSIZE; |
| 6549 | *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE; |
| 6550 | |
| 6551 | /* advance to next buffer entry in linked list */ |
| 6552 | Index++; |
| 6553 | if ( Index == info->rx_buffer_count ) |
| 6554 | Index = 0; |
| 6555 | } |
| 6556 | |
| 6557 | /* set current buffer to next buffer after last buffer of frame */ |
| 6558 | info->current_rx_buffer = Index; |
| 6559 | |
| 6560 | } /* end of free_rx_frame_buffers() */ |
| 6561 | |
| 6562 | /* mgsl_get_rx_frame() |
| 6563 | * |
| 6564 | * This function attempts to return a received SDLC frame from the |
| 6565 | * receive DMA buffers. Only frames received without errors are returned. |
| 6566 | * |
| 6567 | * Arguments: info pointer to device extension |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6568 | * Return Value: true if frame returned, otherwise false |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6569 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6570 | static bool mgsl_get_rx_frame(struct mgsl_struct *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6571 | { |
| 6572 | unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ |
| 6573 | unsigned short status; |
| 6574 | DMABUFFERENTRY *pBufEntry; |
| 6575 | unsigned int framesize = 0; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6576 | bool ReturnCode = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6577 | unsigned long flags; |
| 6578 | struct tty_struct *tty = info->tty; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6579 | bool return_frame = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6580 | |
| 6581 | /* |
| 6582 | * current_rx_buffer points to the 1st buffer of the next available |
| 6583 | * receive frame. To find the last buffer of the frame look for |
| 6584 | * a non-zero status field in the buffer entries. (The status |
| 6585 | * field is set by the 16C32 after completing a receive frame. |
| 6586 | */ |
| 6587 | |
| 6588 | StartIndex = EndIndex = info->current_rx_buffer; |
| 6589 | |
| 6590 | while( !info->rx_buffer_list[EndIndex].status ) { |
| 6591 | /* |
| 6592 | * If the count field of the buffer entry is non-zero then |
| 6593 | * this buffer has not been used. (The 16C32 clears the count |
| 6594 | * field when it starts using the buffer.) If an unused buffer |
| 6595 | * is encountered then there are no frames available. |
| 6596 | */ |
| 6597 | |
| 6598 | if ( info->rx_buffer_list[EndIndex].count ) |
| 6599 | goto Cleanup; |
| 6600 | |
| 6601 | /* advance to next buffer entry in linked list */ |
| 6602 | EndIndex++; |
| 6603 | if ( EndIndex == info->rx_buffer_count ) |
| 6604 | EndIndex = 0; |
| 6605 | |
| 6606 | /* if entire list searched then no frame available */ |
| 6607 | if ( EndIndex == StartIndex ) { |
| 6608 | /* If this occurs then something bad happened, |
| 6609 | * all buffers have been 'used' but none mark |
| 6610 | * the end of a frame. Reset buffers and receiver. |
| 6611 | */ |
| 6612 | |
| 6613 | if ( info->rx_enabled ){ |
| 6614 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 6615 | usc_start_receiver(info); |
| 6616 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 6617 | } |
| 6618 | goto Cleanup; |
| 6619 | } |
| 6620 | } |
| 6621 | |
| 6622 | |
| 6623 | /* check status of receive frame */ |
| 6624 | |
| 6625 | status = info->rx_buffer_list[EndIndex].status; |
| 6626 | |
| 6627 | if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN + |
| 6628 | RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) { |
| 6629 | if ( status & RXSTATUS_SHORT_FRAME ) |
| 6630 | info->icount.rxshort++; |
| 6631 | else if ( status & RXSTATUS_ABORT ) |
| 6632 | info->icount.rxabort++; |
| 6633 | else if ( status & RXSTATUS_OVERRUN ) |
| 6634 | info->icount.rxover++; |
| 6635 | else { |
| 6636 | info->icount.rxcrc++; |
| 6637 | if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6638 | return_frame = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6639 | } |
| 6640 | framesize = 0; |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 6641 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6642 | { |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 6643 | info->netdev->stats.rx_errors++; |
| 6644 | info->netdev->stats.rx_frame_errors++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6645 | } |
| 6646 | #endif |
| 6647 | } else |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6648 | return_frame = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6649 | |
| 6650 | if ( return_frame ) { |
| 6651 | /* receive frame has no errors, get frame size. |
| 6652 | * The frame size is the starting value of the RCC (which was |
| 6653 | * set to 0xffff) minus the ending value of the RCC (decremented |
| 6654 | * once for each receive character) minus 2 for the 16-bit CRC. |
| 6655 | */ |
| 6656 | |
| 6657 | framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc; |
| 6658 | |
| 6659 | /* adjust frame size for CRC if any */ |
| 6660 | if ( info->params.crc_type == HDLC_CRC_16_CCITT ) |
| 6661 | framesize -= 2; |
| 6662 | else if ( info->params.crc_type == HDLC_CRC_32_CCITT ) |
| 6663 | framesize -= 4; |
| 6664 | } |
| 6665 | |
| 6666 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 6667 | printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n", |
| 6668 | __FILE__,__LINE__,info->device_name,status,framesize); |
| 6669 | |
| 6670 | if ( debug_level >= DEBUG_LEVEL_DATA ) |
| 6671 | mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr, |
| 6672 | min_t(int, framesize, DMABUFFERSIZE),0); |
| 6673 | |
| 6674 | if (framesize) { |
| 6675 | if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) && |
| 6676 | ((framesize+1) > info->max_frame_size) ) || |
| 6677 | (framesize > info->max_frame_size) ) |
| 6678 | info->icount.rxlong++; |
| 6679 | else { |
| 6680 | /* copy dma buffer(s) to contiguous intermediate buffer */ |
| 6681 | int copy_count = framesize; |
| 6682 | int index = StartIndex; |
| 6683 | unsigned char *ptmp = info->intermediate_rxbuffer; |
| 6684 | |
| 6685 | if ( !(status & RXSTATUS_CRC_ERROR)) |
| 6686 | info->icount.rxok++; |
| 6687 | |
| 6688 | while(copy_count) { |
| 6689 | int partial_count; |
| 6690 | if ( copy_count > DMABUFFERSIZE ) |
| 6691 | partial_count = DMABUFFERSIZE; |
| 6692 | else |
| 6693 | partial_count = copy_count; |
| 6694 | |
| 6695 | pBufEntry = &(info->rx_buffer_list[index]); |
| 6696 | memcpy( ptmp, pBufEntry->virt_addr, partial_count ); |
| 6697 | ptmp += partial_count; |
| 6698 | copy_count -= partial_count; |
| 6699 | |
| 6700 | if ( ++index == info->rx_buffer_count ) |
| 6701 | index = 0; |
| 6702 | } |
| 6703 | |
| 6704 | if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) { |
| 6705 | ++framesize; |
| 6706 | *ptmp = (status & RXSTATUS_CRC_ERROR ? |
| 6707 | RX_CRC_ERROR : |
| 6708 | RX_OK); |
| 6709 | |
| 6710 | if ( debug_level >= DEBUG_LEVEL_DATA ) |
| 6711 | printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n", |
| 6712 | __FILE__,__LINE__,info->device_name, |
| 6713 | *ptmp); |
| 6714 | } |
| 6715 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 6716 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6717 | if (info->netcount) |
| 6718 | hdlcdev_rx(info,info->intermediate_rxbuffer,framesize); |
| 6719 | else |
| 6720 | #endif |
| 6721 | ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize); |
| 6722 | } |
| 6723 | } |
| 6724 | /* Free the buffers used by this frame. */ |
| 6725 | mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex ); |
| 6726 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6727 | ReturnCode = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6728 | |
| 6729 | Cleanup: |
| 6730 | |
| 6731 | if ( info->rx_enabled && info->rx_overflow ) { |
| 6732 | /* The receiver needs to restarted because of |
| 6733 | * a receive overflow (buffer or FIFO). If the |
| 6734 | * receive buffers are now empty, then restart receiver. |
| 6735 | */ |
| 6736 | |
| 6737 | if ( !info->rx_buffer_list[EndIndex].status && |
| 6738 | info->rx_buffer_list[EndIndex].count ) { |
| 6739 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 6740 | usc_start_receiver(info); |
| 6741 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 6742 | } |
| 6743 | } |
| 6744 | |
| 6745 | return ReturnCode; |
| 6746 | |
| 6747 | } /* end of mgsl_get_rx_frame() */ |
| 6748 | |
| 6749 | /* mgsl_get_raw_rx_frame() |
| 6750 | * |
| 6751 | * This function attempts to return a received frame from the |
| 6752 | * receive DMA buffers when running in external loop mode. In this mode, |
| 6753 | * we will return at most one DMABUFFERSIZE frame to the application. |
| 6754 | * The USC receiver is triggering off of DCD going active to start a new |
| 6755 | * frame, and DCD going inactive to terminate the frame (similar to |
| 6756 | * processing a closing flag character). |
| 6757 | * |
| 6758 | * In this routine, we will return DMABUFFERSIZE "chunks" at a time. |
| 6759 | * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero |
| 6760 | * status field and the RCC field will indicate the length of the |
| 6761 | * entire received frame. We take this RCC field and get the modulus |
| 6762 | * of RCC and DMABUFFERSIZE to determine if number of bytes in the |
| 6763 | * last Rx DMA buffer and return that last portion of the frame. |
| 6764 | * |
| 6765 | * Arguments: info pointer to device extension |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6766 | * Return Value: true if frame returned, otherwise false |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6767 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6768 | static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6769 | { |
| 6770 | unsigned int CurrentIndex, NextIndex; |
| 6771 | unsigned short status; |
| 6772 | DMABUFFERENTRY *pBufEntry; |
| 6773 | unsigned int framesize = 0; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6774 | bool ReturnCode = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6775 | unsigned long flags; |
| 6776 | struct tty_struct *tty = info->tty; |
| 6777 | |
| 6778 | /* |
| 6779 | * current_rx_buffer points to the 1st buffer of the next available |
| 6780 | * receive frame. The status field is set by the 16C32 after |
| 6781 | * completing a receive frame. If the status field of this buffer |
| 6782 | * is zero, either the USC is still filling this buffer or this |
| 6783 | * is one of a series of buffers making up a received frame. |
| 6784 | * |
| 6785 | * If the count field of this buffer is zero, the USC is either |
| 6786 | * using this buffer or has used this buffer. Look at the count |
| 6787 | * field of the next buffer. If that next buffer's count is |
| 6788 | * non-zero, the USC is still actively using the current buffer. |
| 6789 | * Otherwise, if the next buffer's count field is zero, the |
| 6790 | * current buffer is complete and the USC is using the next |
| 6791 | * buffer. |
| 6792 | */ |
| 6793 | CurrentIndex = NextIndex = info->current_rx_buffer; |
| 6794 | ++NextIndex; |
| 6795 | if ( NextIndex == info->rx_buffer_count ) |
| 6796 | NextIndex = 0; |
| 6797 | |
| 6798 | if ( info->rx_buffer_list[CurrentIndex].status != 0 || |
| 6799 | (info->rx_buffer_list[CurrentIndex].count == 0 && |
| 6800 | info->rx_buffer_list[NextIndex].count == 0)) { |
| 6801 | /* |
| 6802 | * Either the status field of this dma buffer is non-zero |
| 6803 | * (indicating the last buffer of a receive frame) or the next |
| 6804 | * buffer is marked as in use -- implying this buffer is complete |
| 6805 | * and an intermediate buffer for this received frame. |
| 6806 | */ |
| 6807 | |
| 6808 | status = info->rx_buffer_list[CurrentIndex].status; |
| 6809 | |
| 6810 | if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN + |
| 6811 | RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) { |
| 6812 | if ( status & RXSTATUS_SHORT_FRAME ) |
| 6813 | info->icount.rxshort++; |
| 6814 | else if ( status & RXSTATUS_ABORT ) |
| 6815 | info->icount.rxabort++; |
| 6816 | else if ( status & RXSTATUS_OVERRUN ) |
| 6817 | info->icount.rxover++; |
| 6818 | else |
| 6819 | info->icount.rxcrc++; |
| 6820 | framesize = 0; |
| 6821 | } else { |
| 6822 | /* |
| 6823 | * A receive frame is available, get frame size and status. |
| 6824 | * |
| 6825 | * The frame size is the starting value of the RCC (which was |
| 6826 | * set to 0xffff) minus the ending value of the RCC (decremented |
| 6827 | * once for each receive character) minus 2 or 4 for the 16-bit |
| 6828 | * or 32-bit CRC. |
| 6829 | * |
| 6830 | * If the status field is zero, this is an intermediate buffer. |
| 6831 | * It's size is 4K. |
| 6832 | * |
| 6833 | * If the DMA Buffer Entry's Status field is non-zero, the |
| 6834 | * receive operation completed normally (ie: DCD dropped). The |
| 6835 | * RCC field is valid and holds the received frame size. |
| 6836 | * It is possible that the RCC field will be zero on a DMA buffer |
| 6837 | * entry with a non-zero status. This can occur if the total |
| 6838 | * frame size (number of bytes between the time DCD goes active |
| 6839 | * to the time DCD goes inactive) exceeds 65535 bytes. In this |
| 6840 | * case the 16C32 has underrun on the RCC count and appears to |
| 6841 | * stop updating this counter to let us know the actual received |
| 6842 | * frame size. If this happens (non-zero status and zero RCC), |
| 6843 | * simply return the entire RxDMA Buffer |
| 6844 | */ |
| 6845 | if ( status ) { |
| 6846 | /* |
| 6847 | * In the event that the final RxDMA Buffer is |
| 6848 | * terminated with a non-zero status and the RCC |
| 6849 | * field is zero, we interpret this as the RCC |
| 6850 | * having underflowed (received frame > 65535 bytes). |
| 6851 | * |
| 6852 | * Signal the event to the user by passing back |
| 6853 | * a status of RxStatus_CrcError returning the full |
| 6854 | * buffer and let the app figure out what data is |
| 6855 | * actually valid |
| 6856 | */ |
| 6857 | if ( info->rx_buffer_list[CurrentIndex].rcc ) |
| 6858 | framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc; |
| 6859 | else |
| 6860 | framesize = DMABUFFERSIZE; |
| 6861 | } |
| 6862 | else |
| 6863 | framesize = DMABUFFERSIZE; |
| 6864 | } |
| 6865 | |
| 6866 | if ( framesize > DMABUFFERSIZE ) { |
| 6867 | /* |
| 6868 | * if running in raw sync mode, ISR handler for |
| 6869 | * End Of Buffer events terminates all buffers at 4K. |
| 6870 | * If this frame size is said to be >4K, get the |
| 6871 | * actual number of bytes of the frame in this buffer. |
| 6872 | */ |
| 6873 | framesize = framesize % DMABUFFERSIZE; |
| 6874 | } |
| 6875 | |
| 6876 | |
| 6877 | if ( debug_level >= DEBUG_LEVEL_BH ) |
| 6878 | printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n", |
| 6879 | __FILE__,__LINE__,info->device_name,status,framesize); |
| 6880 | |
| 6881 | if ( debug_level >= DEBUG_LEVEL_DATA ) |
| 6882 | mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr, |
| 6883 | min_t(int, framesize, DMABUFFERSIZE),0); |
| 6884 | |
| 6885 | if (framesize) { |
| 6886 | /* copy dma buffer(s) to contiguous intermediate buffer */ |
| 6887 | /* NOTE: we never copy more than DMABUFFERSIZE bytes */ |
| 6888 | |
| 6889 | pBufEntry = &(info->rx_buffer_list[CurrentIndex]); |
| 6890 | memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize); |
| 6891 | info->icount.rxok++; |
| 6892 | |
| 6893 | ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize); |
| 6894 | } |
| 6895 | |
| 6896 | /* Free the buffers used by this frame. */ |
| 6897 | mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex ); |
| 6898 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 6899 | ReturnCode = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6900 | } |
| 6901 | |
| 6902 | |
| 6903 | if ( info->rx_enabled && info->rx_overflow ) { |
| 6904 | /* The receiver needs to restarted because of |
| 6905 | * a receive overflow (buffer or FIFO). If the |
| 6906 | * receive buffers are now empty, then restart receiver. |
| 6907 | */ |
| 6908 | |
| 6909 | if ( !info->rx_buffer_list[CurrentIndex].status && |
| 6910 | info->rx_buffer_list[CurrentIndex].count ) { |
| 6911 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 6912 | usc_start_receiver(info); |
| 6913 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 6914 | } |
| 6915 | } |
| 6916 | |
| 6917 | return ReturnCode; |
| 6918 | |
| 6919 | } /* end of mgsl_get_raw_rx_frame() */ |
| 6920 | |
| 6921 | /* mgsl_load_tx_dma_buffer() |
| 6922 | * |
| 6923 | * Load the transmit DMA buffer with the specified data. |
| 6924 | * |
| 6925 | * Arguments: |
| 6926 | * |
| 6927 | * info pointer to device extension |
| 6928 | * Buffer pointer to buffer containing frame to load |
| 6929 | * BufferSize size in bytes of frame in Buffer |
| 6930 | * |
| 6931 | * Return Value: None |
| 6932 | */ |
| 6933 | static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, |
| 6934 | const char *Buffer, unsigned int BufferSize) |
| 6935 | { |
| 6936 | unsigned short Copycount; |
| 6937 | unsigned int i = 0; |
| 6938 | DMABUFFERENTRY *pBufEntry; |
| 6939 | |
| 6940 | if ( debug_level >= DEBUG_LEVEL_DATA ) |
| 6941 | mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1); |
| 6942 | |
| 6943 | if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) { |
| 6944 | /* set CMR:13 to start transmit when |
| 6945 | * next GoAhead (abort) is received |
| 6946 | */ |
| 6947 | info->cmr_value |= BIT13; |
| 6948 | } |
| 6949 | |
| 6950 | /* begin loading the frame in the next available tx dma |
| 6951 | * buffer, remember it's starting location for setting |
| 6952 | * up tx dma operation |
| 6953 | */ |
| 6954 | i = info->current_tx_buffer; |
| 6955 | info->start_tx_dma_buffer = i; |
| 6956 | |
| 6957 | /* Setup the status and RCC (Frame Size) fields of the 1st */ |
| 6958 | /* buffer entry in the transmit DMA buffer list. */ |
| 6959 | |
| 6960 | info->tx_buffer_list[i].status = info->cmr_value & 0xf000; |
| 6961 | info->tx_buffer_list[i].rcc = BufferSize; |
| 6962 | info->tx_buffer_list[i].count = BufferSize; |
| 6963 | |
| 6964 | /* Copy frame data from 1st source buffer to the DMA buffers. */ |
| 6965 | /* The frame data may span multiple DMA buffers. */ |
| 6966 | |
| 6967 | while( BufferSize ){ |
| 6968 | /* Get a pointer to next DMA buffer entry. */ |
| 6969 | pBufEntry = &info->tx_buffer_list[i++]; |
| 6970 | |
| 6971 | if ( i == info->tx_buffer_count ) |
| 6972 | i=0; |
| 6973 | |
| 6974 | /* Calculate the number of bytes that can be copied from */ |
| 6975 | /* the source buffer to this DMA buffer. */ |
| 6976 | if ( BufferSize > DMABUFFERSIZE ) |
| 6977 | Copycount = DMABUFFERSIZE; |
| 6978 | else |
| 6979 | Copycount = BufferSize; |
| 6980 | |
| 6981 | /* Actually copy data from source buffer to DMA buffer. */ |
| 6982 | /* Also set the data count for this individual DMA buffer. */ |
| 6983 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) |
| 6984 | mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount); |
| 6985 | else |
| 6986 | memcpy(pBufEntry->virt_addr, Buffer, Copycount); |
| 6987 | |
| 6988 | pBufEntry->count = Copycount; |
| 6989 | |
| 6990 | /* Advance source pointer and reduce remaining data count. */ |
| 6991 | Buffer += Copycount; |
| 6992 | BufferSize -= Copycount; |
| 6993 | |
| 6994 | ++info->tx_dma_buffers_used; |
| 6995 | } |
| 6996 | |
| 6997 | /* remember next available tx dma buffer */ |
| 6998 | info->current_tx_buffer = i; |
| 6999 | |
| 7000 | } /* end of mgsl_load_tx_dma_buffer() */ |
| 7001 | |
| 7002 | /* |
| 7003 | * mgsl_register_test() |
| 7004 | * |
| 7005 | * Performs a register test of the 16C32. |
| 7006 | * |
| 7007 | * Arguments: info pointer to device instance data |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7008 | * Return Value: true if test passed, otherwise false |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7009 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7010 | static bool mgsl_register_test( struct mgsl_struct *info ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7011 | { |
| 7012 | static unsigned short BitPatterns[] = |
| 7013 | { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f }; |
Tobias Klauser | fe97107 | 2006-01-09 20:54:02 -0800 | [diff] [blame] | 7014 | static unsigned int Patterncount = ARRAY_SIZE(BitPatterns); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7015 | unsigned int i; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7016 | bool rc = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7017 | unsigned long flags; |
| 7018 | |
| 7019 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7020 | usc_reset(info); |
| 7021 | |
| 7022 | /* Verify the reset state of some registers. */ |
| 7023 | |
| 7024 | if ( (usc_InReg( info, SICR ) != 0) || |
| 7025 | (usc_InReg( info, IVR ) != 0) || |
| 7026 | (usc_InDmaReg( info, DIVR ) != 0) ){ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7027 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7028 | } |
| 7029 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7030 | if ( rc ){ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7031 | /* Write bit patterns to various registers but do it out of */ |
| 7032 | /* sync, then read back and verify values. */ |
| 7033 | |
| 7034 | for ( i = 0 ; i < Patterncount ; i++ ) { |
| 7035 | usc_OutReg( info, TC0R, BitPatterns[i] ); |
| 7036 | usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] ); |
| 7037 | usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] ); |
| 7038 | usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] ); |
| 7039 | usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] ); |
| 7040 | usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] ); |
| 7041 | |
| 7042 | if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) || |
| 7043 | (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) || |
| 7044 | (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) || |
| 7045 | (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) || |
| 7046 | (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) || |
| 7047 | (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7048 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7049 | break; |
| 7050 | } |
| 7051 | } |
| 7052 | } |
| 7053 | |
| 7054 | usc_reset(info); |
| 7055 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7056 | |
| 7057 | return rc; |
| 7058 | |
| 7059 | } /* end of mgsl_register_test() */ |
| 7060 | |
| 7061 | /* mgsl_irq_test() Perform interrupt test of the 16C32. |
| 7062 | * |
| 7063 | * Arguments: info pointer to device instance data |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7064 | * Return Value: true if test passed, otherwise false |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7065 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7066 | static bool mgsl_irq_test( struct mgsl_struct *info ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7067 | { |
| 7068 | unsigned long EndTime; |
| 7069 | unsigned long flags; |
| 7070 | |
| 7071 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7072 | usc_reset(info); |
| 7073 | |
| 7074 | /* |
| 7075 | * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition. |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7076 | * The ISR sets irq_occurred to true. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7077 | */ |
| 7078 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7079 | info->irq_occurred = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7080 | |
| 7081 | /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */ |
| 7082 | /* Enable INTEN (Port 6, Bit12) */ |
| 7083 | /* This connects the IRQ request signal to the ISA bus */ |
| 7084 | /* on the ISA adapter. This has no effect for the PCI adapter */ |
| 7085 | usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) ); |
| 7086 | |
| 7087 | usc_EnableMasterIrqBit(info); |
| 7088 | usc_EnableInterrupts(info, IO_PIN); |
| 7089 | usc_ClearIrqPendingBits(info, IO_PIN); |
| 7090 | |
| 7091 | usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED); |
| 7092 | usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE); |
| 7093 | |
| 7094 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7095 | |
| 7096 | EndTime=100; |
| 7097 | while( EndTime-- && !info->irq_occurred ) { |
| 7098 | msleep_interruptible(10); |
| 7099 | } |
| 7100 | |
| 7101 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7102 | usc_reset(info); |
| 7103 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7104 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7105 | return info->irq_occurred; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7106 | |
| 7107 | } /* end of mgsl_irq_test() */ |
| 7108 | |
| 7109 | /* mgsl_dma_test() |
| 7110 | * |
| 7111 | * Perform a DMA test of the 16C32. A small frame is |
| 7112 | * transmitted via DMA from a transmit buffer to a receive buffer |
| 7113 | * using single buffer DMA mode. |
| 7114 | * |
| 7115 | * Arguments: info pointer to device instance data |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7116 | * Return Value: true if test passed, otherwise false |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7117 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7118 | static bool mgsl_dma_test( struct mgsl_struct *info ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7119 | { |
| 7120 | unsigned short FifoLevel; |
| 7121 | unsigned long phys_addr; |
| 7122 | unsigned int FrameSize; |
| 7123 | unsigned int i; |
| 7124 | char *TmpPtr; |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7125 | bool rc = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7126 | unsigned short status=0; |
| 7127 | unsigned long EndTime; |
| 7128 | unsigned long flags; |
| 7129 | MGSL_PARAMS tmp_params; |
| 7130 | |
| 7131 | /* save current port options */ |
| 7132 | memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS)); |
| 7133 | /* load default port options */ |
| 7134 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); |
| 7135 | |
| 7136 | #define TESTFRAMESIZE 40 |
| 7137 | |
| 7138 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7139 | |
| 7140 | /* setup 16C32 for SDLC DMA transfer mode */ |
| 7141 | |
| 7142 | usc_reset(info); |
| 7143 | usc_set_sdlc_mode(info); |
| 7144 | usc_enable_loopback(info,1); |
| 7145 | |
| 7146 | /* Reprogram the RDMR so that the 16C32 does NOT clear the count |
| 7147 | * field of the buffer entry after fetching buffer address. This |
| 7148 | * way we can detect a DMA failure for a DMA read (which should be |
| 7149 | * non-destructive to system memory) before we try and write to |
| 7150 | * memory (where a failure could corrupt system memory). |
| 7151 | */ |
| 7152 | |
| 7153 | /* Receive DMA mode Register (RDMR) |
| 7154 | * |
| 7155 | * <15..14> 11 DMA mode = Linked List Buffer mode |
| 7156 | * <13> 1 RSBinA/L = store Rx status Block in List entry |
| 7157 | * <12> 0 1 = Clear count of List Entry after fetching |
| 7158 | * <11..10> 00 Address mode = Increment |
| 7159 | * <9> 1 Terminate Buffer on RxBound |
| 7160 | * <8> 0 Bus Width = 16bits |
| 7161 | * <7..0> ? status Bits (write as 0s) |
| 7162 | * |
| 7163 | * 1110 0010 0000 0000 = 0xe200 |
| 7164 | */ |
| 7165 | |
| 7166 | usc_OutDmaReg( info, RDMR, 0xe200 ); |
| 7167 | |
| 7168 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7169 | |
| 7170 | |
| 7171 | /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */ |
| 7172 | |
| 7173 | FrameSize = TESTFRAMESIZE; |
| 7174 | |
| 7175 | /* setup 1st transmit buffer entry: */ |
| 7176 | /* with frame size and transmit control word */ |
| 7177 | |
| 7178 | info->tx_buffer_list[0].count = FrameSize; |
| 7179 | info->tx_buffer_list[0].rcc = FrameSize; |
| 7180 | info->tx_buffer_list[0].status = 0x4000; |
| 7181 | |
| 7182 | /* build a transmit frame in 1st transmit DMA buffer */ |
| 7183 | |
| 7184 | TmpPtr = info->tx_buffer_list[0].virt_addr; |
| 7185 | for (i = 0; i < FrameSize; i++ ) |
| 7186 | *TmpPtr++ = i; |
| 7187 | |
| 7188 | /* setup 1st receive buffer entry: */ |
| 7189 | /* clear status, set max receive buffer size */ |
| 7190 | |
| 7191 | info->rx_buffer_list[0].status = 0; |
| 7192 | info->rx_buffer_list[0].count = FrameSize + 4; |
| 7193 | |
| 7194 | /* zero out the 1st receive buffer */ |
| 7195 | |
| 7196 | memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 ); |
| 7197 | |
| 7198 | /* Set count field of next buffer entries to prevent */ |
| 7199 | /* 16C32 from using buffers after the 1st one. */ |
| 7200 | |
| 7201 | info->tx_buffer_list[1].count = 0; |
| 7202 | info->rx_buffer_list[1].count = 0; |
| 7203 | |
| 7204 | |
| 7205 | /***************************/ |
| 7206 | /* Program 16C32 receiver. */ |
| 7207 | /***************************/ |
| 7208 | |
| 7209 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7210 | |
| 7211 | /* setup DMA transfers */ |
| 7212 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
| 7213 | |
| 7214 | /* program 16C32 receiver with physical address of 1st DMA buffer entry */ |
| 7215 | phys_addr = info->rx_buffer_list[0].phys_entry; |
| 7216 | usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr ); |
| 7217 | usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) ); |
| 7218 | |
| 7219 | /* Clear the Rx DMA status bits (read RDMR) and start channel */ |
| 7220 | usc_InDmaReg( info, RDMR ); |
| 7221 | usc_DmaCmd( info, DmaCmd_InitRxChannel ); |
| 7222 | |
| 7223 | /* Enable Receiver (RMR <1..0> = 10) */ |
| 7224 | usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) ); |
| 7225 | |
| 7226 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7227 | |
| 7228 | |
| 7229 | /*************************************************************/ |
| 7230 | /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */ |
| 7231 | /*************************************************************/ |
| 7232 | |
| 7233 | /* Wait 100ms for interrupt. */ |
| 7234 | EndTime = jiffies + msecs_to_jiffies(100); |
| 7235 | |
| 7236 | for(;;) { |
| 7237 | if (time_after(jiffies, EndTime)) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7238 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7239 | break; |
| 7240 | } |
| 7241 | |
| 7242 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7243 | status = usc_InDmaReg( info, RDMR ); |
| 7244 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7245 | |
| 7246 | if ( !(status & BIT4) && (status & BIT5) ) { |
| 7247 | /* INITG (BIT 4) is inactive (no entry read in progress) AND */ |
| 7248 | /* BUSY (BIT 5) is active (channel still active). */ |
| 7249 | /* This means the buffer entry read has completed. */ |
| 7250 | break; |
| 7251 | } |
| 7252 | } |
| 7253 | |
| 7254 | |
| 7255 | /******************************/ |
| 7256 | /* Program 16C32 transmitter. */ |
| 7257 | /******************************/ |
| 7258 | |
| 7259 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7260 | |
| 7261 | /* Program the Transmit Character Length Register (TCLR) */ |
| 7262 | /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */ |
| 7263 | |
| 7264 | usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count ); |
| 7265 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
| 7266 | |
| 7267 | /* Program the address of the 1st DMA Buffer Entry in linked list */ |
| 7268 | |
| 7269 | phys_addr = info->tx_buffer_list[0].phys_entry; |
| 7270 | usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr ); |
| 7271 | usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) ); |
| 7272 | |
| 7273 | /* unlatch Tx status bits, and start transmit channel. */ |
| 7274 | |
| 7275 | usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) ); |
| 7276 | usc_DmaCmd( info, DmaCmd_InitTxChannel ); |
| 7277 | |
| 7278 | /* wait for DMA controller to fill transmit FIFO */ |
| 7279 | |
| 7280 | usc_TCmd( info, TCmd_SelectTicrTxFifostatus ); |
| 7281 | |
| 7282 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7283 | |
| 7284 | |
| 7285 | /**********************************/ |
| 7286 | /* WAIT FOR TRANSMIT FIFO TO FILL */ |
| 7287 | /**********************************/ |
| 7288 | |
| 7289 | /* Wait 100ms */ |
| 7290 | EndTime = jiffies + msecs_to_jiffies(100); |
| 7291 | |
| 7292 | for(;;) { |
| 7293 | if (time_after(jiffies, EndTime)) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7294 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7295 | break; |
| 7296 | } |
| 7297 | |
| 7298 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7299 | FifoLevel = usc_InReg(info, TICR) >> 8; |
| 7300 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7301 | |
| 7302 | if ( FifoLevel < 16 ) |
| 7303 | break; |
| 7304 | else |
| 7305 | if ( FrameSize < 32 ) { |
| 7306 | /* This frame is smaller than the entire transmit FIFO */ |
| 7307 | /* so wait for the entire frame to be loaded. */ |
| 7308 | if ( FifoLevel <= (32 - FrameSize) ) |
| 7309 | break; |
| 7310 | } |
| 7311 | } |
| 7312 | |
| 7313 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7314 | if ( rc ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7315 | { |
| 7316 | /* Enable 16C32 transmitter. */ |
| 7317 | |
| 7318 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7319 | |
| 7320 | /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */ |
| 7321 | usc_TCmd( info, TCmd_SendFrame ); |
| 7322 | usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) ); |
| 7323 | |
| 7324 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7325 | |
| 7326 | |
| 7327 | /******************************/ |
| 7328 | /* WAIT FOR TRANSMIT COMPLETE */ |
| 7329 | /******************************/ |
| 7330 | |
| 7331 | /* Wait 100ms */ |
| 7332 | EndTime = jiffies + msecs_to_jiffies(100); |
| 7333 | |
| 7334 | /* While timer not expired wait for transmit complete */ |
| 7335 | |
| 7336 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7337 | status = usc_InReg( info, TCSR ); |
| 7338 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7339 | |
| 7340 | while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) { |
| 7341 | if (time_after(jiffies, EndTime)) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7342 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7343 | break; |
| 7344 | } |
| 7345 | |
| 7346 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7347 | status = usc_InReg( info, TCSR ); |
| 7348 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7349 | } |
| 7350 | } |
| 7351 | |
| 7352 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7353 | if ( rc ){ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7354 | /* CHECK FOR TRANSMIT ERRORS */ |
| 7355 | if ( status & (BIT5 + BIT1) ) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7356 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7357 | } |
| 7358 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7359 | if ( rc ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7360 | /* WAIT FOR RECEIVE COMPLETE */ |
| 7361 | |
| 7362 | /* Wait 100ms */ |
| 7363 | EndTime = jiffies + msecs_to_jiffies(100); |
| 7364 | |
| 7365 | /* Wait for 16C32 to write receive status to buffer entry. */ |
| 7366 | status=info->rx_buffer_list[0].status; |
| 7367 | while ( status == 0 ) { |
| 7368 | if (time_after(jiffies, EndTime)) { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7369 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7370 | break; |
| 7371 | } |
| 7372 | status=info->rx_buffer_list[0].status; |
| 7373 | } |
| 7374 | } |
| 7375 | |
| 7376 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7377 | if ( rc ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7378 | /* CHECK FOR RECEIVE ERRORS */ |
| 7379 | status = info->rx_buffer_list[0].status; |
| 7380 | |
| 7381 | if ( status & (BIT8 + BIT3 + BIT1) ) { |
| 7382 | /* receive error has occurred */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7383 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7384 | } else { |
| 7385 | if ( memcmp( info->tx_buffer_list[0].virt_addr , |
| 7386 | info->rx_buffer_list[0].virt_addr, FrameSize ) ){ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7387 | rc = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7388 | } |
| 7389 | } |
| 7390 | } |
| 7391 | |
| 7392 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7393 | usc_reset( info ); |
| 7394 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7395 | |
| 7396 | /* restore current port options */ |
| 7397 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); |
| 7398 | |
| 7399 | return rc; |
| 7400 | |
| 7401 | } /* end of mgsl_dma_test() */ |
| 7402 | |
| 7403 | /* mgsl_adapter_test() |
| 7404 | * |
| 7405 | * Perform the register, IRQ, and DMA tests for the 16C32. |
| 7406 | * |
| 7407 | * Arguments: info pointer to device instance data |
| 7408 | * Return Value: 0 if success, otherwise -ENODEV |
| 7409 | */ |
| 7410 | static int mgsl_adapter_test( struct mgsl_struct *info ) |
| 7411 | { |
| 7412 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 7413 | printk( "%s(%d):Testing device %s\n", |
| 7414 | __FILE__,__LINE__,info->device_name ); |
| 7415 | |
| 7416 | if ( !mgsl_register_test( info ) ) { |
| 7417 | info->init_error = DiagStatus_AddressFailure; |
| 7418 | printk( "%s(%d):Register test failure for device %s Addr=%04X\n", |
| 7419 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) ); |
| 7420 | return -ENODEV; |
| 7421 | } |
| 7422 | |
| 7423 | if ( !mgsl_irq_test( info ) ) { |
| 7424 | info->init_error = DiagStatus_IrqFailure; |
| 7425 | printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", |
| 7426 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); |
| 7427 | return -ENODEV; |
| 7428 | } |
| 7429 | |
| 7430 | if ( !mgsl_dma_test( info ) ) { |
| 7431 | info->init_error = DiagStatus_DmaFailure; |
| 7432 | printk( "%s(%d):DMA test failure for device %s DMA=%d\n", |
| 7433 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) ); |
| 7434 | return -ENODEV; |
| 7435 | } |
| 7436 | |
| 7437 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 7438 | printk( "%s(%d):device %s passed diagnostics\n", |
| 7439 | __FILE__,__LINE__,info->device_name ); |
| 7440 | |
| 7441 | return 0; |
| 7442 | |
| 7443 | } /* end of mgsl_adapter_test() */ |
| 7444 | |
| 7445 | /* mgsl_memory_test() |
| 7446 | * |
| 7447 | * Test the shared memory on a PCI adapter. |
| 7448 | * |
| 7449 | * Arguments: info pointer to device instance data |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7450 | * Return Value: true if test passed, otherwise false |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7451 | */ |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7452 | static bool mgsl_memory_test( struct mgsl_struct *info ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7453 | { |
Tobias Klauser | fe97107 | 2006-01-09 20:54:02 -0800 | [diff] [blame] | 7454 | static unsigned long BitPatterns[] = |
| 7455 | { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; |
| 7456 | unsigned long Patterncount = ARRAY_SIZE(BitPatterns); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7457 | unsigned long i; |
| 7458 | unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long); |
| 7459 | unsigned long * TestAddr; |
| 7460 | |
| 7461 | if ( info->bus_type != MGSL_BUS_TYPE_PCI ) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7462 | return true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7463 | |
| 7464 | TestAddr = (unsigned long *)info->memory_base; |
| 7465 | |
| 7466 | /* Test data lines with test pattern at one location. */ |
| 7467 | |
| 7468 | for ( i = 0 ; i < Patterncount ; i++ ) { |
| 7469 | *TestAddr = BitPatterns[i]; |
| 7470 | if ( *TestAddr != BitPatterns[i] ) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7471 | return false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7472 | } |
| 7473 | |
| 7474 | /* Test address lines with incrementing pattern over */ |
| 7475 | /* entire address range. */ |
| 7476 | |
| 7477 | for ( i = 0 ; i < TestLimit ; i++ ) { |
| 7478 | *TestAddr = i * 4; |
| 7479 | TestAddr++; |
| 7480 | } |
| 7481 | |
| 7482 | TestAddr = (unsigned long *)info->memory_base; |
| 7483 | |
| 7484 | for ( i = 0 ; i < TestLimit ; i++ ) { |
| 7485 | if ( *TestAddr != i * 4 ) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7486 | return false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7487 | TestAddr++; |
| 7488 | } |
| 7489 | |
| 7490 | memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE ); |
| 7491 | |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7492 | return true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7493 | |
| 7494 | } /* End Of mgsl_memory_test() */ |
| 7495 | |
| 7496 | |
| 7497 | /* mgsl_load_pci_memory() |
| 7498 | * |
| 7499 | * Load a large block of data into the PCI shared memory. |
| 7500 | * Use this instead of memcpy() or memmove() to move data |
| 7501 | * into the PCI shared memory. |
| 7502 | * |
| 7503 | * Notes: |
| 7504 | * |
| 7505 | * This function prevents the PCI9050 interface chip from hogging |
| 7506 | * the adapter local bus, which can starve the 16C32 by preventing |
| 7507 | * 16C32 bus master cycles. |
| 7508 | * |
| 7509 | * The PCI9050 documentation says that the 9050 will always release |
| 7510 | * control of the local bus after completing the current read |
| 7511 | * or write operation. |
| 7512 | * |
| 7513 | * It appears that as long as the PCI9050 write FIFO is full, the |
| 7514 | * PCI9050 treats all of the writes as a single burst transaction |
| 7515 | * and will not release the bus. This causes DMA latency problems |
| 7516 | * at high speeds when copying large data blocks to the shared |
| 7517 | * memory. |
| 7518 | * |
| 7519 | * This function in effect, breaks the a large shared memory write |
| 7520 | * into multiple transations by interleaving a shared memory read |
| 7521 | * which will flush the write FIFO and 'complete' the write |
| 7522 | * transation. This allows any pending DMA request to gain control |
| 7523 | * of the local bus in a timely fasion. |
| 7524 | * |
| 7525 | * Arguments: |
| 7526 | * |
| 7527 | * TargetPtr pointer to target address in PCI shared memory |
| 7528 | * SourcePtr pointer to source buffer for data |
| 7529 | * count count in bytes of data to copy |
| 7530 | * |
| 7531 | * Return Value: None |
| 7532 | */ |
| 7533 | static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr, |
| 7534 | unsigned short count ) |
| 7535 | { |
| 7536 | /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */ |
| 7537 | #define PCI_LOAD_INTERVAL 64 |
| 7538 | |
| 7539 | unsigned short Intervalcount = count / PCI_LOAD_INTERVAL; |
| 7540 | unsigned short Index; |
| 7541 | unsigned long Dummy; |
| 7542 | |
| 7543 | for ( Index = 0 ; Index < Intervalcount ; Index++ ) |
| 7544 | { |
| 7545 | memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL); |
| 7546 | Dummy = *((volatile unsigned long *)TargetPtr); |
| 7547 | TargetPtr += PCI_LOAD_INTERVAL; |
| 7548 | SourcePtr += PCI_LOAD_INTERVAL; |
| 7549 | } |
| 7550 | |
| 7551 | memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL ); |
| 7552 | |
| 7553 | } /* End Of mgsl_load_pci_memory() */ |
| 7554 | |
| 7555 | static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit) |
| 7556 | { |
| 7557 | int i; |
| 7558 | int linecount; |
| 7559 | if (xmit) |
| 7560 | printk("%s tx data:\n",info->device_name); |
| 7561 | else |
| 7562 | printk("%s rx data:\n",info->device_name); |
| 7563 | |
| 7564 | while(count) { |
| 7565 | if (count > 16) |
| 7566 | linecount = 16; |
| 7567 | else |
| 7568 | linecount = count; |
| 7569 | |
| 7570 | for(i=0;i<linecount;i++) |
| 7571 | printk("%02X ",(unsigned char)data[i]); |
| 7572 | for(;i<17;i++) |
| 7573 | printk(" "); |
| 7574 | for(i=0;i<linecount;i++) { |
| 7575 | if (data[i]>=040 && data[i]<=0176) |
| 7576 | printk("%c",data[i]); |
| 7577 | else |
| 7578 | printk("."); |
| 7579 | } |
| 7580 | printk("\n"); |
| 7581 | |
| 7582 | data += linecount; |
| 7583 | count -= linecount; |
| 7584 | } |
| 7585 | } /* end of mgsl_trace_block() */ |
| 7586 | |
| 7587 | /* mgsl_tx_timeout() |
| 7588 | * |
| 7589 | * called when HDLC frame times out |
| 7590 | * update stats and do tx completion processing |
| 7591 | * |
| 7592 | * Arguments: context pointer to device instance data |
| 7593 | * Return Value: None |
| 7594 | */ |
| 7595 | static void mgsl_tx_timeout(unsigned long context) |
| 7596 | { |
| 7597 | struct mgsl_struct *info = (struct mgsl_struct*)context; |
| 7598 | unsigned long flags; |
| 7599 | |
| 7600 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
| 7601 | printk( "%s(%d):mgsl_tx_timeout(%s)\n", |
| 7602 | __FILE__,__LINE__,info->device_name); |
| 7603 | if(info->tx_active && |
| 7604 | (info->params.mode == MGSL_MODE_HDLC || |
| 7605 | info->params.mode == MGSL_MODE_RAW) ) { |
| 7606 | info->icount.txtimeout++; |
| 7607 | } |
| 7608 | spin_lock_irqsave(&info->irq_spinlock,flags); |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7609 | info->tx_active = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7610 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
| 7611 | |
| 7612 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) |
| 7613 | usc_loopmode_cancel_transmit( info ); |
| 7614 | |
| 7615 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7616 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 7617 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7618 | if (info->netcount) |
| 7619 | hdlcdev_tx_done(info); |
| 7620 | else |
| 7621 | #endif |
| 7622 | mgsl_bh_transmit(info); |
| 7623 | |
| 7624 | } /* end of mgsl_tx_timeout() */ |
| 7625 | |
| 7626 | /* signal that there are no more frames to send, so that |
| 7627 | * line is 'released' by echoing RxD to TxD when current |
| 7628 | * transmission is complete (or immediately if no tx in progress). |
| 7629 | */ |
| 7630 | static int mgsl_loopmode_send_done( struct mgsl_struct * info ) |
| 7631 | { |
| 7632 | unsigned long flags; |
| 7633 | |
| 7634 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7635 | if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) { |
| 7636 | if (info->tx_active) |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7637 | info->loopmode_send_done_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7638 | else |
| 7639 | usc_loopmode_send_done(info); |
| 7640 | } |
| 7641 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7642 | |
| 7643 | return 0; |
| 7644 | } |
| 7645 | |
| 7646 | /* release the line by echoing RxD to TxD |
| 7647 | * upon completion of a transmit frame |
| 7648 | */ |
| 7649 | static void usc_loopmode_send_done( struct mgsl_struct * info ) |
| 7650 | { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7651 | info->loopmode_send_done_requested = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7652 | /* clear CMR:13 to 0 to start echoing RxData to TxData */ |
| 7653 | info->cmr_value &= ~BIT13; |
| 7654 | usc_OutReg(info, CMR, info->cmr_value); |
| 7655 | } |
| 7656 | |
| 7657 | /* abort a transmit in progress while in HDLC LoopMode |
| 7658 | */ |
| 7659 | static void usc_loopmode_cancel_transmit( struct mgsl_struct * info ) |
| 7660 | { |
| 7661 | /* reset tx dma channel and purge TxFifo */ |
| 7662 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
| 7663 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); |
| 7664 | usc_loopmode_send_done( info ); |
| 7665 | } |
| 7666 | |
| 7667 | /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled |
| 7668 | * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort) |
| 7669 | * we must clear CMR:13 to begin repeating TxData to RxData |
| 7670 | */ |
| 7671 | static void usc_loopmode_insert_request( struct mgsl_struct * info ) |
| 7672 | { |
Joe Perches | 0fab6de | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 7673 | info->loopmode_insert_requested = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7674 | |
| 7675 | /* enable RxAbort irq. On next RxAbort, clear CMR:13 to |
| 7676 | * begin repeating TxData on RxData (complete insertion) |
| 7677 | */ |
| 7678 | usc_OutReg( info, RICR, |
| 7679 | (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) ); |
| 7680 | |
| 7681 | /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */ |
| 7682 | info->cmr_value |= BIT13; |
| 7683 | usc_OutReg(info, CMR, info->cmr_value); |
| 7684 | } |
| 7685 | |
| 7686 | /* return 1 if station is inserted into the loop, otherwise 0 |
| 7687 | */ |
| 7688 | static int usc_loopmode_active( struct mgsl_struct * info) |
| 7689 | { |
| 7690 | return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ; |
| 7691 | } |
| 7692 | |
Paul Fulghum | af69c7f | 2006-12-06 20:40:24 -0800 | [diff] [blame] | 7693 | #if SYNCLINK_GENERIC_HDLC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7694 | |
| 7695 | /** |
| 7696 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) |
| 7697 | * set encoding and frame check sequence (FCS) options |
| 7698 | * |
| 7699 | * dev pointer to network device structure |
| 7700 | * encoding serial encoding setting |
| 7701 | * parity FCS setting |
| 7702 | * |
| 7703 | * returns 0 if success, otherwise error code |
| 7704 | */ |
| 7705 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, |
| 7706 | unsigned short parity) |
| 7707 | { |
| 7708 | struct mgsl_struct *info = dev_to_port(dev); |
| 7709 | unsigned char new_encoding; |
| 7710 | unsigned short new_crctype; |
| 7711 | |
| 7712 | /* return error if TTY interface open */ |
| 7713 | if (info->count) |
| 7714 | return -EBUSY; |
| 7715 | |
| 7716 | switch (encoding) |
| 7717 | { |
| 7718 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; |
| 7719 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; |
| 7720 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; |
| 7721 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; |
| 7722 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; |
| 7723 | default: return -EINVAL; |
| 7724 | } |
| 7725 | |
| 7726 | switch (parity) |
| 7727 | { |
| 7728 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; |
| 7729 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; |
| 7730 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; |
| 7731 | default: return -EINVAL; |
| 7732 | } |
| 7733 | |
| 7734 | info->params.encoding = new_encoding; |
Alexey Dobriyan | 53b3531 | 2006-03-24 03:16:13 -0800 | [diff] [blame] | 7735 | info->params.crc_type = new_crctype; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7736 | |
| 7737 | /* if network interface up, reprogram hardware */ |
| 7738 | if (info->netcount) |
| 7739 | mgsl_program_hw(info); |
| 7740 | |
| 7741 | return 0; |
| 7742 | } |
| 7743 | |
| 7744 | /** |
| 7745 | * called by generic HDLC layer to send frame |
| 7746 | * |
| 7747 | * skb socket buffer containing HDLC frame |
| 7748 | * dev pointer to network device structure |
| 7749 | * |
| 7750 | * returns 0 if success, otherwise error code |
| 7751 | */ |
| 7752 | static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev) |
| 7753 | { |
| 7754 | struct mgsl_struct *info = dev_to_port(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7755 | unsigned long flags; |
| 7756 | |
| 7757 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 7758 | printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); |
| 7759 | |
| 7760 | /* stop sending until this frame completes */ |
| 7761 | netif_stop_queue(dev); |
| 7762 | |
| 7763 | /* copy data to device buffers */ |
| 7764 | info->xmit_cnt = skb->len; |
| 7765 | mgsl_load_tx_dma_buffer(info, skb->data, skb->len); |
| 7766 | |
| 7767 | /* update network statistics */ |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 7768 | dev->stats.tx_packets++; |
| 7769 | dev->stats.tx_bytes += skb->len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7770 | |
| 7771 | /* done with socket buffer, so free it */ |
| 7772 | dev_kfree_skb(skb); |
| 7773 | |
| 7774 | /* save start time for transmit timeout detection */ |
| 7775 | dev->trans_start = jiffies; |
| 7776 | |
| 7777 | /* start hardware transmitter if necessary */ |
| 7778 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7779 | if (!info->tx_active) |
| 7780 | usc_start_transmitter(info); |
| 7781 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7782 | |
| 7783 | return 0; |
| 7784 | } |
| 7785 | |
| 7786 | /** |
| 7787 | * called by network layer when interface enabled |
| 7788 | * claim resources and initialize hardware |
| 7789 | * |
| 7790 | * dev pointer to network device structure |
| 7791 | * |
| 7792 | * returns 0 if success, otherwise error code |
| 7793 | */ |
| 7794 | static int hdlcdev_open(struct net_device *dev) |
| 7795 | { |
| 7796 | struct mgsl_struct *info = dev_to_port(dev); |
| 7797 | int rc; |
| 7798 | unsigned long flags; |
| 7799 | |
| 7800 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 7801 | printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); |
| 7802 | |
| 7803 | /* generic HDLC layer open processing */ |
| 7804 | if ((rc = hdlc_open(dev))) |
| 7805 | return rc; |
| 7806 | |
| 7807 | /* arbitrate between network and tty opens */ |
| 7808 | spin_lock_irqsave(&info->netlock, flags); |
| 7809 | if (info->count != 0 || info->netcount != 0) { |
| 7810 | printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); |
| 7811 | spin_unlock_irqrestore(&info->netlock, flags); |
| 7812 | return -EBUSY; |
| 7813 | } |
| 7814 | info->netcount=1; |
| 7815 | spin_unlock_irqrestore(&info->netlock, flags); |
| 7816 | |
| 7817 | /* claim resources and init adapter */ |
| 7818 | if ((rc = startup(info)) != 0) { |
| 7819 | spin_lock_irqsave(&info->netlock, flags); |
| 7820 | info->netcount=0; |
| 7821 | spin_unlock_irqrestore(&info->netlock, flags); |
| 7822 | return rc; |
| 7823 | } |
| 7824 | |
| 7825 | /* assert DTR and RTS, apply hardware settings */ |
| 7826 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; |
| 7827 | mgsl_program_hw(info); |
| 7828 | |
| 7829 | /* enable network layer transmit */ |
| 7830 | dev->trans_start = jiffies; |
| 7831 | netif_start_queue(dev); |
| 7832 | |
| 7833 | /* inform generic HDLC layer of current DCD status */ |
| 7834 | spin_lock_irqsave(&info->irq_spinlock, flags); |
| 7835 | usc_get_serial_signals(info); |
| 7836 | spin_unlock_irqrestore(&info->irq_spinlock, flags); |
Krzysztof Halasa | fbeff3c | 2006-07-21 14:44:55 -0700 | [diff] [blame] | 7837 | if (info->serial_signals & SerialSignal_DCD) |
| 7838 | netif_carrier_on(dev); |
| 7839 | else |
| 7840 | netif_carrier_off(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7841 | return 0; |
| 7842 | } |
| 7843 | |
| 7844 | /** |
| 7845 | * called by network layer when interface is disabled |
| 7846 | * shutdown hardware and release resources |
| 7847 | * |
| 7848 | * dev pointer to network device structure |
| 7849 | * |
| 7850 | * returns 0 if success, otherwise error code |
| 7851 | */ |
| 7852 | static int hdlcdev_close(struct net_device *dev) |
| 7853 | { |
| 7854 | struct mgsl_struct *info = dev_to_port(dev); |
| 7855 | unsigned long flags; |
| 7856 | |
| 7857 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 7858 | printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); |
| 7859 | |
| 7860 | netif_stop_queue(dev); |
| 7861 | |
| 7862 | /* shutdown adapter and release resources */ |
| 7863 | shutdown(info); |
| 7864 | |
| 7865 | hdlc_close(dev); |
| 7866 | |
| 7867 | spin_lock_irqsave(&info->netlock, flags); |
| 7868 | info->netcount=0; |
| 7869 | spin_unlock_irqrestore(&info->netlock, flags); |
| 7870 | |
| 7871 | return 0; |
| 7872 | } |
| 7873 | |
| 7874 | /** |
| 7875 | * called by network layer to process IOCTL call to network device |
| 7876 | * |
| 7877 | * dev pointer to network device structure |
| 7878 | * ifr pointer to network interface request structure |
| 7879 | * cmd IOCTL command code |
| 7880 | * |
| 7881 | * returns 0 if success, otherwise error code |
| 7882 | */ |
| 7883 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 7884 | { |
| 7885 | const size_t size = sizeof(sync_serial_settings); |
| 7886 | sync_serial_settings new_line; |
| 7887 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; |
| 7888 | struct mgsl_struct *info = dev_to_port(dev); |
| 7889 | unsigned int flags; |
| 7890 | |
| 7891 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 7892 | printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); |
| 7893 | |
| 7894 | /* return error if TTY interface open */ |
| 7895 | if (info->count) |
| 7896 | return -EBUSY; |
| 7897 | |
| 7898 | if (cmd != SIOCWANDEV) |
| 7899 | return hdlc_ioctl(dev, ifr, cmd); |
| 7900 | |
| 7901 | switch(ifr->ifr_settings.type) { |
| 7902 | case IF_GET_IFACE: /* return current sync_serial_settings */ |
| 7903 | |
| 7904 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; |
| 7905 | if (ifr->ifr_settings.size < size) { |
| 7906 | ifr->ifr_settings.size = size; /* data size wanted */ |
| 7907 | return -ENOBUFS; |
| 7908 | } |
| 7909 | |
| 7910 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | |
| 7911 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | |
| 7912 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | |
| 7913 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); |
| 7914 | |
| 7915 | switch (flags){ |
| 7916 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; |
| 7917 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; |
| 7918 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; |
| 7919 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; |
| 7920 | default: new_line.clock_type = CLOCK_DEFAULT; |
| 7921 | } |
| 7922 | |
| 7923 | new_line.clock_rate = info->params.clock_speed; |
| 7924 | new_line.loopback = info->params.loopback ? 1:0; |
| 7925 | |
| 7926 | if (copy_to_user(line, &new_line, size)) |
| 7927 | return -EFAULT; |
| 7928 | return 0; |
| 7929 | |
| 7930 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ |
| 7931 | |
| 7932 | if(!capable(CAP_NET_ADMIN)) |
| 7933 | return -EPERM; |
| 7934 | if (copy_from_user(&new_line, line, size)) |
| 7935 | return -EFAULT; |
| 7936 | |
| 7937 | switch (new_line.clock_type) |
| 7938 | { |
| 7939 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; |
| 7940 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; |
| 7941 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; |
| 7942 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; |
| 7943 | case CLOCK_DEFAULT: flags = info->params.flags & |
| 7944 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | |
| 7945 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | |
| 7946 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | |
| 7947 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; |
| 7948 | default: return -EINVAL; |
| 7949 | } |
| 7950 | |
| 7951 | if (new_line.loopback != 0 && new_line.loopback != 1) |
| 7952 | return -EINVAL; |
| 7953 | |
| 7954 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | |
| 7955 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | |
| 7956 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | |
| 7957 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); |
| 7958 | info->params.flags |= flags; |
| 7959 | |
| 7960 | info->params.loopback = new_line.loopback; |
| 7961 | |
| 7962 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) |
| 7963 | info->params.clock_speed = new_line.clock_rate; |
| 7964 | else |
| 7965 | info->params.clock_speed = 0; |
| 7966 | |
| 7967 | /* if network interface up, reprogram hardware */ |
| 7968 | if (info->netcount) |
| 7969 | mgsl_program_hw(info); |
| 7970 | return 0; |
| 7971 | |
| 7972 | default: |
| 7973 | return hdlc_ioctl(dev, ifr, cmd); |
| 7974 | } |
| 7975 | } |
| 7976 | |
| 7977 | /** |
| 7978 | * called by network layer when transmit timeout is detected |
| 7979 | * |
| 7980 | * dev pointer to network device structure |
| 7981 | */ |
| 7982 | static void hdlcdev_tx_timeout(struct net_device *dev) |
| 7983 | { |
| 7984 | struct mgsl_struct *info = dev_to_port(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7985 | unsigned long flags; |
| 7986 | |
| 7987 | if (debug_level >= DEBUG_LEVEL_INFO) |
| 7988 | printk("hdlcdev_tx_timeout(%s)\n",dev->name); |
| 7989 | |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 7990 | dev->stats.tx_errors++; |
| 7991 | dev->stats.tx_aborted_errors++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7992 | |
| 7993 | spin_lock_irqsave(&info->irq_spinlock,flags); |
| 7994 | usc_stop_transmitter(info); |
| 7995 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
| 7996 | |
| 7997 | netif_wake_queue(dev); |
| 7998 | } |
| 7999 | |
| 8000 | /** |
| 8001 | * called by device driver when transmit completes |
| 8002 | * reenable network layer transmit if stopped |
| 8003 | * |
| 8004 | * info pointer to device instance information |
| 8005 | */ |
| 8006 | static void hdlcdev_tx_done(struct mgsl_struct *info) |
| 8007 | { |
| 8008 | if (netif_queue_stopped(info->netdev)) |
| 8009 | netif_wake_queue(info->netdev); |
| 8010 | } |
| 8011 | |
| 8012 | /** |
| 8013 | * called by device driver when frame received |
| 8014 | * pass frame to network layer |
| 8015 | * |
| 8016 | * info pointer to device instance information |
| 8017 | * buf pointer to buffer contianing frame data |
| 8018 | * size count of data bytes in buf |
| 8019 | */ |
| 8020 | static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size) |
| 8021 | { |
| 8022 | struct sk_buff *skb = dev_alloc_skb(size); |
| 8023 | struct net_device *dev = info->netdev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8024 | |
| 8025 | if (debug_level >= DEBUG_LEVEL_INFO) |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 8026 | printk("hdlcdev_rx(%s)\n", dev->name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8027 | |
| 8028 | if (skb == NULL) { |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 8029 | printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", |
| 8030 | dev->name); |
| 8031 | dev->stats.rx_dropped++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8032 | return; |
| 8033 | } |
| 8034 | |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 8035 | memcpy(skb_put(skb, size), buf, size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8036 | |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 8037 | skb->protocol = hdlc_type_trans(skb, dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8038 | |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 8039 | dev->stats.rx_packets++; |
| 8040 | dev->stats.rx_bytes += size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8041 | |
| 8042 | netif_rx(skb); |
| 8043 | |
Krzysztof Halasa | 198191c | 2008-06-30 23:26:53 +0200 | [diff] [blame] | 8044 | dev->last_rx = jiffies; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8045 | } |
| 8046 | |
| 8047 | /** |
| 8048 | * called by device driver when adding device instance |
| 8049 | * do generic HDLC initialization |
| 8050 | * |
| 8051 | * info pointer to device instance information |
| 8052 | * |
| 8053 | * returns 0 if success, otherwise error code |
| 8054 | */ |
| 8055 | static int hdlcdev_init(struct mgsl_struct *info) |
| 8056 | { |
| 8057 | int rc; |
| 8058 | struct net_device *dev; |
| 8059 | hdlc_device *hdlc; |
| 8060 | |
| 8061 | /* allocate and initialize network and HDLC layer objects */ |
| 8062 | |
| 8063 | if (!(dev = alloc_hdlcdev(info))) { |
| 8064 | printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); |
| 8065 | return -ENOMEM; |
| 8066 | } |
| 8067 | |
| 8068 | /* for network layer reporting purposes only */ |
| 8069 | dev->base_addr = info->io_base; |
| 8070 | dev->irq = info->irq_level; |
| 8071 | dev->dma = info->dma_level; |
| 8072 | |
| 8073 | /* network layer callbacks and settings */ |
| 8074 | dev->do_ioctl = hdlcdev_ioctl; |
| 8075 | dev->open = hdlcdev_open; |
| 8076 | dev->stop = hdlcdev_close; |
| 8077 | dev->tx_timeout = hdlcdev_tx_timeout; |
| 8078 | dev->watchdog_timeo = 10*HZ; |
| 8079 | dev->tx_queue_len = 50; |
| 8080 | |
| 8081 | /* generic HDLC layer callbacks and settings */ |
| 8082 | hdlc = dev_to_hdlc(dev); |
| 8083 | hdlc->attach = hdlcdev_attach; |
| 8084 | hdlc->xmit = hdlcdev_xmit; |
| 8085 | |
| 8086 | /* register objects with HDLC layer */ |
| 8087 | if ((rc = register_hdlc_device(dev))) { |
| 8088 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); |
| 8089 | free_netdev(dev); |
| 8090 | return rc; |
| 8091 | } |
| 8092 | |
| 8093 | info->netdev = dev; |
| 8094 | return 0; |
| 8095 | } |
| 8096 | |
| 8097 | /** |
| 8098 | * called by device driver when removing device instance |
| 8099 | * do generic HDLC cleanup |
| 8100 | * |
| 8101 | * info pointer to device instance information |
| 8102 | */ |
| 8103 | static void hdlcdev_exit(struct mgsl_struct *info) |
| 8104 | { |
| 8105 | unregister_hdlc_device(info->netdev); |
| 8106 | free_netdev(info->netdev); |
| 8107 | info->netdev = NULL; |
| 8108 | } |
| 8109 | |
| 8110 | #endif /* CONFIG_HDLC */ |
| 8111 | |
| 8112 | |
| 8113 | static int __devinit synclink_init_one (struct pci_dev *dev, |
| 8114 | const struct pci_device_id *ent) |
| 8115 | { |
| 8116 | struct mgsl_struct *info; |
| 8117 | |
| 8118 | if (pci_enable_device(dev)) { |
| 8119 | printk("error enabling pci device %p\n", dev); |
| 8120 | return -EIO; |
| 8121 | } |
| 8122 | |
| 8123 | if (!(info = mgsl_allocate_device())) { |
| 8124 | printk("can't allocate device instance data.\n"); |
| 8125 | return -EIO; |
| 8126 | } |
| 8127 | |
| 8128 | /* Copy user configuration info to device instance data */ |
| 8129 | |
| 8130 | info->io_base = pci_resource_start(dev, 2); |
| 8131 | info->irq_level = dev->irq; |
| 8132 | info->phys_memory_base = pci_resource_start(dev, 3); |
| 8133 | |
| 8134 | /* Because veremap only works on page boundaries we must map |
| 8135 | * a larger area than is actually implemented for the LCR |
| 8136 | * memory range. We map a full page starting at the page boundary. |
| 8137 | */ |
| 8138 | info->phys_lcr_base = pci_resource_start(dev, 0); |
| 8139 | info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); |
| 8140 | info->phys_lcr_base &= ~(PAGE_SIZE-1); |
| 8141 | |
| 8142 | info->bus_type = MGSL_BUS_TYPE_PCI; |
| 8143 | info->io_addr_size = 8; |
Thomas Gleixner | 0f2ed4c | 2006-07-01 19:29:33 -0700 | [diff] [blame] | 8144 | info->irq_flags = IRQF_SHARED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8145 | |
| 8146 | if (dev->device == 0x0210) { |
| 8147 | /* Version 1 PCI9030 based universal PCI adapter */ |
| 8148 | info->misc_ctrl_value = 0x007c4080; |
| 8149 | info->hw_version = 1; |
| 8150 | } else { |
| 8151 | /* Version 0 PCI9050 based 5V PCI adapter |
| 8152 | * A PCI9050 bug prevents reading LCR registers if |
| 8153 | * LCR base address bit 7 is set. Maintain shadow |
| 8154 | * value so we can write to LCR misc control reg. |
| 8155 | */ |
| 8156 | info->misc_ctrl_value = 0x087e4546; |
| 8157 | info->hw_version = 0; |
| 8158 | } |
| 8159 | |
| 8160 | mgsl_add_device(info); |
| 8161 | |
| 8162 | return 0; |
| 8163 | } |
| 8164 | |
| 8165 | static void __devexit synclink_remove_one (struct pci_dev *dev) |
| 8166 | { |
| 8167 | } |
| 8168 | |