Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Processor capabilities determination functions. |
| 3 | * |
| 4 | * Copyright (C) xxxx the Anonymous |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 7 | * Copyright (C) 2001, 2004 MIPS Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/ptrace.h> |
| 17 | #include <linux/stddef.h> |
| 18 | |
Ralf Baechle | 5759906 | 2007-02-18 19:07:31 +0000 | [diff] [blame] | 19 | #include <asm/bugs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <asm/cpu.h> |
| 21 | #include <asm/fpu.h> |
| 22 | #include <asm/mipsregs.h> |
| 23 | #include <asm/system.h> |
| 24 | |
| 25 | /* |
| 26 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, |
| 27 | * the implementation of the "wait" feature differs between CPU families. This |
| 28 | * points to the function that implements CPU specific wait. |
| 29 | * The wait instruction stops the pipeline and reduces the power consumption of |
| 30 | * the CPU very much. |
| 31 | */ |
| 32 | void (*cpu_wait)(void) = NULL; |
| 33 | |
| 34 | static void r3081_wait(void) |
| 35 | { |
| 36 | unsigned long cfg = read_c0_conf(); |
| 37 | write_c0_conf(cfg | R30XX_CONF_HALT); |
| 38 | } |
| 39 | |
| 40 | static void r39xx_wait(void) |
| 41 | { |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 42 | local_irq_disable(); |
| 43 | if (!need_resched()) |
| 44 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); |
| 45 | local_irq_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | } |
| 47 | |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 48 | /* |
| 49 | * There is a race when WAIT instruction executed with interrupt |
| 50 | * enabled. |
| 51 | * But it is implementation-dependent wheter the pipelie restarts when |
| 52 | * a non-enabled interrupt is requested. |
| 53 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | static void r4k_wait(void) |
| 55 | { |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 56 | __asm__(" .set mips3 \n" |
| 57 | " wait \n" |
| 58 | " .set mips0 \n"); |
| 59 | } |
| 60 | |
| 61 | /* |
| 62 | * This variant is preferable as it allows testing need_resched and going to |
| 63 | * sleep depending on the outcome atomically. Unfortunately the "It is |
| 64 | * implementation-dependent whether the pipeline restarts when a non-enabled |
| 65 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes |
| 66 | * using this version a gamble. |
| 67 | */ |
| 68 | static void r4k_wait_irqoff(void) |
| 69 | { |
| 70 | local_irq_disable(); |
| 71 | if (!need_resched()) |
| 72 | __asm__(" .set mips3 \n" |
| 73 | " wait \n" |
| 74 | " .set mips0 \n"); |
| 75 | local_irq_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Pete Popov | 494900a | 2005-04-07 00:42:10 +0000 | [diff] [blame] | 78 | /* The Au1xxx wait is available only if using 32khz counter or |
| 79 | * external timer source, but specifically not CP0 Counter. */ |
Pete Popov | fe359bf | 2005-04-08 08:34:43 +0000 | [diff] [blame] | 80 | int allow_au1k_wait; |
Ralf Baechle | 10f650d | 2005-05-25 13:32:49 +0000 | [diff] [blame] | 81 | |
Pete Popov | 494900a | 2005-04-07 00:42:10 +0000 | [diff] [blame] | 82 | static void au1k_wait(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | /* using the wait instruction makes CP0 counter unusable */ |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 85 | __asm__(" .set mips3 \n" |
| 86 | " cache 0x14, 0(%0) \n" |
| 87 | " cache 0x14, 32(%0) \n" |
| 88 | " sync \n" |
| 89 | " nop \n" |
| 90 | " wait \n" |
| 91 | " nop \n" |
| 92 | " nop \n" |
| 93 | " nop \n" |
| 94 | " nop \n" |
| 95 | " .set mips0 \n" |
Ralf Baechle | 10f650d | 2005-05-25 13:32:49 +0000 | [diff] [blame] | 96 | : : "r" (au1k_wait)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | } |
| 98 | |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 99 | static int __initdata nowait = 0; |
| 100 | |
Atsushi Nemoto | f49a747 | 2007-02-18 01:02:14 +0900 | [diff] [blame^] | 101 | static int __init wait_disable(char *s) |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 102 | { |
| 103 | nowait = 1; |
| 104 | |
| 105 | return 1; |
| 106 | } |
| 107 | |
| 108 | __setup("nowait", wait_disable); |
| 109 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | static inline void check_wait(void) |
| 111 | { |
| 112 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 113 | |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 114 | if (nowait) { |
Ralf Baechle | c237923 | 2006-11-30 01:14:44 +0000 | [diff] [blame] | 115 | printk("Wait instruction disabled.\n"); |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 116 | return; |
| 117 | } |
| 118 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | switch (c->cputype) { |
| 120 | case CPU_R3081: |
| 121 | case CPU_R3081E: |
| 122 | cpu_wait = r3081_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | break; |
| 124 | case CPU_TX3927: |
| 125 | cpu_wait = r39xx_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | break; |
| 127 | case CPU_R4200: |
| 128 | /* case CPU_R4300: */ |
| 129 | case CPU_R4600: |
| 130 | case CPU_R4640: |
| 131 | case CPU_R4650: |
| 132 | case CPU_R4700: |
| 133 | case CPU_R5000: |
| 134 | case CPU_NEVADA: |
| 135 | case CPU_RM7000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | case CPU_4KC: |
| 137 | case CPU_4KEC: |
| 138 | case CPU_4KSC: |
| 139 | case CPU_5KC: |
| 140 | /* case CPU_20KC:*/ |
| 141 | case CPU_24K: |
| 142 | case CPU_25KF: |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 143 | case CPU_34K: |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 144 | case CPU_74K: |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 145 | case CPU_PR4450: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | cpu_wait = r4k_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | break; |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 148 | case CPU_TX49XX: |
| 149 | cpu_wait = r4k_wait_irqoff; |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 150 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | case CPU_AU1000: |
| 152 | case CPU_AU1100: |
| 153 | case CPU_AU1500: |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 154 | case CPU_AU1550: |
| 155 | case CPU_AU1200: |
Ralf Baechle | c237923 | 2006-11-30 01:14:44 +0000 | [diff] [blame] | 156 | if (allow_au1k_wait) |
Pete Popov | fe359bf | 2005-04-08 08:34:43 +0000 | [diff] [blame] | 157 | cpu_wait = au1k_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | break; |
Ralf Baechle | 441ee34 | 2006-06-02 11:48:11 +0100 | [diff] [blame] | 159 | case CPU_RM9000: |
Ralf Baechle | c237923 | 2006-11-30 01:14:44 +0000 | [diff] [blame] | 160 | if ((c->processor_id & 0x00ff) >= 0x40) |
Ralf Baechle | 441ee34 | 2006-06-02 11:48:11 +0100 | [diff] [blame] | 161 | cpu_wait = r4k_wait; |
Ralf Baechle | 441ee34 | 2006-06-02 11:48:11 +0100 | [diff] [blame] | 162 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | default: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | break; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | void __init check_bugs32(void) |
| 169 | { |
| 170 | check_wait(); |
| 171 | } |
| 172 | |
| 173 | /* |
| 174 | * Probe whether cpu has config register by trying to play with |
| 175 | * alternate cache bit and see whether it matters. |
| 176 | * It's used by cpu_probe to distinguish between R3000A and R3081. |
| 177 | */ |
| 178 | static inline int cpu_has_confreg(void) |
| 179 | { |
| 180 | #ifdef CONFIG_CPU_R3000 |
| 181 | extern unsigned long r3k_cache_size(unsigned long); |
| 182 | unsigned long size1, size2; |
| 183 | unsigned long cfg = read_c0_conf(); |
| 184 | |
| 185 | size1 = r3k_cache_size(ST0_ISC); |
| 186 | write_c0_conf(cfg ^ R30XX_CONF_AC); |
| 187 | size2 = r3k_cache_size(ST0_ISC); |
| 188 | write_c0_conf(cfg); |
| 189 | return size1 != size2; |
| 190 | #else |
| 191 | return 0; |
| 192 | #endif |
| 193 | } |
| 194 | |
| 195 | /* |
| 196 | * Get the FPU Implementation/Revision. |
| 197 | */ |
| 198 | static inline unsigned long cpu_get_fpu_id(void) |
| 199 | { |
| 200 | unsigned long tmp, fpu_id; |
| 201 | |
| 202 | tmp = read_c0_status(); |
| 203 | __enable_fpu(); |
| 204 | fpu_id = read_32bit_cp1_register(CP1_REVISION); |
| 205 | write_c0_status(tmp); |
| 206 | return fpu_id; |
| 207 | } |
| 208 | |
| 209 | /* |
| 210 | * Check the CPU has an FPU the official way. |
| 211 | */ |
| 212 | static inline int __cpu_has_fpu(void) |
| 213 | { |
| 214 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); |
| 215 | } |
| 216 | |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 217 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | | MIPS_CPU_COUNTER) |
| 219 | |
| 220 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c) |
| 221 | { |
| 222 | switch (c->processor_id & 0xff00) { |
| 223 | case PRID_IMP_R2000: |
| 224 | c->cputype = CPU_R2000; |
| 225 | c->isa_level = MIPS_CPU_ISA_I; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 226 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
| 227 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | if (__cpu_has_fpu()) |
| 229 | c->options |= MIPS_CPU_FPU; |
| 230 | c->tlbsize = 64; |
| 231 | break; |
| 232 | case PRID_IMP_R3000: |
| 233 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) |
| 234 | if (cpu_has_confreg()) |
| 235 | c->cputype = CPU_R3081E; |
| 236 | else |
| 237 | c->cputype = CPU_R3000A; |
| 238 | else |
| 239 | c->cputype = CPU_R3000; |
| 240 | c->isa_level = MIPS_CPU_ISA_I; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 241 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
| 242 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | if (__cpu_has_fpu()) |
| 244 | c->options |= MIPS_CPU_FPU; |
| 245 | c->tlbsize = 64; |
| 246 | break; |
| 247 | case PRID_IMP_R4000: |
| 248 | if (read_c0_config() & CONF_SC) { |
| 249 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) |
| 250 | c->cputype = CPU_R4400PC; |
| 251 | else |
| 252 | c->cputype = CPU_R4000PC; |
| 253 | } else { |
| 254 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) |
| 255 | c->cputype = CPU_R4400SC; |
| 256 | else |
| 257 | c->cputype = CPU_R4000SC; |
| 258 | } |
| 259 | |
| 260 | c->isa_level = MIPS_CPU_ISA_III; |
| 261 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 262 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
| 263 | MIPS_CPU_LLSC; |
| 264 | c->tlbsize = 48; |
| 265 | break; |
| 266 | case PRID_IMP_VR41XX: |
| 267 | switch (c->processor_id & 0xf0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | case PRID_REV_VR4111: |
| 269 | c->cputype = CPU_VR4111; |
| 270 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | case PRID_REV_VR4121: |
| 272 | c->cputype = CPU_VR4121; |
| 273 | break; |
| 274 | case PRID_REV_VR4122: |
| 275 | if ((c->processor_id & 0xf) < 0x3) |
| 276 | c->cputype = CPU_VR4122; |
| 277 | else |
| 278 | c->cputype = CPU_VR4181A; |
| 279 | break; |
| 280 | case PRID_REV_VR4130: |
| 281 | if ((c->processor_id & 0xf) < 0x4) |
| 282 | c->cputype = CPU_VR4131; |
| 283 | else |
| 284 | c->cputype = CPU_VR4133; |
| 285 | break; |
| 286 | default: |
| 287 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); |
| 288 | c->cputype = CPU_VR41XX; |
| 289 | break; |
| 290 | } |
| 291 | c->isa_level = MIPS_CPU_ISA_III; |
| 292 | c->options = R4K_OPTS; |
| 293 | c->tlbsize = 32; |
| 294 | break; |
| 295 | case PRID_IMP_R4300: |
| 296 | c->cputype = CPU_R4300; |
| 297 | c->isa_level = MIPS_CPU_ISA_III; |
| 298 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 299 | MIPS_CPU_LLSC; |
| 300 | c->tlbsize = 32; |
| 301 | break; |
| 302 | case PRID_IMP_R4600: |
| 303 | c->cputype = CPU_R4600; |
| 304 | c->isa_level = MIPS_CPU_ISA_III; |
Thiemo Seufer | 075e750 | 2005-07-27 21:48:12 +0000 | [diff] [blame] | 305 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 306 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 307 | c->tlbsize = 48; |
| 308 | break; |
| 309 | #if 0 |
| 310 | case PRID_IMP_R4650: |
| 311 | /* |
| 312 | * This processor doesn't have an MMU, so it's not |
| 313 | * "real easy" to run Linux on it. It is left purely |
| 314 | * for documentation. Commented out because it shares |
| 315 | * it's c0_prid id number with the TX3900. |
| 316 | */ |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 317 | c->cputype = CPU_R4650; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | c->isa_level = MIPS_CPU_ISA_III; |
| 319 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
| 320 | c->tlbsize = 48; |
| 321 | break; |
| 322 | #endif |
| 323 | case PRID_IMP_TX39: |
| 324 | c->isa_level = MIPS_CPU_ISA_I; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 325 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | |
| 327 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { |
| 328 | c->cputype = CPU_TX3927; |
| 329 | c->tlbsize = 64; |
| 330 | } else { |
| 331 | switch (c->processor_id & 0xff) { |
| 332 | case PRID_REV_TX3912: |
| 333 | c->cputype = CPU_TX3912; |
| 334 | c->tlbsize = 32; |
| 335 | break; |
| 336 | case PRID_REV_TX3922: |
| 337 | c->cputype = CPU_TX3922; |
| 338 | c->tlbsize = 64; |
| 339 | break; |
| 340 | default: |
| 341 | c->cputype = CPU_UNKNOWN; |
| 342 | break; |
| 343 | } |
| 344 | } |
| 345 | break; |
| 346 | case PRID_IMP_R4700: |
| 347 | c->cputype = CPU_R4700; |
| 348 | c->isa_level = MIPS_CPU_ISA_III; |
| 349 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 350 | MIPS_CPU_LLSC; |
| 351 | c->tlbsize = 48; |
| 352 | break; |
| 353 | case PRID_IMP_TX49: |
| 354 | c->cputype = CPU_TX49XX; |
| 355 | c->isa_level = MIPS_CPU_ISA_III; |
| 356 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
| 357 | if (!(c->processor_id & 0x08)) |
| 358 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; |
| 359 | c->tlbsize = 48; |
| 360 | break; |
| 361 | case PRID_IMP_R5000: |
| 362 | c->cputype = CPU_R5000; |
| 363 | c->isa_level = MIPS_CPU_ISA_IV; |
| 364 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 365 | MIPS_CPU_LLSC; |
| 366 | c->tlbsize = 48; |
| 367 | break; |
| 368 | case PRID_IMP_R5432: |
| 369 | c->cputype = CPU_R5432; |
| 370 | c->isa_level = MIPS_CPU_ISA_IV; |
| 371 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 372 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
| 373 | c->tlbsize = 48; |
| 374 | break; |
| 375 | case PRID_IMP_R5500: |
| 376 | c->cputype = CPU_R5500; |
| 377 | c->isa_level = MIPS_CPU_ISA_IV; |
| 378 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 379 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
| 380 | c->tlbsize = 48; |
| 381 | break; |
| 382 | case PRID_IMP_NEVADA: |
| 383 | c->cputype = CPU_NEVADA; |
| 384 | c->isa_level = MIPS_CPU_ISA_IV; |
| 385 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 386 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
| 387 | c->tlbsize = 48; |
| 388 | break; |
| 389 | case PRID_IMP_R6000: |
| 390 | c->cputype = CPU_R6000; |
| 391 | c->isa_level = MIPS_CPU_ISA_II; |
| 392 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
| 393 | MIPS_CPU_LLSC; |
| 394 | c->tlbsize = 32; |
| 395 | break; |
| 396 | case PRID_IMP_R6000A: |
| 397 | c->cputype = CPU_R6000A; |
| 398 | c->isa_level = MIPS_CPU_ISA_II; |
| 399 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
| 400 | MIPS_CPU_LLSC; |
| 401 | c->tlbsize = 32; |
| 402 | break; |
| 403 | case PRID_IMP_RM7000: |
| 404 | c->cputype = CPU_RM7000; |
| 405 | c->isa_level = MIPS_CPU_ISA_IV; |
| 406 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 407 | MIPS_CPU_LLSC; |
| 408 | /* |
| 409 | * Undocumented RM7000: Bit 29 in the info register of |
| 410 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
| 411 | * entries. |
| 412 | * |
| 413 | * 29 1 => 64 entry JTLB |
| 414 | * 0 => 48 entry JTLB |
| 415 | */ |
| 416 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 417 | break; |
| 418 | case PRID_IMP_RM9000: |
| 419 | c->cputype = CPU_RM9000; |
| 420 | c->isa_level = MIPS_CPU_ISA_IV; |
| 421 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 422 | MIPS_CPU_LLSC; |
| 423 | /* |
| 424 | * Bit 29 in the info register of the RM9000 |
| 425 | * indicates if the TLB has 48 or 64 entries. |
| 426 | * |
| 427 | * 29 1 => 64 entry JTLB |
| 428 | * 0 => 48 entry JTLB |
| 429 | */ |
| 430 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 431 | break; |
| 432 | case PRID_IMP_R8000: |
| 433 | c->cputype = CPU_R8000; |
| 434 | c->isa_level = MIPS_CPU_ISA_IV; |
| 435 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
| 436 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 437 | MIPS_CPU_LLSC; |
| 438 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
| 439 | break; |
| 440 | case PRID_IMP_R10000: |
| 441 | c->cputype = CPU_R10000; |
| 442 | c->isa_level = MIPS_CPU_ISA_IV; |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 443 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 445 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
| 446 | MIPS_CPU_LLSC; |
| 447 | c->tlbsize = 64; |
| 448 | break; |
| 449 | case PRID_IMP_R12000: |
| 450 | c->cputype = CPU_R12000; |
| 451 | c->isa_level = MIPS_CPU_ISA_IV; |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 452 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 454 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
| 455 | MIPS_CPU_LLSC; |
| 456 | c->tlbsize = 64; |
| 457 | break; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 458 | case PRID_IMP_R14000: |
| 459 | c->cputype = CPU_R14000; |
| 460 | c->isa_level = MIPS_CPU_ISA_IV; |
| 461 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
| 462 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 463 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
| 464 | MIPS_CPU_LLSC; |
| 465 | c->tlbsize = 64; |
| 466 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | } |
| 468 | } |
| 469 | |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 470 | static char unknown_isa[] __initdata = KERN_ERR \ |
| 471 | "Unsupported ISA type, c0.config0: %d."; |
| 472 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 473 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 475 | unsigned int config0; |
| 476 | int isa; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 478 | config0 = read_c0_config(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 480 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 481 | c->options |= MIPS_CPU_TLB; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 482 | isa = (config0 & MIPS_CONF_AT) >> 13; |
| 483 | switch (isa) { |
| 484 | case 0: |
Thiemo Seufer | 3a01c49 | 2006-07-03 13:30:01 +0100 | [diff] [blame] | 485 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 486 | case 0: |
| 487 | c->isa_level = MIPS_CPU_ISA_M32R1; |
| 488 | break; |
| 489 | case 1: |
| 490 | c->isa_level = MIPS_CPU_ISA_M32R2; |
| 491 | break; |
| 492 | default: |
| 493 | goto unknown; |
| 494 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 495 | break; |
| 496 | case 2: |
Thiemo Seufer | 3a01c49 | 2006-07-03 13:30:01 +0100 | [diff] [blame] | 497 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 498 | case 0: |
| 499 | c->isa_level = MIPS_CPU_ISA_M64R1; |
| 500 | break; |
| 501 | case 1: |
| 502 | c->isa_level = MIPS_CPU_ISA_M64R2; |
| 503 | break; |
| 504 | default: |
| 505 | goto unknown; |
| 506 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 507 | break; |
| 508 | default: |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 509 | goto unknown; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | return config0 & MIPS_CONF_M; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 513 | |
| 514 | unknown: |
| 515 | panic(unknown_isa, config0); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) |
| 519 | { |
| 520 | unsigned int config1; |
| 521 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | config1 = read_c0_config1(); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 523 | |
| 524 | if (config1 & MIPS_CONF1_MD) |
| 525 | c->ases |= MIPS_ASE_MDMX; |
| 526 | if (config1 & MIPS_CONF1_WR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | c->options |= MIPS_CPU_WATCH; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 528 | if (config1 & MIPS_CONF1_CA) |
| 529 | c->ases |= MIPS_ASE_MIPS16; |
| 530 | if (config1 & MIPS_CONF1_EP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | c->options |= MIPS_CPU_EJTAG; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 532 | if (config1 & MIPS_CONF1_FP) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 533 | c->options |= MIPS_CPU_FPU; |
| 534 | c->options |= MIPS_CPU_32FPR; |
| 535 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 536 | if (cpu_has_tlb) |
| 537 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
| 538 | |
| 539 | return config1 & MIPS_CONF_M; |
| 540 | } |
| 541 | |
| 542 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) |
| 543 | { |
| 544 | unsigned int config2; |
| 545 | |
| 546 | config2 = read_c0_config2(); |
| 547 | |
| 548 | if (config2 & MIPS_CONF2_SL) |
| 549 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
| 550 | |
| 551 | return config2 & MIPS_CONF_M; |
| 552 | } |
| 553 | |
| 554 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) |
| 555 | { |
| 556 | unsigned int config3; |
| 557 | |
| 558 | config3 = read_c0_config3(); |
| 559 | |
| 560 | if (config3 & MIPS_CONF3_SM) |
| 561 | c->ases |= MIPS_ASE_SMARTMIPS; |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 562 | if (config3 & MIPS_CONF3_DSP) |
| 563 | c->ases |= MIPS_ASE_DSP; |
Ralf Baechle | 8f40611 | 2005-07-14 07:34:18 +0000 | [diff] [blame] | 564 | if (config3 & MIPS_CONF3_VINT) |
| 565 | c->options |= MIPS_CPU_VINT; |
| 566 | if (config3 & MIPS_CONF3_VEIC) |
| 567 | c->options |= MIPS_CPU_VEIC; |
| 568 | if (config3 & MIPS_CONF3_MT) |
Ralf Baechle | e0daad4 | 2007-02-05 00:10:11 +0000 | [diff] [blame] | 569 | c->ases |= MIPS_ASE_MIPSMT; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 570 | |
| 571 | return config3 & MIPS_CONF_M; |
| 572 | } |
| 573 | |
Thiemo Seufer | c36cd4b | 2006-07-03 13:30:01 +0100 | [diff] [blame] | 574 | static void __init decode_configs(struct cpuinfo_mips *c) |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 575 | { |
| 576 | /* MIPS32 or MIPS64 compliant CPU. */ |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 577 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
| 578 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 579 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
| 581 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 582 | /* Read Config registers. */ |
| 583 | if (!decode_config0(c)) |
| 584 | return; /* actually worth a panic() */ |
| 585 | if (!decode_config1(c)) |
| 586 | return; |
| 587 | if (!decode_config2(c)) |
| 588 | return; |
| 589 | if (!decode_config3(c)) |
| 590 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | static inline void cpu_probe_mips(struct cpuinfo_mips *c) |
| 594 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 595 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | switch (c->processor_id & 0xff00) { |
| 597 | case PRID_IMP_4KC: |
| 598 | c->cputype = CPU_4KC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | break; |
| 600 | case PRID_IMP_4KEC: |
| 601 | c->cputype = CPU_4KEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | break; |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 603 | case PRID_IMP_4KECR2: |
| 604 | c->cputype = CPU_4KEC; |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 605 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | case PRID_IMP_4KSC: |
Ralf Baechle | 8afcb5d | 2005-10-04 15:01:26 +0100 | [diff] [blame] | 607 | case PRID_IMP_4KSD: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | c->cputype = CPU_4KSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 609 | break; |
| 610 | case PRID_IMP_5KC: |
| 611 | c->cputype = CPU_5KC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | break; |
| 613 | case PRID_IMP_20KC: |
| 614 | c->cputype = CPU_20KC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | break; |
| 616 | case PRID_IMP_24K: |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 617 | case PRID_IMP_24KE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | c->cputype = CPU_24K; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | break; |
| 620 | case PRID_IMP_25KF: |
| 621 | c->cputype = CPU_25KF; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | break; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 623 | case PRID_IMP_34K: |
| 624 | c->cputype = CPU_34K; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 625 | break; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 626 | case PRID_IMP_74K: |
| 627 | c->cputype = CPU_74K; |
| 628 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | } |
| 630 | } |
| 631 | |
| 632 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) |
| 633 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 634 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | switch (c->processor_id & 0xff00) { |
| 636 | case PRID_IMP_AU1_REV1: |
| 637 | case PRID_IMP_AU1_REV2: |
| 638 | switch ((c->processor_id >> 24) & 0xff) { |
| 639 | case 0: |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 640 | c->cputype = CPU_AU1000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 641 | break; |
| 642 | case 1: |
| 643 | c->cputype = CPU_AU1500; |
| 644 | break; |
| 645 | case 2: |
| 646 | c->cputype = CPU_AU1100; |
| 647 | break; |
| 648 | case 3: |
| 649 | c->cputype = CPU_AU1550; |
| 650 | break; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 651 | case 4: |
| 652 | c->cputype = CPU_AU1200; |
| 653 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | default: |
| 655 | panic("Unknown Au Core!"); |
| 656 | break; |
| 657 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | break; |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) |
| 663 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 664 | decode_configs(c); |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 665 | |
| 666 | /* |
| 667 | * For historical reasons the SB1 comes with it's own variant of |
| 668 | * cache code which eventually will be folded into c-r4k.c. Until |
| 669 | * then we pretend it's got it's own cache architecture. |
| 670 | */ |
Andrew Isaacson | d121ced | 2005-10-19 23:54:43 -0700 | [diff] [blame] | 671 | c->options &= ~MIPS_CPU_4K_CACHE; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 672 | c->options |= MIPS_CPU_SB1_CACHE; |
| 673 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | switch (c->processor_id & 0xff00) { |
| 675 | case PRID_IMP_SB1: |
| 676 | c->cputype = CPU_SB1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | /* FPU in pass1 is known to have issues. */ |
Ralf Baechle | aa32374 | 2006-05-29 00:02:12 +0100 | [diff] [blame] | 678 | if ((c->processor_id & 0xff) < 0x02) |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 679 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | break; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 681 | case PRID_IMP_SB1A: |
| 682 | c->cputype = CPU_SB1A; |
| 683 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | } |
| 685 | } |
| 686 | |
| 687 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) |
| 688 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 689 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 690 | switch (c->processor_id & 0xff00) { |
| 691 | case PRID_IMP_SR71000: |
| 692 | c->cputype = CPU_SR71000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | c->scache.ways = 8; |
| 694 | c->tlbsize = 64; |
| 695 | break; |
| 696 | } |
| 697 | } |
| 698 | |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 699 | static inline void cpu_probe_philips(struct cpuinfo_mips *c) |
| 700 | { |
| 701 | decode_configs(c); |
| 702 | switch (c->processor_id & 0xff00) { |
| 703 | case PRID_IMP_PR4450: |
| 704 | c->cputype = CPU_PR4450; |
Ralf Baechle | e7958bb | 2005-12-08 13:00:20 +0000 | [diff] [blame] | 705 | c->isa_level = MIPS_CPU_ISA_M32R1; |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 706 | break; |
| 707 | default: |
| 708 | panic("Unknown Philips Core!"); /* REVISIT: die? */ |
| 709 | break; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | __init void cpu_probe(void) |
| 715 | { |
| 716 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 717 | |
| 718 | c->processor_id = PRID_IMP_UNKNOWN; |
| 719 | c->fpu_id = FPIR_IMP_NONE; |
| 720 | c->cputype = CPU_UNKNOWN; |
| 721 | |
| 722 | c->processor_id = read_c0_prid(); |
| 723 | switch (c->processor_id & 0xff0000) { |
| 724 | case PRID_COMP_LEGACY: |
| 725 | cpu_probe_legacy(c); |
| 726 | break; |
| 727 | case PRID_COMP_MIPS: |
| 728 | cpu_probe_mips(c); |
| 729 | break; |
| 730 | case PRID_COMP_ALCHEMY: |
| 731 | cpu_probe_alchemy(c); |
| 732 | break; |
| 733 | case PRID_COMP_SIBYTE: |
| 734 | cpu_probe_sibyte(c); |
| 735 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 736 | case PRID_COMP_SANDCRAFT: |
| 737 | cpu_probe_sandcraft(c); |
| 738 | break; |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 739 | case PRID_COMP_PHILIPS: |
| 740 | cpu_probe_philips(c); |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 741 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | default: |
| 743 | c->cputype = CPU_UNKNOWN; |
| 744 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 745 | if (c->options & MIPS_CPU_FPU) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 746 | c->fpu_id = cpu_get_fpu_id(); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 747 | |
Ralf Baechle | e7958bb | 2005-12-08 13:00:20 +0000 | [diff] [blame] | 748 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 749 | c->isa_level == MIPS_CPU_ISA_M32R2 || |
| 750 | c->isa_level == MIPS_CPU_ISA_M64R1 || |
| 751 | c->isa_level == MIPS_CPU_ISA_M64R2) { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 752 | if (c->fpu_id & MIPS_FPIR_3D) |
| 753 | c->ases |= MIPS_ASE_MIPS3D; |
| 754 | } |
| 755 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | } |
| 757 | |
| 758 | __init void cpu_report(void) |
| 759 | { |
| 760 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 761 | |
| 762 | printk("CPU revision is: %08x\n", c->processor_id); |
| 763 | if (c->options & MIPS_CPU_FPU) |
| 764 | printk("FPU revision is: %08x\n", c->fpu_id); |
| 765 | } |