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Gabor Juhosd4a67d92011-01-04 21:28:14 +01001/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
Gabor Juhos88896122012-03-14 10:45:22 +01004 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
Gabor Juhosd4a67d92011-01-04 21:28:14 +01005 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
Gabor Juhos88896122012-03-14 10:45:22 +01007 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *
Gabor Juhosd4a67d92011-01-04 21:28:14 +01009 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/clk.h>
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020019#include <linux/clkdev.h>
Alban Bedel411520a2015-04-19 14:30:04 +020020#include <linux/clk-provider.h>
Gabor Juhosd4a67d92011-01-04 21:28:14 +010021
Gabor Juhos97541cc2012-09-08 14:02:21 +020022#include <asm/div64.h>
23
Gabor Juhosd4a67d92011-01-04 21:28:14 +010024#include <asm/mach-ath79/ath79.h>
25#include <asm/mach-ath79/ar71xx_regs.h>
26#include "common.h"
27
28#define AR71XX_BASE_FREQ 40000000
Weijie Gaoc338d592016-03-17 06:34:09 +030029#define AR724X_BASE_FREQ 40000000
Gabor Juhosd4a67d92011-01-04 21:28:14 +010030
Alban Bedel6451af02015-05-31 02:18:22 +020031static struct clk *clks[3];
32static struct clk_onecell_data clk_data = {
33 .clks = clks,
34 .clk_num = ARRAY_SIZE(clks),
35};
36
37static struct clk *__init ath79_add_sys_clkdev(
38 const char *id, unsigned long rate)
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020039{
40 struct clk *clk;
41 int err;
42
Alban Bedel411520a2015-04-19 14:30:04 +020043 clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020044 if (!clk)
45 panic("failed to allocate %s clock structure", id);
46
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020047 err = clk_register_clkdev(clk, id, NULL);
48 if (err)
49 panic("unable to register %s clock device", id);
Alban Bedel6451af02015-05-31 02:18:22 +020050
51 return clk;
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020052}
Gabor Juhosd4a67d92011-01-04 21:28:14 +010053
54static void __init ar71xx_clocks_init(void)
55{
Gabor Juhos6612a682013-08-28 10:41:46 +020056 unsigned long ref_rate;
57 unsigned long cpu_rate;
58 unsigned long ddr_rate;
59 unsigned long ahb_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010060 u32 pll;
61 u32 freq;
62 u32 div;
63
Gabor Juhos6612a682013-08-28 10:41:46 +020064 ref_rate = AR71XX_BASE_FREQ;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010065
66 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
67
Alban Bedel626a0692015-04-19 14:30:02 +020068 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020069 freq = div * ref_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010070
71 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020072 cpu_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010073
74 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020075 ddr_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010076
77 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
Gabor Juhos6612a682013-08-28 10:41:46 +020078 ahb_rate = cpu_rate / div;
79
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020080 ath79_add_sys_clkdev("ref", ref_rate);
Alban Bedel6451af02015-05-31 02:18:22 +020081 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
82 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
83 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhosd4a67d92011-01-04 21:28:14 +010084
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020085 clk_add_alias("wdt", NULL, "ahb", NULL);
86 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +010087}
88
89static void __init ar724x_clocks_init(void)
90{
Gabor Juhos6612a682013-08-28 10:41:46 +020091 unsigned long ref_rate;
92 unsigned long cpu_rate;
93 unsigned long ddr_rate;
94 unsigned long ahb_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010095 u32 pll;
96 u32 freq;
97 u32 div;
98
Gabor Juhos6612a682013-08-28 10:41:46 +020099 ref_rate = AR724X_BASE_FREQ;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100100 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
101
Alban Bedel626a0692015-04-19 14:30:02 +0200102 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
Gabor Juhos6612a682013-08-28 10:41:46 +0200103 freq = div * ref_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100104
Weijie Gaoc338d592016-03-17 06:34:09 +0300105 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
106 freq /= div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100107
Gabor Juhos6612a682013-08-28 10:41:46 +0200108 cpu_rate = freq;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100109
110 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200111 ddr_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100112
113 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
Gabor Juhos6612a682013-08-28 10:41:46 +0200114 ahb_rate = cpu_rate / div;
115
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200116 ath79_add_sys_clkdev("ref", ref_rate);
Alban Bedel6451af02015-05-31 02:18:22 +0200117 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
118 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
119 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100120
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200121 clk_add_alias("wdt", NULL, "ahb", NULL);
122 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100123}
124
Gabor Juhos04225e12011-06-20 21:26:04 +0200125static void __init ar933x_clocks_init(void)
126{
Gabor Juhos6612a682013-08-28 10:41:46 +0200127 unsigned long ref_rate;
128 unsigned long cpu_rate;
129 unsigned long ddr_rate;
130 unsigned long ahb_rate;
Gabor Juhos04225e12011-06-20 21:26:04 +0200131 u32 clock_ctrl;
132 u32 cpu_config;
133 u32 freq;
134 u32 t;
135
136 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
137 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200138 ref_rate = (40 * 1000 * 1000);
Gabor Juhos04225e12011-06-20 21:26:04 +0200139 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200140 ref_rate = (25 * 1000 * 1000);
Gabor Juhos04225e12011-06-20 21:26:04 +0200141
142 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
143 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
Gabor Juhos6612a682013-08-28 10:41:46 +0200144 cpu_rate = ref_rate;
145 ahb_rate = ref_rate;
146 ddr_rate = ref_rate;
Gabor Juhos04225e12011-06-20 21:26:04 +0200147 } else {
148 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
149
150 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
151 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
Gabor Juhos6612a682013-08-28 10:41:46 +0200152 freq = ref_rate / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200153
154 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
155 AR933X_PLL_CPU_CONFIG_NINT_MASK;
156 freq *= t;
157
158 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
159 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
160 if (t == 0)
161 t = 1;
162
163 freq >>= t;
164
165 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
166 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200167 cpu_rate = freq / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200168
169 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
170 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200171 ddr_rate = freq / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200172
173 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
174 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +0200175 ahb_rate = freq / t;
Gabor Juhos04225e12011-06-20 21:26:04 +0200176 }
177
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200178 ath79_add_sys_clkdev("ref", ref_rate);
Alban Bedel6451af02015-05-31 02:18:22 +0200179 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
180 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
181 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos6612a682013-08-28 10:41:46 +0200182
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200183 clk_add_alias("wdt", NULL, "ahb", NULL);
184 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos04225e12011-06-20 21:26:04 +0200185}
186
Gabor Juhos97541cc2012-09-08 14:02:21 +0200187static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
188 u32 frac, u32 out_div)
189{
190 u64 t;
191 u32 ret;
192
Gabor Juhos837f0362013-08-28 10:41:43 +0200193 t = ref;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200194 t *= nint;
195 do_div(t, ref_div);
196 ret = t;
197
Gabor Juhos837f0362013-08-28 10:41:43 +0200198 t = ref;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200199 t *= nfrac;
200 do_div(t, ref_div * frac);
201 ret += t;
202
203 ret /= (1 << out_div);
204 return ret;
205}
206
Gabor Juhos88896122012-03-14 10:45:22 +0100207static void __init ar934x_clocks_init(void)
208{
Gabor Juhos6612a682013-08-28 10:41:46 +0200209 unsigned long ref_rate;
210 unsigned long cpu_rate;
211 unsigned long ddr_rate;
212 unsigned long ahb_rate;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200213 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
Gabor Juhos88896122012-03-14 10:45:22 +0100214 u32 cpu_pll, ddr_pll;
215 u32 bootstrap;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200216 void __iomem *dpll_base;
217
218 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
Gabor Juhos88896122012-03-14 10:45:22 +0100219
220 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
Ralf Baechle70342282013-01-22 12:59:30 +0100221 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200222 ref_rate = 40 * 1000 * 1000;
Gabor Juhos88896122012-03-14 10:45:22 +0100223 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200224 ref_rate = 25 * 1000 * 1000;
Gabor Juhos88896122012-03-14 10:45:22 +0100225
Gabor Juhos97541cc2012-09-08 14:02:21 +0200226 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
227 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
228 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
229 AR934X_SRIF_DPLL2_OUTDIV_MASK;
230 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
231 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
232 AR934X_SRIF_DPLL1_NINT_MASK;
233 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
234 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
235 AR934X_SRIF_DPLL1_REFDIV_MASK;
236 frac = 1 << 18;
237 } else {
238 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
239 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
240 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
241 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
242 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
243 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
244 AR934X_PLL_CPU_CONFIG_NINT_MASK;
245 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
246 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
247 frac = 1 << 6;
248 }
Gabor Juhos88896122012-03-14 10:45:22 +0100249
Gabor Juhos6612a682013-08-28 10:41:46 +0200250 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
Gabor Juhos97541cc2012-09-08 14:02:21 +0200251 nfrac, frac, out_div);
Gabor Juhos88896122012-03-14 10:45:22 +0100252
Gabor Juhos97541cc2012-09-08 14:02:21 +0200253 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
254 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
255 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
256 AR934X_SRIF_DPLL2_OUTDIV_MASK;
257 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
258 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
259 AR934X_SRIF_DPLL1_NINT_MASK;
260 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
261 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
262 AR934X_SRIF_DPLL1_REFDIV_MASK;
263 frac = 1 << 18;
264 } else {
265 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
266 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
267 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
268 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
269 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
270 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
271 AR934X_PLL_DDR_CONFIG_NINT_MASK;
272 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
273 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
274 frac = 1 << 10;
275 }
Gabor Juhos88896122012-03-14 10:45:22 +0100276
Gabor Juhos6612a682013-08-28 10:41:46 +0200277 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
Gabor Juhos97541cc2012-09-08 14:02:21 +0200278 nfrac, frac, out_div);
Gabor Juhos88896122012-03-14 10:45:22 +0100279
280 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
281
282 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
283 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
284
285 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200286 cpu_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100287 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200288 cpu_rate = cpu_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100289 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200290 cpu_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100291
292 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
293 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
294
295 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200296 ddr_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100297 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200298 ddr_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100299 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200300 ddr_rate = cpu_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100301
302 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
303 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
304
305 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200306 ahb_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100307 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200308 ahb_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100309 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200310 ahb_rate = cpu_pll / (postdiv + 1);
311
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200312 ath79_add_sys_clkdev("ref", ref_rate);
Alban Bedel6451af02015-05-31 02:18:22 +0200313 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
314 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
315 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos88896122012-03-14 10:45:22 +0100316
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200317 clk_add_alias("wdt", NULL, "ref", NULL);
318 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos97541cc2012-09-08 14:02:21 +0200319
320 iounmap(dpll_base);
Gabor Juhos88896122012-03-14 10:45:22 +0100321}
322
Gabor Juhos41583c02013-02-15 13:38:17 +0000323static void __init qca955x_clocks_init(void)
324{
Gabor Juhos6612a682013-08-28 10:41:46 +0200325 unsigned long ref_rate;
326 unsigned long cpu_rate;
327 unsigned long ddr_rate;
328 unsigned long ahb_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000329 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
330 u32 cpu_pll, ddr_pll;
331 u32 bootstrap;
332
333 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
334 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200335 ref_rate = 40 * 1000 * 1000;
Gabor Juhos41583c02013-02-15 13:38:17 +0000336 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200337 ref_rate = 25 * 1000 * 1000;
Gabor Juhos41583c02013-02-15 13:38:17 +0000338
339 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
340 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
341 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
342 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
343 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
344 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
345 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
346 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
347 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
348
Gabor Juhos6612a682013-08-28 10:41:46 +0200349 cpu_pll = nint * ref_rate / ref_div;
350 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
Gabor Juhos41583c02013-02-15 13:38:17 +0000351 cpu_pll /= (1 << out_div);
352
353 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
354 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
355 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
356 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
357 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
358 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
359 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
360 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
361 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
362
Gabor Juhos6612a682013-08-28 10:41:46 +0200363 ddr_pll = nint * ref_rate / ref_div;
364 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
Gabor Juhos41583c02013-02-15 13:38:17 +0000365 ddr_pll /= (1 << out_div);
366
367 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
368
369 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
370 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
371
372 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200373 cpu_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000374 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200375 cpu_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000376 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200377 cpu_rate = cpu_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000378
379 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
380 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
381
382 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200383 ddr_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000384 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200385 ddr_rate = cpu_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000386 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200387 ddr_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000388
389 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
390 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
391
392 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200393 ahb_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000394 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200395 ahb_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000396 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200397 ahb_rate = cpu_pll / (postdiv + 1);
398
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200399 ath79_add_sys_clkdev("ref", ref_rate);
Alban Bedel6451af02015-05-31 02:18:22 +0200400 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
401 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
402 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos41583c02013-02-15 13:38:17 +0000403
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200404 clk_add_alias("wdt", NULL, "ref", NULL);
405 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos41583c02013-02-15 13:38:17 +0000406}
407
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100408void __init ath79_clocks_init(void)
409{
410 if (soc_is_ar71xx())
411 ar71xx_clocks_init();
Alban Bedelf4c87b72016-03-17 06:34:10 +0300412 else if (soc_is_ar724x() || soc_is_ar913x())
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100413 ar724x_clocks_init();
Gabor Juhos04225e12011-06-20 21:26:04 +0200414 else if (soc_is_ar933x())
415 ar933x_clocks_init();
Gabor Juhos88896122012-03-14 10:45:22 +0100416 else if (soc_is_ar934x())
417 ar934x_clocks_init();
Gabor Juhos41583c02013-02-15 13:38:17 +0000418 else if (soc_is_qca955x())
419 qca955x_clocks_init();
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100420 else
421 BUG();
Alban Bedel6451af02015-05-31 02:18:22 +0200422
423 of_clk_init(NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100424}
425
Gabor Juhos23107802013-08-28 10:41:44 +0200426unsigned long __init
427ath79_get_sys_clk_rate(const char *id)
428{
429 struct clk *clk;
430 unsigned long rate;
431
432 clk = clk_get(NULL, id);
433 if (IS_ERR(clk))
434 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
435
436 rate = clk_get_rate(clk);
437 clk_put(clk);
438
439 return rate;
440}
Alban Bedel6451af02015-05-31 02:18:22 +0200441
442#ifdef CONFIG_OF
443static void __init ath79_clocks_init_dt(struct device_node *np)
444{
445 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
446}
447
448CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
449CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
450CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
451CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
452CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
453CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
454#endif