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Kalle Valo5e3dd152013-06-12 20:52:10 +03001/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _CORE_H_
19#define _CORE_H_
20
21#include <linux/completion.h>
22#include <linux/if_ether.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25
Michal Kazioredb82362013-07-05 16:15:14 +030026#include "htt.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030027#include "htc.h"
28#include "hw.h"
29#include "targaddrs.h"
30#include "wmi.h"
31#include "../ath.h"
32#include "../regd.h"
33
34#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
35#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
36#define WO(_f) ((_f##_OFFSET) >> 2)
37
38#define ATH10K_SCAN_ID 0
39#define WMI_READY_TIMEOUT (5 * HZ)
40#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
41
42/* Antenna noise floor */
43#define ATH10K_DEFAULT_NOISE_FLOOR -95
44
45struct ath10k;
46
Kalle Valo5e3dd152013-06-12 20:52:10 +030047struct ath10k_skb_cb {
48 dma_addr_t paddr;
49 bool is_mapped;
50 bool is_aborted;
51
52 struct {
53 u8 vdev_id;
54 u16 msdu_id;
55 u8 tid;
56 bool is_offchan;
57 bool is_conf;
58 bool discard;
59 bool no_ack;
60 u8 refcount;
61 struct sk_buff *txfrag;
62 struct sk_buff *msdu;
63 } __packed htt;
64
65 /* 4 bytes left on 64bit arch */
66} __packed;
67
68static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
69{
70 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
71 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
72 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
73}
74
75static inline int ath10k_skb_map(struct device *dev, struct sk_buff *skb)
76{
77 if (ATH10K_SKB_CB(skb)->is_mapped)
78 return -EINVAL;
79
80 ATH10K_SKB_CB(skb)->paddr = dma_map_single(dev, skb->data, skb->len,
81 DMA_TO_DEVICE);
82
83 if (unlikely(dma_mapping_error(dev, ATH10K_SKB_CB(skb)->paddr)))
84 return -EIO;
85
86 ATH10K_SKB_CB(skb)->is_mapped = true;
87 return 0;
88}
89
90static inline int ath10k_skb_unmap(struct device *dev, struct sk_buff *skb)
91{
92 if (!ATH10K_SKB_CB(skb)->is_mapped)
93 return -EINVAL;
94
95 dma_unmap_single(dev, ATH10K_SKB_CB(skb)->paddr, skb->len,
96 DMA_TO_DEVICE);
97 ATH10K_SKB_CB(skb)->is_mapped = false;
98 return 0;
99}
100
101static inline u32 host_interest_item_address(u32 item_offset)
102{
103 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
104}
105
106struct ath10k_bmi {
107 bool done_sent;
108};
109
110struct ath10k_wmi {
111 enum ath10k_htc_ep_id eid;
112 struct completion service_ready;
113 struct completion unified_ready;
114 atomic_t pending_tx_count;
115 wait_queue_head_t wq;
116
117 struct sk_buff_head wmi_event_list;
118 struct work_struct wmi_event_work;
119};
120
121struct ath10k_peer_stat {
122 u8 peer_macaddr[ETH_ALEN];
123 u32 peer_rssi;
124 u32 peer_tx_rate;
125};
126
127struct ath10k_target_stats {
128 /* PDEV stats */
129 s32 ch_noise_floor;
130 u32 tx_frame_count;
131 u32 rx_frame_count;
132 u32 rx_clear_count;
133 u32 cycle_count;
134 u32 phy_err_count;
135 u32 chan_tx_power;
136
137 /* PDEV TX stats */
138 s32 comp_queued;
139 s32 comp_delivered;
140 s32 msdu_enqued;
141 s32 mpdu_enqued;
142 s32 wmm_drop;
143 s32 local_enqued;
144 s32 local_freed;
145 s32 hw_queued;
146 s32 hw_reaped;
147 s32 underrun;
148 s32 tx_abort;
149 s32 mpdus_requed;
150 u32 tx_ko;
151 u32 data_rc;
152 u32 self_triggers;
153 u32 sw_retry_failure;
154 u32 illgl_rate_phy_err;
155 u32 pdev_cont_xretry;
156 u32 pdev_tx_timeout;
157 u32 pdev_resets;
158 u32 phy_underrun;
159 u32 txop_ovf;
160
161 /* PDEV RX stats */
162 s32 mid_ppdu_route_change;
163 s32 status_rcvd;
164 s32 r0_frags;
165 s32 r1_frags;
166 s32 r2_frags;
167 s32 r3_frags;
168 s32 htt_msdus;
169 s32 htt_mpdus;
170 s32 loc_msdus;
171 s32 loc_mpdus;
172 s32 oversize_amsdu;
173 s32 phy_errs;
174 s32 phy_err_drop;
175 s32 mpdu_errs;
176
177 /* VDEV STATS */
178
179 /* PEER STATS */
180 u8 peers;
181 struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];
182
183 /* TODO: Beacon filter stats */
184
185};
186
187#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
188
189struct ath10k_peer {
190 struct list_head list;
191 int vdev_id;
192 u8 addr[ETH_ALEN];
193 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
194 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
195};
196
197#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
198
199struct ath10k_vif {
200 u32 vdev_id;
201 enum wmi_vdev_type vdev_type;
202 enum wmi_vdev_subtype vdev_subtype;
203 u32 beacon_interval;
204 u32 dtim_period;
205
206 struct ath10k *ar;
207 struct ieee80211_vif *vif;
208
209 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
210 u8 def_wep_key_index;
211
212 u16 tx_seq_no;
213
214 union {
215 struct {
216 u8 bssid[ETH_ALEN];
217 u32 uapsd;
218 } sta;
219 struct {
220 /* 127 stations; wmi limit */
221 u8 tim_bitmap[16];
222 u8 tim_len;
223 u32 ssid_len;
224 u8 ssid[IEEE80211_MAX_SSID_LEN];
225 bool hidden_ssid;
226 /* P2P_IE with NoA attribute for P2P_GO case */
227 u32 noa_len;
228 u8 *noa_data;
229 } ap;
230 struct {
231 u8 bssid[ETH_ALEN];
232 } ibss;
233 } u;
234};
235
236struct ath10k_vif_iter {
237 u32 vdev_id;
238 struct ath10k_vif *arvif;
239};
240
241struct ath10k_debug {
242 struct dentry *debugfs_phy;
243
244 struct ath10k_target_stats target_stats;
245 u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
246
247 struct completion event_stats_compl;
248};
249
Michal Kaziorf7843d72013-07-16 09:38:52 +0200250enum ath10k_state {
251 ATH10K_STATE_OFF = 0,
252 ATH10K_STATE_ON,
253};
254
Kalle Valo5e3dd152013-06-12 20:52:10 +0300255struct ath10k {
256 struct ath_common ath_common;
257 struct ieee80211_hw *hw;
258 struct device *dev;
259 u8 mac_addr[ETH_ALEN];
260
261 u32 target_version;
262 u8 fw_version_major;
263 u32 fw_version_minor;
264 u16 fw_version_release;
265 u16 fw_version_build;
266 u32 phy_capability;
267 u32 hw_min_tx_power;
268 u32 hw_max_tx_power;
269 u32 ht_cap_info;
270 u32 vht_cap_info;
271
272 struct targetdef *targetdef;
273 struct hostdef *hostdef;
274
275 bool p2p;
276
277 struct {
278 void *priv;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300279 const struct ath10k_hif_ops *ops;
280 } hif;
281
Kalle Valo5e3dd152013-06-12 20:52:10 +0300282 wait_queue_head_t event_queue;
283 bool is_target_paused;
284
285 struct ath10k_bmi bmi;
Michal Kazioredb82362013-07-05 16:15:14 +0300286 struct ath10k_wmi wmi;
Michal Kaziorcd003fa2013-07-05 16:15:13 +0300287 struct ath10k_htc htc;
Michal Kazioredb82362013-07-05 16:15:14 +0300288 struct ath10k_htt htt;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300289
290 struct ath10k_hw_params {
291 u32 id;
292 const char *name;
293 u32 patch_load_addr;
294
295 struct ath10k_hw_params_fw {
296 const char *dir;
297 const char *fw;
298 const char *otp;
299 const char *board;
300 } fw;
301 } hw_params;
302
303 struct {
304 struct completion started;
305 struct completion completed;
306 struct completion on_channel;
307 struct timer_list timeout;
308 bool is_roc;
309 bool in_progress;
310 bool aborting;
311 int vdev_id;
312 int roc_freq;
313 } scan;
314
315 struct {
316 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
317 } mac;
318
319 /* should never be NULL; needed for regular htt rx */
320 struct ieee80211_channel *rx_channel;
321
322 /* valid during scan; needed for mgmt rx during scan */
323 struct ieee80211_channel *scan_channel;
324
325 int free_vdev_map;
326 int monitor_vdev_id;
327 bool monitor_enabled;
328 bool monitor_present;
329 unsigned int filter_flags;
330
331 struct wmi_pdev_set_wmm_params_arg wmm_params;
332 struct completion install_key_done;
333
334 struct completion vdev_setup_done;
335
336 struct workqueue_struct *workqueue;
337
338 /* prevents concurrent FW reconfiguration */
339 struct mutex conf_mutex;
340
341 /* protects shared structure data */
342 spinlock_t data_lock;
343
344 struct list_head peers;
345 wait_queue_head_t peer_mapping_wq;
346
347 struct work_struct offchan_tx_work;
348 struct sk_buff_head offchan_tx_queue;
349 struct completion offchan_tx_completed;
350 struct sk_buff *offchan_tx_skb;
351
Michal Kaziorf7843d72013-07-16 09:38:52 +0200352 enum ath10k_state state;
353
Kalle Valo5e3dd152013-06-12 20:52:10 +0300354#ifdef CONFIG_ATH10K_DEBUGFS
355 struct ath10k_debug debug;
356#endif
357};
358
359struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
Kalle Valo5e3dd152013-06-12 20:52:10 +0300360 const struct ath10k_hif_ops *hif_ops);
361void ath10k_core_destroy(struct ath10k *ar);
362
Michal Kaziordd30a362013-07-16 09:38:51 +0200363int ath10k_core_start(struct ath10k *ar);
364void ath10k_core_stop(struct ath10k *ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300365int ath10k_core_register(struct ath10k *ar);
366void ath10k_core_unregister(struct ath10k *ar);
367
368int ath10k_core_target_suspend(struct ath10k *ar);
369int ath10k_core_target_resume(struct ath10k *ar);
370
371#endif /* _CORE_H_ */