Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Terje Bergstrom | 4231c6b | 2013-03-22 16:34:05 +0200 | [diff] [blame] | 10 | #ifndef HOST1X_DRM_H |
| 11 | #define HOST1X_DRM_H 1 |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 12 | |
Thierry Reding | e1e9064 | 2013-09-24 13:59:01 +0200 | [diff] [blame] | 13 | #include <uapi/drm/tegra_drm.h> |
| 14 | #include <linux/host1x.h> |
| 15 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 16 | #include <drm/drmP.h> |
| 17 | #include <drm/drm_crtc_helper.h> |
| 18 | #include <drm/drm_edid.h> |
| 19 | #include <drm/drm_fb_helper.h> |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | #include <drm/drm_fixed.h> |
| 21 | |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 22 | #include "gem.h" |
| 23 | |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 24 | struct reset_control; |
| 25 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 26 | struct tegra_fb { |
| 27 | struct drm_framebuffer base; |
| 28 | struct tegra_bo **planes; |
| 29 | unsigned int num_planes; |
| 30 | }; |
| 31 | |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 32 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 33 | struct tegra_fbdev { |
| 34 | struct drm_fb_helper base; |
| 35 | struct tegra_fb *fb; |
| 36 | }; |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 37 | #endif |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 38 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 39 | struct tegra_drm { |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 40 | struct drm_device *drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 41 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 42 | struct iommu_domain *domain; |
| 43 | struct drm_mm mm; |
| 44 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 45 | struct mutex clients_lock; |
| 46 | struct list_head clients; |
| 47 | |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 48 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 49 | struct tegra_fbdev *fbdev; |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 50 | #endif |
Thierry Reding | d1f3e1e | 2014-07-11 08:29:14 +0200 | [diff] [blame] | 51 | |
| 52 | unsigned int pitch_align; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 53 | }; |
| 54 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 55 | struct tegra_drm_client; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 56 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 57 | struct tegra_drm_context { |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 58 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 59 | struct host1x_channel *channel; |
| 60 | struct list_head list; |
| 61 | }; |
| 62 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 63 | struct tegra_drm_client_ops { |
| 64 | int (*open_channel)(struct tegra_drm_client *client, |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 65 | struct tegra_drm_context *context); |
| 66 | void (*close_channel)(struct tegra_drm_context *context); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 67 | int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 68 | int (*submit)(struct tegra_drm_context *context, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 69 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 70 | struct drm_file *file); |
| 71 | }; |
| 72 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 73 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 74 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 75 | struct drm_file *file); |
| 76 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 77 | struct tegra_drm_client { |
| 78 | struct host1x_client base; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 79 | struct list_head list; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 80 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 81 | const struct tegra_drm_client_ops *ops; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 82 | }; |
| 83 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 84 | static inline struct tegra_drm_client * |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 85 | host1x_to_drm_client(struct host1x_client *client) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 86 | { |
| 87 | return container_of(client, struct tegra_drm_client, base); |
| 88 | } |
| 89 | |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 90 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 91 | struct tegra_drm_client *client); |
| 92 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 93 | struct tegra_drm_client *client); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 94 | |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 95 | int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
| 96 | int tegra_drm_exit(struct tegra_drm *tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 97 | |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 98 | struct tegra_dc_soc_info; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 99 | struct tegra_output; |
| 100 | |
| 101 | struct tegra_dc { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 102 | struct host1x_client client; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 103 | struct device *dev; |
Thierry Reding | d18d303 | 2013-09-26 16:09:19 +0200 | [diff] [blame] | 104 | spinlock_t lock; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 105 | |
| 106 | struct drm_crtc base; |
Thierry Reding | 9c01270 | 2014-07-07 15:32:53 +0200 | [diff] [blame] | 107 | int powergate; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 108 | int pipe; |
| 109 | |
| 110 | struct clk *clk; |
Stephen Warren | ca48080 | 2013-11-06 16:20:54 -0700 | [diff] [blame] | 111 | struct reset_control *rst; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 112 | void __iomem *regs; |
| 113 | int irq; |
| 114 | |
| 115 | struct tegra_output *rgb; |
| 116 | |
| 117 | struct list_head list; |
| 118 | |
| 119 | struct drm_info_list *debugfs_files; |
| 120 | struct drm_minor *minor; |
| 121 | struct dentry *debugfs; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 122 | |
| 123 | /* page-flip handling */ |
| 124 | struct drm_pending_vblank_event *event; |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 125 | |
| 126 | const struct tegra_dc_soc_info *soc; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 127 | |
| 128 | struct iommu_domain *domain; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 129 | }; |
| 130 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 131 | static inline struct tegra_dc * |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 132 | host1x_client_to_dc(struct host1x_client *client) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 133 | { |
| 134 | return container_of(client, struct tegra_dc, client); |
| 135 | } |
| 136 | |
| 137 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) |
| 138 | { |
Thierry Reding | 3782651 | 2013-11-08 12:30:37 +0100 | [diff] [blame] | 139 | return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 140 | } |
| 141 | |
Thierry Reding | 03a6056 | 2014-10-21 13:48:48 +0200 | [diff] [blame] | 142 | static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, |
| 143 | unsigned long offset) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 144 | { |
Thierry Reding | 03a6056 | 2014-10-21 13:48:48 +0200 | [diff] [blame] | 145 | writel(value, dc->regs + (offset << 2)); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Thierry Reding | 03a6056 | 2014-10-21 13:48:48 +0200 | [diff] [blame] | 148 | static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 149 | { |
Thierry Reding | 03a6056 | 2014-10-21 13:48:48 +0200 | [diff] [blame] | 150 | return readl(dc->regs + (offset << 2)); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 151 | } |
| 152 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 153 | struct tegra_dc_window { |
| 154 | struct { |
| 155 | unsigned int x; |
| 156 | unsigned int y; |
| 157 | unsigned int w; |
| 158 | unsigned int h; |
| 159 | } src; |
| 160 | struct { |
| 161 | unsigned int x; |
| 162 | unsigned int y; |
| 163 | unsigned int w; |
| 164 | unsigned int h; |
| 165 | } dst; |
| 166 | unsigned int bits_per_pixel; |
| 167 | unsigned int format; |
Thierry Reding | f925390 | 2014-01-29 20:31:17 +0100 | [diff] [blame] | 168 | unsigned int swap; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 169 | unsigned int stride[2]; |
| 170 | unsigned long base[3]; |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 171 | bool bottom_up; |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 172 | |
| 173 | struct tegra_bo_tiling tiling; |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 174 | }; |
| 175 | |
| 176 | /* from dc.c */ |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 177 | void tegra_dc_enable_vblank(struct tegra_dc *dc); |
| 178 | void tegra_dc_disable_vblank(struct tegra_dc *dc); |
| 179 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); |
Thierry Reding | 62b9e06 | 2014-11-21 17:33:33 +0100 | [diff] [blame] | 180 | void tegra_dc_commit(struct tegra_dc *dc); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 181 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 182 | struct tegra_output_ops { |
| 183 | int (*enable)(struct tegra_output *output); |
| 184 | int (*disable)(struct tegra_output *output); |
| 185 | int (*setup_clock)(struct tegra_output *output, struct clk *clk, |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 186 | unsigned long pclk, unsigned int *div); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 187 | int (*check_mode)(struct tegra_output *output, |
| 188 | struct drm_display_mode *mode, |
| 189 | enum drm_mode_status *status); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 190 | enum drm_connector_status (*detect)(struct tegra_output *output); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | enum tegra_output_type { |
| 194 | TEGRA_OUTPUT_RGB, |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 195 | TEGRA_OUTPUT_HDMI, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 196 | TEGRA_OUTPUT_DSI, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 197 | TEGRA_OUTPUT_EDP, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 198 | }; |
| 199 | |
| 200 | struct tegra_output { |
| 201 | struct device_node *of_node; |
| 202 | struct device *dev; |
| 203 | |
| 204 | const struct tegra_output_ops *ops; |
| 205 | enum tegra_output_type type; |
| 206 | |
Thierry Reding | 9be7d86 | 2013-08-30 15:22:36 +0200 | [diff] [blame] | 207 | struct drm_panel *panel; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 208 | struct i2c_adapter *ddc; |
| 209 | const struct edid *edid; |
| 210 | unsigned int hpd_irq; |
| 211 | int hpd_gpio; |
| 212 | |
| 213 | struct drm_encoder encoder; |
| 214 | struct drm_connector connector; |
| 215 | }; |
| 216 | |
| 217 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) |
| 218 | { |
| 219 | return container_of(e, struct tegra_output, encoder); |
| 220 | } |
| 221 | |
| 222 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) |
| 223 | { |
| 224 | return container_of(c, struct tegra_output, connector); |
| 225 | } |
| 226 | |
| 227 | static inline int tegra_output_enable(struct tegra_output *output) |
| 228 | { |
| 229 | if (output && output->ops && output->ops->enable) |
| 230 | return output->ops->enable(output); |
| 231 | |
| 232 | return output ? -ENOSYS : -EINVAL; |
| 233 | } |
| 234 | |
| 235 | static inline int tegra_output_disable(struct tegra_output *output) |
| 236 | { |
| 237 | if (output && output->ops && output->ops->disable) |
| 238 | return output->ops->disable(output); |
| 239 | |
| 240 | return output ? -ENOSYS : -EINVAL; |
| 241 | } |
| 242 | |
| 243 | static inline int tegra_output_setup_clock(struct tegra_output *output, |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 244 | struct clk *clk, unsigned long pclk, |
| 245 | unsigned int *div) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 246 | { |
| 247 | if (output && output->ops && output->ops->setup_clock) |
Thierry Reding | 91eded9 | 2014-03-26 13:32:21 +0100 | [diff] [blame] | 248 | return output->ops->setup_clock(output, clk, pclk, div); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 249 | |
| 250 | return output ? -ENOSYS : -EINVAL; |
| 251 | } |
| 252 | |
| 253 | static inline int tegra_output_check_mode(struct tegra_output *output, |
| 254 | struct drm_display_mode *mode, |
| 255 | enum drm_mode_status *status) |
| 256 | { |
| 257 | if (output && output->ops && output->ops->check_mode) |
| 258 | return output->ops->check_mode(output, mode, status); |
| 259 | |
| 260 | return output ? -ENOSYS : -EINVAL; |
| 261 | } |
| 262 | |
| 263 | /* from rgb.c */ |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 264 | int tegra_dc_rgb_probe(struct tegra_dc *dc); |
| 265 | int tegra_dc_rgb_remove(struct tegra_dc *dc); |
| 266 | int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); |
| 267 | int tegra_dc_rgb_exit(struct tegra_dc *dc); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 268 | |
| 269 | /* from output.c */ |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 270 | int tegra_output_probe(struct tegra_output *output); |
| 271 | int tegra_output_remove(struct tegra_output *output); |
| 272 | int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
| 273 | int tegra_output_exit(struct tegra_output *output); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 274 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 275 | /* from dpaux.c */ |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 276 | struct tegra_dpaux; |
| 277 | struct drm_dp_link; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 278 | |
| 279 | struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np); |
| 280 | enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux); |
| 281 | int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output); |
| 282 | int tegra_dpaux_detach(struct tegra_dpaux *dpaux); |
| 283 | int tegra_dpaux_enable(struct tegra_dpaux *dpaux); |
| 284 | int tegra_dpaux_disable(struct tegra_dpaux *dpaux); |
| 285 | int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding); |
| 286 | int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, |
| 287 | u8 pattern); |
| 288 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 289 | /* from fb.c */ |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 290 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
| 291 | unsigned int index); |
Thierry Reding | db7fbdf | 2013-10-07 09:47:58 +0200 | [diff] [blame] | 292 | bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); |
Thierry Reding | c134f01 | 2014-06-03 14:48:12 +0200 | [diff] [blame] | 293 | int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, |
| 294 | struct tegra_bo_tiling *tiling); |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame^] | 295 | struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, |
| 296 | struct drm_file *file, |
| 297 | struct drm_mode_fb_cmd2 *cmd); |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 298 | int tegra_drm_fb_prepare(struct drm_device *drm); |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 299 | void tegra_drm_fb_free(struct drm_device *drm); |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 300 | int tegra_drm_fb_init(struct drm_device *drm); |
| 301 | void tegra_drm_fb_exit(struct drm_device *drm); |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 302 | #ifdef CONFIG_DRM_TEGRA_FBDEV |
Thierry Reding | 688c59a | 2014-04-16 09:54:21 +0200 | [diff] [blame] | 303 | void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame^] | 304 | void tegra_fb_output_poll_changed(struct drm_device *drm); |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 305 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 306 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 307 | extern struct platform_driver tegra_dc_driver; |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 308 | extern struct platform_driver tegra_dsi_driver; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 309 | extern struct platform_driver tegra_sor_driver; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 310 | extern struct platform_driver tegra_hdmi_driver; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 311 | extern struct platform_driver tegra_dpaux_driver; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 312 | extern struct platform_driver tegra_gr2d_driver; |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 313 | extern struct platform_driver tegra_gr3d_driver; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 314 | |
Terje Bergstrom | 4231c6b | 2013-03-22 16:34:05 +0200 | [diff] [blame] | 315 | #endif /* HOST1X_DRM_H */ |