blob: a806ee7d7d07d7d2d9385514a63c9d6dd3c8aa07 [file] [log] [blame]
MyungJoo Hama3c98b82011-10-02 00:19:15 +02001menuconfig PM_DEVFREQ
2 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
Pranith Kumar83fe27e2014-12-05 11:24:45 -05003 select SRCU
MyungJoo Hama3c98b82011-10-02 00:19:15 +02004 help
MyungJoo Ham6c81f902011-11-14 23:31:35 +01005 A device may have a list of frequencies and voltages available.
6 devfreq, a generic DVFS framework can be registered for a device
7 in order to let the governor provided to devfreq choose an
8 operating frequency based on the device driver's policy.
MyungJoo Hama3c98b82011-10-02 00:19:15 +02009
MyungJoo Ham6c81f902011-11-14 23:31:35 +010010 Each device may have its own governor and policy. Devfreq can
MyungJoo Hama3c98b82011-10-02 00:19:15 +020011 reevaluate the device state periodically and/or based on the
MyungJoo Ham6c81f902011-11-14 23:31:35 +010012 notification to "nb", a notifier block, of devfreq.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020013
MyungJoo Ham6c81f902011-11-14 23:31:35 +010014 Like some CPUs with CPUfreq, a device may have multiple clocks.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020015 However, because the clock frequencies of a single device are
MyungJoo Ham6c81f902011-11-14 23:31:35 +010016 determined by the single device's state, an instance of devfreq
MyungJoo Hama3c98b82011-10-02 00:19:15 +020017 is attached to a single device and returns a "representative"
MyungJoo Ham6c81f902011-11-14 23:31:35 +010018 clock frequency of the device, which is also attached
19 to a device by 1-to-1. The device registering devfreq takes the
Masanari Iida6b2aac42012-04-14 00:14:11 +090020 responsibility to "interpret" the representative frequency and
MyungJoo Hama3c98b82011-10-02 00:19:15 +020021 to set its every clock accordingly with the "target" callback
MyungJoo Ham6c81f902011-11-14 23:31:35 +010022 given to devfreq.
23
24 When OPP is used with the devfreq device, it is recommended to
25 register devfreq's nb to the OPP's notifier head. If OPP is
26 used with the devfreq device, you may use OPP helper
27 functions defined in devfreq.h.
MyungJoo Hama3c98b82011-10-02 00:19:15 +020028
29if PM_DEVFREQ
30
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020031comment "DEVFREQ Governors"
32
33config DEVFREQ_GOV_SIMPLE_ONDEMAND
Nishanth Menoneff607f2012-10-29 15:01:46 -050034 tristate "Simple Ondemand"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020035 help
36 Chooses frequency based on the recent load on the device. Works
37 similar as ONDEMAND governor of CPUFREQ does. A device with
38 Simple-Ondemand should be able to provide busy/total counter
39 values that imply the usage rate. A device may provide tuned
40 values to the governor with data field at devfreq_add_device().
41
42config DEVFREQ_GOV_PERFORMANCE
Nishanth Menoneff607f2012-10-29 15:01:46 -050043 tristate "Performance"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020044 help
45 Sets the frequency at the maximum available frequency.
46 This governor always returns UINT_MAX as frequency so that
47 the DEVFREQ framework returns the highest frequency available
48 at any time.
49
50config DEVFREQ_GOV_POWERSAVE
Nishanth Menoneff607f2012-10-29 15:01:46 -050051 tristate "Powersave"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020052 help
53 Sets the frequency at the minimum available frequency.
54 This governor always returns 0 as frequency so that
55 the DEVFREQ framework returns the lowest frequency available
56 at any time.
57
58config DEVFREQ_GOV_USERSPACE
Nishanth Menoneff607f2012-10-29 15:01:46 -050059 tristate "Userspace"
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020060 help
61 Sets the frequency at the user specified one.
62 This governor returns the user configured frequency if there
63 has been an input to /sys/devices/.../power/devfreq_set_freq.
Geert Uytterhoeven027b6932016-03-14 16:29:02 +010064 Otherwise, the governor does not change the frequency
MyungJoo Hamce26c5b2011-10-02 00:19:34 +020065 given at the initialization.
66
Chanwoo Choi99613312016-03-22 13:44:03 +090067config DEVFREQ_GOV_PASSIVE
68 tristate "Passive"
69 help
70 Sets the frequency based on the frequency of its parent devfreq
71 device. This governor does not change the frequency by itself
72 through sysfs entries. The passive governor recommends that
73 devfreq device uses the OPP table to get the frequency/voltage.
74
Saravana Kannandbf2cae2014-04-11 18:48:38 -070075config DEVFREQ_GOV_CPUFREQ
76 tristate "CPUfreq"
77 depends on CPU_FREQ
78 help
79 Chooses frequency based on the online CPUs' current frequency and a
80 CPU frequency to device frequency mapping table(s). This governor
81 can be useful for controlling devices such as DDR, cache, CCI, etc.
82
Saravana Kannaned84c522014-05-28 18:59:54 -070083config QCOM_BIMC_BWMON
84 tristate "QCOM BIMC Bandwidth monitor hardware"
85 depends on ARCH_QCOM
86 help
87 The BIMC Bandwidth monitor hardware allows for monitoring the
88 traffic coming from each master port connected to the BIMC. It also
89 has the capability to raise an IRQ when the count exceeds a
90 programmable limit.
91
Rohit Gupta5e4358c2014-07-18 16:16:02 -070092config ARM_MEMLAT_MON
93 tristate "ARM CPU Memory Latency monitor hardware"
94 depends on ARCH_QCOM
95 help
96 The PMU present on these ARM cores allow for the use of counters to
97 monitor the memory latency characteristics of an ARM CPU workload.
98 This driver uses these counters to implement the APIs needed by
99 the mem_latency devfreq governor.
100
Junjie Wu198779b2014-10-31 16:18:02 -0700101config QCOMCCI_HWMON
Stephen Boydf5dc0082017-04-03 16:46:24 -0700102 tristate "QTI CCI Cache monitor hardware"
Junjie Wu198779b2014-10-31 16:18:02 -0700103 depends on ARCH_QCOM
104 help
Stephen Boydf5dc0082017-04-03 16:46:24 -0700105 QTI CCI has additional PMU counters that can be used to monitor
106 cache requests. QTI CCI hardware monitor device configures these
Junjie Wu198779b2014-10-31 16:18:02 -0700107 registers to monitor cache and inform governor. It can also set an
108 IRQ when count exceeds a programmable limit.
109
Junjie Wu85817c22015-07-23 14:20:14 -0700110config QCOM_M4M_HWMON
111 tristate "QCOM M4M cache monitor hardware"
112 depends on ARCH_QCOM
113 help
114 QCOM M4M has counters that can be used to monitor requests coming to
115 M4M. QCOM M4M hardware monitor device programs corresponding registers
116 to monitor cache and inform governor. It can also set an IRQ when
117 count exceeds a programmable limit.
118
Saravana Kannanedad3012013-09-23 19:27:57 -0700119config DEVFREQ_GOV_QCOM_BW_HWMON
120 tristate "HW monitor based governor for device BW"
121 depends on QCOM_BIMC_BWMON
122 help
123 HW monitor based governor for device to DDR bandwidth voting.
124 This governor sets the CPU BW vote by using BIMC counters to monitor
125 the CPU's use of DDR. Since this uses target specific counters it
126 can conflict with existing profiling tools. This governor is unlikely
127 to be useful for non-QCOM devices.
128
Saravana Kannancedb32e2014-01-22 00:15:33 -0800129config DEVFREQ_GOV_QCOM_CACHE_HWMON
130 tristate "HW monitor based governor for cache frequency"
131 help
132 HW monitor based governor for cache frequency scaling. This
133 governor sets the cache frequency by using PM counters to monitor the
134 CPU's use of cache. Since this governor uses some of the PM counters
135 it can conflict with existing profiling tools. This governor is
136 unlikely to be useful for other devices.
137
Odelu Kukatla73820752017-10-30 13:27:16 +0530138config DEVFREQ_GOV_SPDM_HYP
139 bool "QTI SPDM Hypervisor Governor"
140 depends on ARCH_QCOM
141 help
142 Hypervisor based governor for CPU bandwidth voting
143 for QTI chipsets.
144 Sets the frequency using a "on-demand" algorithm.
145 This governor is unlikely to be useful for other devices.
146
Rohit Gupta5e4358c2014-07-18 16:16:02 -0700147config DEVFREQ_GOV_MEMLAT
148 tristate "HW monitor based governor for device BW"
149 depends on ARM_MEMLAT_MON
150 help
151 HW monitor based governor for device to DDR bandwidth voting.
152 This governor sets the CPU BW vote based on stats obtained from memalat
153 monitor if it determines that a workload is memory latency bound. Since
154 this uses target specific counters it can conflict with existing profiling
155 tools.
156
MyungJoo Hama3c98b82011-10-02 00:19:15 +0200157comment "DEVFREQ Drivers"
158
Oleg Pereletb906a192017-01-04 09:50:02 -0800159config DEVFREQ_GOV_QCOM_ADRENO_TZ
160 tristate "Qualcomm Technologies Inc Adreno Trustzone"
161 depends on QCOM_KGSL && QCOM_SCM
162 help
163 Trustzone based governor for the Adreno GPU. Sets
164 the frequency using a "on-demand" algorithm. This
165 governor is unlikely to be useful for other
166 devices.
167
Oleg Perelet5d612102017-04-05 11:03:38 -0700168config DEVFREQ_GOV_QCOM_GPUBW_MON
169 tristate "GPU BW voting governor"
170 depends on DEVFREQ_GOV_QCOM_ADRENO_TZ
171 help
172 This governor works together with Adreno Trustzone governor,
173 and select bus frequency votes using an "on-demand" alorithm.
174 This governor is unlikely to be useful for non-Adreno
175 devices.
176
Chanwoo Choi07222492015-11-03 19:04:16 +0900177config ARM_EXYNOS_BUS_DEVFREQ
Paul Gortmaker5b3c3162016-06-26 03:43:49 +0900178 tristate "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
Krzysztof Kozlowski797da552016-08-19 08:36:55 +0200179 depends on ARCH_EXYNOS || COMPILE_TEST
Chanwoo Choi07222492015-11-03 19:04:16 +0900180 select DEVFREQ_GOV_SIMPLE_ONDEMAND
Chanwoo Choi403e0682015-11-05 18:29:27 +0900181 select DEVFREQ_GOV_PASSIVE
Chanwoo Choi07222492015-11-03 19:04:16 +0900182 select DEVFREQ_EVENT_EXYNOS_PPMU
183 select PM_DEVFREQ_EVENT
184 select PM_OPP
185 help
186 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
187 Memory bus has one more group of memory bus (e.g, MIF and INT block).
188 Each memory bus group could contain many memoby bus block. It reads
189 PPMU counters of memory controllers by using DEVFREQ-event device
190 and adjusts the operating frequencies and voltages with OPP support.
191 This does not yet operate with optimal voltages.
192
Tomeu Vizoso6234f382014-11-24 13:28:17 +0100193config ARM_TEGRA_DEVFREQ
Jisheng Zhang989a0fc2016-08-25 20:06:14 +0800194 tristate "Tegra DEVFREQ Driver"
Stephen Rothwell290128a2016-09-14 14:22:25 +1000195 depends on ARCH_TEGRA_124_SOC
Jisheng Zhang989a0fc2016-08-25 20:06:14 +0800196 select DEVFREQ_GOV_SIMPLE_ONDEMAND
197 select PM_OPP
198 help
199 This adds the DEVFREQ driver for the Tegra family of SoCs.
200 It reads ACTMON counters of memory controllers and adjusts the
201 operating frequencies and voltages with OPP support.
Tomeu Vizoso6234f382014-11-24 13:28:17 +0100202
Lin Huang5a893e32016-09-05 13:06:10 +0800203config ARM_RK3399_DMC_DEVFREQ
204 tristate "ARM RK3399 DMC DEVFREQ Driver"
Chanwoo Choic673faa2019-12-12 11:20:30 +0900205 depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
206 (COMPILE_TEST && HAVE_ARM_SMCCC)
Lin Huang5a893e32016-09-05 13:06:10 +0800207 select DEVFREQ_EVENT_ROCKCHIP_DFI
208 select DEVFREQ_GOV_SIMPLE_ONDEMAND
Arnd Bergmann54dec692016-09-15 17:44:58 +0200209 select PM_DEVFREQ_EVENT
Lin Huang5a893e32016-09-05 13:06:10 +0800210 select PM_OPP
211 help
212 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
213 It sets the frequency for the memory controller and reads the usage counts
214 from hardware.
215
Saravana Kannand905e652014-01-21 18:49:37 -0800216config DEVFREQ_SIMPLE_DEV
217 tristate "Device driver for simple clock device with no status info"
218 select DEVFREQ_GOV_PERFORMANCE
219 select DEVFREQ_GOV_POWERSAVE
220 select DEVFREQ_GOV_USERSPACE
221 select DEVFREQ_GOV_CPUFREQ
222 help
223 Device driver for simple devices that control their frequency using
224 clock APIs and don't have any form of status reporting.
225
Saravana Kannan89445cf2013-11-22 16:46:16 -0800226config QCOM_DEVFREQ_DEVBW
Stephen Boydf5dc0082017-04-03 16:46:24 -0700227 bool "Qualcomm Technologies Inc. DEVFREQ device for device master <-> slave IB/AB BW voting"
Saravana Kannan89445cf2013-11-22 16:46:16 -0800228 depends on ARCH_QCOM
229 select DEVFREQ_GOV_PERFORMANCE
230 select DEVFREQ_GOV_POWERSAVE
231 select DEVFREQ_GOV_USERSPACE
232 select DEVFREQ_GOV_CPUFREQ
233 default n
234 help
235 Different devfreq governors use this devfreq device to make CPU to
236 DDR IB/AB bandwidth votes. This driver provides a SoC topology
237 agnostic interface to so that some of the devfreq governors can be
238 shared across SoCs.
239
Odelu Kukatla73820752017-10-30 13:27:16 +0530240config SPDM_SCM
241 bool "QTI SPDM SCM based call support"
242 depends on DEVFREQ_SPDM
243 help
244 SPDM driver support the dcvs algorithm logic being accessed via
245 scm or hvc calls. This adds the support for SPDM interaction to
246 tz via SCM based call. If not selected then Hypervior interaction
247 will be activated.
248
249config DEVFREQ_SPDM
250 bool "QTI SPDM based bandwidth voting"
251 depends on ARCH_QCOM
252 select DEVFREQ_GOV_SPDM_HYP
253 help
254 This adds the support for SPDM based bandwidth voting on QTI chipsets.
255 This driver allows any SPDM based client to vote for bandwidth.
256 Used with the QTI SPDM Hypervisor Governor.
257
Chanwoo Choif262f282015-01-26 13:16:27 +0900258source "drivers/devfreq/event/Kconfig"
259
MyungJoo Hama3c98b82011-10-02 00:19:15 +0200260endif # PM_DEVFREQ