Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Ring initialization rules: |
| 25 | * 1. Each segment is initialized to zero, except for link TRBs. |
| 26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or |
| 27 | * Consumer Cycle State (CCS), depending on ring function. |
| 28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. |
| 29 | * |
| 30 | * Ring behavior rules: |
| 31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at |
| 32 | * least one free TRB in the ring. This is useful if you want to turn that |
| 33 | * into a link TRB and expand the ring. |
| 34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a |
| 35 | * link TRB, then load the pointer with the address in the link TRB. If the |
| 36 | * link TRB had its toggle bit set, you may need to update the ring cycle |
| 37 | * state (see cycle bit rules). You may have to do this multiple times |
| 38 | * until you reach a non-link TRB. |
| 39 | * 3. A ring is full if enqueue++ (for the definition of increment above) |
| 40 | * equals the dequeue pointer. |
| 41 | * |
| 42 | * Cycle bit rules: |
| 43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit |
| 44 | * in a link TRB, it must toggle the ring cycle state. |
| 45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit |
| 46 | * in a link TRB, it must toggle the ring cycle state. |
| 47 | * |
| 48 | * Producer rules: |
| 49 | * 1. Check if ring is full before you enqueue. |
| 50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. |
| 51 | * Update enqueue pointer between each write (which may update the ring |
| 52 | * cycle state). |
| 53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command |
| 54 | * and endpoint rings. If HC is the producer for the event ring, |
| 55 | * and it generates an interrupt according to interrupt modulation rules. |
| 56 | * |
| 57 | * Consumer rules: |
| 58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, |
| 59 | * the TRB is owned by the consumer. |
| 60 | * 2. Update dequeue pointer (which may update the ring cycle state) and |
| 61 | * continue processing TRBs until you reach a TRB which is not owned by you. |
| 62 | * 3. Notify the producer. SW is the consumer for the event ring, and it |
| 63 | * updates event ring dequeue pointer. HC is the consumer for the command and |
| 64 | * endpoint rings; it generates events on the event ring for these. |
| 65 | */ |
| 66 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 67 | #include <linux/scatterlist.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 68 | #include <linux/slab.h> |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 69 | #include <linux/dma-mapping.h> |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 70 | #include "xhci.h" |
Xenia Ragiadakou | 3a7fa5b | 2013-07-31 07:35:27 +0300 | [diff] [blame] | 71 | #include "xhci-trace.h" |
Chunfeng Yun | 0cbd4b3 | 2015-11-24 13:09:55 +0200 | [diff] [blame] | 72 | #include "xhci-mtk.h" |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA |
| 76 | * address of the TRB. |
| 77 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 78 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 79 | union xhci_trb *trb) |
| 80 | { |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 81 | unsigned long segment_offset; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 82 | |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 83 | if (!seg || !trb || trb < seg->trbs) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 84 | return 0; |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 85 | /* offset in TRBs */ |
| 86 | segment_offset = trb - seg->trbs; |
Mathias Nyman | 7895086 | 2015-08-03 16:07:48 +0300 | [diff] [blame] | 87 | if (segment_offset >= TRBS_PER_SEGMENT) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 88 | return 0; |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 89 | return seg->dma + (segment_offset * sizeof(*trb)); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 92 | static bool trb_is_link(union xhci_trb *trb) |
| 93 | { |
| 94 | return TRB_TYPE_LINK_LE32(trb->link.control); |
| 95 | } |
| 96 | |
Mathias Nyman | bd5e67f | 2016-06-21 10:58:05 +0300 | [diff] [blame] | 97 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
| 98 | { |
| 99 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; |
| 100 | } |
| 101 | |
| 102 | static bool last_trb_on_ring(struct xhci_ring *ring, |
| 103 | struct xhci_segment *seg, union xhci_trb *trb) |
| 104 | { |
| 105 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); |
| 106 | } |
| 107 | |
Mathias Nyman | d0c77d8 | 2016-06-21 10:58:07 +0300 | [diff] [blame] | 108 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
| 109 | { |
| 110 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
| 111 | } |
| 112 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 113 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
| 114 | * TRB is in a new segment. This does not skip over link TRBs, and it does not |
| 115 | * effect the ring dequeue or enqueue pointers. |
| 116 | */ |
| 117 | static void next_trb(struct xhci_hcd *xhci, |
| 118 | struct xhci_ring *ring, |
| 119 | struct xhci_segment **seg, |
| 120 | union xhci_trb **trb) |
| 121 | { |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 122 | if (trb_is_link(*trb)) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 123 | *seg = (*seg)->next; |
| 124 | *trb = ((*seg)->trbs); |
| 125 | } else { |
John Youn | a1669b2 | 2010-08-09 13:56:11 -0700 | [diff] [blame] | 126 | (*trb)++; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 127 | } |
| 128 | } |
| 129 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 130 | /* |
| 131 | * See Cycle bit rules. SW is the consumer for the event ring only. |
| 132 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. |
| 133 | */ |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 134 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 135 | { |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 136 | ring->deq_updates++; |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 137 | |
Mathias Nyman | bd5e67f | 2016-06-21 10:58:05 +0300 | [diff] [blame] | 138 | /* event ring doesn't have link trbs, check for last trb */ |
| 139 | if (ring->type == TYPE_EVENT) { |
| 140 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { |
Sarah Sharp | 50d0206 | 2012-07-26 12:03:59 -0700 | [diff] [blame] | 141 | ring->dequeue++; |
Mathias Nyman | bd5e67f | 2016-06-21 10:58:05 +0300 | [diff] [blame] | 142 | return; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 143 | } |
Mathias Nyman | bd5e67f | 2016-06-21 10:58:05 +0300 | [diff] [blame] | 144 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
| 145 | ring->cycle_state ^= 1; |
| 146 | ring->deq_seg = ring->deq_seg->next; |
| 147 | ring->dequeue = ring->deq_seg->trbs; |
| 148 | return; |
| 149 | } |
| 150 | |
| 151 | /* All other rings have link trbs */ |
| 152 | if (!trb_is_link(ring->dequeue)) { |
| 153 | ring->dequeue++; |
| 154 | ring->num_trbs_free++; |
| 155 | } |
| 156 | while (trb_is_link(ring->dequeue)) { |
| 157 | ring->deq_seg = ring->deq_seg->next; |
| 158 | ring->dequeue = ring->deq_seg->trbs; |
| 159 | } |
| 160 | return; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* |
| 164 | * See Cycle bit rules. SW is the consumer for the event ring only. |
| 165 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. |
| 166 | * |
| 167 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the |
| 168 | * chain bit is set), then set the chain bit in all the following link TRBs. |
| 169 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs |
| 170 | * have their chain bit cleared (so that each Link TRB is a separate TD). |
| 171 | * |
| 172 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 173 | * set, but other sections talk about dealing with the chain bit set. This was |
| 174 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 |
| 175 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 176 | * |
| 177 | * @more_trbs_coming: Will you enqueue more TRBs before calling |
| 178 | * prepare_transfer()? |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 179 | */ |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 180 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 181 | bool more_trbs_coming) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 182 | { |
| 183 | u32 chain; |
| 184 | union xhci_trb *next; |
| 185 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 186 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 187 | /* If this is not event ring, there is one less usable TRB */ |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 188 | if (!trb_is_link(ring->enqueue)) |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 189 | ring->num_trbs_free--; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 190 | next = ++(ring->enqueue); |
| 191 | |
| 192 | ring->enq_updates++; |
Mathias Nyman | 2251198 | 2016-06-21 10:58:03 +0300 | [diff] [blame] | 193 | /* Update the dequeue pointer further if that was a link TRB */ |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 194 | while (trb_is_link(next)) { |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 195 | |
Mathias Nyman | 2251198 | 2016-06-21 10:58:03 +0300 | [diff] [blame] | 196 | /* |
| 197 | * If the caller doesn't plan on enqueueing more TDs before |
| 198 | * ringing the doorbell, then we don't want to give the link TRB |
| 199 | * to the hardware just yet. We'll give the link TRB back in |
| 200 | * prepare_ring() just before we enqueue the TD at the top of |
| 201 | * the ring. |
| 202 | */ |
| 203 | if (!chain && !more_trbs_coming) |
| 204 | break; |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 205 | |
Mathias Nyman | 2251198 | 2016-06-21 10:58:03 +0300 | [diff] [blame] | 206 | /* If we're not dealing with 0.95 hardware or isoc rings on |
| 207 | * AMD 0.96 host, carry over the chain bit of the previous TRB |
| 208 | * (which may mean the chain bit is cleared). |
| 209 | */ |
| 210 | if (!(ring->type == TYPE_ISOC && |
| 211 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && |
| 212 | !xhci_link_trb_quirk(xhci)) { |
| 213 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
| 214 | next->link.control |= cpu_to_le32(chain); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 215 | } |
Mathias Nyman | 2251198 | 2016-06-21 10:58:03 +0300 | [diff] [blame] | 216 | /* Give this link TRB to the hardware */ |
| 217 | wmb(); |
| 218 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
| 219 | |
| 220 | /* Toggle the cycle bit after the last ring segment. */ |
Mathias Nyman | d0c77d8 | 2016-06-21 10:58:07 +0300 | [diff] [blame] | 221 | if (link_trb_toggles_cycle(next)) |
Mathias Nyman | 2251198 | 2016-06-21 10:58:03 +0300 | [diff] [blame] | 222 | ring->cycle_state ^= 1; |
| 223 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 224 | ring->enq_seg = ring->enq_seg->next; |
| 225 | ring->enqueue = ring->enq_seg->trbs; |
| 226 | next = ring->enqueue; |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | /* |
Andiry Xu | 085deb1 | 2012-03-05 17:49:40 +0800 | [diff] [blame] | 231 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
| 232 | * enqueue pointer will not advance into dequeue segment. See rules above. |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 233 | */ |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 234 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 235 | unsigned int num_trbs) |
| 236 | { |
Andiry Xu | 085deb1 | 2012-03-05 17:49:40 +0800 | [diff] [blame] | 237 | int num_trbs_in_deq_seg; |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 238 | |
Andiry Xu | 085deb1 | 2012-03-05 17:49:40 +0800 | [diff] [blame] | 239 | if (ring->num_trbs_free < num_trbs) |
| 240 | return 0; |
| 241 | |
| 242 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { |
| 243 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; |
| 244 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) |
| 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | return 1; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 249 | } |
| 250 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 251 | /* Ring the host controller doorbell after placing a command on the ring */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 252 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 253 | { |
Elric Fu | c181bc5 | 2012-06-27 16:30:57 +0800 | [diff] [blame] | 254 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
| 255 | return; |
| 256 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 257 | xhci_dbg(xhci, "// Ding dong!\n"); |
Xenia Ragiadakou | 204b779 | 2013-11-15 05:34:07 +0200 | [diff] [blame] | 258 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 259 | /* Flush PCI posted writes */ |
Xenia Ragiadakou | b0ba972 | 2013-11-15 05:34:06 +0200 | [diff] [blame] | 260 | readl(&xhci->dba->doorbell[0]); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 261 | } |
| 262 | |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 263 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
| 264 | { |
| 265 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); |
| 266 | } |
| 267 | |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 268 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
| 269 | { |
| 270 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, |
| 271 | cmd_list); |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. |
| 276 | * If there are other commands waiting then restart the ring and kick the timer. |
| 277 | * This must be called with command ring stopped and xhci->lock held. |
| 278 | */ |
| 279 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, |
| 280 | struct xhci_command *cur_cmd) |
| 281 | { |
| 282 | struct xhci_command *i_cmd; |
| 283 | u32 cycle_state; |
| 284 | |
| 285 | /* Turn all aborted commands in list to no-ops, then restart */ |
| 286 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { |
| 287 | |
| 288 | if (i_cmd->status != COMP_CMD_ABORT) |
| 289 | continue; |
| 290 | |
| 291 | i_cmd->status = COMP_CMD_STOP; |
| 292 | |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 293 | xhci_dbg(xhci, "Turn aborted command %pK to no-op\n", |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 294 | i_cmd->command_trb); |
| 295 | /* get cycle state from the original cmd trb */ |
| 296 | cycle_state = le32_to_cpu( |
| 297 | i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; |
| 298 | /* modify the command trb to no-op command */ |
| 299 | i_cmd->command_trb->generic.field[0] = 0; |
| 300 | i_cmd->command_trb->generic.field[1] = 0; |
| 301 | i_cmd->command_trb->generic.field[2] = 0; |
| 302 | i_cmd->command_trb->generic.field[3] = cpu_to_le32( |
| 303 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); |
| 304 | |
| 305 | /* |
| 306 | * caller waiting for completion is called when command |
| 307 | * completion event is received for these no-op commands |
| 308 | */ |
| 309 | } |
| 310 | |
| 311 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
| 312 | |
| 313 | /* ring command ring doorbell to restart the command ring */ |
| 314 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && |
| 315 | !(xhci->xhc_state & XHCI_STATE_DYING)) { |
| 316 | xhci->current_cmd = cur_cmd; |
| 317 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
| 318 | xhci_ring_cmd_db(xhci); |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | /* Must be called with xhci->lock held, releases and aquires lock back */ |
| 323 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) |
Elric Fu | b92cc66 | 2012-06-27 16:31:12 +0800 | [diff] [blame] | 324 | { |
| 325 | u64 temp_64; |
| 326 | int ret; |
| 327 | |
| 328 | xhci_dbg(xhci, "Abort command ring\n"); |
| 329 | |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 330 | reinit_completion(&xhci->cmd_ring_stop_completion); |
Mathias Nyman | 3425aa0 | 2016-06-01 18:09:08 +0300 | [diff] [blame] | 331 | |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 332 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
Sarah Sharp | 477632d | 2014-01-29 14:02:00 -0800 | [diff] [blame] | 333 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
| 334 | &xhci->op_regs->cmd_ring); |
Elric Fu | b92cc66 | 2012-06-27 16:31:12 +0800 | [diff] [blame] | 335 | |
| 336 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should |
Hemant Kumar | 960be8d | 2018-03-12 12:38:06 -0700 | [diff] [blame] | 337 | * time the completion of all xHCI commands, including |
Elric Fu | b92cc66 | 2012-06-27 16:31:12 +0800 | [diff] [blame] | 338 | * the Command Abort operation. If software doesn't see |
Hemant Kumar | 960be8d | 2018-03-12 12:38:06 -0700 | [diff] [blame] | 339 | * CRR negated in a timely manner, then it should assume |
| 340 | * that the there are larger problems with the xHC and assert HCRST. |
Elric Fu | b92cc66 | 2012-06-27 16:31:12 +0800 | [diff] [blame] | 341 | */ |
Hemant Kumar | 8a73ebe | 2018-03-05 18:51:43 -0800 | [diff] [blame] | 342 | ret = xhci_handshake_check_state(xhci, &xhci->op_regs->cmd_ring, |
Hemant Kumar | 960be8d | 2018-03-12 12:38:06 -0700 | [diff] [blame] | 343 | CMD_RING_RUNNING, 0, 1000 * 1000); |
Elric Fu | b92cc66 | 2012-06-27 16:31:12 +0800 | [diff] [blame] | 344 | if (ret < 0) { |
Xin Long | a62bf71 | 2017-01-23 14:19:55 +0200 | [diff] [blame] | 345 | xhci_err(xhci, |
| 346 | "Stop command ring failed, maybe the host is dead\n"); |
| 347 | xhci->xhc_state |= XHCI_STATE_DYING; |
| 348 | xhci_halt(xhci); |
| 349 | return -ESHUTDOWN; |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 350 | } |
| 351 | /* |
| 352 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, |
| 353 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared |
| 354 | * but the completion event in never sent. Wait 2 secs (arbitrary |
| 355 | * number) to handle those cases after negation of CMD_RING_RUNNING. |
| 356 | */ |
| 357 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 358 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, |
| 359 | msecs_to_jiffies(2000)); |
| 360 | spin_lock_irqsave(&xhci->lock, flags); |
| 361 | if (!ret) { |
| 362 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); |
| 363 | xhci_cleanup_command_queue(xhci); |
| 364 | } else { |
| 365 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); |
Elric Fu | b92cc66 | 2012-06-27 16:31:12 +0800 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 371 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 372 | unsigned int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 373 | unsigned int ep_index, |
| 374 | unsigned int stream_id) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 375 | { |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 376 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 377 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 378 | unsigned int ep_state = ep->ep_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 379 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 380 | /* Don't ring the doorbell for this endpoint if there are pending |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 381 | * cancellations because we don't want to interrupt processing. |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 382 | * We don't want to restart any stream rings if there's a set dequeue |
| 383 | * pointer command pending because the device can choose to start any |
| 384 | * stream once the endpoint is on the HW schedule. |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 385 | */ |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 386 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
| 387 | (ep_state & EP_HALTED)) |
| 388 | return; |
Xenia Ragiadakou | 204b779 | 2013-11-15 05:34:07 +0200 | [diff] [blame] | 389 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 390 | /* The CPU has better things to do at this point than wait for a |
| 391 | * write-posting flush. It'll get there soon enough. |
| 392 | */ |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 393 | } |
| 394 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 395 | /* Ring the doorbell for any rings with pending URBs */ |
| 396 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, |
| 397 | unsigned int slot_id, |
| 398 | unsigned int ep_index) |
| 399 | { |
| 400 | unsigned int stream_id; |
| 401 | struct xhci_virt_ep *ep; |
| 402 | |
| 403 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 404 | |
| 405 | /* A ring has pending URBs if its TD list is not empty */ |
| 406 | if (!(ep->ep_state & EP_HAS_STREAMS)) { |
Oleksij Rempel | d66eaf9 | 2013-07-21 15:36:19 +0200 | [diff] [blame] | 407 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 408 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 409 | return; |
| 410 | } |
| 411 | |
| 412 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
| 413 | stream_id++) { |
| 414 | struct xhci_stream_info *stream_info = ep->stream_info; |
| 415 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 416 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
| 417 | stream_id); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 418 | } |
| 419 | } |
| 420 | |
Alexandr Ivanov | 75b040e | 2016-04-22 13:17:10 +0300 | [diff] [blame] | 421 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
| 422 | * If the endpoint supports streams, boundary check the URB's stream ID. |
| 423 | * If the endpoint doesn't support streams, return the singular endpoint ring. |
| 424 | */ |
| 425 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, |
Sarah Sharp | 021bff9 | 2010-07-29 22:12:20 -0700 | [diff] [blame] | 426 | unsigned int slot_id, unsigned int ep_index, |
| 427 | unsigned int stream_id) |
| 428 | { |
| 429 | struct xhci_virt_ep *ep; |
| 430 | |
| 431 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 432 | /* Common case: no streams */ |
| 433 | if (!(ep->ep_state & EP_HAS_STREAMS)) |
| 434 | return ep->ring; |
| 435 | |
| 436 | if (stream_id == 0) { |
| 437 | xhci_warn(xhci, |
| 438 | "WARN: Slot ID %u, ep index %u has streams, " |
| 439 | "but URB has no stream ID.\n", |
| 440 | slot_id, ep_index); |
| 441 | return NULL; |
| 442 | } |
| 443 | |
| 444 | if (stream_id < ep->stream_info->num_streams) |
| 445 | return ep->stream_info->stream_rings[stream_id]; |
| 446 | |
| 447 | xhci_warn(xhci, |
| 448 | "WARN: Slot ID %u, ep index %u has " |
| 449 | "stream IDs 1 to %u allocated, " |
| 450 | "but stream ID %u is requested.\n", |
| 451 | slot_id, ep_index, |
| 452 | ep->stream_info->num_streams - 1, |
| 453 | stream_id); |
| 454 | return NULL; |
| 455 | } |
| 456 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 457 | /* |
| 458 | * Move the xHC's endpoint ring dequeue pointer past cur_td. |
| 459 | * Record the new state of the xHC's endpoint ring dequeue segment, |
| 460 | * dequeue pointer, and new consumer cycle state in state. |
| 461 | * Update our internal representation of the ring's dequeue pointer. |
| 462 | * |
| 463 | * We do this in three jumps: |
| 464 | * - First we update our new ring state to be the same as when the xHC stopped. |
| 465 | * - Then we traverse the ring to find the segment that contains |
| 466 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass |
| 467 | * any link TRBs with the toggle cycle bit set. |
| 468 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit |
| 469 | * if we've moved it past a link TRB with the toggle cycle bit set. |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 470 | * |
| 471 | * Some of the uses of xhci_generic_trb are grotty, but if they're done |
| 472 | * with correct __le32 accesses they should work fine. Only users of this are |
| 473 | * in here. |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 474 | */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 475 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 476 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 477 | unsigned int stream_id, struct xhci_td *cur_td, |
| 478 | struct xhci_dequeue_state *state) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 479 | { |
| 480 | struct xhci_virt_device *dev = xhci->devs[slot_id]; |
Hans de Goede | c4bedb7 | 2013-10-04 00:29:47 +0200 | [diff] [blame] | 481 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 482 | struct xhci_ring *ep_ring; |
Mathias Nyman | 365038d | 2014-08-19 15:17:58 +0300 | [diff] [blame] | 483 | struct xhci_segment *new_seg; |
| 484 | union xhci_trb *new_deq; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 485 | dma_addr_t addr; |
Julius Werner | 1f81b6d | 2014-04-25 19:20:13 +0300 | [diff] [blame] | 486 | u64 hw_dequeue; |
Mathias Nyman | 365038d | 2014-08-19 15:17:58 +0300 | [diff] [blame] | 487 | bool cycle_found = false; |
| 488 | bool td_last_trb_found = false; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 489 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 490 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
| 491 | ep_index, stream_id); |
| 492 | if (!ep_ring) { |
| 493 | xhci_warn(xhci, "WARN can't find new dequeue state " |
| 494 | "for invalid stream ID %u.\n", |
| 495 | stream_id); |
| 496 | return; |
| 497 | } |
Paul Zimmerman | 68e41c5 | 2011-02-12 14:06:06 -0800 | [diff] [blame] | 498 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 499 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 500 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 501 | "Finding endpoint context"); |
Hans de Goede | c4bedb7 | 2013-10-04 00:29:47 +0200 | [diff] [blame] | 502 | /* 4.6.9 the css flag is written to the stream context for streams */ |
| 503 | if (ep->ep_state & EP_HAS_STREAMS) { |
| 504 | struct xhci_stream_ctx *ctx = |
| 505 | &ep->stream_info->stream_ctx_array[stream_id]; |
Julius Werner | 1f81b6d | 2014-04-25 19:20:13 +0300 | [diff] [blame] | 506 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
Hans de Goede | c4bedb7 | 2013-10-04 00:29:47 +0200 | [diff] [blame] | 507 | } else { |
| 508 | struct xhci_ep_ctx *ep_ctx |
| 509 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
Julius Werner | 1f81b6d | 2014-04-25 19:20:13 +0300 | [diff] [blame] | 510 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
Hans de Goede | c4bedb7 | 2013-10-04 00:29:47 +0200 | [diff] [blame] | 511 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 512 | |
Mathias Nyman | 365038d | 2014-08-19 15:17:58 +0300 | [diff] [blame] | 513 | new_seg = ep_ring->deq_seg; |
| 514 | new_deq = ep_ring->dequeue; |
| 515 | state->new_cycle_state = hw_dequeue & 0x1; |
| 516 | |
| 517 | /* |
| 518 | * We want to find the pointer, segment and cycle state of the new trb |
| 519 | * (the one after current TD's last_trb). We know the cycle state at |
| 520 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are |
| 521 | * found. |
| 522 | */ |
| 523 | do { |
| 524 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) |
| 525 | == (dma_addr_t)(hw_dequeue & ~0xf)) { |
| 526 | cycle_found = true; |
| 527 | if (td_last_trb_found) |
| 528 | break; |
| 529 | } |
| 530 | if (new_deq == cur_td->last_trb) |
| 531 | td_last_trb_found = true; |
| 532 | |
| 533 | if (cycle_found && |
| 534 | TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) && |
| 535 | new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE)) |
| 536 | state->new_cycle_state ^= 0x1; |
| 537 | |
| 538 | next_trb(xhci, ep_ring, &new_seg, &new_deq); |
| 539 | |
| 540 | /* Search wrapped around, bail out */ |
| 541 | if (new_deq == ep->ring->dequeue) { |
| 542 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); |
| 543 | state->new_deq_seg = NULL; |
| 544 | state->new_deq_ptr = NULL; |
Julius Werner | 1f81b6d | 2014-04-25 19:20:13 +0300 | [diff] [blame] | 545 | return; |
| 546 | } |
Julius Werner | 1f81b6d | 2014-04-25 19:20:13 +0300 | [diff] [blame] | 547 | |
Mathias Nyman | 365038d | 2014-08-19 15:17:58 +0300 | [diff] [blame] | 548 | } while (!cycle_found || !td_last_trb_found); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 549 | |
Mathias Nyman | 365038d | 2014-08-19 15:17:58 +0300 | [diff] [blame] | 550 | state->new_deq_seg = new_seg; |
| 551 | state->new_deq_ptr = new_deq; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 552 | |
Julius Werner | 1f81b6d | 2014-04-25 19:20:13 +0300 | [diff] [blame] | 553 | /* Don't update the ring cycle state for the producer (us). */ |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 554 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 555 | "Cycle state = 0x%x", state->new_cycle_state); |
Sarah Sharp | 01a1fdb | 2011-02-23 18:12:29 -0800 | [diff] [blame] | 556 | |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 557 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 558 | "New dequeue segment = %pK (virtual)", |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 559 | state->new_deq_seg); |
| 560 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 561 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 562 | "New dequeue pointer = 0x%llx (DMA)", |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 563 | (unsigned long long) addr); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 564 | } |
| 565 | |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 566 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
| 567 | * (The last TRB actually points to the ring enqueue pointer, which is not part |
| 568 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. |
| 569 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 570 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 571 | struct xhci_td *cur_td, bool flip_cycle) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 572 | { |
| 573 | struct xhci_segment *cur_seg; |
| 574 | union xhci_trb *cur_trb; |
| 575 | |
| 576 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; |
| 577 | true; |
| 578 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 579 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 580 | /* Unchain any chained Link TRBs, but |
| 581 | * leave the pointers intact. |
| 582 | */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 583 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 584 | /* Flip the cycle bit (link TRBs can't be the first |
| 585 | * or last TRB). |
| 586 | */ |
| 587 | if (flip_cycle) |
| 588 | cur_trb->generic.field[3] ^= |
| 589 | cpu_to_le32(TRB_CYCLE); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 590 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 591 | "Cancel (unchain) link TRB"); |
| 592 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 593 | "Address = %pK (0x%llx dma); " |
| 594 | "in seg %pK (0x%llx dma)", |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 595 | cur_trb, |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 596 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 597 | cur_seg, |
| 598 | (unsigned long long)cur_seg->dma); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 599 | } else { |
| 600 | cur_trb->generic.field[0] = 0; |
| 601 | cur_trb->generic.field[1] = 0; |
| 602 | cur_trb->generic.field[2] = 0; |
| 603 | /* Preserve only the cycle bit of this TRB */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 604 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 605 | /* Flip the cycle bit except on the first or last TRB */ |
| 606 | if (flip_cycle && cur_trb != cur_td->first_trb && |
| 607 | cur_trb != cur_td->last_trb) |
| 608 | cur_trb->generic.field[3] ^= |
| 609 | cpu_to_le32(TRB_CYCLE); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 610 | cur_trb->generic.field[3] |= cpu_to_le32( |
| 611 | TRB_TYPE(TRB_TR_NOOP)); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 612 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 613 | "TRB to noop at offset 0x%llx", |
Sarah Sharp | 79688ac | 2011-12-19 16:56:04 -0800 | [diff] [blame] | 614 | (unsigned long long) |
| 615 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 616 | } |
| 617 | if (cur_trb == cur_td->last_trb) |
| 618 | break; |
| 619 | } |
| 620 | } |
| 621 | |
Dmitry Torokhov | 575688e | 2011-03-20 02:15:16 -0700 | [diff] [blame] | 622 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 623 | struct xhci_virt_ep *ep) |
| 624 | { |
| 625 | ep->ep_state &= ~EP_HALT_PENDING; |
| 626 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the |
| 627 | * timer is running on another CPU, we don't decrement stop_cmds_pending |
| 628 | * (since we didn't successfully stop the watchdog timer). |
| 629 | */ |
| 630 | if (del_timer(&ep->stop_cmd_timer)) |
| 631 | ep->stop_cmds_pending--; |
| 632 | } |
| 633 | |
| 634 | /* Must be called with xhci->lock held in interrupt context */ |
| 635 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
Xenia Ragiadakou | 07a37e9 | 2013-09-09 13:29:45 +0300 | [diff] [blame] | 636 | struct xhci_td *cur_td, int status) |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 637 | { |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 638 | struct usb_hcd *hcd; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 639 | struct urb *urb; |
| 640 | struct urb_priv *urb_priv; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 641 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 642 | urb = cur_td->urb; |
| 643 | urb_priv = urb->hcpriv; |
| 644 | urb_priv->td_cnt++; |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 645 | hcd = bus_to_hcd(urb->dev->bus); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 646 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 647 | /* Only giveback urb when this is the last td in urb */ |
| 648 | if (urb_priv->td_cnt == urb_priv->length) { |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 649 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
| 650 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; |
| 651 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
| 652 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
| 653 | usb_amd_quirk_pll_enable(); |
| 654 | } |
| 655 | } |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 656 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 657 | |
| 658 | spin_unlock(&xhci->lock); |
| 659 | usb_hcd_giveback_urb(hcd, urb, status); |
Lin Wang | 4daf9df | 2015-01-09 16:06:31 +0200 | [diff] [blame] | 660 | xhci_urb_free_priv(urb_priv); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 661 | spin_lock(&xhci->lock); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 662 | } |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 663 | } |
| 664 | |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 665 | void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring, |
| 666 | struct xhci_td *td) |
| 667 | { |
Jack Pham | f556be0 | 2017-04-04 16:12:31 -0700 | [diff] [blame] | 668 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 669 | struct xhci_segment *seg = td->bounce_seg; |
| 670 | struct urb *urb = td->urb; |
| 671 | |
| 672 | if (!seg || !urb) |
| 673 | return; |
| 674 | |
| 675 | if (usb_urb_dir_out(urb)) { |
| 676 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, |
| 677 | DMA_TO_DEVICE); |
| 678 | return; |
| 679 | } |
| 680 | |
| 681 | /* for in tranfers we need to copy the data from bounce to sg */ |
| 682 | sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, |
| 683 | seg->bounce_len, seg->bounce_offs); |
| 684 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, |
| 685 | DMA_FROM_DEVICE); |
| 686 | seg->bounce_len = 0; |
| 687 | seg->bounce_offs = 0; |
| 688 | } |
| 689 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 690 | /* |
| 691 | * When we get a command completion for a Stop Endpoint Command, we need to |
| 692 | * unlink any cancelled TDs from the ring. There are two ways to do that: |
| 693 | * |
| 694 | * 1. If the HW was in the middle of processing the TD that needs to be |
| 695 | * cancelled, then we must move the ring's dequeue pointer past the last TRB |
| 696 | * in the TD with a Set Dequeue Pointer Command. |
| 697 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain |
| 698 | * bit cleared) so that the HW will skip over them. |
| 699 | */ |
Xenia Ragiadakou | b8200c9 | 2013-09-09 13:30:00 +0300 | [diff] [blame] | 700 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 701 | union xhci_trb *trb, struct xhci_event_cmd *event) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 702 | { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 703 | unsigned int ep_index; |
| 704 | struct xhci_ring *ep_ring; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 705 | struct xhci_virt_ep *ep; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 706 | struct list_head *entry; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 707 | struct xhci_td *cur_td = NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 708 | struct xhci_td *last_unlinked_td; |
| 709 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 710 | struct xhci_dequeue_state deq_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 711 | |
Xenia Ragiadakou | bc752bd | 2013-09-09 13:29:59 +0300 | [diff] [blame] | 712 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 713 | if (!xhci->devs[slot_id]) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 714 | xhci_warn(xhci, "Stop endpoint command " |
| 715 | "completion for disabled slot %u\n", |
| 716 | slot_id); |
| 717 | return; |
| 718 | } |
| 719 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 720 | memset(&deq_state, 0, sizeof(deq_state)); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 721 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 722 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 723 | |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 724 | if (list_empty(&ep->cancelled_td_list)) { |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 725 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
Sarah Sharp | 0714a57 | 2011-05-24 11:53:29 -0700 | [diff] [blame] | 726 | ep->stopped_td = NULL; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 727 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 728 | return; |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 729 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 730 | |
| 731 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. |
| 732 | * We have the xHCI lock, so nothing can modify this list until we drop |
| 733 | * it. We're also in the event handler, so we can't get re-interrupted |
| 734 | * if another Stop Endpoint command completes |
| 735 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 736 | list_for_each(entry, &ep->cancelled_td_list) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 737 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 738 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 739 | "Removing canceled TD starting at 0x%llx (dma).", |
Sarah Sharp | 79688ac | 2011-12-19 16:56:04 -0800 | [diff] [blame] | 740 | (unsigned long long)xhci_trb_virt_to_dma( |
| 741 | cur_td->start_seg, cur_td->first_trb)); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 742 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
| 743 | if (!ep_ring) { |
| 744 | /* This shouldn't happen unless a driver is mucking |
| 745 | * with the stream ID after submission. This will |
| 746 | * leave the TD on the hardware ring, and the hardware |
| 747 | * will try to execute it, and may access a buffer |
| 748 | * that has already been freed. In the best case, the |
| 749 | * hardware will execute it, and the event handler will |
| 750 | * ignore the completion event for that TD, since it was |
| 751 | * removed from the td_list for that endpoint. In |
| 752 | * short, don't muck with the stream ID after |
| 753 | * submission. |
| 754 | */ |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 755 | xhci_warn(xhci, "WARN Cancelled URB %pK " |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 756 | "has invalid stream ID %u.\n", |
| 757 | cur_td->urb, |
| 758 | cur_td->urb->stream_id); |
| 759 | goto remove_finished_td; |
| 760 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 761 | /* |
| 762 | * If we stopped on the TD we need to cancel, then we have to |
| 763 | * move the xHC endpoint ring dequeue pointer past this TD. |
| 764 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 765 | if (cur_td == ep->stopped_td) |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 766 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
| 767 | cur_td->urb->stream_id, |
| 768 | cur_td, &deq_state); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 769 | else |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 770 | td_to_noop(xhci, ep_ring, cur_td, false); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 771 | remove_finished_td: |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 772 | /* |
| 773 | * The event handler won't see a completion for this TD anymore, |
| 774 | * so remove it from the endpoint ring's TD list. Keep it in |
| 775 | * the cancelled TD list for URB completion later. |
| 776 | */ |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 777 | list_del_init(&cur_td->td_list); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 778 | } |
| 779 | last_unlinked_td = cur_td; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 780 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 781 | |
| 782 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ |
| 783 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 784 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
| 785 | ep->stopped_td->urb->stream_id, &deq_state); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 786 | xhci_ring_cmd_db(xhci); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 787 | } else { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 788 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
| 789 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 790 | } |
Florian Wolter | 526867c | 2013-08-14 10:33:16 +0200 | [diff] [blame] | 791 | |
Mathias Nyman | d97b4f8 | 2014-11-27 18:19:16 +0200 | [diff] [blame] | 792 | ep->stopped_td = NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 793 | |
| 794 | /* |
| 795 | * Drop the lock and complete the URBs in the cancelled TD list. |
| 796 | * New TDs to be cancelled might be added to the end of the list before |
| 797 | * we can complete all the URBs for the TDs we already unlinked. |
| 798 | * So stop when we've completed the URB for the last TD we unlinked. |
| 799 | */ |
| 800 | do { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 801 | cur_td = list_entry(ep->cancelled_td_list.next, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 802 | struct xhci_td, cancelled_td_list); |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 803 | list_del_init(&cur_td->cancelled_td_list); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 804 | |
| 805 | /* Clean up the cancelled URB */ |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 806 | /* Doesn't matter what we pass for status, since the core will |
| 807 | * just overwrite it (because the URB has been unlinked). |
| 808 | */ |
Arnd Bergmann | f76a28a | 2016-06-30 14:26:17 +0200 | [diff] [blame] | 809 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 810 | if (ep_ring && cur_td->bounce_seg) |
| 811 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); |
Xenia Ragiadakou | 07a37e9 | 2013-09-09 13:29:45 +0300 | [diff] [blame] | 812 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 813 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 814 | /* Stop processing the cancelled list if the watchdog timer is |
| 815 | * running. |
| 816 | */ |
| 817 | if (xhci->xhc_state & XHCI_STATE_DYING) |
| 818 | return; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 819 | } while (cur_td != last_unlinked_td); |
| 820 | |
| 821 | /* Return to the event handler with xhci->lock re-acquired */ |
| 822 | } |
| 823 | |
Sarah Sharp | 50e8725 | 2014-02-21 09:27:30 -0800 | [diff] [blame] | 824 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
| 825 | { |
| 826 | struct xhci_td *cur_td; |
| 827 | |
| 828 | while (!list_empty(&ring->td_list)) { |
| 829 | cur_td = list_first_entry(&ring->td_list, |
| 830 | struct xhci_td, td_list); |
| 831 | list_del_init(&cur_td->td_list); |
| 832 | if (!list_empty(&cur_td->cancelled_td_list)) |
| 833 | list_del_init(&cur_td->cancelled_td_list); |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 834 | |
| 835 | if (cur_td->bounce_seg) |
| 836 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
Sarah Sharp | 50e8725 | 2014-02-21 09:27:30 -0800 | [diff] [blame] | 837 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); |
| 838 | } |
| 839 | } |
| 840 | |
| 841 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, |
| 842 | int slot_id, int ep_index) |
| 843 | { |
| 844 | struct xhci_td *cur_td; |
| 845 | struct xhci_virt_ep *ep; |
| 846 | struct xhci_ring *ring; |
| 847 | |
| 848 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
Sarah Sharp | 21d0e51 | 2014-02-21 14:29:02 -0800 | [diff] [blame] | 849 | if ((ep->ep_state & EP_HAS_STREAMS) || |
| 850 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { |
| 851 | int stream_id; |
| 852 | |
Mathias Nyman | 01845a8 | 2017-07-20 14:48:26 +0300 | [diff] [blame] | 853 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
Sarah Sharp | 21d0e51 | 2014-02-21 14:29:02 -0800 | [diff] [blame] | 854 | stream_id++) { |
Mathias Nyman | 01845a8 | 2017-07-20 14:48:26 +0300 | [diff] [blame] | 855 | ring = ep->stream_info->stream_rings[stream_id]; |
| 856 | if (!ring) |
| 857 | continue; |
| 858 | |
Sarah Sharp | 21d0e51 | 2014-02-21 14:29:02 -0800 | [diff] [blame] | 859 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 860 | "Killing URBs for slot ID %u, ep index %u, stream %u", |
Mathias Nyman | 01845a8 | 2017-07-20 14:48:26 +0300 | [diff] [blame] | 861 | slot_id, ep_index, stream_id); |
| 862 | xhci_kill_ring_urbs(xhci, ring); |
Sarah Sharp | 21d0e51 | 2014-02-21 14:29:02 -0800 | [diff] [blame] | 863 | } |
| 864 | } else { |
| 865 | ring = ep->ring; |
| 866 | if (!ring) |
| 867 | return; |
| 868 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 869 | "Killing URBs for slot ID %u, ep index %u", |
| 870 | slot_id, ep_index); |
| 871 | xhci_kill_ring_urbs(xhci, ring); |
| 872 | } |
Sarah Sharp | 50e8725 | 2014-02-21 09:27:30 -0800 | [diff] [blame] | 873 | while (!list_empty(&ep->cancelled_td_list)) { |
| 874 | cur_td = list_first_entry(&ep->cancelled_td_list, |
| 875 | struct xhci_td, cancelled_td_list); |
| 876 | list_del_init(&cur_td->cancelled_td_list); |
| 877 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); |
| 878 | } |
| 879 | } |
| 880 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 881 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
| 882 | * In this case, we assume the host controller is broken or dying or dead. The |
| 883 | * host may still be completing some other events, so we have to be careful to |
| 884 | * let the event ring handler and the URB dequeueing/enqueueing functions know |
| 885 | * through xhci->state. |
| 886 | * |
| 887 | * The timer may also fire if the host takes a very long time to respond to the |
| 888 | * command, and the stop endpoint command completion handler cannot delete the |
| 889 | * timer before the timer function is called. Another endpoint cancellation may |
| 890 | * sneak in before the timer function can grab the lock, and that may queue |
| 891 | * another stop endpoint command and add the timer back. So we cannot use a |
| 892 | * simple flag to say whether there is a pending stop endpoint command for a |
| 893 | * particular endpoint. |
| 894 | * |
| 895 | * Instead we use a combination of that flag and a counter for the number of |
| 896 | * pending stop endpoint commands. If the timer is the tail end of the last |
| 897 | * stop endpoint command, and the endpoint's command is still pending, we assume |
| 898 | * the host is dying. |
| 899 | */ |
| 900 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) |
| 901 | { |
| 902 | struct xhci_hcd *xhci; |
| 903 | struct xhci_virt_ep *ep; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 904 | int ret, i, j; |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 905 | unsigned long flags; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 906 | |
| 907 | ep = (struct xhci_virt_ep *) arg; |
| 908 | xhci = ep->xhci; |
| 909 | |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 910 | spin_lock_irqsave(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 911 | |
| 912 | ep->stop_cmds_pending--; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 913 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 914 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 915 | "Stop EP timer ran, but no command pending, " |
| 916 | "exiting."); |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 917 | spin_unlock_irqrestore(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 918 | return; |
| 919 | } |
| 920 | |
| 921 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); |
| 922 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); |
| 923 | /* Oops, HC is dead or dying or at least not responding to the stop |
| 924 | * endpoint command. |
| 925 | */ |
| 926 | xhci->xhc_state |= XHCI_STATE_DYING; |
| 927 | /* Disable interrupts from the host controller and start halting it */ |
| 928 | xhci_quiesce(xhci); |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 929 | spin_unlock_irqrestore(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 930 | |
| 931 | ret = xhci_halt(xhci); |
| 932 | |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 933 | spin_lock_irqsave(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 934 | if (ret < 0) { |
| 935 | /* This is bad; the host is not responding to commands and it's |
| 936 | * not allowing itself to be halted. At least interrupts are |
Sarah Sharp | ac04e6f | 2011-03-11 08:47:33 -0800 | [diff] [blame] | 937 | * disabled. If we call usb_hc_died(), it will attempt to |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 938 | * disconnect all device drivers under this host. Those |
| 939 | * disconnect() methods will wait for all URBs to be unlinked, |
| 940 | * so we must complete them. |
| 941 | */ |
| 942 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); |
| 943 | xhci_warn(xhci, "Completing active URBs anyway.\n"); |
| 944 | /* We could turn all TDs on the rings to no-ops. This won't |
| 945 | * help if the host has cached part of the ring, and is slow if |
| 946 | * we want to preserve the cycle bit. Skip it and hope the host |
| 947 | * doesn't touch the memory. |
| 948 | */ |
| 949 | } |
| 950 | for (i = 0; i < MAX_HC_SLOTS; i++) { |
| 951 | if (!xhci->devs[i]) |
| 952 | continue; |
Sarah Sharp | 50e8725 | 2014-02-21 09:27:30 -0800 | [diff] [blame] | 953 | for (j = 0; j < 31; j++) |
| 954 | xhci_kill_endpoint_urbs(xhci, i, j); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 955 | } |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 956 | spin_unlock_irqrestore(&xhci->lock, flags); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 957 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 958 | "Calling usb_hc_died()"); |
Mathias Nyman | bcf42aa | 2016-09-07 17:26:33 +0300 | [diff] [blame] | 959 | usb_hc_died(xhci_to_hcd(xhci)); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 960 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 961 | "xHCI host controller is dead."); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 962 | } |
| 963 | |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 964 | |
| 965 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, |
| 966 | struct xhci_virt_device *dev, |
| 967 | struct xhci_ring *ep_ring, |
| 968 | unsigned int ep_index) |
| 969 | { |
| 970 | union xhci_trb *dequeue_temp; |
| 971 | int num_trbs_free_temp; |
| 972 | bool revert = false; |
| 973 | |
| 974 | num_trbs_free_temp = ep_ring->num_trbs_free; |
| 975 | dequeue_temp = ep_ring->dequeue; |
| 976 | |
Sarah Sharp | 0d9f78a | 2012-06-21 16:28:30 -0700 | [diff] [blame] | 977 | /* If we get two back-to-back stalls, and the first stalled transfer |
| 978 | * ends just before a link TRB, the dequeue pointer will be left on |
| 979 | * the link TRB by the code in the while loop. So we have to update |
| 980 | * the dequeue pointer one segment further, or we'll jump off |
| 981 | * the segment into la-la-land. |
| 982 | */ |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 983 | if (trb_is_link(ep_ring->dequeue)) { |
Sarah Sharp | 0d9f78a | 2012-06-21 16:28:30 -0700 | [diff] [blame] | 984 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
| 985 | ep_ring->dequeue = ep_ring->deq_seg->trbs; |
| 986 | } |
| 987 | |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 988 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
| 989 | /* We have more usable TRBs */ |
| 990 | ep_ring->num_trbs_free++; |
| 991 | ep_ring->dequeue++; |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 992 | if (trb_is_link(ep_ring->dequeue)) { |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 993 | if (ep_ring->dequeue == |
| 994 | dev->eps[ep_index].queued_deq_ptr) |
| 995 | break; |
| 996 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
| 997 | ep_ring->dequeue = ep_ring->deq_seg->trbs; |
| 998 | } |
| 999 | if (ep_ring->dequeue == dequeue_temp) { |
| 1000 | revert = true; |
| 1001 | break; |
| 1002 | } |
| 1003 | } |
| 1004 | |
| 1005 | if (revert) { |
| 1006 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); |
| 1007 | ep_ring->num_trbs_free = num_trbs_free_temp; |
| 1008 | } |
| 1009 | } |
| 1010 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1011 | /* |
| 1012 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, |
| 1013 | * we need to clear the set deq pending flag in the endpoint ring state, so that |
| 1014 | * the TD queueing code can ring the doorbell again. We also need to ring the |
| 1015 | * endpoint doorbell to restart the ring, but only if there aren't more |
| 1016 | * cancellations pending. |
| 1017 | */ |
Xenia Ragiadakou | b8200c9 | 2013-09-09 13:30:00 +0300 | [diff] [blame] | 1018 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1019 | union xhci_trb *trb, u32 cmd_comp_code) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1020 | { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1021 | unsigned int ep_index; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1022 | unsigned int stream_id; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1023 | struct xhci_ring *ep_ring; |
| 1024 | struct xhci_virt_device *dev; |
Hans de Goede | 9aad95e | 2013-10-04 00:29:49 +0200 | [diff] [blame] | 1025 | struct xhci_virt_ep *ep; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1026 | struct xhci_ep_ctx *ep_ctx; |
| 1027 | struct xhci_slot_ctx *slot_ctx; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1028 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1029 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
| 1030 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1031 | dev = xhci->devs[slot_id]; |
Hans de Goede | 9aad95e | 2013-10-04 00:29:49 +0200 | [diff] [blame] | 1032 | ep = &dev->eps[ep_index]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1033 | |
| 1034 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); |
| 1035 | if (!ep_ring) { |
Oliver Neukum | e587b8b | 2014-01-08 17:13:11 +0100 | [diff] [blame] | 1036 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1037 | stream_id); |
| 1038 | /* XXX: Harmless??? */ |
Hans de Goede | 0d4976e | 2014-08-20 16:41:55 +0300 | [diff] [blame] | 1039 | goto cleanup; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1040 | } |
| 1041 | |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1042 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
| 1043 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1044 | |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1045 | if (cmd_comp_code != COMP_SUCCESS) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1046 | unsigned int ep_state; |
| 1047 | unsigned int slot_state; |
| 1048 | |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1049 | switch (cmd_comp_code) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1050 | case COMP_TRB_ERR: |
Oliver Neukum | e587b8b | 2014-01-08 17:13:11 +0100 | [diff] [blame] | 1051 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1052 | break; |
| 1053 | case COMP_CTX_STATE: |
Oliver Neukum | e587b8b | 2014-01-08 17:13:11 +0100 | [diff] [blame] | 1054 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1055 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1056 | ep_state &= EP_STATE_MASK; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1057 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1058 | slot_state = GET_SLOT_STATE(slot_state); |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 1059 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
| 1060 | "Slot state = %u, EP state = %u", |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1061 | slot_state, ep_state); |
| 1062 | break; |
| 1063 | case COMP_EBADSLT: |
Oliver Neukum | e587b8b | 2014-01-08 17:13:11 +0100 | [diff] [blame] | 1064 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
| 1065 | slot_id); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1066 | break; |
| 1067 | default: |
Oliver Neukum | e587b8b | 2014-01-08 17:13:11 +0100 | [diff] [blame] | 1068 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
| 1069 | cmd_comp_code); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1070 | break; |
| 1071 | } |
| 1072 | /* OK what do we do now? The endpoint state is hosed, and we |
| 1073 | * should never get to this point if the synchronization between |
| 1074 | * queueing, and endpoint state are correct. This might happen |
| 1075 | * if the device gets disconnected after we've finished |
| 1076 | * cancelling URBs, which might not be an error... |
| 1077 | */ |
| 1078 | } else { |
Hans de Goede | 9aad95e | 2013-10-04 00:29:49 +0200 | [diff] [blame] | 1079 | u64 deq; |
| 1080 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ |
| 1081 | if (ep->ep_state & EP_HAS_STREAMS) { |
| 1082 | struct xhci_stream_ctx *ctx = |
| 1083 | &ep->stream_info->stream_ctx_array[stream_id]; |
| 1084 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; |
| 1085 | } else { |
| 1086 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; |
| 1087 | } |
Xenia Ragiadakou | aa50b29 | 2013-08-14 06:33:54 +0300 | [diff] [blame] | 1088 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
Hans de Goede | 9aad95e | 2013-10-04 00:29:49 +0200 | [diff] [blame] | 1089 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
| 1090 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, |
| 1091 | ep->queued_deq_ptr) == deq) { |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 1092 | /* Update the ring's dequeue segment and dequeue pointer |
| 1093 | * to reflect the new position. |
| 1094 | */ |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 1095 | update_ring_for_set_deq_completion(xhci, dev, |
| 1096 | ep_ring, ep_index); |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 1097 | } else { |
Oliver Neukum | e587b8b | 2014-01-08 17:13:11 +0100 | [diff] [blame] | 1098 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 1099 | xhci_warn(xhci, "ep deq seg = %pK, deq ptr = %pK\n", |
Hans de Goede | 9aad95e | 2013-10-04 00:29:49 +0200 | [diff] [blame] | 1100 | ep->queued_deq_seg, ep->queued_deq_ptr); |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 1101 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1102 | } |
| 1103 | |
Hans de Goede | 0d4976e | 2014-08-20 16:41:55 +0300 | [diff] [blame] | 1104 | cleanup: |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1105 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 1106 | dev->eps[ep_index].queued_deq_seg = NULL; |
| 1107 | dev->eps[ep_index].queued_deq_ptr = NULL; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1108 | /* Restart any rings with pending URBs */ |
| 1109 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1110 | } |
| 1111 | |
Xenia Ragiadakou | b8200c9 | 2013-09-09 13:30:00 +0300 | [diff] [blame] | 1112 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1113 | union xhci_trb *trb, u32 cmd_comp_code) |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1114 | { |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1115 | unsigned int ep_index; |
| 1116 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1117 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1118 | /* This command will only fail if the endpoint wasn't halted, |
| 1119 | * but we don't care. |
| 1120 | */ |
Xenia Ragiadakou | a025432 | 2013-08-06 07:52:46 +0300 | [diff] [blame] | 1121 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1122 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1123 | |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1124 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
| 1125 | * command complete before the endpoint can be used. Queue that here |
| 1126 | * because the HW can't handle two commands being queued in a row. |
| 1127 | */ |
| 1128 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 1129 | struct xhci_command *command; |
| 1130 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
Hans de Goede | a0ee619 | 2014-07-25 22:01:21 +0200 | [diff] [blame] | 1131 | if (!command) { |
| 1132 | xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); |
| 1133 | return; |
| 1134 | } |
Xenia Ragiadakou | 4bdfe4c | 2013-08-06 07:52:45 +0300 | [diff] [blame] | 1135 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
| 1136 | "Queueing configure endpoint command"); |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 1137 | xhci_queue_configure_endpoint(xhci, command, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1138 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
| 1139 | false); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1140 | xhci_ring_cmd_db(xhci); |
| 1141 | } else { |
Mathias Nyman | c3492db | 2014-11-18 11:27:11 +0200 | [diff] [blame] | 1142 | /* Clear our internal halted state */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1143 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1144 | } |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1145 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1146 | |
Xenia Ragiadakou | b244b43 | 2013-09-09 13:29:47 +0300 | [diff] [blame] | 1147 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
| 1148 | u32 cmd_comp_code) |
| 1149 | { |
| 1150 | if (cmd_comp_code == COMP_SUCCESS) |
| 1151 | xhci->slot_id = slot_id; |
| 1152 | else |
| 1153 | xhci->slot_id = 0; |
Xenia Ragiadakou | b244b43 | 2013-09-09 13:29:47 +0300 | [diff] [blame] | 1154 | } |
| 1155 | |
Xenia Ragiadakou | 6c02dd1 | 2013-09-09 13:29:48 +0300 | [diff] [blame] | 1156 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
| 1157 | { |
| 1158 | struct xhci_virt_device *virt_dev; |
| 1159 | |
| 1160 | virt_dev = xhci->devs[slot_id]; |
| 1161 | if (!virt_dev) |
| 1162 | return; |
| 1163 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
| 1164 | /* Delete default control endpoint resources */ |
| 1165 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); |
| 1166 | xhci_free_virt_device(xhci, slot_id); |
| 1167 | } |
| 1168 | |
Xenia Ragiadakou | 6ed46d3 | 2013-09-09 13:29:55 +0300 | [diff] [blame] | 1169 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
| 1170 | struct xhci_event_cmd *event, u32 cmd_comp_code) |
| 1171 | { |
| 1172 | struct xhci_virt_device *virt_dev; |
| 1173 | struct xhci_input_control_ctx *ctrl_ctx; |
| 1174 | unsigned int ep_index; |
| 1175 | unsigned int ep_state; |
| 1176 | u32 add_flags, drop_flags; |
| 1177 | |
Xenia Ragiadakou | 6ed46d3 | 2013-09-09 13:29:55 +0300 | [diff] [blame] | 1178 | /* |
| 1179 | * Configure endpoint commands can come from the USB core |
| 1180 | * configuration or alt setting changes, or because the HW |
| 1181 | * needed an extra configure endpoint command after a reset |
| 1182 | * endpoint command or streams were being configured. |
| 1183 | * If the command was for a halted endpoint, the xHCI driver |
| 1184 | * is not waiting on the configure endpoint command. |
| 1185 | */ |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1186 | virt_dev = xhci->devs[slot_id]; |
Lin Wang | 4daf9df | 2015-01-09 16:06:31 +0200 | [diff] [blame] | 1187 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
Xenia Ragiadakou | 6ed46d3 | 2013-09-09 13:29:55 +0300 | [diff] [blame] | 1188 | if (!ctrl_ctx) { |
| 1189 | xhci_warn(xhci, "Could not get input context, bad type.\n"); |
| 1190 | return; |
| 1191 | } |
| 1192 | |
| 1193 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); |
| 1194 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
| 1195 | /* Input ctx add_flags are the endpoint index plus one */ |
| 1196 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; |
| 1197 | |
| 1198 | /* A usb_set_interface() call directly after clearing a halted |
| 1199 | * condition may race on this quirky hardware. Not worth |
| 1200 | * worrying about, since this is prototype hardware. Not sure |
| 1201 | * if this will work for streams, but streams support was |
| 1202 | * untested on this prototype. |
| 1203 | */ |
| 1204 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
| 1205 | ep_index != (unsigned int) -1 && |
| 1206 | add_flags - SLOT_FLAG == drop_flags) { |
| 1207 | ep_state = virt_dev->eps[ep_index].ep_state; |
| 1208 | if (!(ep_state & EP_HALTED)) |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 1209 | return; |
Xenia Ragiadakou | 6ed46d3 | 2013-09-09 13:29:55 +0300 | [diff] [blame] | 1210 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
| 1211 | "Completed config ep cmd - " |
| 1212 | "last ep index = %d, state = %d", |
| 1213 | ep_index, ep_state); |
| 1214 | /* Clear internal halted state and restart ring(s) */ |
| 1215 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; |
| 1216 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
| 1217 | return; |
| 1218 | } |
Xenia Ragiadakou | 6ed46d3 | 2013-09-09 13:29:55 +0300 | [diff] [blame] | 1219 | return; |
| 1220 | } |
| 1221 | |
Xenia Ragiadakou | f681321 | 2013-09-09 13:29:51 +0300 | [diff] [blame] | 1222 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
| 1223 | struct xhci_event_cmd *event) |
| 1224 | { |
Xenia Ragiadakou | f681321 | 2013-09-09 13:29:51 +0300 | [diff] [blame] | 1225 | xhci_dbg(xhci, "Completed reset device command.\n"); |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1226 | if (!xhci->devs[slot_id]) |
Xenia Ragiadakou | f681321 | 2013-09-09 13:29:51 +0300 | [diff] [blame] | 1227 | xhci_warn(xhci, "Reset device command completion " |
| 1228 | "for disabled slot %u\n", slot_id); |
| 1229 | } |
| 1230 | |
Xenia Ragiadakou | 2c07082 | 2013-09-09 13:29:52 +0300 | [diff] [blame] | 1231 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
| 1232 | struct xhci_event_cmd *event) |
| 1233 | { |
| 1234 | if (!(xhci->quirks & XHCI_NEC_HOST)) { |
| 1235 | xhci->error_bitmask |= 1 << 6; |
| 1236 | return; |
| 1237 | } |
| 1238 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
| 1239 | "NEC firmware version %2x.%02x", |
| 1240 | NEC_FW_MAJOR(le32_to_cpu(event->status)), |
| 1241 | NEC_FW_MINOR(le32_to_cpu(event->status))); |
| 1242 | } |
| 1243 | |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1244 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1245 | { |
| 1246 | list_del(&cmd->cmd_list); |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1247 | |
| 1248 | if (cmd->completion) { |
| 1249 | cmd->status = status; |
| 1250 | complete(cmd->completion); |
| 1251 | } else { |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1252 | kfree(cmd); |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1253 | } |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1254 | } |
| 1255 | |
| 1256 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) |
| 1257 | { |
| 1258 | struct xhci_command *cur_cmd, *tmp_cmd; |
| 1259 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1260 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1261 | } |
| 1262 | |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 1263 | void xhci_handle_command_timeout(struct work_struct *work) |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1264 | { |
| 1265 | struct xhci_hcd *xhci; |
| 1266 | int ret; |
| 1267 | unsigned long flags; |
| 1268 | u64 hw_ring_state; |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 1269 | |
| 1270 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1271 | |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1272 | spin_lock_irqsave(&xhci->lock, flags); |
Lu Baolu | 9da8e3e | 2017-01-03 18:28:46 +0200 | [diff] [blame] | 1273 | |
Mathias Nyman | 9e6c400 | 2017-01-03 18:28:48 +0200 | [diff] [blame] | 1274 | /* |
| 1275 | * If timeout work is pending, or current_cmd is NULL, it means we |
| 1276 | * raced with command completion. Command is handled so just return. |
| 1277 | */ |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 1278 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
Lu Baolu | 9da8e3e | 2017-01-03 18:28:46 +0200 | [diff] [blame] | 1279 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 1280 | return; |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1281 | } |
Lu Baolu | 9da8e3e | 2017-01-03 18:28:46 +0200 | [diff] [blame] | 1282 | /* mark this command to be cancelled */ |
Lu Baolu | 9da8e3e | 2017-01-03 18:28:46 +0200 | [diff] [blame] | 1283 | xhci->current_cmd->status = COMP_CMD_ABORT; |
| 1284 | |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1285 | /* Make sure command ring is running before aborting it */ |
| 1286 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
| 1287 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && |
| 1288 | (hw_ring_state & CMD_RING_RUNNING)) { |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 1289 | /* Prevent new doorbell, and start command abort */ |
| 1290 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1291 | xhci_dbg(xhci, "Command timeout\n"); |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 1292 | ret = xhci_abort_cmd_ring(xhci, flags); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1293 | if (unlikely(ret == -ESHUTDOWN)) { |
| 1294 | xhci_err(xhci, "Abort command ring failed\n"); |
| 1295 | xhci_cleanup_command_queue(xhci); |
Lu Baolu | cb02cce | 2017-01-03 18:28:49 +0200 | [diff] [blame] | 1296 | spin_unlock_irqrestore(&xhci->lock, flags); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1297 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
| 1298 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); |
Lu Baolu | cb02cce | 2017-01-03 18:28:49 +0200 | [diff] [blame] | 1299 | |
| 1300 | return; |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1301 | } |
Lu Baolu | cb02cce | 2017-01-03 18:28:49 +0200 | [diff] [blame] | 1302 | |
| 1303 | goto time_out_completed; |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1304 | } |
Mathias Nyman | 3425aa0 | 2016-06-01 18:09:08 +0300 | [diff] [blame] | 1305 | |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 1306 | /* host removed. Bail out */ |
| 1307 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { |
| 1308 | xhci_dbg(xhci, "host removed, ring start fail?\n"); |
Mathias Nyman | 3425aa0 | 2016-06-01 18:09:08 +0300 | [diff] [blame] | 1309 | xhci_cleanup_command_queue(xhci); |
Lu Baolu | cb02cce | 2017-01-03 18:28:49 +0200 | [diff] [blame] | 1310 | |
| 1311 | goto time_out_completed; |
Mathias Nyman | 3425aa0 | 2016-06-01 18:09:08 +0300 | [diff] [blame] | 1312 | } |
| 1313 | |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1314 | /* command timeout on stopped ring, ring can't be aborted */ |
| 1315 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); |
| 1316 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); |
Lu Baolu | cb02cce | 2017-01-03 18:28:49 +0200 | [diff] [blame] | 1317 | |
| 1318 | time_out_completed: |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1319 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 1320 | return; |
| 1321 | } |
| 1322 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1323 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
| 1324 | struct xhci_event_cmd *event) |
| 1325 | { |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1326 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1327 | u64 cmd_dma; |
| 1328 | dma_addr_t cmd_dequeue_dma; |
Xenia Ragiadakou | e7a79a1 | 2013-09-09 13:29:56 +0300 | [diff] [blame] | 1329 | u32 cmd_comp_code; |
Xenia Ragiadakou | 9124b12 | 2013-09-09 13:29:57 +0300 | [diff] [blame] | 1330 | union xhci_trb *cmd_trb; |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1331 | struct xhci_command *cmd; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1332 | u32 cmd_type; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1333 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1334 | cmd_dma = le64_to_cpu(event->cmd_trb); |
Xenia Ragiadakou | 9124b12 | 2013-09-09 13:29:57 +0300 | [diff] [blame] | 1335 | cmd_trb = xhci->cmd_ring->dequeue; |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1336 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
Xenia Ragiadakou | 9124b12 | 2013-09-09 13:29:57 +0300 | [diff] [blame] | 1337 | cmd_trb); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1338 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
| 1339 | if (cmd_dequeue_dma == 0) { |
| 1340 | xhci->error_bitmask |= 1 << 4; |
| 1341 | return; |
| 1342 | } |
| 1343 | /* Does the DMA address match our internal dequeue pointer address? */ |
| 1344 | if (cmd_dma != (u64) cmd_dequeue_dma) { |
| 1345 | xhci->error_bitmask |= 1 << 5; |
| 1346 | return; |
| 1347 | } |
Elric Fu | b63f405 | 2012-06-27 16:55:43 +0800 | [diff] [blame] | 1348 | |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1349 | cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); |
| 1350 | |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 1351 | cancel_delayed_work(&xhci->cmd_timer); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1352 | |
Xenia Ragiadakou | 9124b12 | 2013-09-09 13:29:57 +0300 | [diff] [blame] | 1353 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
Xenia Ragiadakou | 63a23b9a | 2013-08-06 07:52:48 +0300 | [diff] [blame] | 1354 | |
Xenia Ragiadakou | e7a79a1 | 2013-09-09 13:29:56 +0300 | [diff] [blame] | 1355 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1356 | |
| 1357 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ |
| 1358 | if (cmd_comp_code == COMP_CMD_STOP) { |
OGAWA Hirofumi | 63d92d1 | 2017-01-03 18:28:51 +0200 | [diff] [blame] | 1359 | complete_all(&xhci->cmd_ring_stop_completion); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1360 | return; |
| 1361 | } |
Mathias Nyman | 33be126 | 2016-08-16 10:18:03 +0300 | [diff] [blame] | 1362 | |
| 1363 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { |
| 1364 | xhci_err(xhci, |
| 1365 | "Command completion event does not match command\n"); |
| 1366 | return; |
| 1367 | } |
| 1368 | |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1369 | /* |
| 1370 | * Host aborted the command ring, check if the current command was |
| 1371 | * supposed to be aborted, otherwise continue normally. |
| 1372 | * The command ring is stopped now, but the xHC will issue a Command |
| 1373 | * Ring Stopped event which will cause us to restart it. |
| 1374 | */ |
| 1375 | if (cmd_comp_code == COMP_CMD_ABORT) { |
| 1376 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
Baolin Wang | 78ccc19 | 2017-01-03 18:28:47 +0200 | [diff] [blame] | 1377 | if (cmd->status == COMP_CMD_ABORT) { |
| 1378 | if (xhci->current_cmd == cmd) |
| 1379 | xhci->current_cmd = NULL; |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1380 | goto event_handled; |
Baolin Wang | 78ccc19 | 2017-01-03 18:28:47 +0200 | [diff] [blame] | 1381 | } |
Elric Fu | b63f405 | 2012-06-27 16:55:43 +0800 | [diff] [blame] | 1382 | } |
| 1383 | |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1384 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
| 1385 | switch (cmd_type) { |
| 1386 | case TRB_ENABLE_SLOT: |
Xenia Ragiadakou | e7a79a1 | 2013-09-09 13:29:56 +0300 | [diff] [blame] | 1387 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1388 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1389 | case TRB_DISABLE_SLOT: |
Xenia Ragiadakou | 6c02dd1 | 2013-09-09 13:29:48 +0300 | [diff] [blame] | 1390 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1391 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1392 | case TRB_CONFIG_EP: |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1393 | if (!cmd->completion) |
| 1394 | xhci_handle_cmd_config_ep(xhci, slot_id, event, |
| 1395 | cmd_comp_code); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1396 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1397 | case TRB_EVAL_CONTEXT: |
Sarah Sharp | 2d3f1fa | 2009-08-07 14:04:49 -0700 | [diff] [blame] | 1398 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1399 | case TRB_ADDR_DEV: |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1400 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1401 | case TRB_STOP_RING: |
Xenia Ragiadakou | b8200c9 | 2013-09-09 13:30:00 +0300 | [diff] [blame] | 1402 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
| 1403 | le32_to_cpu(cmd_trb->generic.field[3]))); |
| 1404 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1405 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1406 | case TRB_SET_DEQ: |
Xenia Ragiadakou | b8200c9 | 2013-09-09 13:30:00 +0300 | [diff] [blame] | 1407 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
| 1408 | le32_to_cpu(cmd_trb->generic.field[3]))); |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1409 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1410 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1411 | case TRB_CMD_NOOP: |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1412 | /* Is this an aborted command turned to NO-OP? */ |
| 1413 | if (cmd->status == COMP_CMD_STOP) |
| 1414 | cmd_comp_code = COMP_CMD_STOP; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1415 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1416 | case TRB_RESET_EP: |
Xenia Ragiadakou | b8200c9 | 2013-09-09 13:30:00 +0300 | [diff] [blame] | 1417 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
| 1418 | le32_to_cpu(cmd_trb->generic.field[3]))); |
Xenia Ragiadakou | c69a059 | 2013-09-09 13:30:01 +0300 | [diff] [blame] | 1419 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1420 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1421 | case TRB_RESET_DEV: |
Mathias Nyman | 6fcfb0d | 2014-06-24 17:14:40 +0300 | [diff] [blame] | 1422 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
| 1423 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) |
| 1424 | */ |
| 1425 | slot_id = TRB_TO_SLOT_ID( |
| 1426 | le32_to_cpu(cmd_trb->generic.field[3])); |
Xenia Ragiadakou | f681321 | 2013-09-09 13:29:51 +0300 | [diff] [blame] | 1427 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 1428 | break; |
Xenia Ragiadakou | b54fc46 | 2013-09-09 13:29:58 +0300 | [diff] [blame] | 1429 | case TRB_NEC_GET_FW: |
Xenia Ragiadakou | 2c07082 | 2013-09-09 13:29:52 +0300 | [diff] [blame] | 1430 | xhci_handle_cmd_nec_get_fw(xhci, event); |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1431 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1432 | default: |
| 1433 | /* Skip over unknown commands on the event ring */ |
| 1434 | xhci->error_bitmask |= 1 << 6; |
| 1435 | break; |
| 1436 | } |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1437 | |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1438 | /* restart timer if this wasn't the last command */ |
| 1439 | if (cmd->cmd_list.next != &xhci->cmd_list) { |
| 1440 | xhci->current_cmd = list_entry(cmd->cmd_list.next, |
| 1441 | struct xhci_command, cmd_list); |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 1442 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
Lu Baolu | 9da8e3e | 2017-01-03 18:28:46 +0200 | [diff] [blame] | 1443 | } else if (xhci->current_cmd == cmd) { |
| 1444 | xhci->current_cmd = NULL; |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 1445 | } |
| 1446 | |
| 1447 | event_handled: |
Mathias Nyman | 9ea1833 | 2014-05-08 19:26:02 +0300 | [diff] [blame] | 1448 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 1449 | |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 1450 | inc_deq(xhci, xhci->cmd_ring); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1451 | } |
| 1452 | |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1453 | static void handle_vendor_event(struct xhci_hcd *xhci, |
| 1454 | union xhci_trb *event) |
| 1455 | { |
| 1456 | u32 trb_type; |
| 1457 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1458 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1459 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
| 1460 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) |
| 1461 | handle_cmd_completion(xhci, &event->event_cmd); |
| 1462 | } |
| 1463 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1464 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
| 1465 | * port registers -- USB 3.0 and USB 2.0). |
| 1466 | * |
| 1467 | * Returns a zero-based port number, which is suitable for indexing into each of |
| 1468 | * the split roothubs' port arrays and bus state arrays. |
Sarah Sharp | d0cd5d4 | 2011-11-14 17:51:39 -0800 | [diff] [blame] | 1469 | * Add one to it in order to call xhci_find_slot_id_by_port. |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1470 | */ |
| 1471 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, |
| 1472 | struct xhci_hcd *xhci, u32 port_id) |
| 1473 | { |
| 1474 | unsigned int i; |
| 1475 | unsigned int num_similar_speed_ports = 0; |
| 1476 | |
| 1477 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], |
| 1478 | * and usb2_ports are 0-based indexes. Count the number of similar |
| 1479 | * speed ports, up to 1 port before this port. |
| 1480 | */ |
| 1481 | for (i = 0; i < (port_id - 1); i++) { |
| 1482 | u8 port_speed = xhci->port_array[i]; |
| 1483 | |
| 1484 | /* |
| 1485 | * Skip ports that don't have known speeds, or have duplicate |
| 1486 | * Extended Capabilities port speed entries. |
| 1487 | */ |
Dan Carpenter | 22e0487 | 2011-03-17 22:39:49 +0300 | [diff] [blame] | 1488 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1489 | continue; |
| 1490 | |
| 1491 | /* |
| 1492 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and |
| 1493 | * 1.1 ports are under the USB 2.0 hub. If the port speed |
| 1494 | * matches the device speed, it's a similar speed port. |
| 1495 | */ |
Mathias Nyman | b50107b | 2015-10-01 18:40:38 +0300 | [diff] [blame] | 1496 | if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1497 | num_similar_speed_ports++; |
| 1498 | } |
| 1499 | return num_similar_speed_ports; |
| 1500 | } |
| 1501 | |
Sarah Sharp | 623bef9 | 2011-11-11 14:57:33 -0800 | [diff] [blame] | 1502 | static void handle_device_notification(struct xhci_hcd *xhci, |
| 1503 | union xhci_trb *event) |
| 1504 | { |
| 1505 | u32 slot_id; |
Sarah Sharp | 4ee823b | 2011-11-14 18:00:01 -0800 | [diff] [blame] | 1506 | struct usb_device *udev; |
Sarah Sharp | 623bef9 | 2011-11-11 14:57:33 -0800 | [diff] [blame] | 1507 | |
Xenia Ragiadakou | 7e76ad4 | 2013-09-09 21:03:10 +0300 | [diff] [blame] | 1508 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
Sarah Sharp | 4ee823b | 2011-11-14 18:00:01 -0800 | [diff] [blame] | 1509 | if (!xhci->devs[slot_id]) { |
Sarah Sharp | 623bef9 | 2011-11-11 14:57:33 -0800 | [diff] [blame] | 1510 | xhci_warn(xhci, "Device Notification event for " |
| 1511 | "unused slot %u\n", slot_id); |
Sarah Sharp | 4ee823b | 2011-11-14 18:00:01 -0800 | [diff] [blame] | 1512 | return; |
| 1513 | } |
| 1514 | |
| 1515 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", |
| 1516 | slot_id); |
| 1517 | udev = xhci->devs[slot_id]->udev; |
| 1518 | if (udev && udev->parent) |
| 1519 | usb_wakeup_notification(udev->parent, udev->portnum); |
Sarah Sharp | 623bef9 | 2011-11-11 14:57:33 -0800 | [diff] [blame] | 1520 | } |
| 1521 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1522 | static void handle_port_status(struct xhci_hcd *xhci, |
| 1523 | union xhci_trb *event) |
| 1524 | { |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1525 | struct usb_hcd *hcd; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1526 | u32 port_id; |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1527 | u32 temp, temp1; |
Sarah Sharp | 518e848 | 2010-12-15 11:56:29 -0800 | [diff] [blame] | 1528 | int max_ports; |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1529 | int slot_id; |
Sarah Sharp | 5308a91 | 2010-12-01 11:34:59 -0800 | [diff] [blame] | 1530 | unsigned int faked_port_index; |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1531 | u8 major_revision; |
Sarah Sharp | 20b67cf | 2010-12-15 12:47:14 -0800 | [diff] [blame] | 1532 | struct xhci_bus_state *bus_state; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1533 | __le32 __iomem **port_array; |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1534 | bool bogus_port_status = false; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1535 | |
| 1536 | /* Port status change events always have a successful completion code */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1537 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1538 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
| 1539 | xhci->error_bitmask |= 1 << 8; |
| 1540 | } |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1541 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1542 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
| 1543 | |
Sarah Sharp | 518e848 | 2010-12-15 11:56:29 -0800 | [diff] [blame] | 1544 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
| 1545 | if ((port_id <= 0) || (port_id > max_ports)) { |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1546 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
Peter Chen | 09ce0c0 | 2013-03-20 09:30:00 +0800 | [diff] [blame] | 1547 | inc_deq(xhci, xhci->event_ring); |
| 1548 | return; |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1549 | } |
| 1550 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1551 | /* Figure out which usb_hcd this port is attached to: |
| 1552 | * is it a USB 3.0 port or a USB 2.0/1.1 port? |
| 1553 | */ |
| 1554 | major_revision = xhci->port_array[port_id - 1]; |
Peter Chen | 09ce0c0 | 2013-03-20 09:30:00 +0800 | [diff] [blame] | 1555 | |
| 1556 | /* Find the right roothub. */ |
| 1557 | hcd = xhci_to_hcd(xhci); |
Mathias Nyman | b50107b | 2015-10-01 18:40:38 +0300 | [diff] [blame] | 1558 | if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) |
Peter Chen | 09ce0c0 | 2013-03-20 09:30:00 +0800 | [diff] [blame] | 1559 | hcd = xhci->shared_hcd; |
| 1560 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1561 | if (major_revision == 0) { |
| 1562 | xhci_warn(xhci, "Event for port %u not in " |
| 1563 | "Extended Capabilities, ignoring.\n", |
| 1564 | port_id); |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1565 | bogus_port_status = true; |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1566 | goto cleanup; |
| 1567 | } |
Dan Carpenter | 22e0487 | 2011-03-17 22:39:49 +0300 | [diff] [blame] | 1568 | if (major_revision == DUPLICATE_ENTRY) { |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1569 | xhci_warn(xhci, "Event for port %u duplicated in" |
| 1570 | "Extended Capabilities, ignoring.\n", |
| 1571 | port_id); |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1572 | bogus_port_status = true; |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1573 | goto cleanup; |
Sarah Sharp | 5308a91 | 2010-12-01 11:34:59 -0800 | [diff] [blame] | 1574 | } |
| 1575 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1576 | /* |
| 1577 | * Hardware port IDs reported by a Port Status Change Event include USB |
| 1578 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a |
| 1579 | * resume event, but we first need to translate the hardware port ID |
| 1580 | * into the index into the ports on the correct split roothub, and the |
| 1581 | * correct bus_state structure. |
| 1582 | */ |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1583 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
Mathias Nyman | b50107b | 2015-10-01 18:40:38 +0300 | [diff] [blame] | 1584 | if (hcd->speed >= HCD_USB3) |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1585 | port_array = xhci->usb3_ports; |
| 1586 | else |
| 1587 | port_array = xhci->usb2_ports; |
| 1588 | /* Find the faked port hub number */ |
| 1589 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, |
| 1590 | port_id); |
| 1591 | |
Xenia Ragiadakou | b0ba972 | 2013-11-15 05:34:06 +0200 | [diff] [blame] | 1592 | temp = readl(port_array[faked_port_index]); |
Sarah Sharp | 7111ebc | 2010-12-14 13:24:55 -0800 | [diff] [blame] | 1593 | if (hcd->state == HC_STATE_SUSPENDED) { |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1594 | xhci_dbg(xhci, "resume root hub\n"); |
| 1595 | usb_hcd_resume_root_hub(hcd); |
| 1596 | } |
| 1597 | |
Mathias Nyman | b50107b | 2015-10-01 18:40:38 +0300 | [diff] [blame] | 1598 | if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
Zhuang Jin Can | fac4271 | 2015-07-21 17:20:30 +0300 | [diff] [blame] | 1599 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); |
| 1600 | |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1601 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
| 1602 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); |
| 1603 | |
Xenia Ragiadakou | b0ba972 | 2013-11-15 05:34:06 +0200 | [diff] [blame] | 1604 | temp1 = readl(&xhci->op_regs->command); |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1605 | if (!(temp1 & CMD_RUN)) { |
| 1606 | xhci_warn(xhci, "xHC is not running.\n"); |
| 1607 | goto cleanup; |
| 1608 | } |
| 1609 | |
Mathias Nyman | 2338b9e | 2015-10-01 18:40:36 +0300 | [diff] [blame] | 1610 | if (DEV_SUPERSPEED_ANY(temp)) { |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1611 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
Sarah Sharp | 4ee823b | 2011-11-14 18:00:01 -0800 | [diff] [blame] | 1612 | /* Set a flag to say the port signaled remote wakeup, |
| 1613 | * so we can tell the difference between the end of |
| 1614 | * device and host initiated resume. |
| 1615 | */ |
| 1616 | bus_state->port_remote_wakeup |= 1 << faked_port_index; |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1617 | xhci_test_and_clear_bit(xhci, port_array, |
| 1618 | faked_port_index, PORT_PLC); |
Andiry Xu | c9682df | 2011-09-23 14:19:48 -0700 | [diff] [blame] | 1619 | xhci_set_link_state(xhci, port_array, faked_port_index, |
| 1620 | XDEV_U0); |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1621 | /* Need to wait until the next link state change |
| 1622 | * indicates the device is actually in U0. |
| 1623 | */ |
| 1624 | bogus_port_status = true; |
| 1625 | goto cleanup; |
Mathias Nyman | f69115f | 2015-12-11 14:38:06 +0200 | [diff] [blame] | 1626 | } else if (!test_bit(faked_port_index, |
| 1627 | &bus_state->resuming_ports)) { |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1628 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1629 | bus_state->resume_done[faked_port_index] = jiffies + |
Felipe Balbi | b9e4518 | 2015-02-13 14:39:13 -0600 | [diff] [blame] | 1630 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
Andiry Xu | f370b99 | 2012-04-14 02:54:30 +0800 | [diff] [blame] | 1631 | set_bit(faked_port_index, &bus_state->resuming_ports); |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1632 | mod_timer(&hcd->rh_timer, |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1633 | bus_state->resume_done[faked_port_index]); |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1634 | /* Do the rest in GetPortStatus */ |
| 1635 | } |
| 1636 | } |
| 1637 | |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1638 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && |
Mathias Nyman | 2338b9e | 2015-10-01 18:40:36 +0300 | [diff] [blame] | 1639 | DEV_SUPERSPEED_ANY(temp)) { |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1640 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
Sarah Sharp | 4ee823b | 2011-11-14 18:00:01 -0800 | [diff] [blame] | 1641 | /* We've just brought the device into U0 through either the |
| 1642 | * Resume state after a device remote wakeup, or through the |
| 1643 | * U3Exit state after a host-initiated resume. If it's a device |
| 1644 | * initiated remote wake, don't pass up the link state change, |
| 1645 | * so the roothub behavior is consistent with external |
| 1646 | * USB 3.0 hub behavior. |
| 1647 | */ |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1648 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
| 1649 | faked_port_index + 1); |
| 1650 | if (slot_id && xhci->devs[slot_id]) |
| 1651 | xhci_ring_device(xhci, slot_id); |
Nickolai Zeldovich | ba7b5c2 | 2013-01-07 22:39:31 -0500 | [diff] [blame] | 1652 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
Sarah Sharp | 4ee823b | 2011-11-14 18:00:01 -0800 | [diff] [blame] | 1653 | bus_state->port_remote_wakeup &= |
| 1654 | ~(1 << faked_port_index); |
| 1655 | xhci_test_and_clear_bit(xhci, port_array, |
| 1656 | faked_port_index, PORT_PLC); |
| 1657 | usb_wakeup_notification(hcd->self.root_hub, |
| 1658 | faked_port_index + 1); |
| 1659 | bogus_port_status = true; |
| 1660 | goto cleanup; |
| 1661 | } |
Sarah Sharp | d93814c | 2012-01-24 16:39:02 -0800 | [diff] [blame] | 1662 | } |
| 1663 | |
Sarah Sharp | 8b3d457 | 2013-08-20 08:12:12 -0700 | [diff] [blame] | 1664 | /* |
| 1665 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or |
| 1666 | * RExit to a disconnect state). If so, let the the driver know it's |
| 1667 | * out of the RExit state. |
| 1668 | */ |
Mathias Nyman | 2338b9e | 2015-10-01 18:40:36 +0300 | [diff] [blame] | 1669 | if (!DEV_SUPERSPEED_ANY(temp) && |
Sarah Sharp | 8b3d457 | 2013-08-20 08:12:12 -0700 | [diff] [blame] | 1670 | test_and_clear_bit(faked_port_index, |
| 1671 | &bus_state->rexit_ports)) { |
| 1672 | complete(&bus_state->rexit_done[faked_port_index]); |
| 1673 | bogus_port_status = true; |
| 1674 | goto cleanup; |
| 1675 | } |
| 1676 | |
Mathias Nyman | b50107b | 2015-10-01 18:40:38 +0300 | [diff] [blame] | 1677 | if (hcd->speed < HCD_USB3) |
Andiry Xu | 6fd4562 | 2011-09-23 14:19:50 -0700 | [diff] [blame] | 1678 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
| 1679 | PORT_PLC); |
| 1680 | |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1681 | cleanup: |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1682 | /* Update event ring dequeue pointer before dropping the lock */ |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 1683 | inc_deq(xhci, xhci->event_ring); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1684 | |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1685 | /* Don't make the USB core poll the roothub if we got a bad port status |
| 1686 | * change event. Besides, at that point we can't tell which roothub |
| 1687 | * (USB 2.0 or USB 3.0) to kick. |
| 1688 | */ |
| 1689 | if (bogus_port_status) |
| 1690 | return; |
| 1691 | |
Sarah Sharp | c52804a | 2012-11-27 12:30:23 -0800 | [diff] [blame] | 1692 | /* |
| 1693 | * xHCI port-status-change events occur when the "or" of all the |
| 1694 | * status-change bits in the portsc register changes from 0 to 1. |
| 1695 | * New status changes won't cause an event if any other change |
| 1696 | * bits are still set. When an event occurs, switch over to |
| 1697 | * polling to avoid losing status changes. |
| 1698 | */ |
| 1699 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); |
| 1700 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1701 | spin_unlock(&xhci->lock); |
| 1702 | /* Pass this up to the core */ |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1703 | usb_hcd_poll_rh_status(hcd); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1704 | spin_lock(&xhci->lock); |
| 1705 | } |
| 1706 | |
| 1707 | /* |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1708 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending |
| 1709 | * at end_trb, which may be in another segment. If the suspect DMA address is a |
| 1710 | * TRB in this TD, this function returns that TRB's segment. Otherwise it |
| 1711 | * returns 0. |
| 1712 | */ |
Hans de Goede | cffb9be | 2014-08-20 16:41:51 +0300 | [diff] [blame] | 1713 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
| 1714 | struct xhci_segment *start_seg, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1715 | union xhci_trb *start_trb, |
| 1716 | union xhci_trb *end_trb, |
Hans de Goede | cffb9be | 2014-08-20 16:41:51 +0300 | [diff] [blame] | 1717 | dma_addr_t suspect_dma, |
| 1718 | bool debug) |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1719 | { |
| 1720 | dma_addr_t start_dma; |
| 1721 | dma_addr_t end_seg_dma; |
| 1722 | dma_addr_t end_trb_dma; |
| 1723 | struct xhci_segment *cur_seg; |
| 1724 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1725 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1726 | cur_seg = start_seg; |
| 1727 | |
| 1728 | do { |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1729 | if (start_dma == 0) |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1730 | return NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1731 | /* We may get an event for a Link TRB in the middle of a TD */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1732 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1733 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1734 | /* If the end TRB isn't in this segment, this is set to 0 */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1735 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1736 | |
Hans de Goede | cffb9be | 2014-08-20 16:41:51 +0300 | [diff] [blame] | 1737 | if (debug) |
| 1738 | xhci_warn(xhci, |
| 1739 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", |
| 1740 | (unsigned long long)suspect_dma, |
| 1741 | (unsigned long long)start_dma, |
| 1742 | (unsigned long long)end_trb_dma, |
| 1743 | (unsigned long long)cur_seg->dma, |
| 1744 | (unsigned long long)end_seg_dma); |
| 1745 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1746 | if (end_trb_dma > 0) { |
| 1747 | /* The end TRB is in this segment, so suspect should be here */ |
| 1748 | if (start_dma <= end_trb_dma) { |
| 1749 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) |
| 1750 | return cur_seg; |
| 1751 | } else { |
| 1752 | /* Case for one segment with |
| 1753 | * a TD wrapped around to the top |
| 1754 | */ |
| 1755 | if ((suspect_dma >= start_dma && |
| 1756 | suspect_dma <= end_seg_dma) || |
| 1757 | (suspect_dma >= cur_seg->dma && |
| 1758 | suspect_dma <= end_trb_dma)) |
| 1759 | return cur_seg; |
| 1760 | } |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1761 | return NULL; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1762 | } else { |
| 1763 | /* Might still be somewhere in this segment */ |
| 1764 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) |
| 1765 | return cur_seg; |
| 1766 | } |
| 1767 | cur_seg = cur_seg->next; |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1768 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1769 | } while (cur_seg != start_seg); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1770 | |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1771 | return NULL; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1772 | } |
| 1773 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1774 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
| 1775 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1776 | unsigned int stream_id, |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1777 | struct xhci_td *td, union xhci_trb *event_trb) |
| 1778 | { |
| 1779 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 1780 | struct xhci_command *command; |
| 1781 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
| 1782 | if (!command) |
| 1783 | return; |
| 1784 | |
Mathias Nyman | d0167ad | 2015-03-10 19:49:00 +0200 | [diff] [blame] | 1785 | ep->ep_state |= EP_HALTED; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1786 | ep->stopped_stream = stream_id; |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1787 | |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 1788 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
Mathias Nyman | d97b4f8 | 2014-11-27 18:19:16 +0200 | [diff] [blame] | 1789 | xhci_cleanup_stalled_ring(xhci, ep_index, td); |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1790 | |
Sarah Sharp | 5e5cf6f | 2010-05-06 13:40:18 -0700 | [diff] [blame] | 1791 | ep->stopped_stream = 0; |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1792 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1793 | xhci_ring_cmd_db(xhci); |
| 1794 | } |
| 1795 | |
| 1796 | /* Check if an error has halted the endpoint ring. The class driver will |
| 1797 | * cleanup the halt for a non-default control endpoint if we indicate a stall. |
| 1798 | * However, a babble and other errors also halt the endpoint ring, and the class |
| 1799 | * driver won't clear the halt in that case, so we need to issue a Set Transfer |
| 1800 | * Ring Dequeue Pointer command manually. |
| 1801 | */ |
| 1802 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, |
| 1803 | struct xhci_ep_ctx *ep_ctx, |
| 1804 | unsigned int trb_comp_code) |
| 1805 | { |
| 1806 | /* TRB completion codes that may require a manual halt cleanup */ |
| 1807 | if (trb_comp_code == COMP_TX_ERR || |
| 1808 | trb_comp_code == COMP_BABBLE || |
| 1809 | trb_comp_code == COMP_SPLIT_ERR) |
Rajesh Bhagat | d4fc8bf | 2016-03-11 10:27:49 +0530 | [diff] [blame] | 1810 | /* The 0.95 spec says a babbling control endpoint |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1811 | * is not halted. The 0.96 spec says it is. Some HW |
| 1812 | * claims to be 0.95 compliant, but it halts the control |
| 1813 | * endpoint anyway. Check if a babble halted the |
| 1814 | * endpoint. |
| 1815 | */ |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 1816 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
| 1817 | cpu_to_le32(EP_STATE_HALTED)) |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1818 | return 1; |
| 1819 | |
| 1820 | return 0; |
| 1821 | } |
| 1822 | |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 1823 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
| 1824 | { |
| 1825 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { |
| 1826 | /* Vendor defined "informational" completion code, |
| 1827 | * treat as not-an-error. |
| 1828 | */ |
| 1829 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", |
| 1830 | trb_comp_code); |
| 1831 | xhci_dbg(xhci, "Treating code as success.\n"); |
| 1832 | return 1; |
| 1833 | } |
| 1834 | return 0; |
| 1835 | } |
| 1836 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1837 | /* |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1838 | * Finish the td processing, remove the td from td list; |
| 1839 | * Return 1 if the urb can be given back. |
| 1840 | */ |
| 1841 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1842 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1843 | struct xhci_virt_ep *ep, int *status, bool skip) |
| 1844 | { |
| 1845 | struct xhci_virt_device *xdev; |
| 1846 | struct xhci_ring *ep_ring; |
| 1847 | unsigned int slot_id; |
| 1848 | int ep_index; |
| 1849 | struct urb *urb = NULL; |
| 1850 | struct xhci_ep_ctx *ep_ctx; |
| 1851 | int ret = 0; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1852 | struct urb_priv *urb_priv; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1853 | u32 trb_comp_code; |
| 1854 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1855 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1856 | xdev = xhci->devs[slot_id]; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1857 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
| 1858 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1859 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1860 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1861 | |
| 1862 | if (skip) |
| 1863 | goto td_cleanup; |
| 1864 | |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 1865 | if (trb_comp_code == COMP_STOP_INVAL || |
| 1866 | trb_comp_code == COMP_STOP || |
| 1867 | trb_comp_code == COMP_STOP_SHORT) { |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1868 | /* The Endpoint Stop Command completion will take care of any |
| 1869 | * stopped TDs. A stopped TD may be restarted, so don't update |
| 1870 | * the ring dequeue pointer or take this TD off any lists yet. |
| 1871 | */ |
| 1872 | ep->stopped_td = td; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1873 | return 0; |
Mathias Nyman | 69defe0 | 2014-11-27 18:19:14 +0200 | [diff] [blame] | 1874 | } |
| 1875 | if (trb_comp_code == COMP_STALL || |
| 1876 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, |
| 1877 | trb_comp_code)) { |
| 1878 | /* Issue a reset endpoint command to clear the host side |
| 1879 | * halt, followed by a set dequeue command to move the |
| 1880 | * dequeue pointer past the TD. |
| 1881 | * The class driver clears the device side halt later. |
| 1882 | */ |
| 1883 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, |
| 1884 | ep_ring->stream_id, td, event_trb); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1885 | } else { |
Mathias Nyman | 69defe0 | 2014-11-27 18:19:14 +0200 | [diff] [blame] | 1886 | /* Update ring dequeue pointer */ |
| 1887 | while (ep_ring->dequeue != td->last_trb) |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 1888 | inc_deq(xhci, ep_ring); |
Mathias Nyman | 69defe0 | 2014-11-27 18:19:14 +0200 | [diff] [blame] | 1889 | inc_deq(xhci, ep_ring); |
| 1890 | } |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1891 | |
| 1892 | td_cleanup: |
Mathias Nyman | 69defe0 | 2014-11-27 18:19:14 +0200 | [diff] [blame] | 1893 | /* Clean up the endpoint's TD list */ |
| 1894 | urb = td->urb; |
| 1895 | urb_priv = urb->hcpriv; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1896 | |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 1897 | /* if a bounce buffer was used to align this td then unmap it */ |
| 1898 | if (td->bounce_seg) |
| 1899 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); |
| 1900 | |
Mathias Nyman | 69defe0 | 2014-11-27 18:19:14 +0200 | [diff] [blame] | 1901 | /* Do one last check of the actual transfer length. |
| 1902 | * If the host controller said we transferred more data than the buffer |
| 1903 | * length, urb->actual_length will be a very big number (since it's |
| 1904 | * unsigned). Play it safe and say we didn't transfer anything. |
| 1905 | */ |
| 1906 | if (urb->actual_length > urb->transfer_buffer_length) { |
| 1907 | xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n", |
| 1908 | urb->transfer_buffer_length, |
| 1909 | urb->actual_length); |
| 1910 | urb->actual_length = 0; |
| 1911 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1912 | *status = -EREMOTEIO; |
| 1913 | else |
| 1914 | *status = 0; |
| 1915 | } |
| 1916 | list_del_init(&td->td_list); |
| 1917 | /* Was this TD slated to be cancelled but completed anyway? */ |
| 1918 | if (!list_empty(&td->cancelled_td_list)) |
| 1919 | list_del_init(&td->cancelled_td_list); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1920 | |
Mathias Nyman | 69defe0 | 2014-11-27 18:19:14 +0200 | [diff] [blame] | 1921 | urb_priv->td_cnt++; |
| 1922 | /* Giveback the urb when all the tds are completed */ |
| 1923 | if (urb_priv->td_cnt == urb_priv->length) { |
| 1924 | ret = 1; |
| 1925 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
| 1926 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; |
| 1927 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
| 1928 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
| 1929 | usb_amd_quirk_pll_enable(); |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 1930 | } |
| 1931 | } |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1932 | } |
| 1933 | |
| 1934 | return ret; |
| 1935 | } |
| 1936 | |
| 1937 | /* |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1938 | * Process control tds, update urb status and actual_length. |
| 1939 | */ |
| 1940 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1941 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1942 | struct xhci_virt_ep *ep, int *status) |
| 1943 | { |
| 1944 | struct xhci_virt_device *xdev; |
| 1945 | struct xhci_ring *ep_ring; |
| 1946 | unsigned int slot_id; |
| 1947 | int ep_index; |
| 1948 | struct xhci_ep_ctx *ep_ctx; |
| 1949 | u32 trb_comp_code; |
| 1950 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1951 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1952 | xdev = xhci->devs[slot_id]; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1953 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
| 1954 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1955 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1956 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1957 | |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1958 | switch (trb_comp_code) { |
| 1959 | case COMP_SUCCESS: |
| 1960 | if (event_trb == ep_ring->dequeue) { |
| 1961 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " |
| 1962 | "without IOC set??\n"); |
| 1963 | *status = -ESHUTDOWN; |
| 1964 | } else if (event_trb != td->last_trb) { |
| 1965 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " |
| 1966 | "without IOC set??\n"); |
| 1967 | *status = -ESHUTDOWN; |
| 1968 | } else { |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1969 | *status = 0; |
| 1970 | } |
| 1971 | break; |
| 1972 | case COMP_SHORT_TX: |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1973 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1974 | *status = -EREMOTEIO; |
| 1975 | else |
| 1976 | *status = 0; |
| 1977 | break; |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 1978 | case COMP_STOP_SHORT: |
| 1979 | if (event_trb == ep_ring->dequeue || event_trb == td->last_trb) |
| 1980 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
| 1981 | else |
| 1982 | td->urb->actual_length = |
| 1983 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
| 1984 | |
| 1985 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
Sarah Sharp | 3abeca9 | 2011-05-05 19:08:09 -0700 | [diff] [blame] | 1986 | case COMP_STOP: |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 1987 | /* Did we stop at data stage? */ |
| 1988 | if (event_trb != ep_ring->dequeue && event_trb != td->last_trb) |
| 1989 | td->urb->actual_length = |
| 1990 | td->urb->transfer_buffer_length - |
| 1991 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
| 1992 | /* fall through */ |
| 1993 | case COMP_STOP_INVAL: |
Sarah Sharp | 3abeca9 | 2011-05-05 19:08:09 -0700 | [diff] [blame] | 1994 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1995 | default: |
| 1996 | if (!xhci_requires_manual_halt_cleanup(xhci, |
| 1997 | ep_ctx, trb_comp_code)) |
| 1998 | break; |
| 1999 | xhci_dbg(xhci, "TRB error code %u, " |
| 2000 | "halted endpoint index = %u\n", |
| 2001 | trb_comp_code, ep_index); |
| 2002 | /* else fall through */ |
| 2003 | case COMP_STALL: |
| 2004 | /* Did we transfer part of the data (middle) phase? */ |
| 2005 | if (event_trb != ep_ring->dequeue && |
| 2006 | event_trb != td->last_trb) |
| 2007 | td->urb->actual_length = |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2008 | td->urb->transfer_buffer_length - |
| 2009 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
Mathias Nyman | 22ae47e | 2015-05-29 17:01:53 +0300 | [diff] [blame] | 2010 | else if (!td->urb_length_set) |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 2011 | td->urb->actual_length = 0; |
| 2012 | |
Mathias Nyman | 8e71a32 | 2014-11-18 11:27:12 +0200 | [diff] [blame] | 2013 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 2014 | } |
| 2015 | /* |
| 2016 | * Did we transfer any data, despite the errors that might have |
| 2017 | * happened? I.e. did we get past the setup stage? |
| 2018 | */ |
| 2019 | if (event_trb != ep_ring->dequeue) { |
| 2020 | /* The event was for the status stage */ |
| 2021 | if (event_trb == td->last_trb) { |
Aleksander Morgado | 45ba215 | 2015-03-06 17:14:21 +0200 | [diff] [blame] | 2022 | if (td->urb_length_set) { |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 2023 | /* Don't overwrite a previously set error code |
| 2024 | */ |
| 2025 | if ((*status == -EINPROGRESS || *status == 0) && |
| 2026 | (td->urb->transfer_flags |
| 2027 | & URB_SHORT_NOT_OK)) |
| 2028 | /* Did we already see a short data |
| 2029 | * stage? */ |
| 2030 | *status = -EREMOTEIO; |
| 2031 | } else { |
| 2032 | td->urb->actual_length = |
| 2033 | td->urb->transfer_buffer_length; |
| 2034 | } |
| 2035 | } else { |
Aleksander Morgado | 45ba215 | 2015-03-06 17:14:21 +0200 | [diff] [blame] | 2036 | /* |
| 2037 | * Maybe the event was for the data stage? If so, update |
| 2038 | * already the actual_length of the URB and flag it as |
| 2039 | * set, so that it is not overwritten in the event for |
| 2040 | * the last TRB. |
| 2041 | */ |
| 2042 | td->urb_length_set = true; |
Sarah Sharp | 3abeca9 | 2011-05-05 19:08:09 -0700 | [diff] [blame] | 2043 | td->urb->actual_length = |
| 2044 | td->urb->transfer_buffer_length - |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2045 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
Sarah Sharp | 3abeca9 | 2011-05-05 19:08:09 -0700 | [diff] [blame] | 2046 | xhci_dbg(xhci, "Waiting for status " |
| 2047 | "stage event\n"); |
| 2048 | return 0; |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 2049 | } |
| 2050 | } |
| 2051 | |
| 2052 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 2053 | } |
| 2054 | |
| 2055 | /* |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2056 | * Process isochronous tds, update urb packet status and actual_length. |
| 2057 | */ |
| 2058 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 2059 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 2060 | struct xhci_virt_ep *ep, int *status) |
| 2061 | { |
| 2062 | struct xhci_ring *ep_ring; |
| 2063 | struct urb_priv *urb_priv; |
| 2064 | int idx; |
| 2065 | int len = 0; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2066 | union xhci_trb *cur_trb; |
| 2067 | struct xhci_segment *cur_seg; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2068 | struct usb_iso_packet_descriptor *frame; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2069 | u32 trb_comp_code; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2070 | bool skip_td = false; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2071 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2072 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
| 2073 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2074 | urb_priv = td->urb->hcpriv; |
| 2075 | idx = urb_priv->td_cnt; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2076 | frame = &td->urb->iso_frame_desc[idx]; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2077 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2078 | /* handle completion code */ |
| 2079 | switch (trb_comp_code) { |
| 2080 | case COMP_SUCCESS: |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2081 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
Sarah Sharp | 1530bbc6 | 2012-05-08 09:22:49 -0700 | [diff] [blame] | 2082 | frame->status = 0; |
| 2083 | break; |
| 2084 | } |
| 2085 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
| 2086 | trb_comp_code = COMP_SHORT_TX; |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 2087 | /* fallthrough */ |
| 2088 | case COMP_STOP_SHORT: |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2089 | case COMP_SHORT_TX: |
| 2090 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? |
| 2091 | -EREMOTEIO : 0; |
| 2092 | break; |
| 2093 | case COMP_BW_OVER: |
| 2094 | frame->status = -ECOMM; |
| 2095 | skip_td = true; |
| 2096 | break; |
| 2097 | case COMP_BUFF_OVER: |
| 2098 | case COMP_BABBLE: |
| 2099 | frame->status = -EOVERFLOW; |
| 2100 | skip_td = true; |
| 2101 | break; |
Alex He | f6ba6fe | 2011-06-08 18:34:06 +0800 | [diff] [blame] | 2102 | case COMP_DEV_ERR: |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2103 | case COMP_STALL: |
Mathias Nyman | d104d01 | 2015-04-30 17:16:02 +0300 | [diff] [blame] | 2104 | frame->status = -EPROTO; |
| 2105 | skip_td = true; |
| 2106 | break; |
Hans de Goede | 9c74599 | 2012-04-23 15:06:09 +0200 | [diff] [blame] | 2107 | case COMP_TX_ERR: |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2108 | frame->status = -EPROTO; |
Mathias Nyman | d104d01 | 2015-04-30 17:16:02 +0300 | [diff] [blame] | 2109 | if (event_trb != td->last_trb) |
| 2110 | return 0; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2111 | skip_td = true; |
| 2112 | break; |
| 2113 | case COMP_STOP: |
| 2114 | case COMP_STOP_INVAL: |
| 2115 | break; |
| 2116 | default: |
| 2117 | frame->status = -1; |
| 2118 | break; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2119 | } |
| 2120 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2121 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
| 2122 | frame->actual_length = frame->length; |
| 2123 | td->urb->actual_length += frame->length; |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 2124 | } else if (trb_comp_code == COMP_STOP_SHORT) { |
| 2125 | frame->actual_length = |
| 2126 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
| 2127 | td->urb->actual_length += frame->actual_length; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2128 | } else { |
| 2129 | for (cur_trb = ep_ring->dequeue, |
| 2130 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; |
| 2131 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 2132 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
| 2133 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2134 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2135 | } |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2136 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2137 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2138 | |
| 2139 | if (trb_comp_code != COMP_STOP_INVAL) { |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2140 | frame->actual_length = len; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2141 | td->urb->actual_length += len; |
| 2142 | } |
| 2143 | } |
| 2144 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2145 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 2146 | } |
| 2147 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2148 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 2149 | struct xhci_transfer_event *event, |
| 2150 | struct xhci_virt_ep *ep, int *status) |
| 2151 | { |
| 2152 | struct xhci_ring *ep_ring; |
| 2153 | struct urb_priv *urb_priv; |
| 2154 | struct usb_iso_packet_descriptor *frame; |
| 2155 | int idx; |
| 2156 | |
Matt Evans | f697531 | 2011-06-01 13:01:01 +1000 | [diff] [blame] | 2157 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2158 | urb_priv = td->urb->hcpriv; |
| 2159 | idx = urb_priv->td_cnt; |
| 2160 | frame = &td->urb->iso_frame_desc[idx]; |
| 2161 | |
Sarah Sharp | b3df3f9 | 2011-06-15 19:57:46 -0700 | [diff] [blame] | 2162 | /* The transfer is partly done. */ |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2163 | frame->status = -EXDEV; |
| 2164 | |
| 2165 | /* calc actual length */ |
| 2166 | frame->actual_length = 0; |
| 2167 | |
| 2168 | /* Update ring dequeue pointer */ |
| 2169 | while (ep_ring->dequeue != td->last_trb) |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2170 | inc_deq(xhci, ep_ring); |
| 2171 | inc_deq(xhci, ep_ring); |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2172 | |
| 2173 | return finish_td(xhci, td, NULL, event, ep, status, true); |
| 2174 | } |
| 2175 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2176 | /* |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2177 | * Process bulk and interrupt tds, update urb status and actual_length. |
| 2178 | */ |
| 2179 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 2180 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 2181 | struct xhci_virt_ep *ep, int *status) |
| 2182 | { |
| 2183 | struct xhci_ring *ep_ring; |
| 2184 | union xhci_trb *cur_trb; |
| 2185 | struct xhci_segment *cur_seg; |
| 2186 | u32 trb_comp_code; |
| 2187 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2188 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
| 2189 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2190 | |
| 2191 | switch (trb_comp_code) { |
| 2192 | case COMP_SUCCESS: |
| 2193 | /* Double check that the HW transferred everything. */ |
Sarah Sharp | 1530bbc6 | 2012-05-08 09:22:49 -0700 | [diff] [blame] | 2194 | if (event_trb != td->last_trb || |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2195 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2196 | xhci_warn(xhci, "WARN Successful completion " |
| 2197 | "on short TX\n"); |
| 2198 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 2199 | *status = -EREMOTEIO; |
| 2200 | else |
| 2201 | *status = 0; |
Sarah Sharp | 1530bbc6 | 2012-05-08 09:22:49 -0700 | [diff] [blame] | 2202 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
| 2203 | trb_comp_code = COMP_SHORT_TX; |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2204 | } else { |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2205 | *status = 0; |
| 2206 | } |
| 2207 | break; |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 2208 | case COMP_STOP_SHORT: |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2209 | case COMP_SHORT_TX: |
| 2210 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 2211 | *status = -EREMOTEIO; |
| 2212 | else |
| 2213 | *status = 0; |
| 2214 | break; |
| 2215 | default: |
| 2216 | /* Others already handled above */ |
| 2217 | break; |
| 2218 | } |
Sarah Sharp | f444ff2 | 2011-04-05 15:53:47 -0700 | [diff] [blame] | 2219 | if (trb_comp_code == COMP_SHORT_TX) |
| 2220 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " |
| 2221 | "%d bytes untransferred\n", |
| 2222 | td->urb->ep->desc.bEndpointAddress, |
| 2223 | td->urb->transfer_buffer_length, |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2224 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 2225 | /* Stopped - short packet completion */ |
| 2226 | if (trb_comp_code == COMP_STOP_SHORT) { |
| 2227 | td->urb->actual_length = |
| 2228 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
| 2229 | |
| 2230 | if (td->urb->transfer_buffer_length < |
| 2231 | td->urb->actual_length) { |
| 2232 | xhci_warn(xhci, "HC gave bad length of %d bytes txed\n", |
| 2233 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
| 2234 | td->urb->actual_length = 0; |
| 2235 | /* status will be set by usb core for canceled urbs */ |
| 2236 | } |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2237 | /* Fast path - was this the last TRB in the TD for this URB? */ |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 2238 | } else if (event_trb == td->last_trb) { |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2239 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2240 | td->urb->actual_length = |
| 2241 | td->urb->transfer_buffer_length - |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2242 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2243 | if (td->urb->transfer_buffer_length < |
| 2244 | td->urb->actual_length) { |
| 2245 | xhci_warn(xhci, "HC gave bad length " |
| 2246 | "of %d bytes left\n", |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2247 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2248 | td->urb->actual_length = 0; |
| 2249 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 2250 | *status = -EREMOTEIO; |
| 2251 | else |
| 2252 | *status = 0; |
| 2253 | } |
| 2254 | /* Don't overwrite a previously set error code */ |
| 2255 | if (*status == -EINPROGRESS) { |
| 2256 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 2257 | *status = -EREMOTEIO; |
| 2258 | else |
| 2259 | *status = 0; |
| 2260 | } |
| 2261 | } else { |
| 2262 | td->urb->actual_length = |
| 2263 | td->urb->transfer_buffer_length; |
| 2264 | /* Ignore a short packet completion if the |
| 2265 | * untransferred length was zero. |
| 2266 | */ |
| 2267 | if (*status == -EREMOTEIO) |
| 2268 | *status = 0; |
| 2269 | } |
| 2270 | } else { |
| 2271 | /* Slow path - walk the list, starting from the dequeue |
| 2272 | * pointer, to get the actual length transferred. |
| 2273 | */ |
| 2274 | td->urb->actual_length = 0; |
| 2275 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
| 2276 | cur_trb != event_trb; |
| 2277 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 2278 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
| 2279 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2280 | td->urb->actual_length += |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2281 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2282 | } |
| 2283 | /* If the ring didn't stop on a Link or No-op TRB, add |
| 2284 | * in the actual bytes transferred from the Normal TRB |
| 2285 | */ |
| 2286 | if (trb_comp_code != COMP_STOP_INVAL) |
| 2287 | td->urb->actual_length += |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2288 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2289 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 2290 | } |
| 2291 | |
| 2292 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 2293 | } |
| 2294 | |
| 2295 | /* |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2296 | * If this function returns an error condition, it means it got a Transfer |
| 2297 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. |
| 2298 | * At this point, the host controller is probably hosed and should be reset. |
| 2299 | */ |
| 2300 | static int handle_tx_event(struct xhci_hcd *xhci, |
| 2301 | struct xhci_transfer_event *event) |
Felipe Balbi | ed384bd | 2012-08-07 14:10:03 +0300 | [diff] [blame] | 2302 | __releases(&xhci->lock) |
| 2303 | __acquires(&xhci->lock) |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2304 | { |
| 2305 | struct xhci_virt_device *xdev; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 2306 | struct xhci_virt_ep *ep; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2307 | struct xhci_ring *ep_ring; |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 2308 | unsigned int slot_id; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2309 | int ep_index; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 2310 | struct xhci_td *td = NULL; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2311 | dma_addr_t event_dma; |
| 2312 | struct xhci_segment *event_seg; |
| 2313 | union xhci_trb *event_trb; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 2314 | struct urb *urb = NULL; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2315 | int status = -EINPROGRESS; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2316 | struct urb_priv *urb_priv; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 2317 | struct xhci_ep_ctx *ep_ctx; |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2318 | struct list_head *tmp; |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 2319 | u32 trb_comp_code; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 2320 | int ret = 0; |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2321 | int td_num = 0; |
Mathias Nyman | 3b4739b | 2015-10-12 11:30:12 +0300 | [diff] [blame] | 2322 | bool handling_skipped_tds = false; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2323 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2324 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 2325 | xdev = xhci->devs[slot_id]; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2326 | if (!xdev) { |
| 2327 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 2328 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
Sarah Sharp | e910b44 | 2012-01-04 16:54:12 -0800 | [diff] [blame] | 2329 | (unsigned long long) xhci_trb_virt_to_dma( |
| 2330 | xhci->event_ring->deq_seg, |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 2331 | xhci->event_ring->dequeue), |
| 2332 | lower_32_bits(le64_to_cpu(event->buffer)), |
| 2333 | upper_32_bits(le64_to_cpu(event->buffer)), |
| 2334 | le32_to_cpu(event->transfer_len), |
| 2335 | le32_to_cpu(event->flags)); |
| 2336 | xhci_dbg(xhci, "Event ring:\n"); |
| 2337 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2338 | return -ENODEV; |
| 2339 | } |
| 2340 | |
| 2341 | /* Endpoint ID is 1 based, our index is zero based */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2342 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 2343 | ep = &xdev->eps[ep_index]; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2344 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 2345 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2346 | if (!ep_ring || |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2347 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
| 2348 | EP_STATE_DISABLED) { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2349 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
| 2350 | "or incorrect stream ring\n"); |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 2351 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
Sarah Sharp | e910b44 | 2012-01-04 16:54:12 -0800 | [diff] [blame] | 2352 | (unsigned long long) xhci_trb_virt_to_dma( |
| 2353 | xhci->event_ring->deq_seg, |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 2354 | xhci->event_ring->dequeue), |
| 2355 | lower_32_bits(le64_to_cpu(event->buffer)), |
| 2356 | upper_32_bits(le64_to_cpu(event->buffer)), |
| 2357 | le32_to_cpu(event->transfer_len), |
| 2358 | le32_to_cpu(event->flags)); |
| 2359 | xhci_dbg(xhci, "Event ring:\n"); |
| 2360 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2361 | return -ENODEV; |
| 2362 | } |
| 2363 | |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2364 | /* Count current td numbers if ep->skip is set */ |
| 2365 | if (ep->skip) { |
| 2366 | list_for_each(tmp, &ep_ring->td_list) |
| 2367 | td_num++; |
| 2368 | } |
| 2369 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2370 | event_dma = le64_to_cpu(event->buffer); |
| 2371 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2372 | /* Look for common error cases */ |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 2373 | switch (trb_comp_code) { |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2374 | /* Skip codes that require special handling depending on |
| 2375 | * transfer type |
| 2376 | */ |
| 2377 | case COMP_SUCCESS: |
Vivek Gautam | 1c11a17 | 2013-03-21 12:06:48 +0530 | [diff] [blame] | 2378 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
Sarah Sharp | 1530bbc6 | 2012-05-08 09:22:49 -0700 | [diff] [blame] | 2379 | break; |
| 2380 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) |
| 2381 | trb_comp_code = COMP_SHORT_TX; |
| 2382 | else |
Sarah Sharp | 8202ce2 | 2012-07-25 10:52:45 -0700 | [diff] [blame] | 2383 | xhci_warn_ratelimited(xhci, |
| 2384 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2385 | case COMP_SHORT_TX: |
| 2386 | break; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 2387 | case COMP_STOP: |
| 2388 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); |
| 2389 | break; |
| 2390 | case COMP_STOP_INVAL: |
| 2391 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); |
| 2392 | break; |
Lu Baolu | 40a3b77 | 2015-08-06 19:24:01 +0300 | [diff] [blame] | 2393 | case COMP_STOP_SHORT: |
| 2394 | xhci_dbg(xhci, "Stopped with short packet transfer detected\n"); |
| 2395 | break; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2396 | case COMP_STALL: |
Sarah Sharp | 2a9227a | 2011-10-25 13:55:30 +0200 | [diff] [blame] | 2397 | xhci_dbg(xhci, "Stalled endpoint\n"); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 2398 | ep->ep_state |= EP_HALTED; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2399 | status = -EPIPE; |
| 2400 | break; |
| 2401 | case COMP_TRB_ERR: |
| 2402 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); |
| 2403 | status = -EILSEQ; |
| 2404 | break; |
Sarah Sharp | ec74e40 | 2009-11-11 10:28:36 -0800 | [diff] [blame] | 2405 | case COMP_SPLIT_ERR: |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2406 | case COMP_TX_ERR: |
Sarah Sharp | 2a9227a | 2011-10-25 13:55:30 +0200 | [diff] [blame] | 2407 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2408 | status = -EPROTO; |
| 2409 | break; |
Sarah Sharp | 4a73143 | 2009-07-27 12:04:32 -0700 | [diff] [blame] | 2410 | case COMP_BABBLE: |
Sarah Sharp | 2a9227a | 2011-10-25 13:55:30 +0200 | [diff] [blame] | 2411 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
Sarah Sharp | 4a73143 | 2009-07-27 12:04:32 -0700 | [diff] [blame] | 2412 | status = -EOVERFLOW; |
| 2413 | break; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2414 | case COMP_DB_ERR: |
| 2415 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); |
| 2416 | status = -ENOSR; |
| 2417 | break; |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2418 | case COMP_BW_OVER: |
| 2419 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); |
| 2420 | break; |
| 2421 | case COMP_BUFF_OVER: |
| 2422 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); |
| 2423 | break; |
| 2424 | case COMP_UNDERRUN: |
| 2425 | /* |
| 2426 | * When the Isoch ring is empty, the xHC will generate |
| 2427 | * a Ring Overrun Event for IN Isoch endpoint or Ring |
| 2428 | * Underrun Event for OUT Isoch endpoint. |
| 2429 | */ |
| 2430 | xhci_dbg(xhci, "underrun event on endpoint\n"); |
| 2431 | if (!list_empty(&ep_ring->td_list)) |
| 2432 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " |
| 2433 | "still with TDs queued?\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2434 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
| 2435 | ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2436 | goto cleanup; |
| 2437 | case COMP_OVERRUN: |
| 2438 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
| 2439 | if (!list_empty(&ep_ring->td_list)) |
| 2440 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " |
| 2441 | "still with TDs queued?\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2442 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
| 2443 | ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2444 | goto cleanup; |
Alex He | f6ba6fe | 2011-06-08 18:34:06 +0800 | [diff] [blame] | 2445 | case COMP_DEV_ERR: |
| 2446 | xhci_warn(xhci, "WARN: detect an incompatible device"); |
| 2447 | status = -EPROTO; |
| 2448 | break; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2449 | case COMP_MISSED_INT: |
| 2450 | /* |
| 2451 | * When encounter missed service error, one or more isoc tds |
| 2452 | * may be missed by xHC. |
| 2453 | * Set skip flag of the ep_ring; Complete the missed tds as |
| 2454 | * short transfer when process the ep_ring next time. |
| 2455 | */ |
| 2456 | ep->skip = true; |
| 2457 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); |
| 2458 | goto cleanup; |
Mathias Nyman | 3b4739b | 2015-10-12 11:30:12 +0300 | [diff] [blame] | 2459 | case COMP_PING_ERR: |
| 2460 | ep->skip = true; |
| 2461 | xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n"); |
| 2462 | goto cleanup; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2463 | default: |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 2464 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
Sarah Sharp | 5ad6a52 | 2009-11-11 10:28:40 -0800 | [diff] [blame] | 2465 | status = 0; |
| 2466 | break; |
| 2467 | } |
Mathias Nyman | 86cd740 | 2015-01-09 16:06:32 +0200 | [diff] [blame] | 2468 | xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n", |
| 2469 | trb_comp_code); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2470 | goto cleanup; |
| 2471 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2472 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2473 | do { |
| 2474 | /* This TRB should be in the TD at the head of this ring's |
| 2475 | * TD list. |
| 2476 | */ |
| 2477 | if (list_empty(&ep_ring->td_list)) { |
Sarah Sharp | a83d675 | 2013-03-18 10:19:51 -0700 | [diff] [blame] | 2478 | /* |
| 2479 | * A stopped endpoint may generate an extra completion |
| 2480 | * event if the device was suspended. Don't print |
| 2481 | * warnings. |
| 2482 | */ |
| 2483 | if (!(trb_comp_code == COMP_STOP || |
| 2484 | trb_comp_code == COMP_STOP_INVAL)) { |
| 2485 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
| 2486 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
| 2487 | ep_index); |
| 2488 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
| 2489 | (le32_to_cpu(event->flags) & |
| 2490 | TRB_TYPE_BITMASK)>>10); |
| 2491 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); |
| 2492 | } |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2493 | if (ep->skip) { |
| 2494 | ep->skip = false; |
| 2495 | xhci_dbg(xhci, "td_list is empty while skip " |
| 2496 | "flag set. Clear skip flag.\n"); |
| 2497 | } |
| 2498 | ret = 0; |
| 2499 | goto cleanup; |
| 2500 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2501 | |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2502 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
| 2503 | if (ep->skip && td_num == 0) { |
| 2504 | ep->skip = false; |
| 2505 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " |
| 2506 | "Clear skip flag.\n"); |
| 2507 | ret = 0; |
| 2508 | goto cleanup; |
| 2509 | } |
| 2510 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2511 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2512 | if (ep->skip) |
| 2513 | td_num--; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2514 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2515 | /* Is this a TRB in the currently executing TD? */ |
Hans de Goede | cffb9be | 2014-08-20 16:41:51 +0300 | [diff] [blame] | 2516 | event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
| 2517 | td->last_trb, event_dma, false); |
Alex He | e1cf486 | 2011-06-03 15:58:25 +0800 | [diff] [blame] | 2518 | |
| 2519 | /* |
| 2520 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE |
| 2521 | * is not in the current TD pointed by ep_ring->dequeue because |
| 2522 | * that the hardware dequeue pointer still at the previous TRB |
| 2523 | * of the current TD. The previous TRB maybe a Link TD or the |
| 2524 | * last TRB of the previous TD. The command completion handle |
| 2525 | * will take care the rest. |
| 2526 | */ |
Hans de Goede | 9a54886 | 2014-08-19 15:17:56 +0300 | [diff] [blame] | 2527 | if (!event_seg && (trb_comp_code == COMP_STOP || |
| 2528 | trb_comp_code == COMP_STOP_INVAL)) { |
Alex He | e1cf486 | 2011-06-03 15:58:25 +0800 | [diff] [blame] | 2529 | ret = 0; |
| 2530 | goto cleanup; |
| 2531 | } |
| 2532 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2533 | if (!event_seg) { |
| 2534 | if (!ep->skip || |
| 2535 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { |
Sarah Sharp | ad80833 | 2011-05-25 10:43:56 -0700 | [diff] [blame] | 2536 | /* Some host controllers give a spurious |
| 2537 | * successful event after a short transfer. |
| 2538 | * Ignore it. |
| 2539 | */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 2540 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
Sarah Sharp | ad80833 | 2011-05-25 10:43:56 -0700 | [diff] [blame] | 2541 | ep_ring->last_td_was_short) { |
| 2542 | ep_ring->last_td_was_short = false; |
| 2543 | ret = 0; |
| 2544 | goto cleanup; |
| 2545 | } |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2546 | /* HC is busted, give up! */ |
| 2547 | xhci_err(xhci, |
| 2548 | "ERROR Transfer event TRB DMA ptr not " |
Hans de Goede | cffb9be | 2014-08-20 16:41:51 +0300 | [diff] [blame] | 2549 | "part of current TD ep_index %d " |
| 2550 | "comp_code %u\n", ep_index, |
| 2551 | trb_comp_code); |
| 2552 | trb_in_td(xhci, ep_ring->deq_seg, |
| 2553 | ep_ring->dequeue, td->last_trb, |
| 2554 | event_dma, true); |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2555 | return -ESHUTDOWN; |
| 2556 | } |
| 2557 | |
| 2558 | ret = skip_isoc_td(xhci, td, event, ep, &status); |
| 2559 | goto cleanup; |
| 2560 | } |
Sarah Sharp | ad80833 | 2011-05-25 10:43:56 -0700 | [diff] [blame] | 2561 | if (trb_comp_code == COMP_SHORT_TX) |
| 2562 | ep_ring->last_td_was_short = true; |
| 2563 | else |
| 2564 | ep_ring->last_td_was_short = false; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2565 | |
| 2566 | if (ep->skip) { |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2567 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
| 2568 | ep->skip = false; |
| 2569 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2570 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2571 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
| 2572 | sizeof(*event_trb)]; |
| 2573 | /* |
| 2574 | * No-op TRB should not trigger interrupts. |
| 2575 | * If event_trb is a no-op TRB, it means the |
| 2576 | * corresponding TD has been cancelled. Just ignore |
| 2577 | * the TD. |
| 2578 | */ |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 2579 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2580 | xhci_dbg(xhci, |
| 2581 | "event_trb is a no-op TRB. Skip it\n"); |
| 2582 | goto cleanup; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2583 | } |
| 2584 | |
| 2585 | /* Now update the urb's actual_length and give back to |
| 2586 | * the core |
| 2587 | */ |
| 2588 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
| 2589 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, |
| 2590 | &status); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2591 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
| 2592 | ret = process_isoc_td(xhci, td, event_trb, event, ep, |
| 2593 | &status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2594 | else |
| 2595 | ret = process_bulk_intr_td(xhci, td, event_trb, event, |
| 2596 | ep, &status); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 2597 | |
| 2598 | cleanup: |
Mathias Nyman | 3b4739b | 2015-10-12 11:30:12 +0300 | [diff] [blame] | 2599 | |
| 2600 | |
| 2601 | handling_skipped_tds = ep->skip && |
| 2602 | trb_comp_code != COMP_MISSED_INT && |
| 2603 | trb_comp_code != COMP_PING_ERR; |
| 2604 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2605 | /* |
Mathias Nyman | 3b4739b | 2015-10-12 11:30:12 +0300 | [diff] [blame] | 2606 | * Do not update event ring dequeue pointer if we're in a loop |
| 2607 | * processing missed tds. |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 2608 | */ |
Mathias Nyman | 3b4739b | 2015-10-12 11:30:12 +0300 | [diff] [blame] | 2609 | if (!handling_skipped_tds) |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2610 | inc_deq(xhci, xhci->event_ring); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2611 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2612 | if (ret) { |
| 2613 | urb = td->urb; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2614 | urb_priv = urb->hcpriv; |
Mathias Nyman | 8e71a32 | 2014-11-18 11:27:12 +0200 | [diff] [blame] | 2615 | |
Lin Wang | 4daf9df | 2015-01-09 16:06:31 +0200 | [diff] [blame] | 2616 | xhci_urb_free_priv(urb_priv); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2617 | |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 2618 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
Sarah Sharp | f444ff2 | 2011-04-05 15:53:47 -0700 | [diff] [blame] | 2619 | if ((urb->actual_length != urb->transfer_buffer_length && |
| 2620 | (urb->transfer_flags & |
| 2621 | URB_SHORT_NOT_OK)) || |
Sarah Sharp | fd984d2 | 2011-09-02 11:05:56 -0700 | [diff] [blame] | 2622 | (status != 0 && |
| 2623 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 2624 | xhci_dbg(xhci, "Giveback URB %pK, len = %d, " |
Alan Stern | 1949f9e | 2012-05-07 13:22:52 -0400 | [diff] [blame] | 2625 | "expected = %d, status = %d\n", |
Sarah Sharp | f444ff2 | 2011-04-05 15:53:47 -0700 | [diff] [blame] | 2626 | urb, urb->actual_length, |
| 2627 | urb->transfer_buffer_length, |
| 2628 | status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2629 | spin_unlock(&xhci->lock); |
Sarah Sharp | b3df3f9 | 2011-06-15 19:57:46 -0700 | [diff] [blame] | 2630 | /* EHCI, UHCI, and OHCI always unconditionally set the |
| 2631 | * urb->status of an isochronous endpoint to 0. |
| 2632 | */ |
| 2633 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) |
| 2634 | status = 0; |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 2635 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2636 | spin_lock(&xhci->lock); |
| 2637 | } |
| 2638 | |
| 2639 | /* |
| 2640 | * If ep->skip is set, it means there are missed tds on the |
| 2641 | * endpoint ring need to take care of. |
| 2642 | * Process them as short transfer until reach the td pointed by |
| 2643 | * the event. |
| 2644 | */ |
Mathias Nyman | 3b4739b | 2015-10-12 11:30:12 +0300 | [diff] [blame] | 2645 | } while (handling_skipped_tds); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2646 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2647 | return 0; |
| 2648 | } |
| 2649 | |
| 2650 | /* |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2651 | * This function handles all OS-owned events on the event ring. It may drop |
| 2652 | * xhci->lock between event processing (e.g. to pass up port status changes). |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2653 | * Returns >0 for "possibly more events to process" (caller should call again), |
| 2654 | * otherwise 0 if done. In future, <0 returns should indicate error code. |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2655 | */ |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2656 | static int xhci_handle_event(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2657 | { |
| 2658 | union xhci_trb *event; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2659 | int update_ptrs = 1; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2660 | int ret; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2661 | |
| 2662 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
| 2663 | xhci->error_bitmask |= 1 << 1; |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2664 | return 0; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2665 | } |
| 2666 | |
| 2667 | event = xhci->event_ring->dequeue; |
| 2668 | /* Does the HC or OS own the TRB? */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2669 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
| 2670 | xhci->event_ring->cycle_state) { |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2671 | xhci->error_bitmask |= 1 << 2; |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2672 | return 0; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2673 | } |
| 2674 | |
Matt Evans | 92a3da4 | 2011-03-29 13:40:51 +1100 | [diff] [blame] | 2675 | /* |
| 2676 | * Barrier between reading the TRB_CYCLE (valid) flag above and any |
| 2677 | * speculative reads of the event's flags/data below. |
| 2678 | */ |
| 2679 | rmb(); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2680 | /* FIXME: Handle more event types. */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2681 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2682 | case TRB_TYPE(TRB_COMPLETION): |
| 2683 | handle_cmd_completion(xhci, &event->event_cmd); |
| 2684 | break; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2685 | case TRB_TYPE(TRB_PORT_STATUS): |
| 2686 | handle_port_status(xhci, event); |
| 2687 | update_ptrs = 0; |
| 2688 | break; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2689 | case TRB_TYPE(TRB_TRANSFER): |
| 2690 | ret = handle_tx_event(xhci, &event->trans_event); |
| 2691 | if (ret < 0) |
| 2692 | xhci->error_bitmask |= 1 << 9; |
| 2693 | else |
| 2694 | update_ptrs = 0; |
| 2695 | break; |
Sarah Sharp | 623bef9 | 2011-11-11 14:57:33 -0800 | [diff] [blame] | 2696 | case TRB_TYPE(TRB_DEV_NOTE): |
| 2697 | handle_device_notification(xhci, event); |
| 2698 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2699 | default: |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2700 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
| 2701 | TRB_TYPE(48)) |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 2702 | handle_vendor_event(xhci, event); |
| 2703 | else |
| 2704 | xhci->error_bitmask |= 1 << 3; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2705 | } |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 2706 | /* Any of the above functions may drop and re-acquire the lock, so check |
| 2707 | * to make sure a watchdog timer didn't mark the host as non-responsive. |
| 2708 | */ |
| 2709 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
| 2710 | xhci_dbg(xhci, "xHCI host dying, returning from " |
| 2711 | "event handler.\n"); |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2712 | return 0; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 2713 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2714 | |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2715 | if (update_ptrs) |
| 2716 | /* Update SW event ring dequeue pointer */ |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2717 | inc_deq(xhci, xhci->event_ring); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2718 | |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2719 | /* Are there more items on the event ring? Caller will call us again to |
| 2720 | * check. |
| 2721 | */ |
| 2722 | return 1; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2723 | } |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2724 | |
| 2725 | /* |
| 2726 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, |
| 2727 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of |
| 2728 | * indicators of an event TRB error, but we check the status *first* to be safe. |
| 2729 | */ |
| 2730 | irqreturn_t xhci_irq(struct usb_hcd *hcd) |
| 2731 | { |
| 2732 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2733 | u32 status; |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2734 | u64 temp_64; |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2735 | union xhci_trb *event_ring_deq; |
| 2736 | dma_addr_t deq; |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2737 | |
| 2738 | spin_lock(&xhci->lock); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2739 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
Xenia Ragiadakou | b0ba972 | 2013-11-15 05:34:06 +0200 | [diff] [blame] | 2740 | status = readl(&xhci->op_regs->status); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2741 | if (status == 0xffffffff) |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2742 | goto hw_died; |
| 2743 | |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2744 | if (!(status & STS_EINT)) { |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2745 | spin_unlock(&xhci->lock); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2746 | return IRQ_NONE; |
| 2747 | } |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2748 | if (status & STS_FATAL) { |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2749 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
| 2750 | xhci_halt(xhci); |
| 2751 | hw_died: |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2752 | spin_unlock(&xhci->lock); |
Joe Lawrence | 948fa13 | 2015-04-30 17:16:04 +0300 | [diff] [blame] | 2753 | return IRQ_HANDLED; |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2754 | } |
| 2755 | |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2756 | /* |
| 2757 | * Clear the op reg interrupt status first, |
| 2758 | * so we can receive interrupts from other MSI-X interrupters. |
| 2759 | * Write 1 to clear the interrupt status. |
| 2760 | */ |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2761 | status |= STS_EINT; |
Xenia Ragiadakou | 204b779 | 2013-11-15 05:34:07 +0200 | [diff] [blame] | 2762 | writel(status, &xhci->op_regs->status); |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2763 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
| 2764 | /* Clear the MSI-X event interrupt status */ |
| 2765 | |
Felipe Balbi | cd70469 | 2012-02-29 16:46:23 +0200 | [diff] [blame] | 2766 | if (hcd->irq) { |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2767 | u32 irq_pending; |
| 2768 | /* Acknowledge the PCI interrupt */ |
Xenia Ragiadakou | b0ba972 | 2013-11-15 05:34:06 +0200 | [diff] [blame] | 2769 | irq_pending = readl(&xhci->ir_set->irq_pending); |
Felipe Balbi | 4e833c0 | 2012-03-15 16:37:08 +0200 | [diff] [blame] | 2770 | irq_pending |= IMAN_IP; |
Xenia Ragiadakou | 204b779 | 2013-11-15 05:34:07 +0200 | [diff] [blame] | 2771 | writel(irq_pending, &xhci->ir_set->irq_pending); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2772 | } |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2773 | |
Gabriel Krisman Bertazi | 27a41a8 | 2016-06-01 18:09:07 +0300 | [diff] [blame] | 2774 | if (xhci->xhc_state & XHCI_STATE_DYING || |
| 2775 | xhci->xhc_state & XHCI_STATE_HALTED) { |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2776 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
| 2777 | "Shouldn't IRQs be disabled?\n"); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2778 | /* Clear the event handler busy flag (RW1C); |
| 2779 | * the event ring should be empty. |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2780 | */ |
Sarah Sharp | f7b2e40 | 2014-01-30 13:27:49 -0800 | [diff] [blame] | 2781 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
Sarah Sharp | 477632d | 2014-01-29 14:02:00 -0800 | [diff] [blame] | 2782 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
| 2783 | &xhci->ir_set->erst_dequeue); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2784 | spin_unlock(&xhci->lock); |
| 2785 | |
| 2786 | return IRQ_HANDLED; |
| 2787 | } |
| 2788 | |
| 2789 | event_ring_deq = xhci->event_ring->dequeue; |
| 2790 | /* FIXME this should be a delayed service routine |
| 2791 | * that clears the EHB. |
| 2792 | */ |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2793 | while (xhci_handle_event(xhci) > 0) {} |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2794 | |
Sarah Sharp | f7b2e40 | 2014-01-30 13:27:49 -0800 | [diff] [blame] | 2795 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2796 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
| 2797 | if (event_ring_deq != xhci->event_ring->dequeue) { |
| 2798 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, |
| 2799 | xhci->event_ring->dequeue); |
| 2800 | if (deq == 0) |
| 2801 | xhci_warn(xhci, "WARN something wrong with SW event " |
| 2802 | "ring dequeue ptr.\n"); |
| 2803 | /* Update HC event ring dequeue pointer */ |
| 2804 | temp_64 &= ERST_PTR_MASK; |
| 2805 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); |
| 2806 | } |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2807 | |
| 2808 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2809 | temp_64 |= ERST_EHB; |
Sarah Sharp | 477632d | 2014-01-29 14:02:00 -0800 | [diff] [blame] | 2810 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2811 | |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2812 | spin_unlock(&xhci->lock); |
| 2813 | |
| 2814 | return IRQ_HANDLED; |
| 2815 | } |
| 2816 | |
Alex Shi | 851ec16 | 2013-05-24 10:54:19 +0800 | [diff] [blame] | 2817 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2818 | { |
Alan Stern | 968b822 | 2011-11-03 12:03:38 -0400 | [diff] [blame] | 2819 | return xhci_irq(hcd); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2820 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2821 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2822 | /**** Endpoint Ring Operations ****/ |
| 2823 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2824 | /* |
| 2825 | * Generic function for queueing a TRB on a ring. |
| 2826 | * The caller must have checked to make sure there's room on the ring. |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2827 | * |
| 2828 | * @more_trbs_coming: Will you enqueue more TRBs before calling |
| 2829 | * prepare_transfer()? |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2830 | */ |
| 2831 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2832 | bool more_trbs_coming, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2833 | u32 field1, u32 field2, u32 field3, u32 field4) |
| 2834 | { |
| 2835 | struct xhci_generic_trb *trb; |
| 2836 | |
| 2837 | trb = &ring->enqueue->generic; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2838 | trb->field[0] = cpu_to_le32(field1); |
| 2839 | trb->field[1] = cpu_to_le32(field2); |
| 2840 | trb->field[2] = cpu_to_le32(field3); |
| 2841 | trb->field[3] = cpu_to_le32(field4); |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2842 | inc_enq(xhci, ring, more_trbs_coming); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2843 | } |
| 2844 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2845 | /* |
| 2846 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. |
| 2847 | * FIXME allocate segments if the ring is full. |
| 2848 | */ |
| 2849 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2850 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2851 | { |
Andiry Xu | 8dfec61 | 2012-03-05 17:49:37 +0800 | [diff] [blame] | 2852 | unsigned int num_trbs_needed; |
| 2853 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2854 | /* Make sure the endpoint has been added to xHC schedule */ |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2855 | switch (ep_state) { |
| 2856 | case EP_STATE_DISABLED: |
| 2857 | /* |
| 2858 | * USB core changed config/interfaces without notifying us, |
| 2859 | * or hardware is reporting the wrong state. |
| 2860 | */ |
| 2861 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); |
| 2862 | return -ENOENT; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2863 | case EP_STATE_ERROR: |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 2864 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2865 | /* FIXME event handling code for error needs to clear it */ |
| 2866 | /* XXX not sure if this should be -ENOENT or not */ |
| 2867 | return -EINVAL; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 2868 | case EP_STATE_HALTED: |
| 2869 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2870 | case EP_STATE_STOPPED: |
| 2871 | case EP_STATE_RUNNING: |
| 2872 | break; |
| 2873 | default: |
| 2874 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); |
| 2875 | /* |
| 2876 | * FIXME issue Configure Endpoint command to try to get the HC |
| 2877 | * back into a known state. |
| 2878 | */ |
| 2879 | return -EINVAL; |
| 2880 | } |
Andiry Xu | 8dfec61 | 2012-03-05 17:49:37 +0800 | [diff] [blame] | 2881 | |
| 2882 | while (1) { |
Sarah Sharp | 3d4b81e | 2014-01-31 11:52:57 -0800 | [diff] [blame] | 2883 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
| 2884 | break; |
Andiry Xu | 8dfec61 | 2012-03-05 17:49:37 +0800 | [diff] [blame] | 2885 | |
| 2886 | if (ep_ring == xhci->cmd_ring) { |
| 2887 | xhci_err(xhci, "Do not support expand command ring\n"); |
| 2888 | return -ENOMEM; |
| 2889 | } |
| 2890 | |
Xenia Ragiadakou | 68ffb01 | 2013-08-14 06:33:56 +0300 | [diff] [blame] | 2891 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
| 2892 | "ERROR no room on ep ring, try ring expansion"); |
Andiry Xu | 8dfec61 | 2012-03-05 17:49:37 +0800 | [diff] [blame] | 2893 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
| 2894 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, |
| 2895 | mem_flags)) { |
| 2896 | xhci_err(xhci, "Ring expansion failed\n"); |
| 2897 | return -ENOMEM; |
| 2898 | } |
Peter Senna Tschudin | 261fa12 | 2012-09-12 19:03:17 +0200 | [diff] [blame] | 2899 | } |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2900 | |
Mathias Nyman | d0c77d8 | 2016-06-21 10:58:07 +0300 | [diff] [blame] | 2901 | while (trb_is_link(ep_ring->enqueue)) { |
| 2902 | /* If we're not dealing with 0.95 hardware or isoc rings |
| 2903 | * on AMD 0.96 host, clear the chain bit. |
| 2904 | */ |
| 2905 | if (!xhci_link_trb_quirk(xhci) && |
| 2906 | !(ep_ring->type == TYPE_ISOC && |
| 2907 | (xhci->quirks & XHCI_AMD_0x96_HOST))) |
| 2908 | ep_ring->enqueue->link.control &= |
| 2909 | cpu_to_le32(~TRB_CHAIN); |
| 2910 | else |
| 2911 | ep_ring->enqueue->link.control |= |
| 2912 | cpu_to_le32(TRB_CHAIN); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2913 | |
Mathias Nyman | d0c77d8 | 2016-06-21 10:58:07 +0300 | [diff] [blame] | 2914 | wmb(); |
| 2915 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2916 | |
Mathias Nyman | d0c77d8 | 2016-06-21 10:58:07 +0300 | [diff] [blame] | 2917 | /* Toggle the cycle bit after the last ring segment. */ |
| 2918 | if (link_trb_toggles_cycle(ep_ring->enqueue)) |
| 2919 | ep_ring->cycle_state ^= 1; |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2920 | |
Mathias Nyman | d0c77d8 | 2016-06-21 10:58:07 +0300 | [diff] [blame] | 2921 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
| 2922 | ep_ring->enqueue = ep_ring->enq_seg->trbs; |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2923 | } |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2924 | return 0; |
| 2925 | } |
| 2926 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2927 | static int prepare_transfer(struct xhci_hcd *xhci, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2928 | struct xhci_virt_device *xdev, |
| 2929 | unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2930 | unsigned int stream_id, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2931 | unsigned int num_trbs, |
| 2932 | struct urb *urb, |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2933 | unsigned int td_index, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2934 | gfp_t mem_flags) |
| 2935 | { |
| 2936 | int ret; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2937 | struct urb_priv *urb_priv; |
| 2938 | struct xhci_td *td; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2939 | struct xhci_ring *ep_ring; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 2940 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2941 | |
| 2942 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); |
| 2943 | if (!ep_ring) { |
| 2944 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", |
| 2945 | stream_id); |
| 2946 | return -EINVAL; |
| 2947 | } |
| 2948 | |
| 2949 | ret = prepare_ring(xhci, ep_ring, |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2950 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 2951 | num_trbs, mem_flags); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2952 | if (ret) |
| 2953 | return ret; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2954 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2955 | urb_priv = urb->hcpriv; |
| 2956 | td = urb_priv->td[td_index]; |
| 2957 | |
| 2958 | INIT_LIST_HEAD(&td->td_list); |
| 2959 | INIT_LIST_HEAD(&td->cancelled_td_list); |
| 2960 | |
| 2961 | if (td_index == 0) { |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 2962 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
Sarah Sharp | d13565c | 2011-07-22 14:34:34 -0700 | [diff] [blame] | 2963 | if (unlikely(ret)) |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2964 | return ret; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2965 | } |
| 2966 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2967 | td->urb = urb; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2968 | /* Add this TD to the tail of the endpoint ring's TD list */ |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2969 | list_add_tail(&td->td_list, &ep_ring->td_list); |
| 2970 | td->start_seg = ep_ring->enq_seg; |
| 2971 | td->first_trb = ep_ring->enqueue; |
| 2972 | |
| 2973 | urb_priv->td[td_index] = td; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2974 | |
| 2975 | return 0; |
| 2976 | } |
| 2977 | |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 2978 | static unsigned int count_trbs(u64 addr, u64 len) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2979 | { |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 2980 | unsigned int num_trbs; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2981 | |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 2982 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
| 2983 | TRB_MAX_BUFF_SIZE); |
| 2984 | if (num_trbs == 0) |
| 2985 | num_trbs++; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2986 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2987 | return num_trbs; |
| 2988 | } |
| 2989 | |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 2990 | static inline unsigned int count_trbs_needed(struct urb *urb) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2991 | { |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 2992 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); |
| 2993 | } |
| 2994 | |
| 2995 | static unsigned int count_sg_trbs_needed(struct urb *urb) |
| 2996 | { |
| 2997 | struct scatterlist *sg; |
| 2998 | unsigned int i, len, full_len, num_trbs = 0; |
| 2999 | |
| 3000 | full_len = urb->transfer_buffer_length; |
| 3001 | |
| 3002 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
| 3003 | len = sg_dma_len(sg); |
| 3004 | num_trbs += count_trbs(sg_dma_address(sg), len); |
| 3005 | len = min_t(unsigned int, len, full_len); |
| 3006 | full_len -= len; |
| 3007 | if (full_len == 0) |
| 3008 | break; |
| 3009 | } |
| 3010 | |
| 3011 | return num_trbs; |
| 3012 | } |
| 3013 | |
| 3014 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
| 3015 | { |
| 3016 | u64 addr, len; |
| 3017 | |
| 3018 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); |
| 3019 | len = urb->iso_frame_desc[i].length; |
| 3020 | |
| 3021 | return count_trbs(addr, len); |
| 3022 | } |
| 3023 | |
| 3024 | static void check_trb_math(struct urb *urb, int running_total) |
| 3025 | { |
| 3026 | if (unlikely(running_total != urb->transfer_buffer_length)) |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 3027 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 3028 | "queued %#x (%d), asked for %#x (%d)\n", |
| 3029 | __func__, |
| 3030 | urb->ep->desc.bEndpointAddress, |
| 3031 | running_total, running_total, |
| 3032 | urb->transfer_buffer_length, |
| 3033 | urb->transfer_buffer_length); |
| 3034 | } |
| 3035 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3036 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3037 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 3038 | struct xhci_generic_trb *start_trb) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 3039 | { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 3040 | /* |
| 3041 | * Pass all the TRBs to the hardware at once and make sure this write |
| 3042 | * isn't reordered. |
| 3043 | */ |
| 3044 | wmb(); |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3045 | if (start_cycle) |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3046 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3047 | else |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3048 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 3049 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 3050 | } |
| 3051 | |
Alexandr Ivanov | 7814015 | 2016-04-22 13:17:11 +0300 | [diff] [blame] | 3052 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
| 3053 | struct xhci_ep_ctx *ep_ctx) |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3054 | { |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3055 | int xhci_interval; |
| 3056 | int ep_interval; |
| 3057 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3058 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3059 | ep_interval = urb->interval; |
Alexandr Ivanov | 7814015 | 2016-04-22 13:17:11 +0300 | [diff] [blame] | 3060 | |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3061 | /* Convert to microframes */ |
| 3062 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3063 | urb->dev->speed == USB_SPEED_FULL) |
| 3064 | ep_interval *= 8; |
Alexandr Ivanov | 7814015 | 2016-04-22 13:17:11 +0300 | [diff] [blame] | 3065 | |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3066 | /* FIXME change this to a warning and a suggestion to use the new API |
| 3067 | * to set the polling interval (once the API is added). |
| 3068 | */ |
| 3069 | if (xhci_interval != ep_interval) { |
Dmitry Kasatkin | 0730d52 | 2013-08-27 17:47:35 +0300 | [diff] [blame] | 3070 | dev_dbg_ratelimited(&urb->dev->dev, |
| 3071 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", |
| 3072 | ep_interval, ep_interval == 1 ? "" : "s", |
| 3073 | xhci_interval, xhci_interval == 1 ? "" : "s"); |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3074 | urb->interval = xhci_interval; |
| 3075 | /* Convert back to frames for LS/FS devices */ |
| 3076 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3077 | urb->dev->speed == USB_SPEED_FULL) |
| 3078 | urb->interval /= 8; |
| 3079 | } |
Alexandr Ivanov | 7814015 | 2016-04-22 13:17:11 +0300 | [diff] [blame] | 3080 | } |
| 3081 | |
| 3082 | /* |
| 3083 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt |
| 3084 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD |
| 3085 | * (comprised of sg list entries) can take several service intervals to |
| 3086 | * transmit. |
| 3087 | */ |
| 3088 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 3089 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3090 | { |
| 3091 | struct xhci_ep_ctx *ep_ctx; |
| 3092 | |
| 3093 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); |
| 3094 | check_interval(xhci, urb, ep_ctx); |
| 3095 | |
Dan Carpenter | 3fc8206 | 2012-03-28 10:30:26 +0300 | [diff] [blame] | 3096 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 3097 | } |
| 3098 | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 3099 | /* |
Sarah Sharp | 4525c0a | 2012-10-25 15:56:40 -0700 | [diff] [blame] | 3100 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
| 3101 | * packets remaining in the TD (*not* including this TRB). |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3102 | * |
| 3103 | * Total TD packet count = total_packet_count = |
Sarah Sharp | 4525c0a | 2012-10-25 15:56:40 -0700 | [diff] [blame] | 3104 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3105 | * |
| 3106 | * Packets transferred up to and including this TRB = packets_transferred = |
| 3107 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) |
| 3108 | * |
| 3109 | * TD size = total_packet_count - packets_transferred |
| 3110 | * |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3111 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
| 3112 | * including this TRB, right shifted by 10 |
| 3113 | * |
| 3114 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. |
| 3115 | * This is taken care of in the TRB_TD_SIZE() macro |
| 3116 | * |
Sarah Sharp | 4525c0a | 2012-10-25 15:56:40 -0700 | [diff] [blame] | 3117 | * The last TRB in a TD must have the TD size set to zero. |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3118 | */ |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3119 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
| 3120 | int trb_buff_len, unsigned int td_total_len, |
Mathias Nyman | 124c393 | 2016-06-21 10:57:59 +0300 | [diff] [blame] | 3121 | struct urb *urb, bool more_trbs_coming) |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3122 | { |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3123 | u32 maxp, total_packet_count; |
| 3124 | |
Chunfeng Yun | cdfe4c0 | 2017-12-08 18:10:06 +0200 | [diff] [blame] | 3125 | /* MTK xHCI 0.96 contains some features from 1.0 */ |
Chunfeng Yun | 0cbd4b3 | 2015-11-24 13:09:55 +0200 | [diff] [blame] | 3126 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3127 | return ((td_total_len - transferred) >> 10); |
| 3128 | |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 3129 | /* One TRB with a zero-length data packet. */ |
Mathias Nyman | 124c393 | 2016-06-21 10:57:59 +0300 | [diff] [blame] | 3130 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3131 | trb_buff_len == td_total_len) |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 3132 | return 0; |
| 3133 | |
Chunfeng Yun | cdfe4c0 | 2017-12-08 18:10:06 +0200 | [diff] [blame] | 3134 | /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ |
| 3135 | if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) |
Chunfeng Yun | 0cbd4b3 | 2015-11-24 13:09:55 +0200 | [diff] [blame] | 3136 | trb_buff_len = 0; |
| 3137 | |
| 3138 | maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
| 3139 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
| 3140 | |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3141 | /* Queueing functions don't count the current TRB into transferred */ |
| 3142 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3143 | } |
| 3144 | |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3145 | |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3146 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3147 | u32 *trb_buff_len, struct xhci_segment *seg) |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3148 | { |
Jack Pham | f556be0 | 2017-04-04 16:12:31 -0700 | [diff] [blame] | 3149 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3150 | unsigned int unalign; |
| 3151 | unsigned int max_pkt; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3152 | u32 new_buff_len; |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3153 | |
| 3154 | max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
| 3155 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
| 3156 | |
| 3157 | /* we got lucky, last normal TRB data on segment is packet aligned */ |
| 3158 | if (unalign == 0) |
| 3159 | return 0; |
| 3160 | |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3161 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
| 3162 | unalign, *trb_buff_len); |
| 3163 | |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3164 | /* is the last nornal TRB alignable by splitting it */ |
| 3165 | if (*trb_buff_len > unalign) { |
| 3166 | *trb_buff_len -= unalign; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3167 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3168 | return 0; |
| 3169 | } |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3170 | |
| 3171 | /* |
| 3172 | * We want enqd_len + trb_buff_len to sum up to a number aligned to |
| 3173 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: |
| 3174 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. |
| 3175 | */ |
| 3176 | new_buff_len = max_pkt - (enqd_len % max_pkt); |
| 3177 | |
| 3178 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) |
| 3179 | new_buff_len = (urb->transfer_buffer_length - enqd_len); |
| 3180 | |
| 3181 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ |
| 3182 | if (usb_urb_dir_out(urb)) { |
| 3183 | sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, |
| 3184 | seg->bounce_buf, new_buff_len, enqd_len); |
| 3185 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, |
| 3186 | max_pkt, DMA_TO_DEVICE); |
| 3187 | } else { |
| 3188 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, |
| 3189 | max_pkt, DMA_FROM_DEVICE); |
| 3190 | } |
| 3191 | |
| 3192 | if (dma_mapping_error(dev, seg->bounce_dma)) { |
| 3193 | /* try without aligning. Some host controllers survive */ |
| 3194 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); |
| 3195 | return 0; |
| 3196 | } |
| 3197 | *trb_buff_len = new_buff_len; |
| 3198 | seg->bounce_len = new_buff_len; |
| 3199 | seg->bounce_offs = enqd_len; |
| 3200 | |
| 3201 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); |
| 3202 | |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3203 | return 1; |
| 3204 | } |
| 3205 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3206 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3207 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3208 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3209 | { |
Mathias Nyman | 5a5a0b1 | 2016-06-21 10:57:57 +0300 | [diff] [blame] | 3210 | struct xhci_ring *ring; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3211 | struct urb_priv *urb_priv; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3212 | struct xhci_td *td; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3213 | struct xhci_generic_trb *start_trb; |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3214 | struct scatterlist *sg = NULL; |
Mathias Nyman | 5a83f04 | 2016-06-21 10:57:58 +0300 | [diff] [blame] | 3215 | bool more_trbs_coming = true; |
| 3216 | bool need_zero_pkt = false; |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3217 | bool first_trb = true; |
| 3218 | unsigned int num_trbs; |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3219 | unsigned int start_cycle, num_sgs = 0; |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3220 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3221 | int sent_len, ret; |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3222 | u32 field, length_field, remainder; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3223 | u64 addr, send_addr; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3224 | |
Mathias Nyman | 5a5a0b1 | 2016-06-21 10:57:57 +0300 | [diff] [blame] | 3225 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 3226 | if (!ring) |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3227 | return -EINVAL; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3228 | |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3229 | full_len = urb->transfer_buffer_length; |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3230 | /* If we have scatter/gather list, we use it. */ |
| 3231 | if (urb->num_sgs) { |
| 3232 | num_sgs = urb->num_mapped_sgs; |
| 3233 | sg = urb->sg; |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3234 | addr = (u64) sg_dma_address(sg); |
| 3235 | block_len = sg_dma_len(sg); |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3236 | num_trbs = count_sg_trbs_needed(urb); |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3237 | } else { |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3238 | num_trbs = count_trbs_needed(urb); |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3239 | addr = (u64) urb->transfer_dma; |
| 3240 | block_len = full_len; |
| 3241 | } |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3242 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 3243 | ep_index, urb->stream_id, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3244 | num_trbs, urb, 0, mem_flags); |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3245 | if (unlikely(ret < 0)) |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3246 | return ret; |
| 3247 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3248 | urb_priv = urb->hcpriv; |
Reyad Attiyat | 4758dcd | 2015-08-06 19:23:58 +0300 | [diff] [blame] | 3249 | |
| 3250 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ |
Mathias Nyman | 5a83f04 | 2016-06-21 10:57:58 +0300 | [diff] [blame] | 3251 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1) |
| 3252 | need_zero_pkt = true; |
Reyad Attiyat | 4758dcd | 2015-08-06 19:23:58 +0300 | [diff] [blame] | 3253 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3254 | td = urb_priv->td[0]; |
| 3255 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3256 | /* |
| 3257 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 3258 | * until we've finished creating all the other TRBs. The ring's cycle |
| 3259 | * state may change as we enqueue the other TRBs, so save it too. |
| 3260 | */ |
Mathias Nyman | 5a5a0b1 | 2016-06-21 10:57:57 +0300 | [diff] [blame] | 3261 | start_trb = &ring->enqueue->generic; |
| 3262 | start_cycle = ring->cycle_state; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3263 | send_addr = addr; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3264 | |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3265 | /* Queue the TRBs, even if they are zero-length */ |
Alban Browaeys | 0d2daad | 2016-08-16 10:18:04 +0300 | [diff] [blame] | 3266 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
| 3267 | enqd_len += trb_buff_len) { |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3268 | field = TRB_TYPE(TRB_NORMAL); |
| 3269 | |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3270 | /* TRB buffer should not cross 64KB boundaries */ |
| 3271 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
| 3272 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3273 | |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3274 | if (enqd_len + trb_buff_len > full_len) |
| 3275 | trb_buff_len = full_len - enqd_len; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3276 | |
| 3277 | /* Don't change the cycle bit of the first TRB until later */ |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3278 | if (first_trb) { |
| 3279 | first_trb = false; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3280 | if (start_cycle == 0) |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3281 | field |= TRB_CYCLE; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3282 | } else |
Mathias Nyman | 5a5a0b1 | 2016-06-21 10:57:57 +0300 | [diff] [blame] | 3283 | field |= ring->cycle_state; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3284 | |
| 3285 | /* Chain all the TRBs together; clear the chain bit in the last |
| 3286 | * TRB to indicate it's the last TRB in the chain. |
| 3287 | */ |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3288 | if (enqd_len + trb_buff_len < full_len) { |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3289 | field |= TRB_CHAIN; |
Mathias Nyman | 2d98ef4 | 2016-06-21 10:58:04 +0300 | [diff] [blame] | 3290 | if (trb_is_link(ring->enqueue + 1)) { |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3291 | if (xhci_align_td(xhci, urb, enqd_len, |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3292 | &trb_buff_len, |
| 3293 | ring->enq_seg)) { |
| 3294 | send_addr = ring->enq_seg->bounce_dma; |
| 3295 | /* assuming TD won't span 2 segs */ |
| 3296 | td->bounce_seg = ring->enq_seg; |
| 3297 | } |
Mathias Nyman | 474ed23 | 2016-06-21 10:58:01 +0300 | [diff] [blame] | 3298 | } |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3299 | } |
| 3300 | if (enqd_len + trb_buff_len >= full_len) { |
| 3301 | field &= ~TRB_CHAIN; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3302 | field |= TRB_IOC; |
Mathias Nyman | 124c393 | 2016-06-21 10:57:59 +0300 | [diff] [blame] | 3303 | more_trbs_coming = false; |
Mathias Nyman | 5a83f04 | 2016-06-21 10:57:58 +0300 | [diff] [blame] | 3304 | td->last_trb = ring->enqueue; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3305 | } |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3306 | |
| 3307 | /* Only set interrupt on short packet for IN endpoints */ |
| 3308 | if (usb_urb_dir_in(urb)) |
| 3309 | field |= TRB_ISP; |
| 3310 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3311 | /* Set the TRB length, TD size, and interrupter fields. */ |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3312 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
| 3313 | full_len, urb, more_trbs_coming); |
| 3314 | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3315 | length_field = TRB_LEN(trb_buff_len) | |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3316 | TRB_TD_SIZE(remainder) | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3317 | TRB_INTR_TARGET(0); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3318 | |
Mathias Nyman | 124c393 | 2016-06-21 10:57:59 +0300 | [diff] [blame] | 3319 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3320 | lower_32_bits(send_addr), |
| 3321 | upper_32_bits(send_addr), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3322 | length_field, |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3323 | field); |
| 3324 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3325 | addr += trb_buff_len; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3326 | sent_len = trb_buff_len; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3327 | |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3328 | while (sg && sent_len >= block_len) { |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3329 | /* New sg entry */ |
| 3330 | --num_sgs; |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3331 | sent_len -= block_len; |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3332 | if (num_sgs != 0) { |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3333 | sg = sg_next(sg); |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3334 | block_len = sg_dma_len(sg); |
| 3335 | addr = (u64) sg_dma_address(sg); |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3336 | addr += sent_len; |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3337 | } |
| 3338 | } |
Mathias Nyman | f9c589e | 2016-06-21 10:58:02 +0300 | [diff] [blame] | 3339 | block_len -= sent_len; |
| 3340 | send_addr = addr; |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3341 | } |
| 3342 | |
Mathias Nyman | 5a83f04 | 2016-06-21 10:57:58 +0300 | [diff] [blame] | 3343 | if (need_zero_pkt) { |
| 3344 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 3345 | ep_index, urb->stream_id, |
| 3346 | 1, urb, 1, mem_flags); |
| 3347 | urb_priv->td[1]->last_trb = ring->enqueue; |
| 3348 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
| 3349 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); |
| 3350 | } |
| 3351 | |
Mathias Nyman | 86065c2 | 2016-06-21 10:58:00 +0300 | [diff] [blame] | 3352 | check_trb_math(urb, enqd_len); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3353 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 3354 | start_cycle, start_trb); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 3355 | return 0; |
| 3356 | } |
| 3357 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3358 | /* Caller must have locked xhci->lock */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3359 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3360 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3361 | { |
| 3362 | struct xhci_ring *ep_ring; |
| 3363 | int num_trbs; |
| 3364 | int ret; |
| 3365 | struct usb_ctrlrequest *setup; |
| 3366 | struct xhci_generic_trb *start_trb; |
| 3367 | int start_cycle; |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3368 | u32 field, length_field, remainder; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3369 | struct urb_priv *urb_priv; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3370 | struct xhci_td *td; |
| 3371 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3372 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 3373 | if (!ep_ring) |
| 3374 | return -EINVAL; |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3375 | |
| 3376 | /* |
| 3377 | * Need to copy setup packet into setup TRB, so we can't use the setup |
| 3378 | * DMA address. |
| 3379 | */ |
| 3380 | if (!urb->setup_packet) |
| 3381 | return -EINVAL; |
| 3382 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3383 | /* 1 TRB for setup, 1 for status */ |
| 3384 | num_trbs = 2; |
| 3385 | /* |
| 3386 | * Don't need to check if we need additional event data and normal TRBs, |
| 3387 | * since data in control transfers will never get bigger than 16MB |
| 3388 | * XXX: can we get a buffer that crosses 64KB boundaries? |
| 3389 | */ |
| 3390 | if (urb->transfer_buffer_length > 0) |
| 3391 | num_trbs++; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3392 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 3393 | ep_index, urb->stream_id, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3394 | num_trbs, urb, 0, mem_flags); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3395 | if (ret < 0) |
| 3396 | return ret; |
| 3397 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3398 | urb_priv = urb->hcpriv; |
| 3399 | td = urb_priv->td[0]; |
| 3400 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3401 | /* |
| 3402 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 3403 | * until we've finished creating all the other TRBs. The ring's cycle |
| 3404 | * state may change as we enqueue the other TRBs, so save it too. |
| 3405 | */ |
| 3406 | start_trb = &ep_ring->enqueue->generic; |
| 3407 | start_cycle = ep_ring->cycle_state; |
| 3408 | |
| 3409 | /* Queue setup TRB - see section 6.4.1.2.1 */ |
| 3410 | /* FIXME better way to translate setup_packet into two u32 fields? */ |
| 3411 | setup = (struct usb_ctrlrequest *) urb->setup_packet; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3412 | field = 0; |
| 3413 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); |
| 3414 | if (start_cycle == 0) |
| 3415 | field |= 0x1; |
Andiry Xu | b83cdc8 | 2011-05-05 18:13:56 +0800 | [diff] [blame] | 3416 | |
Mathias Nyman | dca7794 | 2015-09-21 17:46:16 +0300 | [diff] [blame] | 3417 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
Chunfeng Yun | 0cbd4b3 | 2015-11-24 13:09:55 +0200 | [diff] [blame] | 3418 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
Andiry Xu | b83cdc8 | 2011-05-05 18:13:56 +0800 | [diff] [blame] | 3419 | if (urb->transfer_buffer_length > 0) { |
| 3420 | if (setup->bRequestType & USB_DIR_IN) |
| 3421 | field |= TRB_TX_TYPE(TRB_DATA_IN); |
| 3422 | else |
| 3423 | field |= TRB_TX_TYPE(TRB_DATA_OUT); |
| 3424 | } |
| 3425 | } |
| 3426 | |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3427 | queue_trb(xhci, ep_ring, true, |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3428 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
| 3429 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, |
| 3430 | TRB_LEN(8) | TRB_INTR_TARGET(0), |
| 3431 | /* Immediate data in pointer */ |
| 3432 | field); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3433 | |
| 3434 | /* If there's data, queue data TRBs */ |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3435 | /* Only set interrupt on short packet for IN endpoints */ |
| 3436 | if (usb_urb_dir_in(urb)) |
| 3437 | field = TRB_ISP | TRB_TYPE(TRB_DATA); |
| 3438 | else |
| 3439 | field = TRB_TYPE(TRB_DATA); |
| 3440 | |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3441 | remainder = xhci_td_remainder(xhci, 0, |
| 3442 | urb->transfer_buffer_length, |
| 3443 | urb->transfer_buffer_length, |
| 3444 | urb, 1); |
| 3445 | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3446 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3447 | TRB_TD_SIZE(remainder) | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3448 | TRB_INTR_TARGET(0); |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3449 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3450 | if (urb->transfer_buffer_length > 0) { |
| 3451 | if (setup->bRequestType & USB_DIR_IN) |
| 3452 | field |= TRB_DIR_IN; |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3453 | queue_trb(xhci, ep_ring, true, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3454 | lower_32_bits(urb->transfer_dma), |
| 3455 | upper_32_bits(urb->transfer_dma), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3456 | length_field, |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3457 | field | ep_ring->cycle_state); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3458 | } |
| 3459 | |
| 3460 | /* Save the DMA address of the last TRB in the TD */ |
| 3461 | td->last_trb = ep_ring->enqueue; |
| 3462 | |
| 3463 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ |
| 3464 | /* If the device sent data, the status stage is an OUT transfer */ |
| 3465 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) |
| 3466 | field = 0; |
| 3467 | else |
| 3468 | field = TRB_DIR_IN; |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3469 | queue_trb(xhci, ep_ring, false, |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3470 | 0, |
| 3471 | 0, |
| 3472 | TRB_INTR_TARGET(0), |
| 3473 | /* Event on completion */ |
| 3474 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); |
| 3475 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3476 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 3477 | start_cycle, start_trb); |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3478 | return 0; |
| 3479 | } |
| 3480 | |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3481 | /* |
Jack Pham | 32788c5 | 2013-06-20 13:31:37 -0700 | [diff] [blame] | 3482 | * Variant of xhci_queue_ctrl_tx() used to implement EHSET |
| 3483 | * SINGLE_STEP_SET_FEATURE test mode. It differs in that the control |
| 3484 | * transfer is broken up so that the SETUP stage can happen and call |
| 3485 | * the URB's completion handler before the DATA/STATUS stages are |
| 3486 | * executed by the xHC hardware. This assumes the control transfer is a |
| 3487 | * GetDescriptor, with a DATA stage in the IN direction, and an OUT |
| 3488 | * STATUS stage. |
| 3489 | * |
| 3490 | * This function is called twice, usually with a 15-second delay in between. |
| 3491 | * - with is_setup==true, the SETUP stage for the control request |
| 3492 | * (GetDescriptor) is queued in the TRB ring and sent to HW immediately |
| 3493 | * - with is_setup==false, the DATA and STATUS TRBs are queued and exceuted |
| 3494 | * |
| 3495 | * Caller must have locked xhci->lock |
| 3496 | */ |
| 3497 | int xhci_submit_single_step_set_feature(struct usb_hcd *hcd, struct urb *urb, |
| 3498 | int is_setup) |
| 3499 | { |
| 3500 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 3501 | struct xhci_ring *ep_ring; |
| 3502 | int num_trbs; |
| 3503 | int ret; |
| 3504 | unsigned int slot_id, ep_index; |
| 3505 | struct usb_ctrlrequest *setup; |
| 3506 | struct xhci_generic_trb *start_trb; |
| 3507 | int start_cycle; |
| 3508 | u32 field, length_field, remainder; |
| 3509 | struct urb_priv *urb_priv; |
| 3510 | struct xhci_td *td; |
| 3511 | |
| 3512 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 3513 | if (!ep_ring) |
| 3514 | return -EINVAL; |
| 3515 | |
| 3516 | /* Need buffer for data stage */ |
| 3517 | if (urb->transfer_buffer_length <= 0) |
| 3518 | return -EINVAL; |
| 3519 | |
| 3520 | /* |
| 3521 | * Need to copy setup packet into setup TRB, so we can't use the setup |
| 3522 | * DMA address. |
| 3523 | */ |
| 3524 | if (!urb->setup_packet) |
| 3525 | return -EINVAL; |
| 3526 | setup = (struct usb_ctrlrequest *) urb->setup_packet; |
| 3527 | |
| 3528 | slot_id = urb->dev->slot_id; |
| 3529 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); |
| 3530 | |
| 3531 | urb_priv = kzalloc(sizeof(struct urb_priv) + |
| 3532 | sizeof(struct xhci_td *), GFP_ATOMIC); |
| 3533 | if (!urb_priv) |
| 3534 | return -ENOMEM; |
| 3535 | |
| 3536 | td = urb_priv->td[0] = kzalloc(sizeof(struct xhci_td), GFP_ATOMIC); |
| 3537 | if (!td) { |
| 3538 | kfree(urb_priv); |
| 3539 | return -ENOMEM; |
| 3540 | } |
| 3541 | |
| 3542 | urb_priv->length = 1; |
| 3543 | urb_priv->td_cnt = 0; |
| 3544 | urb->hcpriv = urb_priv; |
| 3545 | |
| 3546 | num_trbs = is_setup ? 1 : 2; |
| 3547 | |
| 3548 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 3549 | ep_index, urb->stream_id, |
| 3550 | num_trbs, urb, 0, GFP_ATOMIC); |
| 3551 | if (ret < 0) { |
| 3552 | kfree(td); |
| 3553 | kfree(urb_priv); |
| 3554 | return ret; |
| 3555 | } |
| 3556 | |
| 3557 | /* |
| 3558 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 3559 | * until we've finished creating all the other TRBs. The ring's cycle |
| 3560 | * state may change as we enqueue the other TRBs, so save it too. |
| 3561 | */ |
| 3562 | start_trb = &ep_ring->enqueue->generic; |
| 3563 | start_cycle = ep_ring->cycle_state; |
| 3564 | |
| 3565 | if (is_setup) { |
| 3566 | /* Queue only the setup TRB */ |
| 3567 | field = TRB_IDT | TRB_IOC | TRB_TYPE(TRB_SETUP); |
| 3568 | if (start_cycle == 0) |
| 3569 | field |= 0x1; |
| 3570 | |
| 3571 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
| 3572 | if (xhci->hci_version >= 0x100) { |
| 3573 | if (setup->bRequestType & USB_DIR_IN) |
| 3574 | field |= TRB_TX_TYPE(TRB_DATA_IN); |
| 3575 | else |
| 3576 | field |= TRB_TX_TYPE(TRB_DATA_OUT); |
| 3577 | } |
| 3578 | |
| 3579 | /* Save the DMA address of the last TRB in the TD */ |
| 3580 | td->last_trb = ep_ring->enqueue; |
| 3581 | |
| 3582 | queue_trb(xhci, ep_ring, false, |
| 3583 | setup->bRequestType | setup->bRequest << 8 | |
| 3584 | le16_to_cpu(setup->wValue) << 16, |
| 3585 | le16_to_cpu(setup->wIndex) | |
| 3586 | le16_to_cpu(setup->wLength) << 16, |
| 3587 | TRB_LEN(8) | TRB_INTR_TARGET(0), |
| 3588 | field); |
| 3589 | } else { |
| 3590 | /* Queue data TRB */ |
| 3591 | field = TRB_ISP | TRB_TYPE(TRB_DATA); |
| 3592 | if (start_cycle == 0) |
| 3593 | field |= 0x1; |
| 3594 | if (setup->bRequestType & USB_DIR_IN) |
| 3595 | field |= TRB_DIR_IN; |
| 3596 | |
| 3597 | remainder = xhci_td_remainder(xhci, 0, |
| 3598 | urb->transfer_buffer_length, |
| 3599 | urb->transfer_buffer_length, |
| 3600 | urb, 1); |
| 3601 | |
| 3602 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
| 3603 | TRB_TD_SIZE(remainder) | |
| 3604 | TRB_INTR_TARGET(0); |
| 3605 | |
| 3606 | queue_trb(xhci, ep_ring, true, |
| 3607 | lower_32_bits(urb->transfer_dma), |
| 3608 | upper_32_bits(urb->transfer_dma), |
| 3609 | length_field, |
| 3610 | field); |
| 3611 | |
| 3612 | /* Save the DMA address of the last TRB in the TD */ |
| 3613 | td->last_trb = ep_ring->enqueue; |
| 3614 | |
| 3615 | /* Queue status TRB */ |
| 3616 | field = TRB_IOC | TRB_TYPE(TRB_STATUS); |
| 3617 | if (!(setup->bRequestType & USB_DIR_IN)) |
| 3618 | field |= TRB_DIR_IN; |
| 3619 | |
| 3620 | queue_trb(xhci, ep_ring, false, |
| 3621 | 0, |
| 3622 | 0, |
| 3623 | TRB_INTR_TARGET(0), |
| 3624 | field | ep_ring->cycle_state); |
| 3625 | } |
| 3626 | |
| 3627 | giveback_first_trb(xhci, slot_id, ep_index, 0, start_cycle, start_trb); |
| 3628 | return 0; |
| 3629 | } |
| 3630 | |
| 3631 | /* |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3632 | * The transfer burst count field of the isochronous TRB defines the number of |
| 3633 | * bursts that are required to move all packets in this TD. Only SuperSpeed |
| 3634 | * devices can burst up to bMaxBurst number of packets per service interval. |
| 3635 | * This field is zero based, meaning a value of zero in the field means one |
| 3636 | * burst. Basically, for everything but SuperSpeed devices, this field will be |
| 3637 | * zero. Only xHCI 1.0 host controllers support this field. |
| 3638 | */ |
| 3639 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3640 | struct urb *urb, unsigned int total_packet_count) |
| 3641 | { |
| 3642 | unsigned int max_burst; |
| 3643 | |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3644 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3645 | return 0; |
| 3646 | |
| 3647 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; |
Mathias Nyman | 3213b15 | 2014-06-24 17:14:41 +0300 | [diff] [blame] | 3648 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3649 | } |
| 3650 | |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3651 | /* |
| 3652 | * Returns the number of packets in the last "burst" of packets. This field is |
| 3653 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so |
| 3654 | * the last burst packet count is equal to the total number of packets in the |
| 3655 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst |
| 3656 | * must contain (bMaxBurst + 1) number of packets, but the last burst can |
| 3657 | * contain 1 to (bMaxBurst + 1) packets. |
| 3658 | */ |
| 3659 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3660 | struct urb *urb, unsigned int total_packet_count) |
| 3661 | { |
| 3662 | unsigned int max_burst; |
| 3663 | unsigned int residue; |
| 3664 | |
| 3665 | if (xhci->hci_version < 0x100) |
| 3666 | return 0; |
| 3667 | |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3668 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3669 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
| 3670 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; |
| 3671 | residue = total_packet_count % (max_burst + 1); |
| 3672 | /* If residue is zero, the last burst contains (max_burst + 1) |
| 3673 | * number of packets, but the TLBPC field is zero-based. |
| 3674 | */ |
| 3675 | if (residue == 0) |
| 3676 | return max_burst; |
| 3677 | return residue - 1; |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3678 | } |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3679 | if (total_packet_count == 0) |
| 3680 | return 0; |
| 3681 | return total_packet_count - 1; |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3682 | } |
| 3683 | |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3684 | /* |
| 3685 | * Calculates Frame ID field of the isochronous TRB identifies the |
| 3686 | * target frame that the Interval associated with this Isochronous |
| 3687 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. |
| 3688 | * |
| 3689 | * Returns actual frame id on success, negative value on error. |
| 3690 | */ |
| 3691 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, |
| 3692 | struct urb *urb, int index) |
| 3693 | { |
| 3694 | int start_frame, ist, ret = 0; |
| 3695 | int start_frame_id, end_frame_id, current_frame_id; |
| 3696 | |
| 3697 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3698 | urb->dev->speed == USB_SPEED_FULL) |
| 3699 | start_frame = urb->start_frame + index * urb->interval; |
| 3700 | else |
| 3701 | start_frame = (urb->start_frame + index * urb->interval) >> 3; |
| 3702 | |
| 3703 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): |
| 3704 | * |
| 3705 | * If bit [3] of IST is cleared to '0', software can add a TRB no |
| 3706 | * later than IST[2:0] Microframes before that TRB is scheduled to |
| 3707 | * be executed. |
| 3708 | * If bit [3] of IST is set to '1', software can add a TRB no later |
| 3709 | * than IST[2:0] Frames before that TRB is scheduled to be executed. |
| 3710 | */ |
| 3711 | ist = HCS_IST(xhci->hcs_params2) & 0x7; |
| 3712 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) |
| 3713 | ist <<= 3; |
| 3714 | |
| 3715 | /* Software shall not schedule an Isoch TD with a Frame ID value that |
| 3716 | * is less than the Start Frame ID or greater than the End Frame ID, |
| 3717 | * where: |
| 3718 | * |
| 3719 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 |
| 3720 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 |
| 3721 | * |
| 3722 | * Both the End Frame ID and Start Frame ID values are calculated |
| 3723 | * in microframes. When software determines the valid Frame ID value; |
| 3724 | * The End Frame ID value should be rounded down to the nearest Frame |
| 3725 | * boundary, and the Start Frame ID value should be rounded up to the |
| 3726 | * nearest Frame boundary. |
| 3727 | */ |
| 3728 | current_frame_id = readl(&xhci->run_regs->microframe_index); |
| 3729 | start_frame_id = roundup(current_frame_id + ist + 1, 8); |
| 3730 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); |
| 3731 | |
| 3732 | start_frame &= 0x7ff; |
| 3733 | start_frame_id = (start_frame_id >> 3) & 0x7ff; |
| 3734 | end_frame_id = (end_frame_id >> 3) & 0x7ff; |
| 3735 | |
| 3736 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", |
| 3737 | __func__, index, readl(&xhci->run_regs->microframe_index), |
| 3738 | start_frame_id, end_frame_id, start_frame); |
| 3739 | |
| 3740 | if (start_frame_id < end_frame_id) { |
| 3741 | if (start_frame > end_frame_id || |
| 3742 | start_frame < start_frame_id) |
| 3743 | ret = -EINVAL; |
| 3744 | } else if (start_frame_id > end_frame_id) { |
| 3745 | if ((start_frame > end_frame_id && |
| 3746 | start_frame < start_frame_id)) |
| 3747 | ret = -EINVAL; |
| 3748 | } else { |
| 3749 | ret = -EINVAL; |
| 3750 | } |
| 3751 | |
| 3752 | if (index == 0) { |
| 3753 | if (ret == -EINVAL || start_frame == start_frame_id) { |
| 3754 | start_frame = start_frame_id + 1; |
| 3755 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3756 | urb->dev->speed == USB_SPEED_FULL) |
| 3757 | urb->start_frame = start_frame; |
| 3758 | else |
| 3759 | urb->start_frame = start_frame << 3; |
| 3760 | ret = 0; |
| 3761 | } |
| 3762 | } |
| 3763 | |
| 3764 | if (ret) { |
| 3765 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", |
| 3766 | start_frame, current_frame_id, index, |
| 3767 | start_frame_id, end_frame_id); |
| 3768 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); |
| 3769 | return ret; |
| 3770 | } |
| 3771 | |
| 3772 | return start_frame; |
| 3773 | } |
| 3774 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3775 | /* This is for isoc transfer */ |
| 3776 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 3777 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3778 | { |
| 3779 | struct xhci_ring *ep_ring; |
| 3780 | struct urb_priv *urb_priv; |
| 3781 | struct xhci_td *td; |
| 3782 | int num_tds, trbs_per_td; |
| 3783 | struct xhci_generic_trb *start_trb; |
| 3784 | bool first_trb; |
| 3785 | int start_cycle; |
| 3786 | u32 field, length_field; |
| 3787 | int running_total, trb_buff_len, td_len, td_remain_len, ret; |
| 3788 | u64 start_addr, addr; |
| 3789 | int i, j; |
Andiry Xu | 47cbf69 | 2010-12-20 14:49:48 +0800 | [diff] [blame] | 3790 | bool more_trbs_coming; |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3791 | struct xhci_virt_ep *xep; |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3792 | int frame_id; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3793 | |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3794 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3795 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
| 3796 | |
| 3797 | num_tds = urb->number_of_packets; |
| 3798 | if (num_tds < 1) { |
| 3799 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); |
| 3800 | return -EINVAL; |
| 3801 | } |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3802 | start_addr = (u64) urb->transfer_dma; |
| 3803 | start_trb = &ep_ring->enqueue->generic; |
| 3804 | start_cycle = ep_ring->cycle_state; |
| 3805 | |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3806 | urb_priv = urb->hcpriv; |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3807 | /* Queue the TRBs for each TD, even if they are zero-length */ |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3808 | for (i = 0; i < num_tds; i++) { |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3809 | unsigned int total_pkt_count, max_pkt; |
| 3810 | unsigned int burst_count, last_burst_pkt_count; |
| 3811 | u32 sia_frame_id; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3812 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3813 | first_trb = true; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3814 | running_total = 0; |
| 3815 | addr = start_addr + urb->iso_frame_desc[i].offset; |
| 3816 | td_len = urb->iso_frame_desc[i].length; |
| 3817 | td_remain_len = td_len; |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3818 | max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
| 3819 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
| 3820 | |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 3821 | /* A zero-length transfer still involves at least one packet. */ |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3822 | if (total_pkt_count == 0) |
| 3823 | total_pkt_count++; |
| 3824 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); |
| 3825 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, |
| 3826 | urb, total_pkt_count); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3827 | |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3828 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3829 | |
| 3830 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3831 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3832 | if (ret < 0) { |
| 3833 | if (i == 0) |
| 3834 | return ret; |
| 3835 | goto cleanup; |
| 3836 | } |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3837 | td = urb_priv->td[i]; |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3838 | |
| 3839 | /* use SIA as default, if frame id is used overwrite it */ |
| 3840 | sia_frame_id = TRB_SIA; |
| 3841 | if (!(urb->transfer_flags & URB_ISO_ASAP) && |
| 3842 | HCC_CFC(xhci->hcc_params)) { |
| 3843 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); |
| 3844 | if (frame_id >= 0) |
| 3845 | sia_frame_id = TRB_FRAME_ID(frame_id); |
| 3846 | } |
| 3847 | /* |
| 3848 | * Set isoc specific data for the first TRB in a TD. |
| 3849 | * Prevent HW from getting the TRBs by keeping the cycle state |
| 3850 | * inverted in the first TDs isoc TRB. |
| 3851 | */ |
Mathias Nyman | 2f6d3b6 | 2016-02-12 16:40:18 +0200 | [diff] [blame] | 3852 | field = TRB_TYPE(TRB_ISOC) | |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3853 | TRB_TLBPC(last_burst_pkt_count) | |
| 3854 | sia_frame_id | |
| 3855 | (i ? ep_ring->cycle_state : !start_cycle); |
| 3856 | |
Mathias Nyman | 2f6d3b6 | 2016-02-12 16:40:18 +0200 | [diff] [blame] | 3857 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
| 3858 | if (!xep->use_extended_tbc) |
| 3859 | field |= TRB_TBC(burst_count); |
| 3860 | |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3861 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3862 | for (j = 0; j < trbs_per_td; j++) { |
| 3863 | u32 remainder = 0; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3864 | |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3865 | /* only first TRB is isoc, overwrite otherwise */ |
| 3866 | if (!first_trb) |
| 3867 | field = TRB_TYPE(TRB_NORMAL) | |
| 3868 | ep_ring->cycle_state; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3869 | |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3870 | /* Only set interrupt on short packet for IN EPs */ |
| 3871 | if (usb_urb_dir_in(urb)) |
| 3872 | field |= TRB_ISP; |
| 3873 | |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3874 | /* Set the chain bit for all except the last TRB */ |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3875 | if (j < trbs_per_td - 1) { |
Andiry Xu | 47cbf69 | 2010-12-20 14:49:48 +0800 | [diff] [blame] | 3876 | more_trbs_coming = true; |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3877 | field |= TRB_CHAIN; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3878 | } else { |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3879 | more_trbs_coming = false; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3880 | td->last_trb = ep_ring->enqueue; |
| 3881 | field |= TRB_IOC; |
Mathias Nyman | 09c352e | 2016-02-12 16:40:17 +0200 | [diff] [blame] | 3882 | /* set BEI, except for the last TD */ |
| 3883 | if (xhci->hci_version >= 0x100 && |
| 3884 | !(xhci->quirks & XHCI_AVOID_BEI) && |
| 3885 | i < num_tds - 1) |
| 3886 | field |= TRB_BEI; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3887 | } |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3888 | /* Calculate TRB length */ |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3889 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3890 | if (trb_buff_len > td_remain_len) |
| 3891 | trb_buff_len = td_remain_len; |
| 3892 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3893 | /* Set the TRB length, TD size, & interrupter fields. */ |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3894 | remainder = xhci_td_remainder(xhci, running_total, |
| 3895 | trb_buff_len, td_len, |
Mathias Nyman | 124c393 | 2016-06-21 10:57:59 +0300 | [diff] [blame] | 3896 | urb, more_trbs_coming); |
Mathias Nyman | c840d6c | 2015-10-09 13:30:08 +0300 | [diff] [blame] | 3897 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3898 | length_field = TRB_LEN(trb_buff_len) | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3899 | TRB_INTR_TARGET(0); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3900 | |
Mathias Nyman | 2f6d3b6 | 2016-02-12 16:40:18 +0200 | [diff] [blame] | 3901 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
| 3902 | if (first_trb && xep->use_extended_tbc) |
| 3903 | length_field |= TRB_TD_SIZE_TBC(burst_count); |
| 3904 | else |
| 3905 | length_field |= TRB_TD_SIZE(remainder); |
| 3906 | first_trb = false; |
| 3907 | |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3908 | queue_trb(xhci, ep_ring, more_trbs_coming, |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3909 | lower_32_bits(addr), |
| 3910 | upper_32_bits(addr), |
| 3911 | length_field, |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3912 | field); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3913 | running_total += trb_buff_len; |
| 3914 | |
| 3915 | addr += trb_buff_len; |
| 3916 | td_remain_len -= trb_buff_len; |
| 3917 | } |
| 3918 | |
| 3919 | /* Check TD length */ |
| 3920 | if (running_total != td_len) { |
| 3921 | xhci_err(xhci, "ISOC TD length unmatch\n"); |
Andiry Xu | cf84055 | 2012-01-18 17:47:12 +0800 | [diff] [blame] | 3922 | ret = -EINVAL; |
| 3923 | goto cleanup; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3924 | } |
| 3925 | } |
| 3926 | |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3927 | /* store the next frame id */ |
| 3928 | if (HCC_CFC(xhci->hcc_params)) |
| 3929 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; |
| 3930 | |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 3931 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
| 3932 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
| 3933 | usb_amd_quirk_pll_disable(); |
| 3934 | } |
| 3935 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; |
| 3936 | |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 3937 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
| 3938 | start_cycle, start_trb); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3939 | return 0; |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3940 | cleanup: |
| 3941 | /* Clean up a partially enqueued isoc transfer. */ |
| 3942 | |
| 3943 | for (i--; i >= 0; i--) |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 3944 | list_del_init(&urb_priv->td[i]->td_list); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3945 | |
| 3946 | /* Use the first TD as a temporary variable to turn the TDs we've queued |
| 3947 | * into No-ops with a software-owned cycle bit. That way the hardware |
| 3948 | * won't accidentally start executing bogus TDs when we partially |
| 3949 | * overwrite them. td->first_trb and td->start_seg are already set. |
| 3950 | */ |
| 3951 | urb_priv->td[0]->last_trb = ep_ring->enqueue; |
| 3952 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
| 3953 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); |
| 3954 | |
| 3955 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ |
| 3956 | ep_ring->enqueue = urb_priv->td[0]->first_trb; |
| 3957 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; |
| 3958 | ep_ring->cycle_state = start_cycle; |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 3959 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3960 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
| 3961 | return ret; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3962 | } |
| 3963 | |
| 3964 | /* |
| 3965 | * Check transfer ring to guarantee there is enough room for the urb. |
| 3966 | * Update ISO URB start_frame and interval. |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3967 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
| 3968 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or |
| 3969 | * Contiguous Frame ID is not supported by HC. |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3970 | */ |
| 3971 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 3972 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3973 | { |
| 3974 | struct xhci_virt_device *xdev; |
| 3975 | struct xhci_ring *ep_ring; |
| 3976 | struct xhci_ep_ctx *ep_ctx; |
| 3977 | int start_frame; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3978 | int num_tds, num_trbs, i; |
| 3979 | int ret; |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3980 | struct xhci_virt_ep *xep; |
| 3981 | int ist; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3982 | |
| 3983 | xdev = xhci->devs[slot_id]; |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 3984 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3985 | ep_ring = xdev->eps[ep_index].ring; |
| 3986 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
| 3987 | |
| 3988 | num_trbs = 0; |
| 3989 | num_tds = urb->number_of_packets; |
| 3990 | for (i = 0; i < num_tds; i++) |
Alexandr Ivanov | d251034 | 2016-04-22 13:17:09 +0300 | [diff] [blame] | 3991 | num_trbs += count_isoc_trbs_needed(urb, i); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3992 | |
| 3993 | /* Check the ring to guarantee there is enough room for the whole urb. |
| 3994 | * Do not insert any td of the urb to the ring if the check failed. |
| 3995 | */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3996 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 3997 | num_trbs, mem_flags); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3998 | if (ret) |
| 3999 | return ret; |
| 4000 | |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 4001 | /* |
| 4002 | * Check interval value. This should be done before we start to |
| 4003 | * calculate the start frame value. |
| 4004 | */ |
Alexandr Ivanov | 7814015 | 2016-04-22 13:17:11 +0300 | [diff] [blame] | 4005 | check_interval(xhci, urb, ep_ctx); |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 4006 | |
| 4007 | /* Calculate the start frame and put it in urb->start_frame. */ |
Lu Baolu | 42df721 | 2015-11-18 10:48:21 +0200 | [diff] [blame] | 4008 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
| 4009 | if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
| 4010 | EP_STATE_RUNNING) { |
| 4011 | urb->start_frame = xep->next_frame_id; |
| 4012 | goto skip_start_over; |
| 4013 | } |
Lu Baolu | 79b8094 | 2015-08-06 19:24:00 +0300 | [diff] [blame] | 4014 | } |
| 4015 | |
| 4016 | start_frame = readl(&xhci->run_regs->microframe_index); |
| 4017 | start_frame &= 0x3fff; |
| 4018 | /* |
| 4019 | * Round up to the next frame and consider the time before trb really |
| 4020 | * gets scheduled by hardare. |
| 4021 | */ |
| 4022 | ist = HCS_IST(xhci->hcs_params2) & 0x7; |
| 4023 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) |
| 4024 | ist <<= 3; |
| 4025 | start_frame += ist + XHCI_CFC_DELAY; |
| 4026 | start_frame = roundup(start_frame, 8); |
| 4027 | |
| 4028 | /* |
| 4029 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT |
| 4030 | * is greate than 8 microframes. |
| 4031 | */ |
| 4032 | if (urb->dev->speed == USB_SPEED_LOW || |
| 4033 | urb->dev->speed == USB_SPEED_FULL) { |
| 4034 | start_frame = roundup(start_frame, urb->interval << 3); |
| 4035 | urb->start_frame = start_frame >> 3; |
| 4036 | } else { |
| 4037 | start_frame = roundup(start_frame, urb->interval); |
| 4038 | urb->start_frame = start_frame; |
| 4039 | } |
| 4040 | |
| 4041 | skip_start_over: |
Andiry Xu | b008df6 | 2012-03-05 17:49:34 +0800 | [diff] [blame] | 4042 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
| 4043 | |
Dan Carpenter | 3fc8206 | 2012-03-28 10:30:26 +0300 | [diff] [blame] | 4044 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 4045 | } |
| 4046 | |
Sarah Sharp | d0e96f5a | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 4047 | /**** Command Ring Operations ****/ |
| 4048 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4049 | /* Generic function for queueing a command TRB on the command ring. |
| 4050 | * Check to make sure there's room on the command ring for one command TRB. |
| 4051 | * Also check that there's room reserved for commands that must not fail. |
| 4052 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, |
| 4053 | * then only check for the number of reserved spots. |
| 4054 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB |
| 4055 | * because the command event handler may want to resubmit a failed command. |
| 4056 | */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4057 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4058 | u32 field1, u32 field2, |
| 4059 | u32 field3, u32 field4, bool command_must_succeed) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 4060 | { |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4061 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 4062 | int ret; |
Roger Quadros | ad6b1d9 | 2015-05-29 17:01:49 +0300 | [diff] [blame] | 4063 | |
Mathias Nyman | 98d74f9 | 2016-04-08 16:25:10 +0300 | [diff] [blame] | 4064 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
| 4065 | (xhci->xhc_state & XHCI_STATE_HALTED)) { |
Roger Quadros | ad6b1d9 | 2015-05-29 17:01:49 +0300 | [diff] [blame] | 4066 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 4067 | return -ESHUTDOWN; |
Roger Quadros | ad6b1d9 | 2015-05-29 17:01:49 +0300 | [diff] [blame] | 4068 | } |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 4069 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4070 | if (!command_must_succeed) |
| 4071 | reserved_trbs++; |
| 4072 | |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 4073 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 4074 | reserved_trbs, GFP_ATOMIC); |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 4075 | if (ret < 0) { |
| 4076 | xhci_err(xhci, "ERR: No room for command on command ring\n"); |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4077 | if (command_must_succeed) |
| 4078 | xhci_err(xhci, "ERR: Reserved TRB counting for " |
| 4079 | "unfailable commands failed.\n"); |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 4080 | return ret; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 4081 | } |
Mathias Nyman | c9aa1a2 | 2014-05-08 19:26:01 +0300 | [diff] [blame] | 4082 | |
| 4083 | cmd->command_trb = xhci->cmd_ring->enqueue; |
| 4084 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4085 | |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 4086 | /* if there are no other commands queued we start the timeout timer */ |
| 4087 | if (xhci->cmd_list.next == &cmd->cmd_list && |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 4088 | !delayed_work_pending(&xhci->cmd_timer)) { |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 4089 | xhci->current_cmd = cmd; |
OGAWA Hirofumi | 799dfde | 2017-01-03 18:28:50 +0200 | [diff] [blame] | 4090 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
Mathias Nyman | c311e39 | 2014-05-08 19:26:03 +0300 | [diff] [blame] | 4091 | } |
| 4092 | |
Andiry Xu | 3b72fca | 2012-03-05 17:49:32 +0800 | [diff] [blame] | 4093 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
| 4094 | field4 | xhci->cmd_ring->cycle_state); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 4095 | return 0; |
| 4096 | } |
| 4097 | |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 4098 | /* Queue a slot enable or disable request on the command ring */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4099 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4100 | u32 trb_type, u32 slot_id) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 4101 | { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4102 | return queue_command(xhci, cmd, 0, 0, 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4103 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 4104 | } |
| 4105 | |
| 4106 | /* Queue an address device command TRB */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4107 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4108 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 4109 | { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4110 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 4111 | upper_32_bits(in_ctx_ptr), 0, |
Dan Williams | 48fc7db | 2013-12-05 17:07:27 -0800 | [diff] [blame] | 4112 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
| 4113 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 4114 | } |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 4115 | |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4116 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 4117 | u32 field1, u32 field2, u32 field3, u32 field4) |
| 4118 | { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4119 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 4120 | } |
| 4121 | |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 4122 | /* Queue a reset device command TRB */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4123 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4124 | u32 slot_id) |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 4125 | { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4126 | return queue_command(xhci, cmd, 0, 0, 0, |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 4127 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
| 4128 | false); |
| 4129 | } |
| 4130 | |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 4131 | /* Queue a configure endpoint command TRB */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4132 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
| 4133 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4134 | u32 slot_id, bool command_must_succeed) |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 4135 | { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4136 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 4137 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4138 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
| 4139 | command_must_succeed); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 4140 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4141 | |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 4142 | /* Queue an evaluate context command TRB */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4143 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4144 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 4145 | { |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4146 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 4147 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 4148 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
Sarah Sharp | 4b26654 | 2012-05-07 15:34:26 -0700 | [diff] [blame] | 4149 | command_must_succeed); |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 4150 | } |
| 4151 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 4152 | /* |
| 4153 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop |
| 4154 | * activity on an endpoint that is about to be suspended. |
| 4155 | */ |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4156 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4157 | int slot_id, unsigned int ep_index, int suspend) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4158 | { |
| 4159 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 4160 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
| 4161 | u32 type = TRB_TYPE(TRB_STOP_RING); |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 4162 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4163 | |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4164 | return queue_command(xhci, cmd, 0, 0, 0, |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 4165 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4166 | } |
| 4167 | |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4168 | /* Set Transfer Ring Dequeue Pointer command */ |
| 4169 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
| 4170 | unsigned int slot_id, unsigned int ep_index, |
| 4171 | unsigned int stream_id, |
| 4172 | struct xhci_dequeue_state *deq_state) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4173 | { |
| 4174 | dma_addr_t addr; |
| 4175 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 4176 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 4177 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
Hans de Goede | 95241db | 2013-10-04 00:29:48 +0200 | [diff] [blame] | 4178 | u32 trb_sct = 0; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4179 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 4180 | struct xhci_virt_ep *ep; |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 4181 | struct xhci_command *cmd; |
| 4182 | int ret; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4183 | |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4184 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 4185 | "Set TR Deq Ptr cmd, new deq seg = %pK (0x%llx dma), new deq ptr = %pK (0x%llx dma), new cycle = %u", |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4186 | deq_state->new_deq_seg, |
| 4187 | (unsigned long long)deq_state->new_deq_seg->dma, |
| 4188 | deq_state->new_deq_ptr, |
| 4189 | (unsigned long long)xhci_trb_virt_to_dma( |
| 4190 | deq_state->new_deq_seg, deq_state->new_deq_ptr), |
| 4191 | deq_state->new_cycle_state); |
| 4192 | |
| 4193 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, |
| 4194 | deq_state->new_deq_ptr); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 4195 | if (addr == 0) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4196 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
Vamsi Krishna Samavedam | f826f83 | 2016-11-03 17:06:34 -0700 | [diff] [blame] | 4197 | xhci_warn(xhci, "WARN deq seg = %pK, deq pt = %pK\n", |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4198 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
| 4199 | return; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 4200 | } |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 4201 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 4202 | if ((ep->ep_state & SET_DEQ_PENDING)) { |
| 4203 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
| 4204 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4205 | return; |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 4206 | } |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 4207 | |
| 4208 | /* This function gets called from contexts where it cannot sleep */ |
| 4209 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
| 4210 | if (!cmd) { |
| 4211 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4212 | return; |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 4213 | } |
| 4214 | |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4215 | ep->queued_deq_seg = deq_state->new_deq_seg; |
| 4216 | ep->queued_deq_ptr = deq_state->new_deq_ptr; |
Hans de Goede | 95241db | 2013-10-04 00:29:48 +0200 | [diff] [blame] | 4217 | if (stream_id) |
| 4218 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 4219 | ret = queue_command(xhci, cmd, |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4220 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
| 4221 | upper_32_bits(addr), trb_stream_id, |
| 4222 | trb_slot_id | trb_ep_index | type, false); |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 4223 | if (ret < 0) { |
| 4224 | xhci_free_command(xhci, cmd); |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4225 | return; |
Hans de Goede | 1e3452e | 2014-08-20 16:41:52 +0300 | [diff] [blame] | 4226 | } |
| 4227 | |
Hans de Goede | d3a43e6 | 2014-08-20 16:41:53 +0300 | [diff] [blame] | 4228 | /* Stop the TD queueing code from ringing the doorbell until |
| 4229 | * this command completes. The HC won't set the dequeue pointer |
| 4230 | * if the ring is running, and ringing the doorbell starts the |
| 4231 | * ring running. |
| 4232 | */ |
| 4233 | ep->ep_state |= SET_DEQ_PENDING; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 4234 | } |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 4235 | |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4236 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
| 4237 | int slot_id, unsigned int ep_index) |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 4238 | { |
| 4239 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 4240 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
| 4241 | u32 type = TRB_TYPE(TRB_RESET_EP); |
| 4242 | |
Mathias Nyman | ddba5cd | 2014-05-08 19:26:00 +0300 | [diff] [blame] | 4243 | return queue_command(xhci, cmd, 0, 0, 0, |
| 4244 | trb_slot_id | trb_ep_index | type, false); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 4245 | } |