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Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Padmavathi Vennaa80258f2013-02-14 09:10:06 +053028#include <linux/of_dma.h>
Sachin Kamatbcc7fa92013-03-04 14:36:27 +053029#include <linux/err.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070030
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000031#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090032#define PL330_MAX_CHAN 8
33#define PL330_MAX_IRQS 32
34#define PL330_MAX_PERI 32
35
36enum pl330_srccachectrl {
37 SCCTRL0, /* Noncacheable and nonbufferable */
38 SCCTRL1, /* Bufferable only */
39 SCCTRL2, /* Cacheable, but do not allocate */
40 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
41 SINVALID1,
42 SINVALID2,
43 SCCTRL6, /* Cacheable write-through, allocate on reads only */
44 SCCTRL7, /* Cacheable write-back, allocate on reads only */
45};
46
47enum pl330_dstcachectrl {
48 DCCTRL0, /* Noncacheable and nonbufferable */
49 DCCTRL1, /* Bufferable only */
50 DCCTRL2, /* Cacheable, but do not allocate */
51 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
Linus Torvaldsef08e782012-03-29 15:34:57 -070052 DINVALID1, /* AWCACHE = 0x1000 */
Boojin Kimb7d861d2011-12-26 18:49:52 +090053 DINVALID2,
54 DCCTRL6, /* Cacheable write-through, allocate on writes only */
55 DCCTRL7, /* Cacheable write-back, allocate on writes only */
56};
57
58enum pl330_byteswap {
59 SWAP_NO,
60 SWAP_2,
61 SWAP_4,
62 SWAP_8,
63 SWAP_16,
64};
65
66enum pl330_reqtype {
67 MEMTOMEM,
68 MEMTODEV,
69 DEVTOMEM,
70 DEVTODEV,
71};
72
73/* Register and Bit field Definitions */
74#define DS 0x0
75#define DS_ST_STOP 0x0
76#define DS_ST_EXEC 0x1
77#define DS_ST_CMISS 0x2
78#define DS_ST_UPDTPC 0x3
79#define DS_ST_WFE 0x4
80#define DS_ST_ATBRR 0x5
81#define DS_ST_QBUSY 0x6
82#define DS_ST_WFP 0x7
83#define DS_ST_KILL 0x8
84#define DS_ST_CMPLT 0x9
85#define DS_ST_FLTCMP 0xe
86#define DS_ST_FAULT 0xf
87
88#define DPC 0x4
89#define INTEN 0x20
90#define ES 0x24
91#define INTSTATUS 0x28
92#define INTCLR 0x2c
93#define FSM 0x30
94#define FSC 0x34
95#define FTM 0x38
96
97#define _FTC 0x40
98#define FTC(n) (_FTC + (n)*0x4)
99
100#define _CS 0x100
101#define CS(n) (_CS + (n)*0x8)
102#define CS_CNS (1 << 21)
103
104#define _CPC 0x104
105#define CPC(n) (_CPC + (n)*0x8)
106
107#define _SA 0x400
108#define SA(n) (_SA + (n)*0x20)
109
110#define _DA 0x404
111#define DA(n) (_DA + (n)*0x20)
112
113#define _CC 0x408
114#define CC(n) (_CC + (n)*0x20)
115
116#define CC_SRCINC (1 << 0)
117#define CC_DSTINC (1 << 14)
118#define CC_SRCPRI (1 << 8)
119#define CC_DSTPRI (1 << 22)
120#define CC_SRCNS (1 << 9)
121#define CC_DSTNS (1 << 23)
122#define CC_SRCIA (1 << 10)
123#define CC_DSTIA (1 << 24)
124#define CC_SRCBRSTLEN_SHFT 4
125#define CC_DSTBRSTLEN_SHFT 18
126#define CC_SRCBRSTSIZE_SHFT 1
127#define CC_DSTBRSTSIZE_SHFT 15
128#define CC_SRCCCTRL_SHFT 11
129#define CC_SRCCCTRL_MASK 0x7
130#define CC_DSTCCTRL_SHFT 25
131#define CC_DRCCCTRL_MASK 0x7
132#define CC_SWAP_SHFT 28
133
134#define _LC0 0x40c
135#define LC0(n) (_LC0 + (n)*0x20)
136
137#define _LC1 0x410
138#define LC1(n) (_LC1 + (n)*0x20)
139
140#define DBGSTATUS 0xd00
141#define DBG_BUSY (1 << 0)
142
143#define DBGCMD 0xd04
144#define DBGINST0 0xd08
145#define DBGINST1 0xd0c
146
147#define CR0 0xe00
148#define CR1 0xe04
149#define CR2 0xe08
150#define CR3 0xe0c
151#define CR4 0xe10
152#define CRD 0xe14
153
154#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900155#define PERIPH_REV_SHIFT 20
156#define PERIPH_REV_MASK 0xf
157#define PERIPH_REV_R0P0 0
158#define PERIPH_REV_R1P0 1
159#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900160
161#define CR0_PERIPH_REQ_SET (1 << 0)
162#define CR0_BOOT_EN_SET (1 << 1)
163#define CR0_BOOT_MAN_NS (1 << 2)
164#define CR0_NUM_CHANS_SHIFT 4
165#define CR0_NUM_CHANS_MASK 0x7
166#define CR0_NUM_PERIPH_SHIFT 12
167#define CR0_NUM_PERIPH_MASK 0x1f
168#define CR0_NUM_EVENTS_SHIFT 17
169#define CR0_NUM_EVENTS_MASK 0x1f
170
171#define CR1_ICACHE_LEN_SHIFT 0
172#define CR1_ICACHE_LEN_MASK 0x7
173#define CR1_NUM_ICACHELINES_SHIFT 4
174#define CR1_NUM_ICACHELINES_MASK 0xf
175
176#define CRD_DATA_WIDTH_SHIFT 0
177#define CRD_DATA_WIDTH_MASK 0x7
178#define CRD_WR_CAP_SHIFT 4
179#define CRD_WR_CAP_MASK 0x7
180#define CRD_WR_Q_DEP_SHIFT 8
181#define CRD_WR_Q_DEP_MASK 0xf
182#define CRD_RD_CAP_SHIFT 12
183#define CRD_RD_CAP_MASK 0x7
184#define CRD_RD_Q_DEP_SHIFT 16
185#define CRD_RD_Q_DEP_MASK 0xf
186#define CRD_DATA_BUFF_SHIFT 20
187#define CRD_DATA_BUFF_MASK 0x3ff
188
189#define PART 0x330
190#define DESIGNER 0x41
191#define REVISION 0x0
192#define INTEG_CFG 0x0
193#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
194
Boojin Kimb7d861d2011-12-26 18:49:52 +0900195#define PL330_STATE_STOPPED (1 << 0)
196#define PL330_STATE_EXECUTING (1 << 1)
197#define PL330_STATE_WFE (1 << 2)
198#define PL330_STATE_FAULTING (1 << 3)
199#define PL330_STATE_COMPLETING (1 << 4)
200#define PL330_STATE_WFP (1 << 5)
201#define PL330_STATE_KILLING (1 << 6)
202#define PL330_STATE_FAULT_COMPLETING (1 << 7)
203#define PL330_STATE_CACHEMISS (1 << 8)
204#define PL330_STATE_UPDTPC (1 << 9)
205#define PL330_STATE_ATBARRIER (1 << 10)
206#define PL330_STATE_QUEUEBUSY (1 << 11)
207#define PL330_STATE_INVALID (1 << 15)
208
209#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
210 | PL330_STATE_WFE | PL330_STATE_FAULTING)
211
212#define CMD_DMAADDH 0x54
213#define CMD_DMAEND 0x00
214#define CMD_DMAFLUSHP 0x35
215#define CMD_DMAGO 0xa0
216#define CMD_DMALD 0x04
217#define CMD_DMALDP 0x25
218#define CMD_DMALP 0x20
219#define CMD_DMALPEND 0x28
220#define CMD_DMAKILL 0x01
221#define CMD_DMAMOV 0xbc
222#define CMD_DMANOP 0x18
223#define CMD_DMARMB 0x12
224#define CMD_DMASEV 0x34
225#define CMD_DMAST 0x08
226#define CMD_DMASTP 0x29
227#define CMD_DMASTZ 0x0c
228#define CMD_DMAWFE 0x36
229#define CMD_DMAWFP 0x30
230#define CMD_DMAWMB 0x13
231
232#define SZ_DMAADDH 3
233#define SZ_DMAEND 1
234#define SZ_DMAFLUSHP 2
235#define SZ_DMALD 1
236#define SZ_DMALDP 2
237#define SZ_DMALP 2
238#define SZ_DMALPEND 2
239#define SZ_DMAKILL 1
240#define SZ_DMAMOV 6
241#define SZ_DMANOP 1
242#define SZ_DMARMB 1
243#define SZ_DMASEV 2
244#define SZ_DMAST 1
245#define SZ_DMASTP 2
246#define SZ_DMASTZ 1
247#define SZ_DMAWFE 2
248#define SZ_DMAWFP 2
249#define SZ_DMAWMB 1
250#define SZ_DMAGO 6
251
252#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
253#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
254
255#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
256#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
257
258/*
259 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
260 * at 1byte/burst for P<->M and M<->M respectively.
261 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
262 * should be enough for P<->M and M<->M respectively.
263 */
264#define MCODE_BUFF_PER_REQ 256
265
266/* If the _pl330_req is available to the client */
267#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
268
269/* Use this _only_ to wait on transient states */
270#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
271
272#ifdef PL330_DEBUG_MCGEN
273static unsigned cmd_line;
274#define PL330_DBGCMD_DUMP(off, x...) do { \
275 printk("%x:", cmd_line); \
276 printk(x); \
277 cmd_line += off; \
278 } while (0)
279#define PL330_DBGMC_START(addr) (cmd_line = addr)
280#else
281#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
282#define PL330_DBGMC_START(addr) do {} while (0)
283#endif
284
285/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000286
Jassi Brarb3040e42010-05-23 20:28:19 -0700287#define NR_DEFAULT_DESC 16
288
Boojin Kimb7d861d2011-12-26 18:49:52 +0900289/* Populated by the PL330 core driver for DMA API driver's info */
290struct pl330_config {
291 u32 periph_id;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900292#define DMAC_MODE_NS (1 << 0)
293 unsigned int mode;
294 unsigned int data_bus_width:10; /* In number of bits */
295 unsigned int data_buf_dep:10;
296 unsigned int num_chan:4;
297 unsigned int num_peri:6;
298 u32 peri_ns;
299 unsigned int num_events:6;
300 u32 irq_ns;
301};
302
303/* Handle to the DMAC provided to the PL330 core */
304struct pl330_info {
305 /* Owning device */
306 struct device *dev;
307 /* Size of MicroCode buffers for each channel. */
308 unsigned mcbufsz;
309 /* ioremap'ed address of PL330 registers. */
310 void __iomem *base;
311 /* Client can freely use it. */
312 void *client_data;
313 /* PL330 core data, Client must not touch it. */
314 void *pl330_data;
315 /* Populated by the PL330 core driver during pl330_add */
316 struct pl330_config pcfg;
317 /*
318 * If the DMAC has some reset mechanism, then the
319 * client may want to provide pointer to the method.
320 */
321 void (*dmac_reset)(struct pl330_info *pi);
322};
323
324/**
325 * Request Configuration.
326 * The PL330 core does not modify this and uses the last
327 * working configuration if the request doesn't provide any.
328 *
329 * The Client may want to provide this info only for the
330 * first request and a request with new settings.
331 */
332struct pl330_reqcfg {
333 /* Address Incrementing */
334 unsigned dst_inc:1;
335 unsigned src_inc:1;
336
337 /*
338 * For now, the SRC & DST protection levels
339 * and burst size/length are assumed same.
340 */
341 bool nonsecure;
342 bool privileged;
343 bool insnaccess;
344 unsigned brst_len:5;
345 unsigned brst_size:3; /* in power of 2 */
346
347 enum pl330_dstcachectrl dcctl;
348 enum pl330_srccachectrl scctl;
349 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900350 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900351};
352
353/*
354 * One cycle of DMAC operation.
355 * There may be more than one xfer in a request.
356 */
357struct pl330_xfer {
358 u32 src_addr;
359 u32 dst_addr;
360 /* Size to xfer */
361 u32 bytes;
362 /*
363 * Pointer to next xfer in the list.
364 * The last xfer in the req must point to NULL.
365 */
366 struct pl330_xfer *next;
367};
368
369/* The xfer callbacks are made with one of these arguments. */
370enum pl330_op_err {
371 /* The all xfers in the request were success. */
372 PL330_ERR_NONE,
373 /* If req aborted due to global error. */
374 PL330_ERR_ABORT,
375 /* If req failed due to problem with Channel. */
376 PL330_ERR_FAIL,
377};
378
379/* A request defining Scatter-Gather List ending with NULL xfer. */
380struct pl330_req {
381 enum pl330_reqtype rqtype;
382 /* Index of peripheral for the xfer. */
383 unsigned peri:5;
384 /* Unique token for this xfer, set by the client. */
385 void *token;
386 /* Callback to be called after xfer. */
387 void (*xfer_cb)(void *token, enum pl330_op_err err);
388 /* If NULL, req will be done at last set parameters. */
389 struct pl330_reqcfg *cfg;
390 /* Pointer to first xfer in the request. */
391 struct pl330_xfer *x;
Javi Merinofdec53d2012-06-13 15:07:00 +0100392 /* Hook to attach to DMAC's list of reqs with due callback */
393 struct list_head rqd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900394};
395
396/*
397 * To know the status of the channel and DMAC, the client
398 * provides a pointer to this structure. The PL330 core
399 * fills it with current information.
400 */
401struct pl330_chanstatus {
402 /*
403 * If the DMAC engine halted due to some error,
404 * the client should remove-add DMAC.
405 */
406 bool dmac_halted;
407 /*
408 * If channel is halted due to some error,
409 * the client should ABORT/FLUSH and START the channel.
410 */
411 bool faulting;
412 /* Location of last load */
413 u32 src_addr;
414 /* Location of last store */
415 u32 dst_addr;
416 /*
417 * Pointer to the currently active req, NULL if channel is
418 * inactive, even though the requests may be present.
419 */
420 struct pl330_req *top_req;
421 /* Pointer to req waiting second in the queue if any. */
422 struct pl330_req *wait_req;
423};
424
425enum pl330_chan_op {
426 /* Start the channel */
427 PL330_OP_START,
428 /* Abort the active xfer */
429 PL330_OP_ABORT,
430 /* Stop xfer and flush queue */
431 PL330_OP_FLUSH,
432};
433
434struct _xfer_spec {
435 u32 ccr;
436 struct pl330_req *r;
437 struct pl330_xfer *x;
438};
439
440enum dmamov_dst {
441 SAR = 0,
442 CCR,
443 DAR,
444};
445
446enum pl330_dst {
447 SRC = 0,
448 DST,
449};
450
451enum pl330_cond {
452 SINGLE,
453 BURST,
454 ALWAYS,
455};
456
457struct _pl330_req {
458 u32 mc_bus;
459 void *mc_cpu;
460 /* Number of bytes taken to setup MC for the req */
461 u32 mc_len;
462 struct pl330_req *r;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900463};
464
465/* ToBeDone for tasklet */
466struct _pl330_tbd {
467 bool reset_dmac;
468 bool reset_mngr;
469 u8 reset_chan;
470};
471
472/* A DMAC Thread */
473struct pl330_thread {
474 u8 id;
475 int ev;
476 /* If the channel is not yet acquired by any client */
477 bool free;
478 /* Parent DMAC */
479 struct pl330_dmac *dmac;
480 /* Only two at a time */
481 struct _pl330_req req[2];
482 /* Index of the last enqueued request */
483 unsigned lstenq;
484 /* Index of the last submitted request or -1 if the DMA is stopped */
485 int req_running;
486};
487
488enum pl330_dmac_state {
489 UNINIT,
490 INIT,
491 DYING,
492};
493
494/* A DMAC */
495struct pl330_dmac {
496 spinlock_t lock;
497 /* Holds list of reqs with due callbacks */
498 struct list_head req_done;
499 /* Pointer to platform specific stuff */
500 struct pl330_info *pinfo;
501 /* Maximum possible events/irqs */
502 int events[32];
503 /* BUS address of MicroCode buffer */
Will Deaconfed8c452013-06-10 19:34:38 +0100504 dma_addr_t mcode_bus;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900505 /* CPU address of MicroCode buffer */
506 void *mcode_cpu;
507 /* List of all Channel threads */
508 struct pl330_thread *channels;
509 /* Pointer to the MANAGER thread */
510 struct pl330_thread *manager;
511 /* To handle bad news in interrupt */
512 struct tasklet_struct tasks;
513 struct _pl330_tbd dmac_tbd;
514 /* State of DMAC operation */
515 enum pl330_dmac_state state;
516};
517
Jassi Brarb3040e42010-05-23 20:28:19 -0700518enum desc_status {
519 /* In the DMAC pool */
520 FREE,
521 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900522 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700523 * Also may be sitting on the work_list.
524 */
525 PREP,
526 /*
527 * Sitting on the work_list and already submitted
528 * to the PL330 core. Not more than two descriptors
529 * of a channel can be BUSY at any time.
530 */
531 BUSY,
532 /*
533 * Sitting on the channel work_list but xfer done
534 * by PL330 core
535 */
536 DONE,
537};
538
539struct dma_pl330_chan {
540 /* Schedule desc completion */
541 struct tasklet_struct task;
542
543 /* DMA-Engine Channel */
544 struct dma_chan chan;
545
Jassi Brarb3040e42010-05-23 20:28:19 -0700546 /* List of to be xfered descriptors */
547 struct list_head work_list;
548
549 /* Pointer to the DMAC that manages this channel,
550 * NULL if the channel is available to be acquired.
551 * As the parent, this DMAC also provides descriptors
552 * to the channel.
553 */
554 struct dma_pl330_dmac *dmac;
555
556 /* To protect channel manipulation */
557 spinlock_t lock;
558
559 /* Token of a hardware channel thread of PL330 DMAC
560 * NULL if the channel is available to be acquired.
561 */
562 void *pl330_chid;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900563
564 /* For D-to-M and M-to-D channels */
565 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900566 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900567 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900568
569 /* for cyclic capability */
570 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700571};
572
573struct dma_pl330_dmac {
574 struct pl330_info pif;
575
576 /* DMA-Engine Device */
577 struct dma_device ddma;
578
579 /* Pool of descriptors available for the DMAC's channels */
580 struct list_head desc_pool;
581 /* To protect desc_pool manipulation */
582 spinlock_t pool_lock;
583
584 /* Peripheral channels connected to this DMAC */
Rob Herring4e0e6102011-07-25 16:05:04 -0500585 struct dma_pl330_chan *peripherals; /* keep at end */
Jassi Brarb3040e42010-05-23 20:28:19 -0700586};
587
588struct dma_pl330_desc {
589 /* To attach to a queue as child */
590 struct list_head node;
591
592 /* Descriptor for the DMA Engine API */
593 struct dma_async_tx_descriptor txd;
594
595 /* Xfer for PL330 core */
596 struct pl330_xfer px;
597
598 struct pl330_reqcfg rqcfg;
599 struct pl330_req req;
600
601 enum desc_status status;
602
603 /* The channel which currently holds this desc */
604 struct dma_pl330_chan *pchan;
605};
606
Padmavathi Venna34d19352013-02-14 09:10:05 +0530607struct dma_pl330_filter_args {
608 struct dma_pl330_dmac *pdmac;
609 unsigned int chan_id;
610};
611
Boojin Kimb7d861d2011-12-26 18:49:52 +0900612static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
613{
614 if (r && r->xfer_cb)
615 r->xfer_cb(r->token, err);
616}
617
618static inline bool _queue_empty(struct pl330_thread *thrd)
619{
620 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
621 ? true : false;
622}
623
624static inline bool _queue_full(struct pl330_thread *thrd)
625{
626 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
627 ? false : true;
628}
629
630static inline bool is_manager(struct pl330_thread *thrd)
631{
632 struct pl330_dmac *pl330 = thrd->dmac;
633
634 /* MANAGER is indexed at the end */
635 if (thrd->id == pl330->pinfo->pcfg.num_chan)
636 return true;
637 else
638 return false;
639}
640
641/* If manager of the thread is in Non-Secure mode */
642static inline bool _manager_ns(struct pl330_thread *thrd)
643{
644 struct pl330_dmac *pl330 = thrd->dmac;
645
646 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
647}
648
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900649static inline u32 get_revision(u32 periph_id)
650{
651 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
652}
653
Boojin Kimb7d861d2011-12-26 18:49:52 +0900654static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
655 enum pl330_dst da, u16 val)
656{
657 if (dry_run)
658 return SZ_DMAADDH;
659
660 buf[0] = CMD_DMAADDH;
661 buf[0] |= (da << 1);
662 *((u16 *)&buf[1]) = val;
663
664 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
665 da == 1 ? "DA" : "SA", val);
666
667 return SZ_DMAADDH;
668}
669
670static inline u32 _emit_END(unsigned dry_run, u8 buf[])
671{
672 if (dry_run)
673 return SZ_DMAEND;
674
675 buf[0] = CMD_DMAEND;
676
677 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
678
679 return SZ_DMAEND;
680}
681
682static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
683{
684 if (dry_run)
685 return SZ_DMAFLUSHP;
686
687 buf[0] = CMD_DMAFLUSHP;
688
689 peri &= 0x1f;
690 peri <<= 3;
691 buf[1] = peri;
692
693 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
694
695 return SZ_DMAFLUSHP;
696}
697
698static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
699{
700 if (dry_run)
701 return SZ_DMALD;
702
703 buf[0] = CMD_DMALD;
704
705 if (cond == SINGLE)
706 buf[0] |= (0 << 1) | (1 << 0);
707 else if (cond == BURST)
708 buf[0] |= (1 << 1) | (1 << 0);
709
710 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
711 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
712
713 return SZ_DMALD;
714}
715
716static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
717 enum pl330_cond cond, u8 peri)
718{
719 if (dry_run)
720 return SZ_DMALDP;
721
722 buf[0] = CMD_DMALDP;
723
724 if (cond == BURST)
725 buf[0] |= (1 << 1);
726
727 peri &= 0x1f;
728 peri <<= 3;
729 buf[1] = peri;
730
731 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
732 cond == SINGLE ? 'S' : 'B', peri >> 3);
733
734 return SZ_DMALDP;
735}
736
737static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
738 unsigned loop, u8 cnt)
739{
740 if (dry_run)
741 return SZ_DMALP;
742
743 buf[0] = CMD_DMALP;
744
745 if (loop)
746 buf[0] |= (1 << 1);
747
748 cnt--; /* DMAC increments by 1 internally */
749 buf[1] = cnt;
750
751 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
752
753 return SZ_DMALP;
754}
755
756struct _arg_LPEND {
757 enum pl330_cond cond;
758 bool forever;
759 unsigned loop;
760 u8 bjump;
761};
762
763static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
764 const struct _arg_LPEND *arg)
765{
766 enum pl330_cond cond = arg->cond;
767 bool forever = arg->forever;
768 unsigned loop = arg->loop;
769 u8 bjump = arg->bjump;
770
771 if (dry_run)
772 return SZ_DMALPEND;
773
774 buf[0] = CMD_DMALPEND;
775
776 if (loop)
777 buf[0] |= (1 << 2);
778
779 if (!forever)
780 buf[0] |= (1 << 4);
781
782 if (cond == SINGLE)
783 buf[0] |= (0 << 1) | (1 << 0);
784 else if (cond == BURST)
785 buf[0] |= (1 << 1) | (1 << 0);
786
787 buf[1] = bjump;
788
789 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
790 forever ? "FE" : "END",
791 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
792 loop ? '1' : '0',
793 bjump);
794
795 return SZ_DMALPEND;
796}
797
798static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
799{
800 if (dry_run)
801 return SZ_DMAKILL;
802
803 buf[0] = CMD_DMAKILL;
804
805 return SZ_DMAKILL;
806}
807
808static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
809 enum dmamov_dst dst, u32 val)
810{
811 if (dry_run)
812 return SZ_DMAMOV;
813
814 buf[0] = CMD_DMAMOV;
815 buf[1] = dst;
816 *((u32 *)&buf[2]) = val;
817
818 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
819 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
820
821 return SZ_DMAMOV;
822}
823
824static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
825{
826 if (dry_run)
827 return SZ_DMANOP;
828
829 buf[0] = CMD_DMANOP;
830
831 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
832
833 return SZ_DMANOP;
834}
835
836static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
837{
838 if (dry_run)
839 return SZ_DMARMB;
840
841 buf[0] = CMD_DMARMB;
842
843 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
844
845 return SZ_DMARMB;
846}
847
848static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
849{
850 if (dry_run)
851 return SZ_DMASEV;
852
853 buf[0] = CMD_DMASEV;
854
855 ev &= 0x1f;
856 ev <<= 3;
857 buf[1] = ev;
858
859 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
860
861 return SZ_DMASEV;
862}
863
864static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
865{
866 if (dry_run)
867 return SZ_DMAST;
868
869 buf[0] = CMD_DMAST;
870
871 if (cond == SINGLE)
872 buf[0] |= (0 << 1) | (1 << 0);
873 else if (cond == BURST)
874 buf[0] |= (1 << 1) | (1 << 0);
875
876 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
877 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
878
879 return SZ_DMAST;
880}
881
882static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
883 enum pl330_cond cond, u8 peri)
884{
885 if (dry_run)
886 return SZ_DMASTP;
887
888 buf[0] = CMD_DMASTP;
889
890 if (cond == BURST)
891 buf[0] |= (1 << 1);
892
893 peri &= 0x1f;
894 peri <<= 3;
895 buf[1] = peri;
896
897 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
898 cond == SINGLE ? 'S' : 'B', peri >> 3);
899
900 return SZ_DMASTP;
901}
902
903static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
904{
905 if (dry_run)
906 return SZ_DMASTZ;
907
908 buf[0] = CMD_DMASTZ;
909
910 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
911
912 return SZ_DMASTZ;
913}
914
915static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
916 unsigned invalidate)
917{
918 if (dry_run)
919 return SZ_DMAWFE;
920
921 buf[0] = CMD_DMAWFE;
922
923 ev &= 0x1f;
924 ev <<= 3;
925 buf[1] = ev;
926
927 if (invalidate)
928 buf[1] |= (1 << 1);
929
930 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
931 ev >> 3, invalidate ? ", I" : "");
932
933 return SZ_DMAWFE;
934}
935
936static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
937 enum pl330_cond cond, u8 peri)
938{
939 if (dry_run)
940 return SZ_DMAWFP;
941
942 buf[0] = CMD_DMAWFP;
943
944 if (cond == SINGLE)
945 buf[0] |= (0 << 1) | (0 << 0);
946 else if (cond == BURST)
947 buf[0] |= (1 << 1) | (0 << 0);
948 else
949 buf[0] |= (0 << 1) | (1 << 0);
950
951 peri &= 0x1f;
952 peri <<= 3;
953 buf[1] = peri;
954
955 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
956 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
957
958 return SZ_DMAWFP;
959}
960
961static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
962{
963 if (dry_run)
964 return SZ_DMAWMB;
965
966 buf[0] = CMD_DMAWMB;
967
968 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
969
970 return SZ_DMAWMB;
971}
972
973struct _arg_GO {
974 u8 chan;
975 u32 addr;
976 unsigned ns;
977};
978
979static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
980 const struct _arg_GO *arg)
981{
982 u8 chan = arg->chan;
983 u32 addr = arg->addr;
984 unsigned ns = arg->ns;
985
986 if (dry_run)
987 return SZ_DMAGO;
988
989 buf[0] = CMD_DMAGO;
990 buf[0] |= (ns << 1);
991
992 buf[1] = chan & 0x7;
993
994 *((u32 *)&buf[2]) = addr;
995
996 return SZ_DMAGO;
997}
998
999#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1000
1001/* Returns Time-Out */
1002static bool _until_dmac_idle(struct pl330_thread *thrd)
1003{
1004 void __iomem *regs = thrd->dmac->pinfo->base;
1005 unsigned long loops = msecs_to_loops(5);
1006
1007 do {
1008 /* Until Manager is Idle */
1009 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
1010 break;
1011
1012 cpu_relax();
1013 } while (--loops);
1014
1015 if (!loops)
1016 return true;
1017
1018 return false;
1019}
1020
1021static inline void _execute_DBGINSN(struct pl330_thread *thrd,
1022 u8 insn[], bool as_manager)
1023{
1024 void __iomem *regs = thrd->dmac->pinfo->base;
1025 u32 val;
1026
1027 val = (insn[0] << 16) | (insn[1] << 24);
1028 if (!as_manager) {
1029 val |= (1 << 0);
1030 val |= (thrd->id << 8); /* Channel Number */
1031 }
1032 writel(val, regs + DBGINST0);
1033
1034 val = *((u32 *)&insn[2]);
1035 writel(val, regs + DBGINST1);
1036
1037 /* If timed out due to halted state-machine */
1038 if (_until_dmac_idle(thrd)) {
1039 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
1040 return;
1041 }
1042
1043 /* Get going */
1044 writel(0, regs + DBGCMD);
1045}
1046
1047/*
1048 * Mark a _pl330_req as free.
1049 * We do it by writing DMAEND as the first instruction
1050 * because no valid request is going to have DMAEND as
1051 * its first instruction to execute.
1052 */
1053static void mark_free(struct pl330_thread *thrd, int idx)
1054{
1055 struct _pl330_req *req = &thrd->req[idx];
1056
1057 _emit_END(0, req->mc_cpu);
1058 req->mc_len = 0;
1059
1060 thrd->req_running = -1;
1061}
1062
1063static inline u32 _state(struct pl330_thread *thrd)
1064{
1065 void __iomem *regs = thrd->dmac->pinfo->base;
1066 u32 val;
1067
1068 if (is_manager(thrd))
1069 val = readl(regs + DS) & 0xf;
1070 else
1071 val = readl(regs + CS(thrd->id)) & 0xf;
1072
1073 switch (val) {
1074 case DS_ST_STOP:
1075 return PL330_STATE_STOPPED;
1076 case DS_ST_EXEC:
1077 return PL330_STATE_EXECUTING;
1078 case DS_ST_CMISS:
1079 return PL330_STATE_CACHEMISS;
1080 case DS_ST_UPDTPC:
1081 return PL330_STATE_UPDTPC;
1082 case DS_ST_WFE:
1083 return PL330_STATE_WFE;
1084 case DS_ST_FAULT:
1085 return PL330_STATE_FAULTING;
1086 case DS_ST_ATBRR:
1087 if (is_manager(thrd))
1088 return PL330_STATE_INVALID;
1089 else
1090 return PL330_STATE_ATBARRIER;
1091 case DS_ST_QBUSY:
1092 if (is_manager(thrd))
1093 return PL330_STATE_INVALID;
1094 else
1095 return PL330_STATE_QUEUEBUSY;
1096 case DS_ST_WFP:
1097 if (is_manager(thrd))
1098 return PL330_STATE_INVALID;
1099 else
1100 return PL330_STATE_WFP;
1101 case DS_ST_KILL:
1102 if (is_manager(thrd))
1103 return PL330_STATE_INVALID;
1104 else
1105 return PL330_STATE_KILLING;
1106 case DS_ST_CMPLT:
1107 if (is_manager(thrd))
1108 return PL330_STATE_INVALID;
1109 else
1110 return PL330_STATE_COMPLETING;
1111 case DS_ST_FLTCMP:
1112 if (is_manager(thrd))
1113 return PL330_STATE_INVALID;
1114 else
1115 return PL330_STATE_FAULT_COMPLETING;
1116 default:
1117 return PL330_STATE_INVALID;
1118 }
1119}
1120
1121static void _stop(struct pl330_thread *thrd)
1122{
1123 void __iomem *regs = thrd->dmac->pinfo->base;
1124 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1125
1126 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1127 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1128
1129 /* Return if nothing needs to be done */
1130 if (_state(thrd) == PL330_STATE_COMPLETING
1131 || _state(thrd) == PL330_STATE_KILLING
1132 || _state(thrd) == PL330_STATE_STOPPED)
1133 return;
1134
1135 _emit_KILL(0, insn);
1136
1137 /* Stop generating interrupts for SEV */
1138 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1139
1140 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1141}
1142
1143/* Start doing req 'idx' of thread 'thrd' */
1144static bool _trigger(struct pl330_thread *thrd)
1145{
1146 void __iomem *regs = thrd->dmac->pinfo->base;
1147 struct _pl330_req *req;
1148 struct pl330_req *r;
1149 struct _arg_GO go;
1150 unsigned ns;
1151 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1152 int idx;
1153
1154 /* Return if already ACTIVE */
1155 if (_state(thrd) != PL330_STATE_STOPPED)
1156 return true;
1157
1158 idx = 1 - thrd->lstenq;
1159 if (!IS_FREE(&thrd->req[idx]))
1160 req = &thrd->req[idx];
1161 else {
1162 idx = thrd->lstenq;
1163 if (!IS_FREE(&thrd->req[idx]))
1164 req = &thrd->req[idx];
1165 else
1166 req = NULL;
1167 }
1168
1169 /* Return if no request */
1170 if (!req || !req->r)
1171 return true;
1172
1173 r = req->r;
1174
1175 if (r->cfg)
1176 ns = r->cfg->nonsecure ? 1 : 0;
1177 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1178 ns = 1;
1179 else
1180 ns = 0;
1181
1182 /* See 'Abort Sources' point-4 at Page 2-25 */
1183 if (_manager_ns(thrd) && !ns)
1184 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1185 __func__, __LINE__);
1186
1187 go.chan = thrd->id;
1188 go.addr = req->mc_bus;
1189 go.ns = ns;
1190 _emit_GO(0, insn, &go);
1191
1192 /* Set to generate interrupts for SEV */
1193 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1194
1195 /* Only manager can execute GO */
1196 _execute_DBGINSN(thrd, insn, true);
1197
1198 thrd->req_running = idx;
1199
1200 return true;
1201}
1202
1203static bool _start(struct pl330_thread *thrd)
1204{
1205 switch (_state(thrd)) {
1206 case PL330_STATE_FAULT_COMPLETING:
1207 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1208
1209 if (_state(thrd) == PL330_STATE_KILLING)
1210 UNTIL(thrd, PL330_STATE_STOPPED)
1211
1212 case PL330_STATE_FAULTING:
1213 _stop(thrd);
1214
1215 case PL330_STATE_KILLING:
1216 case PL330_STATE_COMPLETING:
1217 UNTIL(thrd, PL330_STATE_STOPPED)
1218
1219 case PL330_STATE_STOPPED:
1220 return _trigger(thrd);
1221
1222 case PL330_STATE_WFP:
1223 case PL330_STATE_QUEUEBUSY:
1224 case PL330_STATE_ATBARRIER:
1225 case PL330_STATE_UPDTPC:
1226 case PL330_STATE_CACHEMISS:
1227 case PL330_STATE_EXECUTING:
1228 return true;
1229
1230 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1231 default:
1232 return false;
1233 }
1234}
1235
1236static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1237 const struct _xfer_spec *pxs, int cyc)
1238{
1239 int off = 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001240 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001241
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001242 /* check lock-up free version */
1243 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1244 while (cyc--) {
1245 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1246 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1247 }
1248 } else {
1249 while (cyc--) {
1250 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1251 off += _emit_RMB(dry_run, &buf[off]);
1252 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1253 off += _emit_WMB(dry_run, &buf[off]);
1254 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001255 }
1256
1257 return off;
1258}
1259
1260static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1261 const struct _xfer_spec *pxs, int cyc)
1262{
1263 int off = 0;
1264
1265 while (cyc--) {
1266 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1267 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1268 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1269 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1270 }
1271
1272 return off;
1273}
1274
1275static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1276 const struct _xfer_spec *pxs, int cyc)
1277{
1278 int off = 0;
1279
1280 while (cyc--) {
1281 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1282 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1283 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1284 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1285 }
1286
1287 return off;
1288}
1289
1290static int _bursts(unsigned dry_run, u8 buf[],
1291 const struct _xfer_spec *pxs, int cyc)
1292{
1293 int off = 0;
1294
1295 switch (pxs->r->rqtype) {
1296 case MEMTODEV:
1297 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1298 break;
1299 case DEVTOMEM:
1300 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1301 break;
1302 case MEMTOMEM:
1303 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1304 break;
1305 default:
1306 off += 0x40000000; /* Scare off the Client */
1307 break;
1308 }
1309
1310 return off;
1311}
1312
1313/* Returns bytes consumed and updates bursts */
1314static inline int _loop(unsigned dry_run, u8 buf[],
1315 unsigned long *bursts, const struct _xfer_spec *pxs)
1316{
1317 int cyc, cycmax, szlp, szlpend, szbrst, off;
1318 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1319 struct _arg_LPEND lpend;
1320
1321 /* Max iterations possible in DMALP is 256 */
1322 if (*bursts >= 256*256) {
1323 lcnt1 = 256;
1324 lcnt0 = 256;
1325 cyc = *bursts / lcnt1 / lcnt0;
1326 } else if (*bursts > 256) {
1327 lcnt1 = 256;
1328 lcnt0 = *bursts / lcnt1;
1329 cyc = 1;
1330 } else {
1331 lcnt1 = *bursts;
1332 lcnt0 = 0;
1333 cyc = 1;
1334 }
1335
1336 szlp = _emit_LP(1, buf, 0, 0);
1337 szbrst = _bursts(1, buf, pxs, 1);
1338
1339 lpend.cond = ALWAYS;
1340 lpend.forever = false;
1341 lpend.loop = 0;
1342 lpend.bjump = 0;
1343 szlpend = _emit_LPEND(1, buf, &lpend);
1344
1345 if (lcnt0) {
1346 szlp *= 2;
1347 szlpend *= 2;
1348 }
1349
1350 /*
1351 * Max bursts that we can unroll due to limit on the
1352 * size of backward jump that can be encoded in DMALPEND
1353 * which is 8-bits and hence 255
1354 */
1355 cycmax = (255 - (szlp + szlpend)) / szbrst;
1356
1357 cyc = (cycmax < cyc) ? cycmax : cyc;
1358
1359 off = 0;
1360
1361 if (lcnt0) {
1362 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1363 ljmp0 = off;
1364 }
1365
1366 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1367 ljmp1 = off;
1368
1369 off += _bursts(dry_run, &buf[off], pxs, cyc);
1370
1371 lpend.cond = ALWAYS;
1372 lpend.forever = false;
1373 lpend.loop = 1;
1374 lpend.bjump = off - ljmp1;
1375 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1376
1377 if (lcnt0) {
1378 lpend.cond = ALWAYS;
1379 lpend.forever = false;
1380 lpend.loop = 0;
1381 lpend.bjump = off - ljmp0;
1382 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1383 }
1384
1385 *bursts = lcnt1 * cyc;
1386 if (lcnt0)
1387 *bursts *= lcnt0;
1388
1389 return off;
1390}
1391
1392static inline int _setup_loops(unsigned dry_run, u8 buf[],
1393 const struct _xfer_spec *pxs)
1394{
1395 struct pl330_xfer *x = pxs->x;
1396 u32 ccr = pxs->ccr;
1397 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1398 int off = 0;
1399
1400 while (bursts) {
1401 c = bursts;
1402 off += _loop(dry_run, &buf[off], &c, pxs);
1403 bursts -= c;
1404 }
1405
1406 return off;
1407}
1408
1409static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1410 const struct _xfer_spec *pxs)
1411{
1412 struct pl330_xfer *x = pxs->x;
1413 int off = 0;
1414
1415 /* DMAMOV SAR, x->src_addr */
1416 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1417 /* DMAMOV DAR, x->dst_addr */
1418 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1419
1420 /* Setup Loop(s) */
1421 off += _setup_loops(dry_run, &buf[off], pxs);
1422
1423 return off;
1424}
1425
1426/*
1427 * A req is a sequence of one or more xfer units.
1428 * Returns the number of bytes taken to setup the MC for the req.
1429 */
1430static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1431 unsigned index, struct _xfer_spec *pxs)
1432{
1433 struct _pl330_req *req = &thrd->req[index];
1434 struct pl330_xfer *x;
1435 u8 *buf = req->mc_cpu;
1436 int off = 0;
1437
1438 PL330_DBGMC_START(req->mc_bus);
1439
1440 /* DMAMOV CCR, ccr */
1441 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1442
1443 x = pxs->r->x;
1444 do {
1445 /* Error if xfer length is not aligned at burst size */
1446 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1447 return -EINVAL;
1448
1449 pxs->x = x;
1450 off += _setup_xfer(dry_run, &buf[off], pxs);
1451
1452 x = x->next;
1453 } while (x);
1454
1455 /* DMASEV peripheral/event */
1456 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1457 /* DMAEND */
1458 off += _emit_END(dry_run, &buf[off]);
1459
1460 return off;
1461}
1462
1463static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1464{
1465 u32 ccr = 0;
1466
1467 if (rqc->src_inc)
1468 ccr |= CC_SRCINC;
1469
1470 if (rqc->dst_inc)
1471 ccr |= CC_DSTINC;
1472
1473 /* We set same protection levels for Src and DST for now */
1474 if (rqc->privileged)
1475 ccr |= CC_SRCPRI | CC_DSTPRI;
1476 if (rqc->nonsecure)
1477 ccr |= CC_SRCNS | CC_DSTNS;
1478 if (rqc->insnaccess)
1479 ccr |= CC_SRCIA | CC_DSTIA;
1480
1481 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1482 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1483
1484 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1485 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1486
1487 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1488 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1489
1490 ccr |= (rqc->swap << CC_SWAP_SHFT);
1491
1492 return ccr;
1493}
1494
1495static inline bool _is_valid(u32 ccr)
1496{
1497 enum pl330_dstcachectrl dcctl;
1498 enum pl330_srccachectrl scctl;
1499
1500 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1501 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1502
1503 if (dcctl == DINVALID1 || dcctl == DINVALID2
1504 || scctl == SINVALID1 || scctl == SINVALID2)
1505 return false;
1506 else
1507 return true;
1508}
1509
1510/*
1511 * Submit a list of xfers after which the client wants notification.
1512 * Client is not notified after each xfer unit, just once after all
1513 * xfer units are done or some error occurs.
1514 */
1515static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1516{
1517 struct pl330_thread *thrd = ch_id;
1518 struct pl330_dmac *pl330;
1519 struct pl330_info *pi;
1520 struct _xfer_spec xs;
1521 unsigned long flags;
1522 void __iomem *regs;
1523 unsigned idx;
1524 u32 ccr;
1525 int ret = 0;
1526
1527 /* No Req or Unacquired Channel or DMAC */
1528 if (!r || !thrd || thrd->free)
1529 return -EINVAL;
1530
1531 pl330 = thrd->dmac;
1532 pi = pl330->pinfo;
1533 regs = pi->base;
1534
1535 if (pl330->state == DYING
1536 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1537 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1538 __func__, __LINE__);
1539 return -EAGAIN;
1540 }
1541
1542 /* If request for non-existing peripheral */
1543 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
1544 dev_info(thrd->dmac->pinfo->dev,
1545 "%s:%d Invalid peripheral(%u)!\n",
1546 __func__, __LINE__, r->peri);
1547 return -EINVAL;
1548 }
1549
1550 spin_lock_irqsave(&pl330->lock, flags);
1551
1552 if (_queue_full(thrd)) {
1553 ret = -EAGAIN;
1554 goto xfer_exit;
1555 }
1556
Boojin Kimb7d861d2011-12-26 18:49:52 +09001557
1558 /* Use last settings, if not provided */
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301559 if (r->cfg) {
1560 /* Prefer Secure Channel */
1561 if (!_manager_ns(thrd))
1562 r->cfg->nonsecure = 0;
1563 else
1564 r->cfg->nonsecure = 1;
1565
Boojin Kimb7d861d2011-12-26 18:49:52 +09001566 ccr = _prepare_ccr(r->cfg);
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301567 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001568 ccr = readl(regs + CC(thrd->id));
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301569 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001570
1571 /* If this req doesn't have valid xfer settings */
1572 if (!_is_valid(ccr)) {
1573 ret = -EINVAL;
1574 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1575 __func__, __LINE__, ccr);
1576 goto xfer_exit;
1577 }
1578
1579 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1580
1581 xs.ccr = ccr;
1582 xs.r = r;
1583
1584 /* First dry run to check if req is acceptable */
1585 ret = _setup_req(1, thrd, idx, &xs);
1586 if (ret < 0)
1587 goto xfer_exit;
1588
1589 if (ret > pi->mcbufsz / 2) {
1590 dev_info(thrd->dmac->pinfo->dev,
1591 "%s:%d Trying increasing mcbufsz\n",
1592 __func__, __LINE__);
1593 ret = -ENOMEM;
1594 goto xfer_exit;
1595 }
1596
1597 /* Hook the request */
1598 thrd->lstenq = idx;
1599 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1600 thrd->req[idx].r = r;
1601
1602 ret = 0;
1603
1604xfer_exit:
1605 spin_unlock_irqrestore(&pl330->lock, flags);
1606
1607 return ret;
1608}
1609
1610static void pl330_dotask(unsigned long data)
1611{
1612 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1613 struct pl330_info *pi = pl330->pinfo;
1614 unsigned long flags;
1615 int i;
1616
1617 spin_lock_irqsave(&pl330->lock, flags);
1618
1619 /* The DMAC itself gone nuts */
1620 if (pl330->dmac_tbd.reset_dmac) {
1621 pl330->state = DYING;
1622 /* Reset the manager too */
1623 pl330->dmac_tbd.reset_mngr = true;
1624 /* Clear the reset flag */
1625 pl330->dmac_tbd.reset_dmac = false;
1626 }
1627
1628 if (pl330->dmac_tbd.reset_mngr) {
1629 _stop(pl330->manager);
1630 /* Reset all channels */
1631 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1632 /* Clear the reset flag */
1633 pl330->dmac_tbd.reset_mngr = false;
1634 }
1635
1636 for (i = 0; i < pi->pcfg.num_chan; i++) {
1637
1638 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1639 struct pl330_thread *thrd = &pl330->channels[i];
1640 void __iomem *regs = pi->base;
1641 enum pl330_op_err err;
1642
1643 _stop(thrd);
1644
1645 if (readl(regs + FSC) & (1 << thrd->id))
1646 err = PL330_ERR_FAIL;
1647 else
1648 err = PL330_ERR_ABORT;
1649
1650 spin_unlock_irqrestore(&pl330->lock, flags);
1651
1652 _callback(thrd->req[1 - thrd->lstenq].r, err);
1653 _callback(thrd->req[thrd->lstenq].r, err);
1654
1655 spin_lock_irqsave(&pl330->lock, flags);
1656
1657 thrd->req[0].r = NULL;
1658 thrd->req[1].r = NULL;
1659 mark_free(thrd, 0);
1660 mark_free(thrd, 1);
1661
1662 /* Clear the reset flag */
1663 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1664 }
1665 }
1666
1667 spin_unlock_irqrestore(&pl330->lock, flags);
1668
1669 return;
1670}
1671
1672/* Returns 1 if state was updated, 0 otherwise */
1673static int pl330_update(const struct pl330_info *pi)
1674{
Javi Merinofdec53d2012-06-13 15:07:00 +01001675 struct pl330_req *rqdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001676 struct pl330_dmac *pl330;
1677 unsigned long flags;
1678 void __iomem *regs;
1679 u32 val;
1680 int id, ev, ret = 0;
1681
1682 if (!pi || !pi->pl330_data)
1683 return 0;
1684
1685 regs = pi->base;
1686 pl330 = pi->pl330_data;
1687
1688 spin_lock_irqsave(&pl330->lock, flags);
1689
1690 val = readl(regs + FSM) & 0x1;
1691 if (val)
1692 pl330->dmac_tbd.reset_mngr = true;
1693 else
1694 pl330->dmac_tbd.reset_mngr = false;
1695
1696 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1697 pl330->dmac_tbd.reset_chan |= val;
1698 if (val) {
1699 int i = 0;
1700 while (i < pi->pcfg.num_chan) {
1701 if (val & (1 << i)) {
1702 dev_info(pi->dev,
1703 "Reset Channel-%d\t CS-%x FTC-%x\n",
1704 i, readl(regs + CS(i)),
1705 readl(regs + FTC(i)));
1706 _stop(&pl330->channels[i]);
1707 }
1708 i++;
1709 }
1710 }
1711
1712 /* Check which event happened i.e, thread notified */
1713 val = readl(regs + ES);
1714 if (pi->pcfg.num_events < 32
1715 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1716 pl330->dmac_tbd.reset_dmac = true;
1717 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1718 ret = 1;
1719 goto updt_exit;
1720 }
1721
1722 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1723 if (val & (1 << ev)) { /* Event occurred */
1724 struct pl330_thread *thrd;
1725 u32 inten = readl(regs + INTEN);
1726 int active;
1727
1728 /* Clear the event */
1729 if (inten & (1 << ev))
1730 writel(1 << ev, regs + INTCLR);
1731
1732 ret = 1;
1733
1734 id = pl330->events[ev];
1735
1736 thrd = &pl330->channels[id];
1737
1738 active = thrd->req_running;
1739 if (active == -1) /* Aborted */
1740 continue;
1741
Javi Merinofdec53d2012-06-13 15:07:00 +01001742 /* Detach the req */
1743 rqdone = thrd->req[active].r;
1744 thrd->req[active].r = NULL;
1745
Boojin Kimb7d861d2011-12-26 18:49:52 +09001746 mark_free(thrd, active);
1747
1748 /* Get going again ASAP */
1749 _start(thrd);
1750
1751 /* For now, just make a list of callbacks to be done */
1752 list_add_tail(&rqdone->rqd, &pl330->req_done);
1753 }
1754 }
1755
1756 /* Now that we are in no hurry, do the callbacks */
Javi Merinofdec53d2012-06-13 15:07:00 +01001757 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1758 list_del(&rqdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001759
1760 spin_unlock_irqrestore(&pl330->lock, flags);
Javi Merinofdec53d2012-06-13 15:07:00 +01001761 _callback(rqdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001762 spin_lock_irqsave(&pl330->lock, flags);
1763 }
1764
1765updt_exit:
1766 spin_unlock_irqrestore(&pl330->lock, flags);
1767
1768 if (pl330->dmac_tbd.reset_dmac
1769 || pl330->dmac_tbd.reset_mngr
1770 || pl330->dmac_tbd.reset_chan) {
1771 ret = 1;
1772 tasklet_schedule(&pl330->tasks);
1773 }
1774
1775 return ret;
1776}
1777
1778static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1779{
1780 struct pl330_thread *thrd = ch_id;
1781 struct pl330_dmac *pl330;
1782 unsigned long flags;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001783 int ret = 0, active;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001784
1785 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1786 return -EINVAL;
1787
1788 pl330 = thrd->dmac;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001789 active = thrd->req_running;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001790
1791 spin_lock_irqsave(&pl330->lock, flags);
1792
1793 switch (op) {
1794 case PL330_OP_FLUSH:
1795 /* Make sure the channel is stopped */
1796 _stop(thrd);
1797
1798 thrd->req[0].r = NULL;
1799 thrd->req[1].r = NULL;
1800 mark_free(thrd, 0);
1801 mark_free(thrd, 1);
1802 break;
1803
1804 case PL330_OP_ABORT:
1805 /* Make sure the channel is stopped */
1806 _stop(thrd);
1807
1808 /* ABORT is only for the active req */
1809 if (active == -1)
1810 break;
1811
1812 thrd->req[active].r = NULL;
1813 mark_free(thrd, active);
1814
1815 /* Start the next */
1816 case PL330_OP_START:
1817 if ((active == -1) && !_start(thrd))
1818 ret = -EIO;
1819 break;
1820
1821 default:
1822 ret = -EINVAL;
1823 }
1824
1825 spin_unlock_irqrestore(&pl330->lock, flags);
1826 return ret;
1827}
1828
Boojin Kimb7d861d2011-12-26 18:49:52 +09001829/* Reserve an event */
1830static inline int _alloc_event(struct pl330_thread *thrd)
1831{
1832 struct pl330_dmac *pl330 = thrd->dmac;
1833 struct pl330_info *pi = pl330->pinfo;
1834 int ev;
1835
1836 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1837 if (pl330->events[ev] == -1) {
1838 pl330->events[ev] = thrd->id;
1839 return ev;
1840 }
1841
1842 return -1;
1843}
1844
1845static bool _chan_ns(const struct pl330_info *pi, int i)
1846{
1847 return pi->pcfg.irq_ns & (1 << i);
1848}
1849
1850/* Upon success, returns IdentityToken for the
1851 * allocated channel, NULL otherwise.
1852 */
1853static void *pl330_request_channel(const struct pl330_info *pi)
1854{
1855 struct pl330_thread *thrd = NULL;
1856 struct pl330_dmac *pl330;
1857 unsigned long flags;
1858 int chans, i;
1859
1860 if (!pi || !pi->pl330_data)
1861 return NULL;
1862
1863 pl330 = pi->pl330_data;
1864
1865 if (pl330->state == DYING)
1866 return NULL;
1867
1868 chans = pi->pcfg.num_chan;
1869
1870 spin_lock_irqsave(&pl330->lock, flags);
1871
1872 for (i = 0; i < chans; i++) {
1873 thrd = &pl330->channels[i];
1874 if ((thrd->free) && (!_manager_ns(thrd) ||
1875 _chan_ns(pi, i))) {
1876 thrd->ev = _alloc_event(thrd);
1877 if (thrd->ev >= 0) {
1878 thrd->free = false;
1879 thrd->lstenq = 1;
1880 thrd->req[0].r = NULL;
1881 mark_free(thrd, 0);
1882 thrd->req[1].r = NULL;
1883 mark_free(thrd, 1);
1884 break;
1885 }
1886 }
1887 thrd = NULL;
1888 }
1889
1890 spin_unlock_irqrestore(&pl330->lock, flags);
1891
1892 return thrd;
1893}
1894
1895/* Release an event */
1896static inline void _free_event(struct pl330_thread *thrd, int ev)
1897{
1898 struct pl330_dmac *pl330 = thrd->dmac;
1899 struct pl330_info *pi = pl330->pinfo;
1900
1901 /* If the event is valid and was held by the thread */
1902 if (ev >= 0 && ev < pi->pcfg.num_events
1903 && pl330->events[ev] == thrd->id)
1904 pl330->events[ev] = -1;
1905}
1906
1907static void pl330_release_channel(void *ch_id)
1908{
1909 struct pl330_thread *thrd = ch_id;
1910 struct pl330_dmac *pl330;
1911 unsigned long flags;
1912
1913 if (!thrd || thrd->free)
1914 return;
1915
1916 _stop(thrd);
1917
1918 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1919 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1920
1921 pl330 = thrd->dmac;
1922
1923 spin_lock_irqsave(&pl330->lock, flags);
1924 _free_event(thrd, thrd->ev);
1925 thrd->free = true;
1926 spin_unlock_irqrestore(&pl330->lock, flags);
1927}
1928
1929/* Initialize the structure for PL330 configuration, that can be used
1930 * by the client driver the make best use of the DMAC
1931 */
1932static void read_dmac_config(struct pl330_info *pi)
1933{
1934 void __iomem *regs = pi->base;
1935 u32 val;
1936
1937 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1938 val &= CRD_DATA_WIDTH_MASK;
1939 pi->pcfg.data_bus_width = 8 * (1 << val);
1940
1941 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1942 val &= CRD_DATA_BUFF_MASK;
1943 pi->pcfg.data_buf_dep = val + 1;
1944
1945 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1946 val &= CR0_NUM_CHANS_MASK;
1947 val += 1;
1948 pi->pcfg.num_chan = val;
1949
1950 val = readl(regs + CR0);
1951 if (val & CR0_PERIPH_REQ_SET) {
1952 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1953 val += 1;
1954 pi->pcfg.num_peri = val;
1955 pi->pcfg.peri_ns = readl(regs + CR4);
1956 } else {
1957 pi->pcfg.num_peri = 0;
1958 }
1959
1960 val = readl(regs + CR0);
1961 if (val & CR0_BOOT_MAN_NS)
1962 pi->pcfg.mode |= DMAC_MODE_NS;
1963 else
1964 pi->pcfg.mode &= ~DMAC_MODE_NS;
1965
1966 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1967 val &= CR0_NUM_EVENTS_MASK;
1968 val += 1;
1969 pi->pcfg.num_events = val;
1970
1971 pi->pcfg.irq_ns = readl(regs + CR3);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001972}
1973
1974static inline void _reset_thread(struct pl330_thread *thrd)
1975{
1976 struct pl330_dmac *pl330 = thrd->dmac;
1977 struct pl330_info *pi = pl330->pinfo;
1978
1979 thrd->req[0].mc_cpu = pl330->mcode_cpu
1980 + (thrd->id * pi->mcbufsz);
1981 thrd->req[0].mc_bus = pl330->mcode_bus
1982 + (thrd->id * pi->mcbufsz);
1983 thrd->req[0].r = NULL;
1984 mark_free(thrd, 0);
1985
1986 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1987 + pi->mcbufsz / 2;
1988 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1989 + pi->mcbufsz / 2;
1990 thrd->req[1].r = NULL;
1991 mark_free(thrd, 1);
1992}
1993
1994static int dmac_alloc_threads(struct pl330_dmac *pl330)
1995{
1996 struct pl330_info *pi = pl330->pinfo;
1997 int chans = pi->pcfg.num_chan;
1998 struct pl330_thread *thrd;
1999 int i;
2000
2001 /* Allocate 1 Manager and 'chans' Channel threads */
2002 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
2003 GFP_KERNEL);
2004 if (!pl330->channels)
2005 return -ENOMEM;
2006
2007 /* Init Channel threads */
2008 for (i = 0; i < chans; i++) {
2009 thrd = &pl330->channels[i];
2010 thrd->id = i;
2011 thrd->dmac = pl330;
2012 _reset_thread(thrd);
2013 thrd->free = true;
2014 }
2015
2016 /* MANAGER is indexed at the end */
2017 thrd = &pl330->channels[chans];
2018 thrd->id = chans;
2019 thrd->dmac = pl330;
2020 thrd->free = false;
2021 pl330->manager = thrd;
2022
2023 return 0;
2024}
2025
2026static int dmac_alloc_resources(struct pl330_dmac *pl330)
2027{
2028 struct pl330_info *pi = pl330->pinfo;
2029 int chans = pi->pcfg.num_chan;
2030 int ret;
2031
2032 /*
2033 * Alloc MicroCode buffer for 'chans' Channel threads.
2034 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2035 */
2036 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
2037 chans * pi->mcbufsz,
2038 &pl330->mcode_bus, GFP_KERNEL);
2039 if (!pl330->mcode_cpu) {
2040 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2041 __func__, __LINE__);
2042 return -ENOMEM;
2043 }
2044
2045 ret = dmac_alloc_threads(pl330);
2046 if (ret) {
2047 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
2048 __func__, __LINE__);
2049 dma_free_coherent(pi->dev,
2050 chans * pi->mcbufsz,
2051 pl330->mcode_cpu, pl330->mcode_bus);
2052 return ret;
2053 }
2054
2055 return 0;
2056}
2057
2058static int pl330_add(struct pl330_info *pi)
2059{
2060 struct pl330_dmac *pl330;
2061 void __iomem *regs;
2062 int i, ret;
2063
2064 if (!pi || !pi->dev)
2065 return -EINVAL;
2066
2067 /* If already added */
2068 if (pi->pl330_data)
2069 return -EINVAL;
2070
2071 /*
2072 * If the SoC can perform reset on the DMAC, then do it
2073 * before reading its configuration.
2074 */
2075 if (pi->dmac_reset)
2076 pi->dmac_reset(pi);
2077
2078 regs = pi->base;
2079
2080 /* Check if we can handle this DMAC */
Will Deacon09677172013-06-10 19:34:37 +01002081 if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
2082 dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id);
Boojin Kimb7d861d2011-12-26 18:49:52 +09002083 return -EINVAL;
2084 }
2085
2086 /* Read the configuration of the DMAC */
2087 read_dmac_config(pi);
2088
2089 if (pi->pcfg.num_events == 0) {
2090 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2091 __func__, __LINE__);
2092 return -EINVAL;
2093 }
2094
2095 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2096 if (!pl330) {
2097 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2098 __func__, __LINE__);
2099 return -ENOMEM;
2100 }
2101
2102 /* Assign the info structure and private data */
2103 pl330->pinfo = pi;
2104 pi->pl330_data = pl330;
2105
2106 spin_lock_init(&pl330->lock);
2107
2108 INIT_LIST_HEAD(&pl330->req_done);
2109
2110 /* Use default MC buffer size if not provided */
2111 if (!pi->mcbufsz)
2112 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2113
2114 /* Mark all events as free */
2115 for (i = 0; i < pi->pcfg.num_events; i++)
2116 pl330->events[i] = -1;
2117
2118 /* Allocate resources needed by the DMAC */
2119 ret = dmac_alloc_resources(pl330);
2120 if (ret) {
2121 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2122 kfree(pl330);
2123 return ret;
2124 }
2125
2126 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2127
2128 pl330->state = INIT;
2129
2130 return 0;
2131}
2132
2133static int dmac_free_threads(struct pl330_dmac *pl330)
2134{
2135 struct pl330_info *pi = pl330->pinfo;
2136 int chans = pi->pcfg.num_chan;
2137 struct pl330_thread *thrd;
2138 int i;
2139
2140 /* Release Channel threads */
2141 for (i = 0; i < chans; i++) {
2142 thrd = &pl330->channels[i];
2143 pl330_release_channel((void *)thrd);
2144 }
2145
2146 /* Free memory */
2147 kfree(pl330->channels);
2148
2149 return 0;
2150}
2151
2152static void dmac_free_resources(struct pl330_dmac *pl330)
2153{
2154 struct pl330_info *pi = pl330->pinfo;
2155 int chans = pi->pcfg.num_chan;
2156
2157 dmac_free_threads(pl330);
2158
2159 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2160 pl330->mcode_cpu, pl330->mcode_bus);
2161}
2162
2163static void pl330_del(struct pl330_info *pi)
2164{
2165 struct pl330_dmac *pl330;
2166
2167 if (!pi || !pi->pl330_data)
2168 return;
2169
2170 pl330 = pi->pl330_data;
2171
2172 pl330->state = UNINIT;
2173
2174 tasklet_kill(&pl330->tasks);
2175
2176 /* Free DMAC resources */
2177 dmac_free_resources(pl330);
2178
2179 kfree(pl330);
2180 pi->pl330_data = NULL;
2181}
2182
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002183/* forward declaration */
2184static struct amba_driver pl330_driver;
2185
Jassi Brarb3040e42010-05-23 20:28:19 -07002186static inline struct dma_pl330_chan *
2187to_pchan(struct dma_chan *ch)
2188{
2189 if (!ch)
2190 return NULL;
2191
2192 return container_of(ch, struct dma_pl330_chan, chan);
2193}
2194
2195static inline struct dma_pl330_desc *
2196to_desc(struct dma_async_tx_descriptor *tx)
2197{
2198 return container_of(tx, struct dma_pl330_desc, txd);
2199}
2200
2201static inline void free_desc_list(struct list_head *list)
2202{
2203 struct dma_pl330_dmac *pdmac;
2204 struct dma_pl330_desc *desc;
Olof Johanssonc8473822012-04-08 16:26:19 -07002205 struct dma_pl330_chan *pch = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002206 unsigned long flags;
2207
Jassi Brarb3040e42010-05-23 20:28:19 -07002208 /* Finish off the work list */
2209 list_for_each_entry(desc, list, node) {
2210 dma_async_tx_callback callback;
2211 void *param;
2212
2213 /* All desc in a list belong to same channel */
2214 pch = desc->pchan;
2215 callback = desc->txd.callback;
2216 param = desc->txd.callback_param;
2217
2218 if (callback)
2219 callback(param);
2220
2221 desc->pchan = NULL;
2222 }
2223
Olof Johanssonc8473822012-04-08 16:26:19 -07002224 /* pch will be unset if list was empty */
2225 if (!pch)
2226 return;
2227
Jassi Brarb3040e42010-05-23 20:28:19 -07002228 pdmac = pch->dmac;
2229
2230 spin_lock_irqsave(&pdmac->pool_lock, flags);
2231 list_splice_tail_init(list, &pdmac->desc_pool);
2232 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2233}
2234
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002235static inline void handle_cyclic_desc_list(struct list_head *list)
2236{
2237 struct dma_pl330_desc *desc;
Olof Johanssonc8473822012-04-08 16:26:19 -07002238 struct dma_pl330_chan *pch = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002239 unsigned long flags;
2240
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002241 list_for_each_entry(desc, list, node) {
2242 dma_async_tx_callback callback;
2243
2244 /* Change status to reload it */
2245 desc->status = PREP;
2246 pch = desc->pchan;
2247 callback = desc->txd.callback;
2248 if (callback)
2249 callback(desc->txd.callback_param);
2250 }
2251
Olof Johanssonc8473822012-04-08 16:26:19 -07002252 /* pch will be unset if list was empty */
2253 if (!pch)
2254 return;
2255
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002256 spin_lock_irqsave(&pch->lock, flags);
2257 list_splice_tail_init(list, &pch->work_list);
2258 spin_unlock_irqrestore(&pch->lock, flags);
2259}
2260
Jassi Brarb3040e42010-05-23 20:28:19 -07002261static inline void fill_queue(struct dma_pl330_chan *pch)
2262{
2263 struct dma_pl330_desc *desc;
2264 int ret;
2265
2266 list_for_each_entry(desc, &pch->work_list, node) {
2267
2268 /* If already submitted */
2269 if (desc->status == BUSY)
Jassi Brar30fb9802013-02-13 16:13:14 +05302270 continue;
Jassi Brarb3040e42010-05-23 20:28:19 -07002271
2272 ret = pl330_submit_req(pch->pl330_chid,
2273 &desc->req);
2274 if (!ret) {
2275 desc->status = BUSY;
Jassi Brarb3040e42010-05-23 20:28:19 -07002276 } else if (ret == -EAGAIN) {
2277 /* QFull or DMAC Dying */
2278 break;
2279 } else {
2280 /* Unacceptable request */
2281 desc->status = DONE;
2282 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2283 __func__, __LINE__, desc->txd.cookie);
2284 tasklet_schedule(&pch->task);
2285 }
2286 }
2287}
2288
2289static void pl330_tasklet(unsigned long data)
2290{
2291 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2292 struct dma_pl330_desc *desc, *_dt;
2293 unsigned long flags;
2294 LIST_HEAD(list);
2295
2296 spin_lock_irqsave(&pch->lock, flags);
2297
2298 /* Pick up ripe tomatoes */
2299 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2300 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05302301 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05302302 dma_cookie_complete(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002303 list_move_tail(&desc->node, &list);
2304 }
2305
2306 /* Try to submit a req imm. next to the last completed cookie */
2307 fill_queue(pch);
2308
2309 /* Make sure the PL330 Channel thread is active */
2310 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2311
2312 spin_unlock_irqrestore(&pch->lock, flags);
2313
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002314 if (pch->cyclic)
2315 handle_cyclic_desc_list(&list);
2316 else
2317 free_desc_list(&list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002318}
2319
2320static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2321{
2322 struct dma_pl330_desc *desc = token;
2323 struct dma_pl330_chan *pch = desc->pchan;
2324 unsigned long flags;
2325
2326 /* If desc aborted */
2327 if (!pch)
2328 return;
2329
2330 spin_lock_irqsave(&pch->lock, flags);
2331
2332 desc->status = DONE;
2333
2334 spin_unlock_irqrestore(&pch->lock, flags);
2335
2336 tasklet_schedule(&pch->task);
2337}
2338
Padmavathi Venna34d19352013-02-14 09:10:05 +05302339static bool pl330_dt_filter(struct dma_chan *chan, void *param)
2340{
2341 struct dma_pl330_filter_args *fargs = param;
2342
2343 if (chan->device != &fargs->pdmac->ddma)
2344 return false;
2345
2346 return (chan->chan_id == fargs->chan_id);
2347}
2348
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002349bool pl330_filter(struct dma_chan *chan, void *param)
2350{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002351 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002352
2353 if (chan->device->dev->driver != &pl330_driver.drv)
2354 return false;
2355
Thomas Abrahamcd072512011-10-24 11:43:11 +02002356 peri_id = chan->private;
2357 return *peri_id == (unsigned)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002358}
2359EXPORT_SYMBOL(pl330_filter);
2360
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302361static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2362 struct of_dma *ofdma)
2363{
2364 int count = dma_spec->args_count;
2365 struct dma_pl330_dmac *pdmac = ofdma->of_dma_data;
2366 struct dma_pl330_filter_args fargs;
2367 dma_cap_mask_t cap;
2368
2369 if (!pdmac)
2370 return NULL;
2371
2372 if (count != 1)
2373 return NULL;
2374
2375 fargs.pdmac = pdmac;
2376 fargs.chan_id = dma_spec->args[0];
2377
2378 dma_cap_zero(cap);
2379 dma_cap_set(DMA_SLAVE, cap);
2380 dma_cap_set(DMA_CYCLIC, cap);
2381
2382 return dma_request_channel(cap, pl330_dt_filter, &fargs);
2383}
2384
Jassi Brarb3040e42010-05-23 20:28:19 -07002385static int pl330_alloc_chan_resources(struct dma_chan *chan)
2386{
2387 struct dma_pl330_chan *pch = to_pchan(chan);
2388 struct dma_pl330_dmac *pdmac = pch->dmac;
2389 unsigned long flags;
2390
2391 spin_lock_irqsave(&pch->lock, flags);
2392
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002393 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002394 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002395
2396 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2397 if (!pch->pl330_chid) {
2398 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302399 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002400 }
2401
2402 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2403
2404 spin_unlock_irqrestore(&pch->lock, flags);
2405
2406 return 1;
2407}
2408
2409static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2410{
2411 struct dma_pl330_chan *pch = to_pchan(chan);
Boojin Kimae43b882011-09-02 09:44:32 +09002412 struct dma_pl330_desc *desc, *_dt;
Jassi Brarb3040e42010-05-23 20:28:19 -07002413 unsigned long flags;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002414 struct dma_pl330_dmac *pdmac = pch->dmac;
2415 struct dma_slave_config *slave_config;
Boojin Kimae43b882011-09-02 09:44:32 +09002416 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002417
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002418 switch (cmd) {
2419 case DMA_TERMINATE_ALL:
2420 spin_lock_irqsave(&pch->lock, flags);
2421
2422 /* FLUSH the PL330 Channel thread */
2423 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2424
2425 /* Mark all desc done */
Boojin Kimae43b882011-09-02 09:44:32 +09002426 list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002427 desc->status = DONE;
Boojin Kimae43b882011-09-02 09:44:32 +09002428 list_move_tail(&desc->node, &list);
2429 }
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002430
Boojin Kimae43b882011-09-02 09:44:32 +09002431 list_splice_tail_init(&list, &pdmac->desc_pool);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002432 spin_unlock_irqrestore(&pch->lock, flags);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002433 break;
2434 case DMA_SLAVE_CONFIG:
2435 slave_config = (struct dma_slave_config *)arg;
2436
Vinod Kouldb8196d2011-10-13 22:34:23 +05302437 if (slave_config->direction == DMA_MEM_TO_DEV) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002438 if (slave_config->dst_addr)
2439 pch->fifo_addr = slave_config->dst_addr;
2440 if (slave_config->dst_addr_width)
2441 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2442 if (slave_config->dst_maxburst)
2443 pch->burst_len = slave_config->dst_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302444 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002445 if (slave_config->src_addr)
2446 pch->fifo_addr = slave_config->src_addr;
2447 if (slave_config->src_addr_width)
2448 pch->burst_sz = __ffs(slave_config->src_addr_width);
2449 if (slave_config->src_maxburst)
2450 pch->burst_len = slave_config->src_maxburst;
2451 }
2452 break;
2453 default:
2454 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
Jassi Brarb3040e42010-05-23 20:28:19 -07002455 return -ENXIO;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002456 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002457
2458 return 0;
2459}
2460
2461static void pl330_free_chan_resources(struct dma_chan *chan)
2462{
2463 struct dma_pl330_chan *pch = to_pchan(chan);
2464 unsigned long flags;
2465
Jassi Brarb3040e42010-05-23 20:28:19 -07002466 tasklet_kill(&pch->task);
2467
Bartlomiej Zolnierkiewiczda331ba2013-07-03 15:00:43 -07002468 spin_lock_irqsave(&pch->lock, flags);
2469
Jassi Brarb3040e42010-05-23 20:28:19 -07002470 pl330_release_channel(pch->pl330_chid);
2471 pch->pl330_chid = NULL;
2472
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002473 if (pch->cyclic)
2474 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2475
Jassi Brarb3040e42010-05-23 20:28:19 -07002476 spin_unlock_irqrestore(&pch->lock, flags);
2477}
2478
2479static enum dma_status
2480pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2481 struct dma_tx_state *txstate)
2482{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002483 return dma_cookie_status(chan, cookie, txstate);
Jassi Brarb3040e42010-05-23 20:28:19 -07002484}
2485
2486static void pl330_issue_pending(struct dma_chan *chan)
2487{
2488 pl330_tasklet((unsigned long) to_pchan(chan));
2489}
2490
2491/*
2492 * We returned the last one of the circular list of descriptor(s)
2493 * from prep_xxx, so the argument to submit corresponds to the last
2494 * descriptor of the list.
2495 */
2496static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2497{
2498 struct dma_pl330_desc *desc, *last = to_desc(tx);
2499 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2500 dma_cookie_t cookie;
2501 unsigned long flags;
2502
2503 spin_lock_irqsave(&pch->lock, flags);
2504
2505 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002506 while (!list_empty(&last->node)) {
2507 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2508
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002509 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002510
2511 list_move_tail(&desc->node, &pch->work_list);
2512 }
2513
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002514 cookie = dma_cookie_assign(&last->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002515 list_add_tail(&last->node, &pch->work_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002516 spin_unlock_irqrestore(&pch->lock, flags);
2517
2518 return cookie;
2519}
2520
2521static inline void _init_desc(struct dma_pl330_desc *desc)
2522{
2523 desc->pchan = NULL;
2524 desc->req.x = &desc->px;
2525 desc->req.token = desc;
2526 desc->rqcfg.swap = SWAP_NO;
2527 desc->rqcfg.privileged = 0;
2528 desc->rqcfg.insnaccess = 0;
2529 desc->rqcfg.scctl = SCCTRL0;
2530 desc->rqcfg.dcctl = DCCTRL0;
2531 desc->req.cfg = &desc->rqcfg;
2532 desc->req.xfer_cb = dma_pl330_rqcb;
2533 desc->txd.tx_submit = pl330_tx_submit;
2534
2535 INIT_LIST_HEAD(&desc->node);
2536}
2537
2538/* Returns the number of descriptors added to the DMAC pool */
Sachin Kamat5a67ac52012-06-04 17:09:45 +05302539static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002540{
2541 struct dma_pl330_desc *desc;
2542 unsigned long flags;
2543 int i;
2544
2545 if (!pdmac)
2546 return 0;
2547
2548 desc = kmalloc(count * sizeof(*desc), flg);
2549 if (!desc)
2550 return 0;
2551
2552 spin_lock_irqsave(&pdmac->pool_lock, flags);
2553
2554 for (i = 0; i < count; i++) {
2555 _init_desc(&desc[i]);
2556 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2557 }
2558
2559 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2560
2561 return count;
2562}
2563
2564static struct dma_pl330_desc *
2565pluck_desc(struct dma_pl330_dmac *pdmac)
2566{
2567 struct dma_pl330_desc *desc = NULL;
2568 unsigned long flags;
2569
2570 if (!pdmac)
2571 return NULL;
2572
2573 spin_lock_irqsave(&pdmac->pool_lock, flags);
2574
2575 if (!list_empty(&pdmac->desc_pool)) {
2576 desc = list_entry(pdmac->desc_pool.next,
2577 struct dma_pl330_desc, node);
2578
2579 list_del_init(&desc->node);
2580
2581 desc->status = PREP;
2582 desc->txd.callback = NULL;
2583 }
2584
2585 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2586
2587 return desc;
2588}
2589
2590static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2591{
2592 struct dma_pl330_dmac *pdmac = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002593 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002594 struct dma_pl330_desc *desc;
2595
2596 /* Pluck one desc from the pool of DMAC */
2597 desc = pluck_desc(pdmac);
2598
2599 /* If the DMAC pool is empty, alloc new */
2600 if (!desc) {
2601 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2602 return NULL;
2603
2604 /* Try again */
2605 desc = pluck_desc(pdmac);
2606 if (!desc) {
2607 dev_err(pch->dmac->pif.dev,
2608 "%s:%d ALERT!\n", __func__, __LINE__);
2609 return NULL;
2610 }
2611 }
2612
2613 /* Initialize the descriptor */
2614 desc->pchan = pch;
2615 desc->txd.cookie = 0;
2616 async_tx_ack(&desc->txd);
2617
Thomas Abrahamcd072512011-10-24 11:43:11 +02002618 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09002619 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002620
2621 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2622
2623 return desc;
2624}
2625
2626static inline void fill_px(struct pl330_xfer *px,
2627 dma_addr_t dst, dma_addr_t src, size_t len)
2628{
2629 px->next = NULL;
2630 px->bytes = len;
2631 px->dst_addr = dst;
2632 px->src_addr = src;
2633}
2634
2635static struct dma_pl330_desc *
2636__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2637 dma_addr_t src, size_t len)
2638{
2639 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2640
2641 if (!desc) {
2642 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2643 __func__, __LINE__);
2644 return NULL;
2645 }
2646
2647 /*
2648 * Ideally we should lookout for reqs bigger than
2649 * those that can be programmed with 256 bytes of
2650 * MC buffer, but considering a req size is seldom
2651 * going to be word-unaligned and more than 200MB,
2652 * we take it easy.
2653 * Also, should the limit is reached we'd rather
2654 * have the platform increase MC buffer size than
2655 * complicating this API driver.
2656 */
2657 fill_px(&desc->px, dst, src, len);
2658
2659 return desc;
2660}
2661
2662/* Call after fixing burst size */
2663static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2664{
2665 struct dma_pl330_chan *pch = desc->pchan;
2666 struct pl330_info *pi = &pch->dmac->pif;
2667 int burst_len;
2668
2669 burst_len = pi->pcfg.data_bus_width / 8;
2670 burst_len *= pi->pcfg.data_buf_dep;
2671 burst_len >>= desc->rqcfg.brst_size;
2672
2673 /* src/dst_burst_len can't be more than 16 */
2674 if (burst_len > 16)
2675 burst_len = 16;
2676
2677 while (burst_len > 1) {
2678 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2679 break;
2680 burst_len--;
2681 }
2682
2683 return burst_len;
2684}
2685
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002686static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2687 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002688 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +03002689 unsigned long flags, void *context)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002690{
2691 struct dma_pl330_desc *desc;
2692 struct dma_pl330_chan *pch = to_pchan(chan);
2693 dma_addr_t dst;
2694 dma_addr_t src;
2695
2696 desc = pl330_get_desc(pch);
2697 if (!desc) {
2698 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2699 __func__, __LINE__);
2700 return NULL;
2701 }
2702
2703 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +05302704 case DMA_MEM_TO_DEV:
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002705 desc->rqcfg.src_inc = 1;
2706 desc->rqcfg.dst_inc = 0;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002707 desc->req.rqtype = MEMTODEV;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002708 src = dma_addr;
2709 dst = pch->fifo_addr;
2710 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302711 case DMA_DEV_TO_MEM:
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002712 desc->rqcfg.src_inc = 0;
2713 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002714 desc->req.rqtype = DEVTOMEM;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002715 src = pch->fifo_addr;
2716 dst = dma_addr;
2717 break;
2718 default:
2719 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2720 __func__, __LINE__);
2721 return NULL;
2722 }
2723
2724 desc->rqcfg.brst_size = pch->burst_sz;
2725 desc->rqcfg.brst_len = 1;
2726
2727 pch->cyclic = true;
2728
2729 fill_px(&desc->px, dst, src, period_len);
2730
2731 return &desc->txd;
2732}
2733
Jassi Brarb3040e42010-05-23 20:28:19 -07002734static struct dma_async_tx_descriptor *
2735pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2736 dma_addr_t src, size_t len, unsigned long flags)
2737{
2738 struct dma_pl330_desc *desc;
2739 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002740 struct pl330_info *pi;
2741 int burst;
2742
Rob Herring4e0e6102011-07-25 16:05:04 -05002743 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002744 return NULL;
2745
Jassi Brarb3040e42010-05-23 20:28:19 -07002746 pi = &pch->dmac->pif;
2747
2748 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2749 if (!desc)
2750 return NULL;
2751
2752 desc->rqcfg.src_inc = 1;
2753 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002754 desc->req.rqtype = MEMTOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002755
2756 /* Select max possible burst size */
2757 burst = pi->pcfg.data_bus_width / 8;
2758
2759 while (burst > 1) {
2760 if (!(len % burst))
2761 break;
2762 burst /= 2;
2763 }
2764
2765 desc->rqcfg.brst_size = 0;
2766 while (burst != (1 << desc->rqcfg.brst_size))
2767 desc->rqcfg.brst_size++;
2768
2769 desc->rqcfg.brst_len = get_burst_len(desc, len);
2770
2771 desc->txd.flags = flags;
2772
2773 return &desc->txd;
2774}
2775
2776static struct dma_async_tx_descriptor *
2777pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302778 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002779 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002780{
2781 struct dma_pl330_desc *first, *desc = NULL;
2782 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002783 struct scatterlist *sg;
2784 unsigned long flags;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002785 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002786 dma_addr_t addr;
2787
Thomas Abrahamcd072512011-10-24 11:43:11 +02002788 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002789 return NULL;
2790
Boojin Kim1b9bb712011-09-02 09:44:30 +09002791 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002792
2793 first = NULL;
2794
2795 for_each_sg(sgl, sg, sg_len, i) {
2796
2797 desc = pl330_get_desc(pch);
2798 if (!desc) {
2799 struct dma_pl330_dmac *pdmac = pch->dmac;
2800
2801 dev_err(pch->dmac->pif.dev,
2802 "%s:%d Unable to fetch desc\n",
2803 __func__, __LINE__);
2804 if (!first)
2805 return NULL;
2806
2807 spin_lock_irqsave(&pdmac->pool_lock, flags);
2808
2809 while (!list_empty(&first->node)) {
2810 desc = list_entry(first->node.next,
2811 struct dma_pl330_desc, node);
2812 list_move_tail(&desc->node, &pdmac->desc_pool);
2813 }
2814
2815 list_move_tail(&first->node, &pdmac->desc_pool);
2816
2817 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2818
2819 return NULL;
2820 }
2821
2822 if (!first)
2823 first = desc;
2824 else
2825 list_add_tail(&desc->node, &first->node);
2826
Vinod Kouldb8196d2011-10-13 22:34:23 +05302827 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002828 desc->rqcfg.src_inc = 1;
2829 desc->rqcfg.dst_inc = 0;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002830 desc->req.rqtype = MEMTODEV;
Jassi Brarb3040e42010-05-23 20:28:19 -07002831 fill_px(&desc->px,
2832 addr, sg_dma_address(sg), sg_dma_len(sg));
2833 } else {
2834 desc->rqcfg.src_inc = 0;
2835 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002836 desc->req.rqtype = DEVTOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002837 fill_px(&desc->px,
2838 sg_dma_address(sg), addr, sg_dma_len(sg));
2839 }
2840
Boojin Kim1b9bb712011-09-02 09:44:30 +09002841 desc->rqcfg.brst_size = pch->burst_sz;
Jassi Brarb3040e42010-05-23 20:28:19 -07002842 desc->rqcfg.brst_len = 1;
2843 }
2844
2845 /* Return the last desc in the chain */
2846 desc->txd.flags = flg;
2847 return &desc->txd;
2848}
2849
2850static irqreturn_t pl330_irq_handler(int irq, void *data)
2851{
2852 if (pl330_update(data))
2853 return IRQ_HANDLED;
2854 else
2855 return IRQ_NONE;
2856}
2857
Bill Pemberton463a1f82012-11-19 13:22:55 -05002858static int
Russell Kingaa25afa2011-02-19 15:55:00 +00002859pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002860{
2861 struct dma_pl330_platdata *pdat;
2862 struct dma_pl330_dmac *pdmac;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302863 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002864 struct pl330_info *pi;
2865 struct dma_device *pd;
2866 struct resource *res;
2867 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002868 int num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002869
2870 pdat = adev->dev.platform_data;
2871
Jassi Brarb3040e42010-05-23 20:28:19 -07002872 /* Allocate a new DMAC and its Channels */
Sachin Kamate4d43c12012-11-15 06:27:50 +00002873 pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL);
Jassi Brarb3040e42010-05-23 20:28:19 -07002874 if (!pdmac) {
2875 dev_err(&adev->dev, "unable to allocate mem\n");
2876 return -ENOMEM;
2877 }
2878
2879 pi = &pdmac->pif;
2880 pi->dev = &adev->dev;
2881 pi->pl330_data = NULL;
Rob Herring4e0e6102011-07-25 16:05:04 -05002882 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002883
2884 res = &adev->res;
Sachin Kamatbcc7fa92013-03-04 14:36:27 +05302885 pi->base = devm_ioremap_resource(&adev->dev, res);
2886 if (IS_ERR(pi->base))
2887 return PTR_ERR(pi->base);
Jassi Brarb3040e42010-05-23 20:28:19 -07002888
Boojin Kima2f52032011-09-02 09:44:29 +09002889 amba_set_drvdata(adev, pdmac);
2890
Jassi Brarb3040e42010-05-23 20:28:19 -07002891 irq = adev->irq[0];
2892 ret = request_irq(irq, pl330_irq_handler, 0,
2893 dev_name(&adev->dev), pi);
2894 if (ret)
Sachin Kamate4d43c12012-11-15 06:27:50 +00002895 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002896
Will Deacon09677172013-06-10 19:34:37 +01002897 pi->pcfg.periph_id = adev->periphid;
Jassi Brarb3040e42010-05-23 20:28:19 -07002898 ret = pl330_add(pi);
2899 if (ret)
Sachin Kamate4d43c12012-11-15 06:27:50 +00002900 goto probe_err1;
Jassi Brarb3040e42010-05-23 20:28:19 -07002901
2902 INIT_LIST_HEAD(&pdmac->desc_pool);
2903 spin_lock_init(&pdmac->pool_lock);
2904
2905 /* Create a descriptor pool of default size */
2906 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
2907 dev_warn(&adev->dev, "unable to allocate desc\n");
2908
2909 pd = &pdmac->ddma;
2910 INIT_LIST_HEAD(&pd->channels);
2911
2912 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002913 if (pdat)
2914 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
2915 else
2916 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
2917
Rob Herring4e0e6102011-07-25 16:05:04 -05002918 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
Sachin Kamat61c6e752012-09-17 15:20:23 +05302919 if (!pdmac->peripherals) {
2920 ret = -ENOMEM;
2921 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
Sachin Kamate4d43c12012-11-15 06:27:50 +00002922 goto probe_err2;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302923 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002924
Rob Herring4e0e6102011-07-25 16:05:04 -05002925 for (i = 0; i < num_chan; i++) {
2926 pch = &pdmac->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002927 if (!adev->dev.of_node)
2928 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2929 else
2930 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002931
2932 INIT_LIST_HEAD(&pch->work_list);
2933 spin_lock_init(&pch->lock);
2934 pch->pl330_chid = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002935 pch->chan.device = pd;
Jassi Brarb3040e42010-05-23 20:28:19 -07002936 pch->dmac = pdmac;
2937
2938 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002939 list_add_tail(&pch->chan.device_node, &pd->channels);
2940 }
2941
2942 pd->dev = &adev->dev;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002943 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002944 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002945 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002946 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002947 if (pi->pcfg.num_peri) {
2948 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2949 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302950 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002951 }
2952 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002953
2954 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2955 pd->device_free_chan_resources = pl330_free_chan_resources;
2956 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002957 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07002958 pd->device_tx_status = pl330_tx_status;
2959 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2960 pd->device_control = pl330_control;
2961 pd->device_issue_pending = pl330_issue_pending;
2962
2963 ret = dma_async_device_register(pd);
2964 if (ret) {
2965 dev_err(&adev->dev, "unable to register DMAC\n");
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302966 goto probe_err3;
2967 }
2968
2969 if (adev->dev.of_node) {
2970 ret = of_dma_controller_register(adev->dev.of_node,
2971 of_dma_pl330_xlate, pdmac);
2972 if (ret) {
2973 dev_err(&adev->dev,
2974 "unable to register DMA to the generic DT DMA helpers\n");
2975 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002976 }
2977
Jassi Brarb3040e42010-05-23 20:28:19 -07002978 dev_info(&adev->dev,
2979 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
2980 dev_info(&adev->dev,
2981 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2982 pi->pcfg.data_buf_dep,
2983 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
2984 pi->pcfg.num_peri, pi->pcfg.num_events);
2985
2986 return 0;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302987probe_err3:
2988 amba_set_drvdata(adev, NULL);
Jassi Brarb3040e42010-05-23 20:28:19 -07002989
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302990 /* Idle the DMAC */
2991 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
2992 chan.device_node) {
2993
2994 /* Remove the channel */
2995 list_del(&pch->chan.device_node);
2996
2997 /* Flush the channel */
2998 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
2999 pl330_free_chan_resources(&pch->chan);
3000 }
Jassi Brarb3040e42010-05-23 20:28:19 -07003001probe_err2:
Sachin Kamate4d43c12012-11-15 06:27:50 +00003002 pl330_del(pi);
Jassi Brarb3040e42010-05-23 20:28:19 -07003003probe_err1:
Sachin Kamate4d43c12012-11-15 06:27:50 +00003004 free_irq(irq, pi);
Jassi Brarb3040e42010-05-23 20:28:19 -07003005
3006 return ret;
3007}
3008
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08003009static int pl330_remove(struct amba_device *adev)
Jassi Brarb3040e42010-05-23 20:28:19 -07003010{
3011 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
3012 struct dma_pl330_chan *pch, *_p;
3013 struct pl330_info *pi;
Jassi Brarb3040e42010-05-23 20:28:19 -07003014 int irq;
3015
3016 if (!pdmac)
3017 return 0;
3018
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303019 if (adev->dev.of_node)
3020 of_dma_controller_free(adev->dev.of_node);
Padmavathi Venna421da892013-02-14 09:10:07 +05303021
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303022 dma_async_device_unregister(&pdmac->ddma);
Jassi Brarb3040e42010-05-23 20:28:19 -07003023 amba_set_drvdata(adev, NULL);
3024
3025 /* Idle the DMAC */
3026 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3027 chan.device_node) {
3028
3029 /* Remove the channel */
3030 list_del(&pch->chan.device_node);
3031
3032 /* Flush the channel */
3033 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3034 pl330_free_chan_resources(&pch->chan);
3035 }
3036
3037 pi = &pdmac->pif;
3038
3039 pl330_del(pi);
3040
3041 irq = adev->irq[0];
3042 free_irq(irq, pi);
3043
Jassi Brarb3040e42010-05-23 20:28:19 -07003044 return 0;
3045}
3046
3047static struct amba_id pl330_ids[] = {
3048 {
3049 .id = 0x00041330,
3050 .mask = 0x000fffff,
3051 },
3052 { 0, 0 },
3053};
3054
Dave Martine8fa5162011-10-05 15:15:20 +01003055MODULE_DEVICE_TABLE(amba, pl330_ids);
3056
Jassi Brarb3040e42010-05-23 20:28:19 -07003057static struct amba_driver pl330_driver = {
3058 .drv = {
3059 .owner = THIS_MODULE,
3060 .name = "dma-pl330",
Jassi Brarb3040e42010-05-23 20:28:19 -07003061 },
3062 .id_table = pl330_ids,
3063 .probe = pl330_probe,
3064 .remove = pl330_remove,
3065};
3066
viresh kumar9e5ed092012-03-15 10:40:38 +01003067module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07003068
3069MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3070MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3071MODULE_LICENSE("GPL");