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Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Jan Engelhardt751cb5e2007-07-15 23:39:27 -07007menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -07008 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +02009 depends on HAS_IOMEM
Andrew Morton4c6a1c12007-07-26 10:41:10 -070010 depends on X86 || PPC
Alan Coxda9bb1d2006-01-18 17:44:13 -080011 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070014 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080017
Tim Small57c432b2006-03-09 17:33:50 -080018 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070030if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080031
32comment "Reporting subsystems"
Alan Coxda9bb1d2006-01-18 17:44:13 -080033
34config EDAC_DEBUG
35 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080036 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020042 config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE
45 default y
46 ---help---
47 Enable this option if you want to decode Machine Check Exceptions
48 occuring on your machine in human-readable form.
49
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
52 has been initialized.
53
Alan Coxda9bb1d2006-01-18 17:44:13 -080054config EDAC_MM_EDAC
55 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080056 help
57 Some systems are able to detect and correct errors in main
58 memory. EDAC can report statistics on memory error
59 detection and correction (EDAC - or commonly referred to ECC
60 errors). EDAC will also try to decode where these errors
61 occurred so that a particular failing memory module can be
62 replaced. If unsure, select 'Y'.
63
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030064config EDAC_MCE
Mauro Carvalho Chehab963c5ba2009-07-09 22:04:30 -030065 bool
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030066
Doug Thompson7d6034d2009-04-27 20:01:01 +020067config EDAC_AMD64
68 tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020069 depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020070 help
Borislav Petkov3d373292009-05-20 20:18:46 +020071 Support for error detection and correction on the AMD 64
72 Families of Memory Controllers (K8, F10h and F11h)
Doug Thompson7d6034d2009-04-27 20:01:01 +020073
74config EDAC_AMD64_ERROR_INJECTION
75 bool "Sysfs Error Injection facilities"
76 depends on EDAC_AMD64
77 help
78 Recent Opterons (Family 10h and later) provide for Memory Error
79 Injection into the ECC detection circuits. The amd64_edac module
80 allows the operator/user to inject Uncorrectable and Correctable
81 errors into DRAM.
82
83 When enabled, in each of the respective memory controller directories
84 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
85
86 - inject_section (0..3, 16-byte section of 64-byte cacheline),
87 - inject_word (0..8, 16-bit word of 16-byte section),
88 - inject_ecc_vector (hex ecc vector: select bits of inject word)
89
90 In addition, there are two control files, inject_read and inject_write,
91 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -080092
93config EDAC_AMD76X
94 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -080095 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -080096 help
97 Support for error detection and correction on the AMD 76x
98 series of chipsets used with the Athlon processor.
99
100config EDAC_E7XXX
101 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800102 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800103 help
104 Support for error detection and correction on the Intel
105 E7205, E7500, E7501 and E7505 server chipsets.
106
107config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700108 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800109 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800110 help
111 Support for error detection and correction on the Intel
112 E7520, E7525, E7320 server chipsets.
113
Tim Small5a2c6752007-07-19 01:49:42 -0700114config EDAC_I82443BXGX
115 tristate "Intel 82443BX/GX (440BX/GX)"
116 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700117 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700118 help
119 Support for error detection and correction on the Intel
120 82443BX/GX memory controllers (440BX/GX chipsets).
121
Alan Coxda9bb1d2006-01-18 17:44:13 -0800122config EDAC_I82875P
123 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800124 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800125 help
126 Support for error detection and correction on the Intel
127 DP82785P and E7210 server chipsets.
128
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700129config EDAC_I82975X
130 tristate "Intel 82975x (D82975x)"
131 depends on EDAC_MM_EDAC && PCI && X86
132 help
133 Support for error detection and correction on the Intel
134 DP82975x server chipsets.
135
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700136config EDAC_I3000
137 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800138 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700139 help
140 Support for error detection and correction on the Intel
141 3000 and 3010 server chipsets.
142
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700143config EDAC_I3200
144 tristate "Intel 3200"
145 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
146 help
147 Support for error detection and correction on the Intel
148 3200 and 3210 server chipsets.
149
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700150config EDAC_X38
151 tristate "Intel X38"
152 depends on EDAC_MM_EDAC && PCI && X86
153 help
154 Support for error detection and correction on the Intel
155 X38 server chipsets.
156
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800157config EDAC_I5400
158 tristate "Intel 5400 (Seaburg) chipsets"
159 depends on EDAC_MM_EDAC && PCI && X86
160 help
161 Support for error detection and correction the Intel
162 i5400 MCH chipset (Seaburg).
163
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300164config EDAC_I7CORE
165 tristate "Intel i7 Core (Nehalem) processors"
166 depends on EDAC_MM_EDAC && PCI && X86
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300167 select EDAC_MCE
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300168 help
169 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300170 i7 Core (Nehalem) Integrated Memory Controller that exists on
171 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
172 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300173
Alan Coxda9bb1d2006-01-18 17:44:13 -0800174config EDAC_I82860
175 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800176 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800177 help
178 Support for error detection and correction on the Intel
179 82860 chipset.
180
181config EDAC_R82600
182 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800183 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800184 help
185 Support for error detection and correction on the Radisys
186 82600 embedded chipset.
187
Eric Wolleseneb607052007-07-19 01:49:39 -0700188config EDAC_I5000
189 tristate "Intel Greencreek/Blackford chipset"
190 depends on EDAC_MM_EDAC && X86 && PCI
191 help
192 Support for error detection and correction the Intel
193 Greekcreek/Blackford chipsets.
194
Arthur Jones8f421c592008-07-25 01:49:04 -0700195config EDAC_I5100
196 tristate "Intel San Clemente MCH"
197 depends on EDAC_MM_EDAC && X86 && PCI
198 help
199 Support for error detection and correction the Intel
200 San Clemente MCH.
201
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300202config EDAC_I7300
203 tristate "Intel Clarksboro MCH"
204 depends on EDAC_MM_EDAC && X86 && PCI
205 help
206 Support for error detection and correction the Intel
207 Clarksboro MCH (Intel 7300 chipset).
208
Dave Jianga9a753d2008-02-07 00:14:55 -0800209config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700210 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700211 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800212 help
213 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700214 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800215
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800216config EDAC_MV64X60
217 tristate "Marvell MV64x60"
218 depends on EDAC_MM_EDAC && MV64X60
219 help
220 Support for error detection and correction on the Marvell
221 MV64360 and MV64460 chipsets.
222
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700223config EDAC_PASEMI
224 tristate "PA Semi PWRficient"
225 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700226 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700227 help
228 Support for error detection and correction on PA Semi
229 PWRficient.
230
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800231config EDAC_CELL
232 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100233 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800234 help
235 Support for error detection and correction on the
236 Cell Broadband Engine internal memory controller
237 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700238
Grant Ericksondba7a772009-04-02 16:58:45 -0700239config EDAC_PPC4XX
240 tristate "PPC4xx IBM DDR2 Memory Controller"
241 depends on EDAC_MM_EDAC && 4xx
242 help
243 This enables support for EDAC on the ECC memory used
244 with the IBM DDR2 memory controller found in various
245 PowerPC 4xx embedded processors such as the 405EX[r],
246 440SP, 440SPe, 460EX, 460GT and 460SX.
247
Harry Ciaoe8765582009-04-02 16:58:51 -0700248config EDAC_AMD8131
249 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700250 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700251 help
252 Support for error detection and correction on the
253 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700254 Note, add more Kconfig dependency if it's adopted
255 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700256
Harry Ciao58b4ce62009-04-02 16:58:51 -0700257config EDAC_AMD8111
258 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700259 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700260 help
261 Support for error detection and correction on the
262 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700263 Note, add more Kconfig dependency if it's adopted
264 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700265
Harry Ciao2a9036a2009-06-17 16:27:58 -0700266config EDAC_CPC925
267 tristate "IBM CPC925 Memory Controller (PPC970FX)"
268 depends on EDAC_MM_EDAC && PPC64
269 help
270 Support for error detection and correction on the
271 IBM CPC925 Bridge and Memory Controller, which is
272 a companion chip to the PowerPC 970 family of
273 processors.
274
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700275endif # EDAC