blob: 13661e129d9634bd3f163d83b1b62d105353ca75 [file] [log] [blame]
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001/*
2 * Copyright (C) 2009 Texas Instruments.
Brian Niebuhr43abb112010-10-06 18:34:47 +05303 * Copyright (C) 2010 EF Johnson Technologies
Sandeep Paulraj358934a2009-12-16 22:02:18 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/err.h>
27#include <linux/clk.h>
Matt Porter048177c2012-08-22 21:09:36 -040028#include <linux/dmaengine.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000029#include <linux/dma-mapping.h>
Matt Porter048177c2012-08-22 21:09:36 -040030#include <linux/edma.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000031#include <linux/spi/spi.h>
32#include <linux/spi/spi_bitbang.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000034
Arnd Bergmannec2a0832012-08-24 15:11:34 +020035#include <linux/platform_data/spi-davinci.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000036
37#define SPI_NO_RESOURCE ((resource_size_t)-1)
38
39#define SPI_MAX_CHIPSELECT 2
40
41#define CS_DEFAULT 0xFF
42
Sandeep Paulraj358934a2009-12-16 22:02:18 +000043#define SPIFMT_PHASE_MASK BIT(16)
44#define SPIFMT_POLARITY_MASK BIT(17)
45#define SPIFMT_DISTIMER_MASK BIT(18)
46#define SPIFMT_SHIFTDIR_MASK BIT(20)
47#define SPIFMT_WAITENA_MASK BIT(21)
48#define SPIFMT_PARITYENA_MASK BIT(22)
49#define SPIFMT_ODD_PARITY_MASK BIT(23)
50#define SPIFMT_WDELAY_MASK 0x3f000000u
51#define SPIFMT_WDELAY_SHIFT 24
Brian Niebuhr7fe00922010-08-13 13:27:23 +053052#define SPIFMT_PRESCALE_SHIFT 8
Sandeep Paulraj358934a2009-12-16 22:02:18 +000053
Sandeep Paulraj358934a2009-12-16 22:02:18 +000054/* SPIPC0 */
55#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
56#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
57#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
58#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000059
60#define SPIINT_MASKALL 0x0101035F
Brian Niebuhre0d205e2010-09-02 16:52:06 +053061#define SPIINT_MASKINT 0x0000015F
62#define SPI_INTLVL_1 0x000001FF
63#define SPI_INTLVL_0 0x00000000
Sandeep Paulraj358934a2009-12-16 22:02:18 +000064
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053065/* SPIDAT1 (upper 16 bit defines) */
66#define SPIDAT1_CSHOLD_MASK BIT(12)
67
68/* SPIGCR1 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000069#define SPIGCR1_CLKMOD_MASK BIT(1)
70#define SPIGCR1_MASTER_MASK BIT(0)
Brian Niebuhr3f27b572010-10-06 18:25:43 +053071#define SPIGCR1_POWERDOWN_MASK BIT(8)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000072#define SPIGCR1_LOOPBACK_MASK BIT(16)
Sekhar Nori8e206f12010-08-20 16:20:49 +053073#define SPIGCR1_SPIENA_MASK BIT(24)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000074
75/* SPIBUF */
76#define SPIBUF_TXFULL_MASK BIT(29)
77#define SPIBUF_RXEMPTY_MASK BIT(31)
78
Brian Niebuhr7abbf232010-08-19 15:07:38 +053079/* SPIDELAY */
80#define SPIDELAY_C2TDELAY_SHIFT 24
81#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
82#define SPIDELAY_T2CDELAY_SHIFT 16
83#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
84#define SPIDELAY_T2EDELAY_SHIFT 8
85#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
86#define SPIDELAY_C2EDELAY_SHIFT 0
87#define SPIDELAY_C2EDELAY_MASK 0xFF
88
Sandeep Paulraj358934a2009-12-16 22:02:18 +000089/* Error Masks */
90#define SPIFLG_DLEN_ERR_MASK BIT(0)
91#define SPIFLG_TIMEOUT_MASK BIT(1)
92#define SPIFLG_PARERR_MASK BIT(2)
93#define SPIFLG_DESYNC_MASK BIT(3)
94#define SPIFLG_BITERR_MASK BIT(4)
95#define SPIFLG_OVRRUN_MASK BIT(6)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000096#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
Brian Niebuhr839c9962010-08-23 16:39:19 +053097#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
98 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
99 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
100 | SPIFLG_OVRRUN_MASK)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000101
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000102#define SPIINT_DMA_REQ_EN BIT(16)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000103
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000104/* SPI Controller registers */
105#define SPIGCR0 0x00
106#define SPIGCR1 0x04
107#define SPIINT 0x08
108#define SPILVL 0x0c
109#define SPIFLG 0x10
110#define SPIPC0 0x14
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000111#define SPIDAT1 0x3c
112#define SPIBUF 0x40
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000113#define SPIDELAY 0x48
114#define SPIDEF 0x4c
115#define SPIFMT0 0x50
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000116
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000117/* SPI Controller driver's private data. */
118struct davinci_spi {
119 struct spi_bitbang bitbang;
120 struct clk *clk;
121
122 u8 version;
123 resource_size_t pbase;
124 void __iomem *base;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530125 u32 irq;
126 struct completion done;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000127
128 const void *tx;
129 void *rx;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530130 int rcount;
131 int wcount;
Matt Porter048177c2012-08-22 21:09:36 -0400132
133 struct dma_chan *dma_rx;
134 struct dma_chan *dma_tx;
135 int dma_rx_chnum;
136 int dma_tx_chnum;
137
Brian Niebuhr778e2612010-09-03 15:15:06 +0530138 struct davinci_spi_platform_data *pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000139
140 void (*get_rx)(u32 rx_data, struct davinci_spi *);
141 u32 (*get_tx)(struct davinci_spi *);
142
Brian Niebuhrcda987e2010-08-19 16:16:28 +0530143 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000144};
145
Brian Niebuhr53a31b02010-08-16 15:05:51 +0530146static struct davinci_spi_config davinci_spi_default_cfg;
147
Sekhar Nori212d4b62010-10-11 10:41:39 +0530148static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000149{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530150 if (dspi->rx) {
151 u8 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530152 *rx++ = (u8)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530153 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530154 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000155}
156
Sekhar Nori212d4b62010-10-11 10:41:39 +0530157static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000158{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530159 if (dspi->rx) {
160 u16 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530161 *rx++ = (u16)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530162 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530163 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000164}
165
Sekhar Nori212d4b62010-10-11 10:41:39 +0530166static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000167{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530168 u32 data = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530169 if (dspi->tx) {
170 const u8 *tx = dspi->tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530171 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530172 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530173 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000174 return data;
175}
176
Sekhar Nori212d4b62010-10-11 10:41:39 +0530177static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000178{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530179 u32 data = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530180 if (dspi->tx) {
181 const u16 *tx = dspi->tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530182 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530183 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530184 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000185 return data;
186}
187
188static inline void set_io_bits(void __iomem *addr, u32 bits)
189{
190 u32 v = ioread32(addr);
191
192 v |= bits;
193 iowrite32(v, addr);
194}
195
196static inline void clear_io_bits(void __iomem *addr, u32 bits)
197{
198 u32 v = ioread32(addr);
199
200 v &= ~bits;
201 iowrite32(v, addr);
202}
203
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000204/*
205 * Interface to control the chip select signal
206 */
207static void davinci_spi_chipselect(struct spi_device *spi, int value)
208{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530209 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000210 struct davinci_spi_platform_data *pdata;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530211 u8 chip_sel = spi->chip_select;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530212 u16 spidat1 = CS_DEFAULT;
Brian Niebuhr23853972010-08-13 10:57:44 +0530213 bool gpio_chipsel = false;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000214
Sekhar Nori212d4b62010-10-11 10:41:39 +0530215 dspi = spi_master_get_devdata(spi->master);
216 pdata = dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000217
Brian Niebuhr23853972010-08-13 10:57:44 +0530218 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
219 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
220 gpio_chipsel = true;
221
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000222 /*
223 * Board specific chip select logic decides the polarity and cs
224 * line for the controller
225 */
Brian Niebuhr23853972010-08-13 10:57:44 +0530226 if (gpio_chipsel) {
227 if (value == BITBANG_CS_ACTIVE)
228 gpio_set_value(pdata->chip_sel[chip_sel], 0);
229 else
230 gpio_set_value(pdata->chip_sel[chip_sel], 1);
231 } else {
232 if (value == BITBANG_CS_ACTIVE) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530233 spidat1 |= SPIDAT1_CSHOLD_MASK;
234 spidat1 &= ~(0x1 << chip_sel);
Brian Niebuhr23853972010-08-13 10:57:44 +0530235 }
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530236
Sekhar Nori212d4b62010-10-11 10:41:39 +0530237 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
Brian Niebuhr23853972010-08-13 10:57:44 +0530238 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000239}
240
241/**
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530242 * davinci_spi_get_prescale - Calculates the correct prescale value
243 * @maxspeed_hz: the maximum rate the SPI clock can run at
244 *
245 * This function calculates the prescale value that generates a clock rate
246 * less than or equal to the specified maximum.
247 *
248 * Returns: calculated prescale - 1 for easy programming into SPI registers
249 * or negative error number if valid prescalar cannot be updated.
250 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530251static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530252 u32 max_speed_hz)
253{
254 int ret;
255
Sekhar Nori212d4b62010-10-11 10:41:39 +0530256 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530257
258 if (ret < 3 || ret > 256)
259 return -EINVAL;
260
261 return ret - 1;
262}
263
264/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000265 * davinci_spi_setup_transfer - This functions will determine transfer method
266 * @spi: spi device on which data transfer to be done
267 * @t: spi transfer in which transfer info is filled
268 *
269 * This function determines data transfer method (8/16/32 bit transfer).
270 * It will also set the SPI Clock Control register according to
271 * SPI slave device freq.
272 */
273static int davinci_spi_setup_transfer(struct spi_device *spi,
274 struct spi_transfer *t)
275{
276
Sekhar Nori212d4b62010-10-11 10:41:39 +0530277 struct davinci_spi *dspi;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530278 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000279 u8 bits_per_word = 0;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530280 u32 hz = 0, spifmt = 0, prescale = 0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000281
Sekhar Nori212d4b62010-10-11 10:41:39 +0530282 dspi = spi_master_get_devdata(spi->master);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530283 spicfg = (struct davinci_spi_config *)spi->controller_data;
284 if (!spicfg)
285 spicfg = &davinci_spi_default_cfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000286
287 if (t) {
288 bits_per_word = t->bits_per_word;
289 hz = t->speed_hz;
290 }
291
292 /* if bits_per_word is not set then set it default */
293 if (!bits_per_word)
294 bits_per_word = spi->bits_per_word;
295
296 /*
297 * Assign function pointer to appropriate transfer method
298 * 8bit, 16bit or 32bit transfer
299 */
300 if (bits_per_word <= 8 && bits_per_word >= 2) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530301 dspi->get_rx = davinci_spi_rx_buf_u8;
302 dspi->get_tx = davinci_spi_tx_buf_u8;
303 dspi->bytes_per_word[spi->chip_select] = 1;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000304 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530305 dspi->get_rx = davinci_spi_rx_buf_u16;
306 dspi->get_tx = davinci_spi_tx_buf_u16;
307 dspi->bytes_per_word[spi->chip_select] = 2;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000308 } else
309 return -EINVAL;
310
311 if (!hz)
312 hz = spi->max_speed_hz;
313
Brian Niebuhr25f33512010-08-19 12:15:22 +0530314 /* Set up SPIFMTn register, unique to this chipselect. */
315
Sekhar Nori212d4b62010-10-11 10:41:39 +0530316 prescale = davinci_spi_get_prescale(dspi, hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530317 if (prescale < 0)
318 return prescale;
319
Brian Niebuhr25f33512010-08-19 12:15:22 +0530320 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000321
Brian Niebuhr25f33512010-08-19 12:15:22 +0530322 if (spi->mode & SPI_LSB_FIRST)
323 spifmt |= SPIFMT_SHIFTDIR_MASK;
324
325 if (spi->mode & SPI_CPOL)
326 spifmt |= SPIFMT_POLARITY_MASK;
327
328 if (!(spi->mode & SPI_CPHA))
329 spifmt |= SPIFMT_PHASE_MASK;
330
331 /*
332 * Version 1 hardware supports two basic SPI modes:
333 * - Standard SPI mode uses 4 pins, with chipselect
334 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
335 * (distinct from SPI_3WIRE, with just one data wire;
336 * or similar variants without MOSI or without MISO)
337 *
338 * Version 2 hardware supports an optional handshaking signal,
339 * so it can support two more modes:
340 * - 5 pin SPI variant is standard SPI plus SPI_READY
341 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
342 */
343
Sekhar Nori212d4b62010-10-11 10:41:39 +0530344 if (dspi->version == SPI_VERSION_2) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530345
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530346 u32 delay = 0;
347
Brian Niebuhr25f33512010-08-19 12:15:22 +0530348 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
349 & SPIFMT_WDELAY_MASK);
350
351 if (spicfg->odd_parity)
352 spifmt |= SPIFMT_ODD_PARITY_MASK;
353
354 if (spicfg->parity_enable)
355 spifmt |= SPIFMT_PARITYENA_MASK;
356
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530357 if (spicfg->timer_disable) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530358 spifmt |= SPIFMT_DISTIMER_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530359 } else {
360 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
361 & SPIDELAY_C2TDELAY_MASK;
362 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
363 & SPIDELAY_T2CDELAY_MASK;
364 }
Brian Niebuhr25f33512010-08-19 12:15:22 +0530365
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530366 if (spi->mode & SPI_READY) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530367 spifmt |= SPIFMT_WAITENA_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530368 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
369 & SPIDELAY_T2EDELAY_MASK;
370 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
371 & SPIDELAY_C2EDELAY_MASK;
372 }
373
Sekhar Nori212d4b62010-10-11 10:41:39 +0530374 iowrite32(delay, dspi->base + SPIDELAY);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530375 }
376
Sekhar Nori212d4b62010-10-11 10:41:39 +0530377 iowrite32(spifmt, dspi->base + SPIFMT0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000378
379 return 0;
380}
381
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000382/**
383 * davinci_spi_setup - This functions will set default transfer method
384 * @spi: spi device on which data transfer to be done
385 *
386 * This functions sets the default transfer method.
387 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000388static int davinci_spi_setup(struct spi_device *spi)
389{
Brian Niebuhrb23a5d42010-09-24 18:53:32 +0530390 int retval = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530391 struct davinci_spi *dspi;
Brian Niebuhrbe884712010-09-03 12:15:28 +0530392 struct davinci_spi_platform_data *pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000393
Sekhar Nori212d4b62010-10-11 10:41:39 +0530394 dspi = spi_master_get_devdata(spi->master);
395 pdata = dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000396
397 /* if bits per word length is zero then set it default 8 */
398 if (!spi->bits_per_word)
399 spi->bits_per_word = 8;
400
Brian Niebuhrbe884712010-09-03 12:15:28 +0530401 if (!(spi->mode & SPI_NO_CS)) {
402 if ((pdata->chip_sel == NULL) ||
403 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
Sekhar Nori212d4b62010-10-11 10:41:39 +0530404 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530405
406 }
407
408 if (spi->mode & SPI_READY)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530409 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530410
411 if (spi->mode & SPI_LOOP)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530412 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530413 else
Sekhar Nori212d4b62010-10-11 10:41:39 +0530414 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530415
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000416 return retval;
417}
418
Sekhar Nori212d4b62010-10-11 10:41:39 +0530419static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000420{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530421 struct device *sdev = dspi->bitbang.master->dev.parent;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000422
423 if (int_status & SPIFLG_TIMEOUT_MASK) {
424 dev_dbg(sdev, "SPI Time-out Error\n");
425 return -ETIMEDOUT;
426 }
427 if (int_status & SPIFLG_DESYNC_MASK) {
428 dev_dbg(sdev, "SPI Desynchronization Error\n");
429 return -EIO;
430 }
431 if (int_status & SPIFLG_BITERR_MASK) {
432 dev_dbg(sdev, "SPI Bit error\n");
433 return -EIO;
434 }
435
Sekhar Nori212d4b62010-10-11 10:41:39 +0530436 if (dspi->version == SPI_VERSION_2) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000437 if (int_status & SPIFLG_DLEN_ERR_MASK) {
438 dev_dbg(sdev, "SPI Data Length Error\n");
439 return -EIO;
440 }
441 if (int_status & SPIFLG_PARERR_MASK) {
442 dev_dbg(sdev, "SPI Parity Error\n");
443 return -EIO;
444 }
445 if (int_status & SPIFLG_OVRRUN_MASK) {
446 dev_dbg(sdev, "SPI Data Overrun error\n");
447 return -EIO;
448 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000449 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
450 dev_dbg(sdev, "SPI Buffer Init Active\n");
451 return -EBUSY;
452 }
453 }
454
455 return 0;
456}
457
458/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530459 * davinci_spi_process_events - check for and handle any SPI controller events
Sekhar Nori212d4b62010-10-11 10:41:39 +0530460 * @dspi: the controller data
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530461 *
462 * This function will check the SPIFLG register and handle any events that are
463 * detected there
464 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530465static int davinci_spi_process_events(struct davinci_spi *dspi)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530466{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530467 u32 buf, status, errors = 0, spidat1;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530468
Sekhar Nori212d4b62010-10-11 10:41:39 +0530469 buf = ioread32(dspi->base + SPIBUF);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530470
Sekhar Nori212d4b62010-10-11 10:41:39 +0530471 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
472 dspi->get_rx(buf & 0xFFFF, dspi);
473 dspi->rcount--;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530474 }
475
Sekhar Nori212d4b62010-10-11 10:41:39 +0530476 status = ioread32(dspi->base + SPIFLG);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530477
478 if (unlikely(status & SPIFLG_ERROR_MASK)) {
479 errors = status & SPIFLG_ERROR_MASK;
480 goto out;
481 }
482
Sekhar Nori212d4b62010-10-11 10:41:39 +0530483 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
484 spidat1 = ioread32(dspi->base + SPIDAT1);
485 dspi->wcount--;
486 spidat1 &= ~0xFFFF;
487 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
488 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530489 }
490
491out:
492 return errors;
493}
494
Matt Porter048177c2012-08-22 21:09:36 -0400495static void davinci_spi_dma_rx_callback(void *data)
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530496{
Matt Porter048177c2012-08-22 21:09:36 -0400497 struct davinci_spi *dspi = (struct davinci_spi *)data;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530498
Matt Porter048177c2012-08-22 21:09:36 -0400499 dspi->rcount = 0;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530500
Matt Porter048177c2012-08-22 21:09:36 -0400501 if (!dspi->wcount && !dspi->rcount)
502 complete(&dspi->done);
503}
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530504
Matt Porter048177c2012-08-22 21:09:36 -0400505static void davinci_spi_dma_tx_callback(void *data)
506{
507 struct davinci_spi *dspi = (struct davinci_spi *)data;
508
509 dspi->wcount = 0;
510
511 if (!dspi->wcount && !dspi->rcount)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530512 complete(&dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530513}
514
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530515/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000516 * davinci_spi_bufs - functions which will handle transfer data
517 * @spi: spi device on which data transfer to be done
518 * @t: spi transfer in which transfer info is filled
519 *
520 * This function will put data to be transferred into data register
521 * of SPI controller and then wait until the completion will be marked
522 * by the IRQ Handler.
523 */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530524static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000525{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530526 struct davinci_spi *dspi;
Matt Porter048177c2012-08-22 21:09:36 -0400527 int data_type, ret = -ENOMEM;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530528 u32 tx_data, spidat1;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530529 u32 errors = 0;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530530 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000531 struct davinci_spi_platform_data *pdata;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530532 unsigned uninitialized_var(rx_buf_count);
Matt Porter048177c2012-08-22 21:09:36 -0400533 void *dummy_buf = NULL;
534 struct scatterlist sg_rx, sg_tx;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000535
Sekhar Nori212d4b62010-10-11 10:41:39 +0530536 dspi = spi_master_get_devdata(spi->master);
537 pdata = dspi->pdata;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530538 spicfg = (struct davinci_spi_config *)spi->controller_data;
539 if (!spicfg)
540 spicfg = &davinci_spi_default_cfg;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530541
542 /* convert len to words based on bits_per_word */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530543 data_type = dspi->bytes_per_word[spi->chip_select];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000544
Sekhar Nori212d4b62010-10-11 10:41:39 +0530545 dspi->tx = t->tx_buf;
546 dspi->rx = t->rx_buf;
547 dspi->wcount = t->len / data_type;
548 dspi->rcount = dspi->wcount;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530549
Sekhar Nori212d4b62010-10-11 10:41:39 +0530550 spidat1 = ioread32(dspi->base + SPIDAT1);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530551
Sekhar Nori212d4b62010-10-11 10:41:39 +0530552 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
553 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000554
Sekhar Nori212d4b62010-10-11 10:41:39 +0530555 INIT_COMPLETION(dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530556
557 if (spicfg->io_type == SPI_IO_TYPE_INTR)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530558 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530559
560 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
561 /* start the transfer */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530562 dspi->wcount--;
563 tx_data = dspi->get_tx(dspi);
564 spidat1 &= 0xFFFF0000;
565 spidat1 |= tx_data & 0xFFFF;
566 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530567 } else {
Matt Porter048177c2012-08-22 21:09:36 -0400568 struct dma_slave_config dma_rx_conf = {
569 .direction = DMA_DEV_TO_MEM,
570 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
571 .src_addr_width = data_type,
572 .src_maxburst = 1,
573 };
574 struct dma_slave_config dma_tx_conf = {
575 .direction = DMA_MEM_TO_DEV,
576 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
577 .dst_addr_width = data_type,
578 .dst_maxburst = 1,
579 };
580 struct dma_async_tx_descriptor *rxdesc;
581 struct dma_async_tx_descriptor *txdesc;
582 void *buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530583
Matt Porter048177c2012-08-22 21:09:36 -0400584 dummy_buf = kzalloc(t->len, GFP_KERNEL);
585 if (!dummy_buf)
586 goto err_alloc_dummy_buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530587
Matt Porter048177c2012-08-22 21:09:36 -0400588 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
589 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530590
Matt Porter048177c2012-08-22 21:09:36 -0400591 sg_init_table(&sg_rx, 1);
592 if (!t->rx_buf)
593 buf = dummy_buf;
Michael Williamsonb1178b22011-03-14 11:49:02 -0400594 else
Matt Porter048177c2012-08-22 21:09:36 -0400595 buf = t->rx_buf;
596 t->rx_dma = dma_map_single(&spi->dev, buf,
597 t->len, DMA_FROM_DEVICE);
598 if (!t->rx_dma) {
599 ret = -EFAULT;
600 goto err_rx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530601 }
Matt Porter048177c2012-08-22 21:09:36 -0400602 sg_dma_address(&sg_rx) = t->rx_dma;
603 sg_dma_len(&sg_rx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530604
Matt Porter048177c2012-08-22 21:09:36 -0400605 sg_init_table(&sg_tx, 1);
606 if (!t->tx_buf)
607 buf = dummy_buf;
608 else
609 buf = (void *)t->tx_buf;
610 t->tx_dma = dma_map_single(&spi->dev, buf,
611 t->len, DMA_FROM_DEVICE);
612 if (!t->tx_dma) {
613 ret = -EFAULT;
614 goto err_tx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530615 }
Matt Porter048177c2012-08-22 21:09:36 -0400616 sg_dma_address(&sg_tx) = t->tx_dma;
617 sg_dma_len(&sg_tx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530618
Matt Porter048177c2012-08-22 21:09:36 -0400619 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
620 &sg_rx, 1, DMA_DEV_TO_MEM,
621 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
622 if (!rxdesc)
623 goto err_desc;
624
625 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
626 &sg_tx, 1, DMA_MEM_TO_DEV,
627 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
628 if (!txdesc)
629 goto err_desc;
630
631 rxdesc->callback = davinci_spi_dma_rx_callback;
632 rxdesc->callback_param = (void *)dspi;
633 txdesc->callback = davinci_spi_dma_tx_callback;
634 txdesc->callback_param = (void *)dspi;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530635
636 if (pdata->cshold_bug)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530637 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530638
Matt Porter048177c2012-08-22 21:09:36 -0400639 dmaengine_submit(rxdesc);
640 dmaengine_submit(txdesc);
641
642 dma_async_issue_pending(dspi->dma_rx);
643 dma_async_issue_pending(dspi->dma_tx);
644
Sekhar Nori212d4b62010-10-11 10:41:39 +0530645 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530646 }
Brian Niebuhrcf90fe72010-08-20 17:02:49 +0530647
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530648 /* Wait for the transfer to complete */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530649 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530650 wait_for_completion_interruptible(&(dspi->done));
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530651 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530652 while (dspi->rcount > 0 || dspi->wcount > 0) {
653 errors = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530654 if (errors)
655 break;
656 cpu_relax();
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000657 }
658 }
659
Sekhar Nori212d4b62010-10-11 10:41:39 +0530660 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530661 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530662 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Matt Porter048177c2012-08-22 21:09:36 -0400663
664 dma_unmap_single(&spi->dev, t->rx_dma,
665 t->len, DMA_FROM_DEVICE);
666 dma_unmap_single(&spi->dev, t->tx_dma,
667 t->len, DMA_TO_DEVICE);
668 kfree(dummy_buf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530669 }
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530670
Sekhar Nori212d4b62010-10-11 10:41:39 +0530671 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
672 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Brian Niebuhr3f27b572010-10-06 18:25:43 +0530673
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000674 /*
675 * Check for bit error, desync error,parity error,timeout error and
676 * receive overflow errors
677 */
Brian Niebuhr839c9962010-08-23 16:39:19 +0530678 if (errors) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530679 ret = davinci_spi_check_error(dspi, errors);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530680 WARN(!ret, "%s: error reported but no error found!\n",
681 dev_name(&spi->dev));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000682 return ret;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530683 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000684
Sekhar Nori212d4b62010-10-11 10:41:39 +0530685 if (dspi->rcount != 0 || dspi->wcount != 0) {
Matt Porter048177c2012-08-22 21:09:36 -0400686 dev_err(&spi->dev, "SPI data transfer error\n");
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530687 return -EIO;
688 }
689
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000690 return t->len;
Matt Porter048177c2012-08-22 21:09:36 -0400691
692err_desc:
693 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
694err_tx_map:
695 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
696err_rx_map:
697 kfree(dummy_buf);
698err_alloc_dummy_buf:
699 return ret;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000700}
701
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530702/**
703 * davinci_spi_irq - Interrupt handler for SPI Master Controller
704 * @irq: IRQ number for this SPI Master
705 * @context_data: structure for SPI Master controller davinci_spi
706 *
707 * ISR will determine that interrupt arrives either for READ or WRITE command.
708 * According to command it will do the appropriate action. It will check
709 * transfer length and if it is not zero then dispatch transfer command again.
710 * If transfer length is zero then it will indicate the COMPLETION so that
711 * davinci_spi_bufs function can go ahead.
712 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530713static irqreturn_t davinci_spi_irq(s32 irq, void *data)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530714{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530715 struct davinci_spi *dspi = data;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530716 int status;
717
Sekhar Nori212d4b62010-10-11 10:41:39 +0530718 status = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530719 if (unlikely(status != 0))
Sekhar Nori212d4b62010-10-11 10:41:39 +0530720 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530721
Sekhar Nori212d4b62010-10-11 10:41:39 +0530722 if ((!dspi->rcount && !dspi->wcount) || status)
723 complete(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530724
725 return IRQ_HANDLED;
726}
727
Sekhar Nori212d4b62010-10-11 10:41:39 +0530728static int davinci_spi_request_dma(struct davinci_spi *dspi)
Sekhar Nori903ca252010-10-01 14:51:40 +0530729{
Matt Porter048177c2012-08-22 21:09:36 -0400730 dma_cap_mask_t mask;
731 struct device *sdev = dspi->bitbang.master->dev.parent;
Sekhar Nori903ca252010-10-01 14:51:40 +0530732 int r;
733
Matt Porter048177c2012-08-22 21:09:36 -0400734 dma_cap_zero(mask);
735 dma_cap_set(DMA_SLAVE, mask);
736
737 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
738 &dspi->dma_rx_chnum);
739 if (!dspi->dma_rx) {
740 dev_err(sdev, "request RX DMA channel failed\n");
741 r = -ENODEV;
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530742 goto rx_dma_failed;
Sekhar Nori903ca252010-10-01 14:51:40 +0530743 }
744
Matt Porter048177c2012-08-22 21:09:36 -0400745 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
746 &dspi->dma_tx_chnum);
747 if (!dspi->dma_tx) {
748 dev_err(sdev, "request TX DMA channel failed\n");
749 r = -ENODEV;
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530750 goto tx_dma_failed;
Sekhar Nori903ca252010-10-01 14:51:40 +0530751 }
752
753 return 0;
Matt Porter048177c2012-08-22 21:09:36 -0400754
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530755tx_dma_failed:
Matt Porter048177c2012-08-22 21:09:36 -0400756 dma_release_channel(dspi->dma_rx);
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530757rx_dma_failed:
758 return r;
Sekhar Nori903ca252010-10-01 14:51:40 +0530759}
760
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000761/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000762 * davinci_spi_probe - probe function for SPI Master Controller
763 * @pdev: platform_device structure which contains plateform specific data
Brian Niebuhr035540f2010-10-06 18:32:40 +0530764 *
765 * According to Linux Device Model this function will be invoked by Linux
766 * with platform_device struct which contains the device specific info.
767 * This function will map the SPI controller's memory, register IRQ,
768 * Reset SPI controller and setting its registers to default value.
769 * It will invoke spi_bitbang_start to create work queue so that client driver
770 * can register transfer method to work queue.
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000771 */
Grant Likelyfd4a3192012-12-07 16:57:14 +0000772static int davinci_spi_probe(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000773{
774 struct spi_master *master;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530775 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000776 struct davinci_spi_platform_data *pdata;
777 struct resource *r, *mem;
778 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
779 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000780 int i = 0, ret = 0;
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530781 u32 spipc0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000782
783 pdata = pdev->dev.platform_data;
784 if (pdata == NULL) {
785 ret = -ENODEV;
786 goto err;
787 }
788
789 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
790 if (master == NULL) {
791 ret = -ENOMEM;
792 goto err;
793 }
794
795 dev_set_drvdata(&pdev->dev, master);
796
Sekhar Nori212d4b62010-10-11 10:41:39 +0530797 dspi = spi_master_get_devdata(master);
798 if (dspi == NULL) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000799 ret = -ENOENT;
800 goto free_master;
801 }
802
803 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
804 if (r == NULL) {
805 ret = -ENOENT;
806 goto free_master;
807 }
808
Sekhar Nori212d4b62010-10-11 10:41:39 +0530809 dspi->pbase = r->start;
810 dspi->pdata = pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000811
Sekhar Nori0e0eae4d12010-10-08 14:04:22 +0530812 mem = request_mem_region(r->start, resource_size(r), pdev->name);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000813 if (mem == NULL) {
814 ret = -EBUSY;
815 goto free_master;
816 }
817
Sekhar Nori212d4b62010-10-11 10:41:39 +0530818 dspi->base = ioremap(r->start, resource_size(r));
819 if (dspi->base == NULL) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000820 ret = -ENOMEM;
821 goto release_region;
822 }
823
Sekhar Nori212d4b62010-10-11 10:41:39 +0530824 dspi->irq = platform_get_irq(pdev, 0);
825 if (dspi->irq <= 0) {
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530826 ret = -EINVAL;
827 goto unmap_io;
828 }
829
Sekhar Nori212d4b62010-10-11 10:41:39 +0530830 ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev),
831 dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530832 if (ret)
833 goto unmap_io;
834
Sekhar Nori212d4b62010-10-11 10:41:39 +0530835 dspi->bitbang.master = spi_master_get(master);
836 if (dspi->bitbang.master == NULL) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000837 ret = -ENODEV;
Brian Niebuhrd3f71412010-09-29 12:31:54 +0530838 goto irq_free;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000839 }
840
Sekhar Nori212d4b62010-10-11 10:41:39 +0530841 dspi->clk = clk_get(&pdev->dev, NULL);
842 if (IS_ERR(dspi->clk)) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000843 ret = -ENODEV;
844 goto put_master;
845 }
Sekhar Nori212d4b62010-10-11 10:41:39 +0530846 clk_enable(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000847
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000848 master->bus_num = pdev->id;
849 master->num_chipselect = pdata->num_chipselect;
850 master->setup = davinci_spi_setup;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000851
Sekhar Nori212d4b62010-10-11 10:41:39 +0530852 dspi->bitbang.chipselect = davinci_spi_chipselect;
853 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000854
Sekhar Nori212d4b62010-10-11 10:41:39 +0530855 dspi->version = pdata->version;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000856
Sekhar Nori212d4b62010-10-11 10:41:39 +0530857 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
858 if (dspi->version == SPI_VERSION_2)
859 dspi->bitbang.flags |= SPI_READY;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000860
Sekhar Nori903ca252010-10-01 14:51:40 +0530861 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
862 if (r)
863 dma_rx_chan = r->start;
864 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
865 if (r)
866 dma_tx_chan = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000867
Sekhar Nori212d4b62010-10-11 10:41:39 +0530868 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
Sekhar Nori903ca252010-10-01 14:51:40 +0530869 if (dma_rx_chan != SPI_NO_RESOURCE &&
Michael Williamson2e3e2a52011-02-08 07:59:55 -0500870 dma_tx_chan != SPI_NO_RESOURCE) {
Matt Porter048177c2012-08-22 21:09:36 -0400871 dspi->dma_rx_chnum = dma_rx_chan;
872 dspi->dma_tx_chnum = dma_tx_chan;
Brian Niebuhr96fd8812010-09-27 22:23:23 +0530873
Sekhar Nori212d4b62010-10-11 10:41:39 +0530874 ret = davinci_spi_request_dma(dspi);
Sekhar Nori903ca252010-10-01 14:51:40 +0530875 if (ret)
876 goto free_clk;
877
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530878 dev_info(&pdev->dev, "DMA: supported\n");
879 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
880 "event queue: %d\n", dma_rx_chan, dma_tx_chan,
Michael Williamson2e3e2a52011-02-08 07:59:55 -0500881 pdata->dma_event_q);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000882 }
883
Sekhar Nori212d4b62010-10-11 10:41:39 +0530884 dspi->get_rx = davinci_spi_rx_buf_u8;
885 dspi->get_tx = davinci_spi_tx_buf_u8;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000886
Sekhar Nori212d4b62010-10-11 10:41:39 +0530887 init_completion(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530888
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000889 /* Reset In/OUT SPI module */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530890 iowrite32(0, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000891 udelay(100);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530892 iowrite32(1, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000893
Brian Niebuhrbe884712010-09-03 12:15:28 +0530894 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530895 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530896 iowrite32(spipc0, dspi->base + SPIPC0);
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530897
Brian Niebuhr23853972010-08-13 10:57:44 +0530898 /* initialize chip selects */
899 if (pdata->chip_sel) {
900 for (i = 0; i < pdata->num_chipselect; i++) {
901 if (pdata->chip_sel[i] != SPI_INTERN_CS)
902 gpio_direction_output(pdata->chip_sel[i], 1);
903 }
904 }
905
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530906 if (pdata->intr_line)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530907 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530908 else
Sekhar Nori212d4b62010-10-11 10:41:39 +0530909 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530910
Sekhar Nori212d4b62010-10-11 10:41:39 +0530911 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
Brian Niebuhr843a7132010-08-12 12:49:05 +0530912
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000913 /* master mode default */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530914 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
915 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
916 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000917
Sekhar Nori212d4b62010-10-11 10:41:39 +0530918 ret = spi_bitbang_start(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000919 if (ret)
Sekhar Nori903ca252010-10-01 14:51:40 +0530920 goto free_dma;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000921
Sekhar Nori212d4b62010-10-11 10:41:39 +0530922 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000923
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000924 return ret;
925
Sekhar Nori903ca252010-10-01 14:51:40 +0530926free_dma:
Matt Porter048177c2012-08-22 21:09:36 -0400927 dma_release_channel(dspi->dma_rx);
928 dma_release_channel(dspi->dma_tx);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000929free_clk:
Sekhar Nori212d4b62010-10-11 10:41:39 +0530930 clk_disable(dspi->clk);
931 clk_put(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000932put_master:
933 spi_master_put(master);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530934irq_free:
Sekhar Nori212d4b62010-10-11 10:41:39 +0530935 free_irq(dspi->irq, dspi);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000936unmap_io:
Sekhar Nori212d4b62010-10-11 10:41:39 +0530937 iounmap(dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000938release_region:
Sekhar Nori212d4b62010-10-11 10:41:39 +0530939 release_mem_region(dspi->pbase, resource_size(r));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000940free_master:
941 kfree(master);
942err:
943 return ret;
944}
945
946/**
947 * davinci_spi_remove - remove function for SPI Master Controller
948 * @pdev: platform_device structure which contains plateform specific data
949 *
950 * This function will do the reverse action of davinci_spi_probe function
951 * It will free the IRQ and SPI controller's memory region.
952 * It will also call spi_bitbang_stop to destroy the work queue which was
953 * created by spi_bitbang_start.
954 */
Grant Likelyfd4a3192012-12-07 16:57:14 +0000955static int davinci_spi_remove(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000956{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530957 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000958 struct spi_master *master;
Sekhar Nori0e0eae4d12010-10-08 14:04:22 +0530959 struct resource *r;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000960
961 master = dev_get_drvdata(&pdev->dev);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530962 dspi = spi_master_get_devdata(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000963
Sekhar Nori212d4b62010-10-11 10:41:39 +0530964 spi_bitbang_stop(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000965
Sekhar Nori212d4b62010-10-11 10:41:39 +0530966 clk_disable(dspi->clk);
967 clk_put(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000968 spi_master_put(master);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530969 free_irq(dspi->irq, dspi);
970 iounmap(dspi->base);
Sekhar Nori0e0eae4d12010-10-08 14:04:22 +0530971 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530972 release_mem_region(dspi->pbase, resource_size(r));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000973
974 return 0;
975}
976
977static struct platform_driver davinci_spi_driver = {
Brian Niebuhrd8c174c2010-10-06 18:47:16 +0530978 .driver = {
979 .name = "spi_davinci",
980 .owner = THIS_MODULE,
981 },
Grant Likely940ab882011-10-05 11:29:49 -0600982 .probe = davinci_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000983 .remove = davinci_spi_remove,
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000984};
Grant Likely940ab882011-10-05 11:29:49 -0600985module_platform_driver(davinci_spi_driver);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000986
987MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
988MODULE_LICENSE("GPL");